Neural network-based bit-by-bit dynamic temperature calibration tdl-tdc system and method

Abstract

This invention discloses a TDL-TDC system and method for bit-by-bit dynamic temperature calibration based on neural networks. It includes a TDL-TDC module, a distributed temperature sensor, an embedded neural network engine, a calibration parameter memory, and an output module. Through a lightweight neural network integrated into an FPGA, it dynamically calculates independent calibration parameters for each delay unit based on real-time local temperature, correcting the original measurement results bit-by-bit. This achieves high-precision (nonlinear error ≤ ±6ps), low-latency (<1μs) adaptive calibration, eliminating the need for a host computer and effectively solving temperature sensitivity issues. It is suitable for high-precision time measurement scenarios such as laser ranging and quantum communication.

Description

Technical Field

[0001] This invention relates to the field of time-to-digital converter technology, specifically to a bit-by-bit dynamic temperature calibration (TDL-TDC) system and method based on neural networks, which is suitable for high-precision time measurement applications such as laser ranging, particle physics, and quantum communication. Background Technology

[0002] TDL-TDC (Tap Delay Chain-Time to Digital Converter) is a high-precision time interval measurement circuit that utilizes the carry chain resources within an FPGA to construct delay cells and quantifies the time interval by measuring the propagation position of the signal within the delay chain. However, the main technical challenge facing TDL-TDC is its temperature sensitivity. The delay cells within the FPGA are significantly affected by process variations and temperature drift, leading to severe nonlinear errors.

[0003] Existing technologies, such as the neural network measurement and calibration system proposed by the Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CN116243583A), employ an offline training method on a host computer combined with online table lookup. This approach suffers from drawbacks such as large response delays, inability to adapt to rapid temperature changes, and the need for external host support. Furthermore, traditional calibration methods typically model the entire delay chain holistically, failing to address the individual differences between delay units. Research published in the *Journal of Electronic Measurement and Instrumentation* in 2024 shows that bin-by-bin calibration can reduce the integral nonlinearity error (INL) from ±15 ps to ±6 ps, but existing solutions lack a real-time online implementation mechanism. Summary of the Invention

[0004] The purpose of this invention is to provide a step-by-step dynamic temperature calibration (TDL-TDC) system and method based on neural networks, which solves the nonlinear error problem caused by temperature drift in the prior art and achieves high-precision, real-time, and adaptive time measurement.

[0005] The technical solution of this invention includes: a TDL-TDC hardware module, a distributed temperature sensor array, an embedded neural network inference engine, a bit-by-bit calibration parameter memory, and a calibration output module. The embedded neural network inference engine is integrated into the programmable logic resources of the FPGA chip and is used to dynamically output the correction values ​​of each delay unit based on real-time temperature and signal characteristics, achieving independent bit-by-bit calibration. The beneficial effects of this invention are:

[0006] 1. Enables independent bin-by-bin calibration, effectively reducing nonlinear errors by 40%~60%; 2. Employs an on-chip real-time adaptive calibration mechanism with a response latency of less than 1μs; 3. No host computer intervention is required, making it suitable for embedded / edge devices; 4. Supports dynamic weight updates to adapt to long-term temperature drift changes. Attached Figure Description

[0007] Figure 1 This is a system architecture diagram of the TDL-TDC system based on neural networks in this invention; Figure 2 This is a flowchart of the neural network bit-by-bit calibration process of the present invention. Detailed Implementation

[0008] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0009] like Figure 1 As shown, the TDL-TDC system based on neural networks of the present invention includes a TDL-TDC hardware module (1), a distributed temperature sensor array (2), an embedded neural network inference engine (3), a bit-by-bit calibration parameter memory (4), and a calibration output module (5).

[0010] The TDL-TDC hardware module (1) uses the CARRY4 or CARRY8 carry chain resources inside the FPGA to construct 64-256 delay units, each delay unit corresponding to a calibration bit. When the start signal arrives, the signal propagates step by step along the delay chain; when the stop signal arrives, the current propagation position is captured and the original time-to-digital conversion result is output.

[0011] The distributed temperature sensor array (2) includes multiple digital temperature sensors, which are evenly distributed around the delay chain of the TDL-TDC hardware module. The temperature sampling frequency is not less than 1kHz and the temperature measurement accuracy is better than ±0.5℃. It is used to monitor the local temperature of each delay unit area in real time.

[0012] The embedded neural network inference engine (3) adopts a lightweight multilayer perceptron structure and is directly integrated into the programmable logic of the FPGA chip. The feature vector received by the input layer includes real-time measurement context features such as the current temperature value, the previous measurement result, the signal edge slope, and the power supply voltage fluctuation value; the output layer outputs 64-256 calibration offsets, which correspond to each delay unit. The engine supports online weight updates and dynamically adjusts the network weights according to the long-term temperature drift trend through an incremental learning algorithm.

[0013] The bit-by-bit calibration parameter memory (4) is implemented using the FPGA's internal Block RAM. The storage depth matches the number of delay units, and it supports single-cycle read and write operations. It is used to store the calibration parameters of each delay unit output by the embedded neural network inference engine.

[0014] The calibration output module (5) adopts a lookup table adder structure, uses the original TDC output code as the address index, reads the corresponding calibration offset from the bit-by-bit calibration parameter memory, and performs arithmetic operations with the original output to obtain the final calibrated time measurement result.

[0015] like Figure 2 As shown, the calibration process of the present invention includes the following steps: S1: Receive start and stop signals through the TDL-TDC hardware module and generate the original time-to-digital conversion result; S2: Real-time acquisition of local temperature data in each delay unit region through a distributed temperature sensor array; S3: Receives temperature data and real-time measurement context features through an embedded neural network inference engine, and calculates independent calibration parameters for each delay unit using a pre-trained lightweight neural network model; S4: Store the calibration parameters into the bit-by-bit calibration parameter memory; S5: Corrects the original digital time conversion result bit by bit according to the calibration parameters, and outputs a high-precision calibrated time measurement result.

[0016] The test results of the embodiments show that the present invention has a nonlinear error of no more than ±6ps, a response delay of less than 1μs, and an effective resolution of 1.5ps within a temperature range of -20°C to 85°C, which is significantly better than the existing technical solutions.

Claims

1. A step-by-step dynamic temperature calibration (TDL-TDC) system based on a neural network, characterized in that, include: The TDL-TDC hardware module receives start and stop signals and outputs the raw time-to-digital conversion result; a distributed temperature sensor array, integrated within the FPGA chip, monitors the local temperature of each delay unit area in real time; an embedded neural network inference engine, directly integrated into the programmable logic of the FPGA chip, receives temperature data and real-time measurement context features, and calculates the independent calibration parameters for each delay unit using a lightweight neural network model; a bit-by-bit calibration parameter memory stores the calibration parameters for each delay unit; and a calibration output module corrects the raw time-to-digital conversion result bit-by-bit according to the calibration parameters, outputting a high-precision calibrated time measurement result.

2. The system according to claim 1, characterized in that, The TDL-TDC hardware module uses the CARRY4 or CARRY8 carry chain inside the FPGA to construct 64-256 delay units, each delay unit corresponding to a calibration bit.

3. The system according to claim 1, characterized in that, The embedded neural network inference engine adopts a lightweight multilayer perceptron structure. The input features include the current temperature value, the previous measurement result, and the signal edge slope. The output is the calibration offset of each delay unit, and it supports online weight updates to adapt to long-term temperature drift.

4. The system according to claim 1, characterized in that, The calibration output module adopts a lookup table adder structure, which reads the corresponding calibration offset by using the original TDC output code as the address index, and performs arithmetic operations with the original output to obtain the final calibration result.

5. A step-by-step dynamic temperature calibration (TDL-TDC) method based on neural networks, characterized in that, include: The raw time-to-digital conversion result is generated by the TDL-TDC hardware module; the local temperature of each delay unit area is collected by a distributed temperature sensor array. The embedded neural network inference engine calculates the independent calibration parameters for each delay unit; the calibration parameters are stored in the bit-by-bit calibration parameter memory; the original results are corrected bit by bit according to the calibration parameters, and the high-precision calibrated time measurement results are output.

6. The method according to claim 5, characterized in that, The lightweight neural network model obtains training data through code density testing and is optimized using the backpropagation algorithm to minimize the mean square error between the predicted calibration offset and the actual calibration offset.

7. The system according to claim 1, characterized in that, Within the operating temperature range of -20℃ to 85℃, the nonlinear error does not exceed ±6ps, and the response delay is less than 1μs.

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