Distance image pickup element and distance image pickup apparatus

Abstract

This invention relates to a distance image capturing element and a distance image capturing device. The distance image capturing element includes: a pixel array having a plurality of pixels arranged in a two-dimensional matrix; and a pixel driving circuit driving the pixels. Each pixel has m selection transistors that output voltage signals corresponding to the amount of charge stored in m charge storage units. A first pixel and a second pixel are arranged in the pixel array. In an m×m merging operation, the first pixel outputs a summed value of a specific voltage signal corresponding to the amount of charge stored in one of the m charge storage units of the pixel. The second pixel does not output the summed value of the specific voltage signals. The control terminals of the selection transistors of the first pixel and the second pixel are connected to different selection signals.

Description

Technical Field

[0001] This invention relates to distance image capturing elements and distance image capturing devices.

[0002] This application claims priority based on Japanese Patent Application No. 2025-051799, filed in Japan on March 26, 2025, the contents of which are incorporated herein by reference. Background Technology

[0003] A distance image camera device has been developed that utilizes the known speed of light to determine the distance between the measuring device and the object based on the time of flight of light in space (measuring space) using the time of flight (hereinafter referred to as "TOF") method (for example, see Patent Document 1 (Japanese Patent No. 4235729)).

[0004] In such distance imaging devices, for example, distance imaging elements including photoelectric conversion elements such as photodiodes are used for imaging. Furthermore, in TOF-type distance imaging devices, distance imaging elements are known to include photoelectric conversion elements that convert incident light into electrical charge and to distribute and store the charge obtained from the photoelectric conversion elements in multiple charge storage units.

[0005] However, in distance imaging devices, a merging operation is sometimes performed by adding the pixels of the distance imaging element. In conventional distance imaging elements, for example, when pixels with four charge storage units are added in a (4×4) pixel manner, only four output signal lines are used. Figure 21G Reading is performed on one of the PIXOUT1 to PIXOUT4 shown. The readout of the pixel signal of each of the four charge accumulation sections requires the time of four rows of pixel rows in the pixel array arranged in a two-dimensional matrix. Summary of the Invention

[0006] The present invention was made to solve the above-mentioned problems, and its object is to provide a distance image imaging element and a distance image imaging device that can shorten the time required to read out the pixel signals of each of the multiple charge accumulation units in the merging operation.

[0007] The distance image imaging element of the present invention includes: a pixel array having a plurality of pixels arranged in a two-dimensional matrix; and a pixel driving circuit driving the pixels, wherein each pixel includes: a photoelectric conversion element that generates a charge corresponding to incident light; m charge storage units that store the charge, wherein m is an integer greater than or equal to 2; and m selection transistors that are respectively provided corresponding to the m charge storage units and output voltage signals corresponding to the amount of charge stored in the charge storage units. A first pixel and a second pixel are arranged in the pixel array. In an m×m merging operation, the first pixel outputs a combined sum of specific voltage signals corresponding to the amount of charge stored in one of the m charge storage units of the pixel, while the second pixel does not output the combined sum of the specific voltage signals. The control terminal of the specific selection transistor that outputs the sum of the specific voltage signals in the m selection transistors of the first pixel and the control terminal of the specific selection transistor in the second pixel are connected to different selection signals.

[0008] The distance image imaging device of the present invention comprises: a light source unit that illuminates a light pulse onto a subject; a light receiving unit having the aforementioned distance image imaging element; and a distance image processing unit that controls the pixel driving circuit to cause the charge storage unit to store the charge respectively, outputs a combined sum of voltage signals corresponding to the amount of charge stored by the charge storage unit, and calculates the distance to the subject based on the combined sum of the values ​​corresponding to the charge storage units respectively.

[0009] Invention Effects According to the present invention, the time required to read out the pixel signals of each of the multiple charge accumulation units in the merging operation can be shortened. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a configuration example of a distance image camera device common to all implementation methods.

[0011] Figure 2 This is a block diagram illustrating a configuration example of a distance image camera element common to implementation methods.

[0012] Figure 3 This is a diagram illustrating an example of pixel configuration in a pixel array common to implementation methods.

[0013] Figure 4 This is a diagram illustrating an example of a wiring image in a pixel array common to implementation methods.

[0014] Figure 5 This is a diagram showing an example of pixel A in the first embodiment.

[0015] Figure 6This is a diagram showing an example of pixel B in the first embodiment.

[0016] Figure 7 This is a diagram showing an example of pixel C in the first embodiment.

[0017] Figure 8 This is a diagram showing an example of pixel D in the first embodiment.

[0018] Figure 9 This is a diagram showing an example of pixel E in the first embodiment.

[0019] Figure 10 This is a diagram illustrating an example of a wiring image in a pixel array according to the first embodiment.

[0020] Figure 11 This is a timing diagram showing the driving of pixels during the merging operation in the first embodiment.

[0021] Figure 12 This is a diagram showing an example of pixel A in the second embodiment.

[0022] Figure 13 This is a diagram showing an example of pixel B in the second embodiment.

[0023] Figure 14 This is a diagram showing an example of pixel C in the second embodiment.

[0024] Figure 15 This is a diagram showing an example of pixel D in the second embodiment.

[0025] Figure 16 This is a diagram showing an example of pixel E in the second embodiment.

[0026] Figure 17 This is a diagram illustrating an example of a wiring image in a pixel array according to the second embodiment.

[0027] Figure 18 This is a timing diagram showing the driving of pixels during the merging operation in the second embodiment.

[0028] Figure 19 This is a diagram illustrating examples of pixel configurations that can be used in an implementation.

[0029] Figure 20 This diagram illustrates an example of a pixel configuration that is not feasible in the implementation method.

[0030] Figure 21A It is a diagram used to illustrate previous pixels.

[0031] Figure 21B It is a diagram used to illustrate previous pixels.

[0032] Figure 21C It is a diagram used to illustrate previous pixels.

[0033] Figure 21D It is a diagram used to illustrate previous pixels.

[0034] Figure 21E It is a diagram used to illustrate previous pixels.

[0035] Figure 21F It is a diagram used to illustrate previous pixels.

[0036] Figure 21G It is a diagram used to illustrate previous pixels.

[0037] Explanation of reference numerals in the attached figures 1... distance to image camera element 2... Light source section 3...Light-receiving section 10... pixels 11...pixel array 12...pixel driving circuit 100… distance image camera device CS, CS1, CS2, CS3, CS4... Charge accumulation section FD, FD1, FD2, FD3, FD4... Floating diffuser section FDC1, FDC2, FDC3, FDC4... Floating diffuser section GT, GT1, GT2, GT3, GT4... Transmission transistors DT... Charge discharge transistor PD... photoelectric conversion element PO...light pulse RL...reflected light RS, RS1, RS2, RS3, RS4... control transistors RST, RST1, RST2, RST3, RST4... Reset transistor SF, SF1, SF2, SF3, SF4... source follower transistors SLT, SLT1, SLT2, SLT3, SLT4... Select transistor PIXOUT...output line SL, SL1, SL2, SL3, SL4... Control signals (selection signals) SL1A, SL2B, SL3C, SL4D... Control signals (selection signals) SLA, SLB, SLC, SLD... control signals (selection signals) RT, RT1, RT2, RT3, RT4... Control signals (control wiring) Detailed Implementation

[0038] Hereinafter, the distance image capturing element and distance image capturing device according to the embodiments will be described with reference to the accompanying drawings.

[0039] (Regarding common aspects of the implementation method) Figure 1 This is a block diagram illustrating a configuration example of a distance image capturing device common to all embodiments. The distance image capturing device 100, for example, includes a light source unit 2, a light receiving unit 3, and a distance image processing unit 4. Figure 1 Also shown is the object, namely the subject OB, whose distance is measured in the distance imaging device 100.

[0040] The light source unit 2 irradiates a light pulse PO onto the subject OB according to the control from the distance image processing unit 4. The light source unit 2 is, for example, a surface-emitting semiconductor laser module such as a vertically oriented surface-emitting laser (VCSEL). The light source unit 2 includes a light source device 21 and a diffuser plate 22.

[0041] The light source device 21 is a laser light source that emits a near-infrared wavelength (e.g., a wavelength range of 850 nm to 940 nm) that forms a light pulse PO that irradiates the subject OB. The light source device 21 is, for example, a semiconductor laser light-emitting element. The light source device 21 emits pulsed laser light according to the control from the measurement and control unit 43.

[0042] The diffuser plate 22 is an optical component that diffuses the near-infrared laser emitted by the light source device 21 into a surface wide enough to irradiate the subject OB. The pulsed laser light diffused by the diffuser plate 22 is emitted as a light pulse PO and irradiates the subject OB existing in the measurement space.

[0043] The light-receiving unit 3 receives the reflected light RL from the light pulse PO reflected by the subject OB and outputs a pixel signal corresponding to the received reflected light RL. The light-receiving unit 3 includes a lens 31 and a distance image imaging element 1.

[0044] Lens 31 is an optical lens that guides the incident reflected light RL to the distance image camera element 1. Lens 31 directs the incident reflected light RL toward the distance image camera element 1, so that the pixels in the light-receiving area of ​​the distance image camera element 1 are illuminated (incidentally).

[0045] The distance image capturing element 1 is a capturing element used in the distance image capturing device 100.

[0046] The distance image processing unit 4 controls the distance image capturing device 100 to calculate the distance to the subject OB. Based on the amount of charge stored in each of the charge storage units CS, the distance image processing unit 4 measures the distance to the subject OB existing in the measurement space, and uses this distance as the measurement distance.

[0047] In addition, the distance image processing unit 4 includes a timing control unit 41, a distance calculation unit 42, and a measurement control unit 43.

[0048] The timing control unit 41, under the control of the measurement control unit 43, controls the timing of various control signals required for measurement. These control signals include, for example, signals controlling the illumination of the light pulse PO, signals distributing and accumulating reflected light RL in multiple charge accumulation units CS, and signals controlling the number of accumulations per frame. The number of accumulations refers to the number of times the process of distributing and accumulating charge in the charge accumulation units CS is repeated; it is a predetermined number of distributions within the frame period. The product of this number of accumulations and the time amplitude (accumulation time amplitude) during each distribution and charge accumulation process constitutes the exposure time.

[0049] The distance calculation unit 42 outputs distance information calculated to the subject OB based on the pixel signal output from the distance image imaging element 1. The distance calculation unit 42 calculates the delay time from the illumination light pulse PO to the reception of the reflected light RL based on the amount of charge stored in the multiple charge storage units CS. The distance calculation unit 42 calculates the distance to the subject OB based on the calculated delay time.

[0050] The distance calculation unit 42 calculates the delay time Td, for example, using the following equation (1). Furthermore, in equation (1), it is assumed that the amount of charge corresponding to the external light component included in the charge stored in the charge storage units CS1 and CS2 is the same as the amount of charge stored in the charge storage unit CS3.

[0051] Td = To × (Q2 - Q3) / (Q1 + Q2 - 2 × Q3) …… (1) Where To is the duration of the irradiation pulse PO.

[0052] Q1 is the amount of charge stored in the charge storage section CS1.

[0053] Q2 is the amount of charge stored in the charge storage section CS2.

[0054] Q3 is the amount of charge stored in the charge storage section CS3.

[0055] In the near-field light-receiving pixel, the distance calculation unit 42 calculates the round-trip distance to the subject OB by multiplying the delay time Td obtained by equation (1) by the speed of light. Then, the distance calculation unit 42 measures the distance to the subject OB by setting the calculated round-trip distance to 1 / 2.

[0056] The measurement control unit 43 controls the timing control unit 41. For example, the measurement control unit 43 sets the cumulative number of times and the accumulation time in one frame, and controls the timing control unit 41 so that the camera is captured according to the set content.

[0057] With this configuration, in the distance image camera device 100, the light receiving unit 3 receives the reflected light RL after the near-infrared light pulse PO irradiated by the light source unit 2 to the subject OB is reflected by the subject OB, and the distance image processing unit 4 outputs distance information (distance image) obtained by measuring the distance to the subject OB.

[0058] Figure 2 This is a block diagram illustrating a configuration example of a distance image imaging element common to all implementations. In the pixel array 11, a plurality of pixels 10 are arranged in a two-dimensional matrix.

[0059] The pixel 10 of the pixel array 11 includes, for example, a photoelectric conversion element PD, a plurality of charge storage units CS corresponding to the photoelectric conversion element PD, and components for distributing charge to each charge storage unit CS. The detailed configuration of the pixel 10 in this embodiment will be described later with reference to the accompanying drawings.

[0060] The pixel driving circuit 12 drives the pixel 10 by controlling the output of control signals (control signals GD, G1~G4, RT1~RT4, RTC1~RTC4, SL1~SL4, ...), and distributes and accumulates charge to the charge accumulation unit CS at a predetermined accumulation timing synchronized with the illumination of the light pulse PO. After repeating this accumulation process a number of times per frame, the pixel driving circuit 12 outputs a pixel signal corresponding to the amount of charge accumulated during the readout period.

[0061] Furthermore, the pixel driving circuit 12 controls the output of the control signal in the Binning mode, so that the output is a pixel signal obtained by adding (binding and adding) multiple pixels 10 together.

[0062] The following example illustrates the case where a pixel unit GU1, consisting of a 4-pixel × 4-pixel matrix, is used as the unit for merging. However, this implementation is not limited to this; the same implementation can be applied when m pixels × m pixels are used as the unit for merging. Here, m is an integer of 2 or more, and the number of charge storage units CS provided in one pixel is m or less.

[0063] Figure 3 This is a diagram illustrating an example of pixel configuration in a pixel array common to implementation methods.

[0064] The figure shows an example of pixel configuration in pixel unit GU1, which consists of a 4-pixel × 4-pixel matrix as the unit for merging. Pixel array 11 is formed by repeating pixel unit GU1.

[0065] In the following description, the horizontal axis will be set as the X-axis and the vertical axis as the Y-axis when viewing the pixel surface of pixel unit GU1 from above. Furthermore, the pixel configuration will be explained using position coordinates (x, y) with the top-left corner of pixel unit GU1 as the origin (0, 0), the right direction as the positive X-axis direction, and the bottom direction as the positive Y-axis direction.

[0066] like Figure 3 As shown, the pixel array 11 has five types of pixels 10, from pixel A to pixel E. Pixel A corresponds to pixel 10-A of type A, described later. Pixel B corresponds to pixel 10-B of type B, described later. Pixel C corresponds to pixel 10-C of type C, described later. Pixel D corresponds to pixel 10-D of type D, described later. Pixel E corresponds to pixel 10-E of type E, described later.

[0067] Pixels A to D of the five types of pixels 10 are arranged along a slanted straight line corresponding to the diagonal of the quadrilateral formed by the matrix of 4 pixels × 4 pixels in pixel unit GU1, and pixel E is arranged in other positions.

[0068] Specifically, pixel A is positioned at coordinate (1,1) in pixel unit GU1. Pixel B is positioned at coordinate (2,2) in pixel unit GU1. Pixel C is positioned at coordinate (3,3) in pixel unit GU1. Pixel D is positioned at coordinate (4,4) in pixel unit GU1. Pixel E is positioned in pixel unit GU1 at the positions where pixels A through D are not positioned, i.e., at coordinates (1,2), (1,3), (1,4), (2,1), (2,3), (2,4), (3,1), (3,2), (3,4), (4,1), (4,2), (4,3).

[0069] Figure 4 This is a diagram illustrating an example of a wiring image in a pixel array common to implementation methods.

[0070] In pixel unit GU1 of pixel array 11 shown in the figure, and Figure 3Similarly, pixel A is positioned at coordinates (1,1). Pixel B is positioned at coordinates (2,2). Pixel C is positioned at coordinates (3,3). Pixel D is positioned at coordinates (4,4). Pixel E is positioned in pixel unit GU1 at a different location than where pixels A through D are located.

[0071] In this diagram, wiring LN1 represents the wiring of floating diffuser FDC1, and wiring LN2 represents the wiring of floating diffuser FDC2. Additionally, wiring LN3 represents the wiring of floating diffuser FDC3, and wiring LN4 represents the wiring of floating diffuser FDC4.

[0072] The floating diffuser FDC (FDC1~FDC4) is a signal line that outputs the added charge during the merging operation.

[0073] More specifically, the floating diffusion unit FDC1 is a signal line that, during the merging operation, outputs a pixel signal corresponding to the sum of the charge accumulated in the charge accumulation unit CS1 for each pixel constituting pixel unit GU1. The floating diffusion unit FDC2 is a signal line that, during the merging operation, outputs a pixel signal corresponding to the sum of the charge accumulated in the charge accumulation unit CS2 for each pixel constituting pixel unit GU1. The floating diffusion unit FDC3 is a signal line that, during the merging operation, outputs a pixel signal corresponding to the sum of the charge accumulated in the charge accumulation unit CS3 for each pixel constituting pixel unit GU1. The floating diffusion unit FDC4 is a signal line that, during the merging operation, outputs a pixel signal corresponding to the sum of the charge accumulated in the charge accumulation unit CS4 for each pixel constituting pixel unit GU1.

[0074] As shown in the figure, by routing the floating diffuser FDC (FDC1~FDC4) with routing LN1~routing LN4, the floating diffuser FDC (FDC1~FDC4) can be shared by 4 pixels × 4 pixels in the pixel unit GU1, and the charge after addition in the merging operation can be output.

[0075] (Regarding previous pixels) Here, Figure 21 is used ( Figures 21A to 21G The previous pixels are explained. Figure 21 is a diagram used to explain the previous pixels.

[0076] Figure 21A An example of pixel 10-A, which is a type A pixel (pixel A) in the prior art, is shown.

[0077] like Figure 21AAs shown, pixel 10-A has one photoelectric conversion element PD, four transmission transistors GT (GT1 to GT4), one charge discharge transistor DT, four reset transistors RST (RST1 to RST4), four capacitors CAP (CAP1 to CAP4), four source follower transistors SF (SF1 to SF4), four select transistors SLT (SLT1 to SLT4), and four control transistors RS (RS1 to RS4).

[0078] A photoelectric conversion element (PD) is an embedded photodiode that converts incident light into photoelectric value, generates a charge corresponding to the incident light, and stores the generated charge. In this embodiment, the incident light enters from the space of the object being measured. The anode terminal of the photoelectric conversion element (PD) is connected to a grounded power supply line, and the cathode terminal is connected to the source terminal of the transmission transistors GT (GT1 to GT4).

[0079] In pixel A, the charge generated by the photoelectric conversion element PD through photoelectric conversion of incident light is distributed to four charge storage units CS (CS1 to CS4), and the voltage signals (pixel signals) corresponding to the amount of charge distributed are output to the output line PIXOUT1.

[0080] The pixel driving circuit 12, under the control of the measurement and control unit 43, synchronously stores the charge generated in the photoelectric conversion element PD according to the frame period and the illumination of the light pulse PO. This charge is then alternately stored in the charge storage units CS1, CS2, CS3, and CS4 by supplying storage control signals G (G1 to G4) to the transmission transistors GT1, GT2, GT3, and GT4 at their respective timings.

[0081] Here, the charge accumulation section CS is composed of a floating diffusion section FD and a capacitor CAP. That is, the charge accumulation section CS1 is composed of a floating diffusion section FD1 and a capacitor CAP1, and the charge accumulation section CS2 is composed of a floating diffusion section FD2 and a capacitor CAP2. In addition, the charge accumulation section CS3 is composed of a floating diffusion section FD3 and a capacitor CAP3, and the charge accumulation section CS4 is composed of a floating diffusion section FD4 and a capacitor CAP4.

[0082] The floating diffusion section FD (FD1~FD4) is the wiring between the transmission transistor GT (GT1~GT4) and the source follower transistor SF (SF1~SF4).

[0083] Capacitors CAP (CAP1~CAP4) are, for example, CMOS capacitors.

[0084] The transfer transistors GT (GT1 to GT4) are turned on (ON state) by the control signal G (G1 to G4), so that the charge generated by the photoelectric conversion element PD is stored in the charge storage section CS (CS1 to CS4), and the charge is transferred to the source follower transistors SF (SF1 to SF4).

[0085] The source follower transistor SF (SF1 to SF4) is a transistor that converts charge into an electrical signal and outputs the electrical signal (voltage) corresponding to the charge stored in the charge storage section CS (CS1 to CS4) to the selection transistor SLT (SLT1 to SLT4).

[0086] Select transistor SLT (SLT1~SLT4) selects the readout of the electrical signal of pixel 10. Select transistor SLT (SLT1~SLT4) enters the ON state through control signal SL (SL1~SL4), and outputs the pixel value (output signal) to output line PIXOUT1.

[0087] The reset transistors RST (RST1 to RST4) correspond to the charge storage sections CS (CS1 to CS4) respectively, resetting the charge storage sections CS (CS1 to CS4) to the specified reset potential supplied from the power supply line VDDPIX. The reset transistors RST (RST1 to RST4) enter the ON state through the control signal RT (RT1 to RT4), resetting the charge storage sections CS (CS1 to CS4) to the reset potential supplied from the power supply line VDDPIX via the control transistors RS (RS1 to RS4) described later.

[0088] The control transistors RS (RS1 to RS4) are the control transistors RS corresponding to the reset transistors RST (RST1 to RST4), and are connected between the reset transistors RST (RST1 to RST4) and the power supply line VDDPIX. The wiring between the control transistors RS (RS1 to RS4) and the reset transistors RST (RST1 to RST4) functions as a floating diffuser FDC (FDC1 to FDC4) that outputs the added charge in the merge mode.

[0089] In pixel A, the control terminal of control transistor RS1 (RS1 to RS4) is connected to the control signal RTC1 (control wiring) that controls the conduction state of control transistor RS1. In addition, the other three control transistors RS, namely control transistors RS2 to RS4 other than control transistor RS1, are connected to the power line VSSIX in a way that keeps control transistor RS in the off state.

[0090] Furthermore, in pixel A, the floating diffuser FDC1 enters the ON state through the wiring of the control signal RTC1 and is reset to the reset potential supplied from the power line VDDPIX.

[0091] The charge discharge transistor DT is connected between the photoelectric conversion element PD and the power line VDDPIX, discharging charge from the photoelectric conversion element PD. The charge discharge transistor DT enters the conducting state through the control signal GD, causing the charge generated in the photoelectric conversion element PD to flow to the power line VDDPIX for discharge (charge elimination).

[0092] In addition, the transfer transistor GT (GT1~GT4), charge discharge transistor DT, reset transistor RST (RST1~RST4), source follower transistor SF (SF1~SF4), select transistor SLT (SLT1~SLT4), and control transistor RS (RS1~RS4) are NMOS (N-channel Metal Oxide Semiconductor) transistors.

[0093] Figure 21B An example of pixel 10-B, which is a type B pixel (pixel B), is shown in this embodiment.

[0094] Figure 21B The basic structure of pixel B shown is the same as that of pixel A above, but the connection of the control signal of the control transistor RS (RS1~RS4) and the output line of the voltage signal (pixel signal) are different.

[0095] In pixel B, the control terminal of control transistor RS2, one of the four control transistors RS (RS1 to RS4), is connected to the control signal RTC2 (control wiring) that controls the conduction state of control transistor RS2. The remaining three control transistors RS, namely control transistors RS1, RS3, and RS4, are connected to the power line VSSIX in a manner that keeps control transistor RS in the off state.

[0096] Furthermore, in pixel B, the floating diffuser FDC2 enters the ON state through the wiring of the control signal RTC2 and is reset to the reset potential supplied from the power line VDDPIX.

[0097] In addition, in pixel B, the selection transistor SLT (SLT1 to SLT4) enters the ON state through the control signal SL (SL1 to SL4), and outputs the pixel value (output signal) to the output line PIXOUT2.

[0098] Figure 21C An example of pixel 10-C, which is a pixel of type C (pixel C) in this embodiment, is shown.

[0099] Figure 21C The basic structure of pixel C shown is the same as that of pixel A above, but the connection of the control signal of the control transistor RS (RS1 to RS4) and the output line of the voltage signal (pixel signal) are different.

[0100] In pixel C, the control terminal of control transistor RS3, one of the four control transistors RS (RS1 to RS4), is connected to the control signal RTC3 (control wiring) that controls the conduction state of control transistor RS3. The remaining three control transistors RS, namely control transistors RS1 to RS2 and RS4, are connected to the power line VSSIX in a manner that keeps control transistor RS in the off state.

[0101] Furthermore, in pixel C, the floating diffuser FDC3 enters the ON state through the wiring of the control signal RTC3 and is reset to the reset potential supplied from the power line VDDPIX.

[0102] In addition, in pixel C, the selection transistor SLT (SLT1 to SLT4) enters the ON state through the control signal SL (SL1 to SL4), and outputs the pixel value (output signal) to the output line PIXOUT3.

[0103] Figure 21D An example of pixel 10-D, which is a pixel of type D (pixel D) in this embodiment, is shown.

[0104] Figure 21D The basic structure of pixel D shown is the same as that of pixel A above, but the connection of the control signal of the control transistor RS (RS1 to RS4) and the output line of the voltage signal (pixel signal) are different.

[0105] In pixel D, the control terminal of control transistor RS4, one of the four control transistors RS (RS1 to RS4), is connected to the control signal RTC4 (control wiring) that controls the conduction state of control transistor RS4. The remaining three control transistors RS, namely control transistors RS1 to RS3 other than control transistor RS4, are connected to the power line VSSIX in a manner that keeps control transistor RS in the off state.

[0106] Furthermore, in pixel D, the floating diffuser FDC4 enters the ON state through the wiring of the control signal RTC4 and is reset to the reset potential supplied from the power line VDDPIX.

[0107] In addition, in pixel D, the selection transistor SLT (SLT1 to SLT4) is turned on by the control signal SL (SL1 to SL4), and the pixel value (output signal) is output to the output line PIXOUT4.

[0108] Figure 21E An example of pixel 10-E, which is a pixel of type E (pixel E) in this embodiment, is shown.

[0109] Figure 21E The basic structure of pixel E shown is the same as that of pixel A mentioned above, but the connection of the control signal of the control transistor RS (RS1 to RS4) and the output line of the voltage signal (pixel signal) are different.

[0110] In pixel E, all four control transistors RS (RS1 to RS4) are connected to the power line VSSIX in a manner that keeps the control transistors RS in the off state.

[0111] In addition, in pixel E, the selection transistor SLT (SLT1 to SLT4) is turned on by the control signal SL (SL1 to SL4), and the pixel value (output signal) is output to any output line among the output lines PIXOUT1 to PIXOUT4.

[0112] The decision of which output line pixel E outputs its pixel value (output signal) to depends on the row in pixel unit GU1 that contains pixel E.

[0113] In the existing pixel array, the pixel configuration is Figure 3 The configuration shown is, and the wiring is Figure 4 In the scenario shown, pixel E, located in the same row as pixel A, outputs its pixel value (output signal) to output line PIXOUT1. Pixel E, located in the same row as pixel B, outputs its pixel value (output signal) to output line PIXOUT2. Pixel E, located in the same row as pixel C, outputs its pixel value (output signal) to output line PIXOUT3. Pixel E, located in the same row as pixel D, outputs its pixel value (output signal) to output line PIXOUT4.

[0114] Thus, for each of the four pixel types (pixels A through D), the positions of the control transistors RS (RS1 through RS4) connected to the control signals RTC (RTC1 through RTC4) are different. Furthermore, for pixel E, all four control transistors RS (RS1 through RS4) are fixed in the off state.

[0115] Figure 21FThis is a diagram illustrating an example of a wiring pattern in a conventional pixel array. In this diagram, i represents the row number.

[0116] In pixel unit GU1 of pixel array 11 shown in the figure, pixel A is located at the left end of the i-th row, i.e., at coordinate (1,1). Pixel B is located at the second position from the left in the (i+1)-th row, i.e., at coordinate (2,2). Pixel C is located at the third position from the left in the (i+2)-th row, i.e., at coordinate (3,3). Pixel D is located at the fourth position from the left in the (i+3)-th row, i.e., at coordinate (4,4). Pixel E is located in pixel unit GU1 at a different position than pixels A through D.

[0117] In this figure, the control signals SL (SL1~SL4) that control the selection transistors SLT (SLT1~SLT4) set in each of the pixels in the i-th row are set as control signals SL1[i], SL2[i], SL3[i], and SL4[i].

[0118] Set the control signals SL (SL1~SL4) that control the selection transistors SLT (SLT1~SLT4) set in each of the pixels configured in the (i+1)th row to control signals SL1[i+1], SL2[i+1], SL3[i+1], and SL4[i+1].

[0119] Set the control signals SL (SL1~SL4) that control the selection transistors SLT (SLT1~SLT4) set in each of the pixels configured in the (i+2)th row to control signals SL1[i+2], SL2[i+2], SL3[i+2], and SL4[i+2].

[0120] Set the control signals SL (SL1~SL4) that control the selection transistors SLT (SLT1~SLT4) set in each of the pixels configured in the (i+3)th row to control signals SL1[i+3], SL2[i+3], SL3[i+3], and SL4[i+3].

[0121] The output signals PIXOUT1 to PIXOUT4 are input to the selection circuit CSEL. The selection circuit CSEL controls the output of the output signals of the output lines PIXOUT1 to PIXOUT4 according to the control signals CSL (CSL1 to CSL4).

[0122] In the selection circuit CSEL, the pixel driving circuit 12 activates the control signals CSL (CSL1 to CSL4), thereby outputting the output signal of the output line PIXOUT corresponding to the activated control signal CSL. That is, activating the control signal CSLn outputs the output signal of the output line PIXOUTn. When the control signal CSLn is deactivated (Reset), the output signal of the output line PIXOUTn is reset. The suffix 'n' in the output line PIXOUT is an integer from 1 to 4.

[0123] Figure 21G This is a timing diagram showing the driving of previous pixels. In this diagram, the horizontal axis represents time, and the vertical axis represents the waveform of the control signal.

[0124] The control signals, from top to bottom, are: control signals G1~G4, control signal GD, control signals RT1[i:i+3], RT2[i:i+3], RT3[i:i+3], RT4[i:i+3], control signals RTC1~RTC4, control signal SLn[i+k], output signals PIXOUT1~PIXOUT4, and control signals CSL1~CSL4. In the control signals SL, the suffix n is an integer from 1 to 4, and k is an integer from 0 to 3. i represents the row number.

[0125] During the merging operation, the pixel driving circuit 12 first fixes the control signal RT to the H (high) state and fixes the reset transistors RST (RST1 to RST4) of all pixels in the pixel unit GU1 to the on state. Additionally, the pixel driving circuit 12 fixes the control signals SL2[i], SL3[i], and SL4[i] to the L (low) state. The pixel driving circuit 12 also fixes the control signals SL1[i+1], SL3[i+1], and SL4[i+1] to the L state. Furthermore, the pixel driving circuit 12 sets the control signals CSL (CSL1 to CSL4) to the L state and resets the output of the selection circuit CSEL.

[0126] During the period up to time T1, the pixel driving circuit 12 turns on the transfer transistors GT1 to GT4 via control signals G1 to G4, causing the charge storage section CS1 to accumulate charge. Furthermore, while the pixel driving circuit 12 is accumulating charge in the charge storage section CS1 to CS4, it turns off the charge discharge transistor DT via control signal GD.

[0127] At time T1, the pixel driving circuit 12 sets the control signal SL1[i] to state H and the control signal CSL1 to state H (Active), and outputs the pixel value (output signal) corresponding to the charge stored in the charge storage section CS1, which is calculated by combining the values ​​from pixel A to the output line PIXOUT1.

[0128] At time T2, the pixel driving circuit 12 sets the control signal RTC1 to state H, which resets the charge stored in the charge storage section CS1 in the pixel unit GU1.

[0129] At time T1, the pixel driving circuit 12 sets the control signal SL1[i] to state H and the control signal CSL1 to state H, and outputs the pixel value (output signal) corresponding to the charge Q1 accumulated in the charge storage section CS1, which is calculated by combining the pixels from pixel A to the output line PIXOUT1.

[0130] At time T2, the pixel driving circuit 12 sets the control signal RTC1 to state H, which resets the charge stored in the charge storage section CS1 in the pixel unit GU1.

[0131] At time T3, the pixel driving circuit 12 sets the control signal SL1[i] to the L state and the control signal SL2[i+1] to the H state, and outputs the pixel value (output signal) corresponding to the charge Q2 accumulated in the charge accumulation section CS2, which is calculated by combining the pixel B, to the output line PIXOUT1.

[0132] At time T4, the pixel driving circuit 12 sets the control signal RTC2 to state H, which resets the charge stored in the charge storage section CS2 in the pixel unit GU1.

[0133] At time T5, the pixel driving circuit 12 sets the control signal SL2[i+1] to the L state and the control signal SL3[i+2] to the H state, and outputs the pixel value (output signal) corresponding to the charge Q3 accumulated in the charge accumulation section CS3, which is calculated by combining the pixel C to the output line PIXOUT1.

[0134] At time T6, the pixel driving circuit 12 sets the control signal RTC3 to the H state, which resets the charge stored in the charge storage section CS3 in the pixel unit GU1.

[0135] At time T7, the pixel driving circuit 12 sets the control signal SL3[i+2] to the L state and the control signal SL4[i+3] to the H state, and outputs the pixel value (output signal) corresponding to the charge Q4 accumulated in the charge accumulation section CS4, which is calculated by combining the pixel D to the output line PIXOUT1.

[0136] At time T8, the pixel driving circuit 12 sets the control signal RTC4 to state H, which resets the charge stored in the charge storage section CS4 in the pixel unit GU1.

[0137] At time T9, the pixel driving circuit 12 sets the control signal RTC4 to the L state.

[0138] Thus, in the previous merging operation, the output signal was read out using only one of the four output lines (PIXOUT1) from PIXOUT1 to PIXOUT4. Therefore, in order to read out the four output signals corresponding to the charges Q1 to Q4 stored in the charge storage sections CS1 to CS4, four lines of readout time are required.

[0139] (Regarding the first implementation method) Here, the first embodiment will be described. In this embodiment, the control signals SL (SL1 to SL4) for each of pixels A, B, C, and D can be controlled on a per-pixel basis.

[0140] Specifically, the previous four control signals SL (SL1 to SL4) are replaced with 16 control signals: SL1A to SL4A for pixel A, SL1B to SL4B for pixel B, SL1C to SL4C for pixel C, and SL1D to SL4D for pixel D. This allows for the selection of the selection transistor SLT to be controlled for each column.

[0141] Furthermore, the configuration of pixels 10 (pixels A to E) in the first embodiment is the same as that of conventional pixels (pixels A to E), except for the connection of the control signal SL.

[0142] Figure 5 This is a diagram showing an example of pixel A in the first embodiment.

[0143] like Figure 5 As shown, the basic structure of pixel A in the first embodiment is the same as that of conventional pixel A, but the connection of the control signal (selection signal) of the selection transistor SLT (SLT1 to SLT4) is different.

[0144] In pixel A of the first embodiment, the control terminal of selection transistor SLT1 is connected to control signal SL1A. The control terminal of selection transistor SLT2 is connected to control signal SL2A. The control terminal of selection transistor SLT3 is connected to control signal SL3A. The control terminal of selection transistor SLT4 is connected to control signal SL4A.

[0145] Figure 6 This is a diagram showing an example of pixel B in the first embodiment.

[0146] like Figure 6 As shown, the basic structure of pixel B in the first embodiment is the same as that of conventional pixel B, but the connection of the control signal (selection signal) of the selection transistor SLT (SLT1 to SLT4) is different.

[0147] In pixel B of the first embodiment, the control terminal of selection transistor SLT1 is connected to control signal SL1B. The control terminal of selection transistor SLT2 is connected to control signal SL2B. The control terminal of selection transistor SLT3 is connected to control signal SL3B. The control terminal of selection transistor SLT4 is connected to control signal SL4B.

[0148] Figure 7 This is a diagram showing an example of pixel C in the first embodiment.

[0149] like Figure 7 As shown, the basic structure of pixel C in the first embodiment is the same as that of conventional pixel C, but the connection of the control signal (selection signal) of the selection transistor SLT (SLT1 to SLT4) is different.

[0150] In pixel C of the first embodiment, the control terminal of selection transistor SLT1 is connected to control signal SL1C. The control terminal of selection transistor SLT2 is connected to control signal SL2C. The control terminal of selection transistor SLT3 is connected to control signal SL3C. The control terminal of selection transistor SLT4 is connected to control signal SL4C.

[0151] Figure 8 This is a diagram showing an example of pixel D in the first embodiment.

[0152] like Figure 8 As shown, the basic structure of pixel D in the first embodiment is the same as that of conventional pixel D, but the connection of the control signal (selection signal) of the selection transistor SLT (SLT1 to SLT4) is different.

[0153] In pixel D of the first embodiment, the control terminal of selection transistor SLT1 is connected to control signal SL1D. The control terminal of selection transistor SLT2 is connected to control signal SL2D. The control terminal of selection transistor SLT3 is connected to control signal SL3D. The control terminal of selection transistor SLT4 is connected to control signal SL4D.

[0154] Figure 9 This is a diagram showing an example of pixel E in the first embodiment.

[0155] like Figure 9As shown, the basic structure of pixel E in the first embodiment is the same as that of conventional pixel E, but the connection of the control signal (selection signal) of the selection transistor SLT (SLT1 to SLT4) is different.

[0156] In pixel E of the first embodiment, the control terminal of the selection transistor SLT1 is connected to any one of the control signals SL1A to SL1D. The control signal to which the selection transistor SLT1 is connected depends on the column in pixel unit GU1 where pixel E is located. The selection transistor SLT1 of pixel E located in the same column as pixel A is connected to control signal SL1A. The selection transistor SLT1 of pixel E located in the same column as pixel B is connected to control signal SL1B. The selection transistor SLT1 of pixel E located in the same column as pixel C is connected to control signal SL1C. The selection transistor SLT1 of pixel E located in the same column as pixel D is connected to control signal SL1D.

[0157] In pixel E of the first embodiment, the control terminal of the selection transistor SLT2 is connected to any one of the control signals SL2A to SL2D. The control signal to which the selection transistor SLT2 is connected depends on the column in pixel unit GU1 where pixel E is located. The selection transistor SLT2 of pixel E located in the same column as pixel A is connected to control signal SL2A. The selection transistor SLT2 of pixel E located in the same column as pixel B is connected to control signal SL2B. The selection transistor SLT2 of pixel E located in the same column as pixel C is connected to control signal SL2C. The selection transistor SLT2 of pixel E located in the same column as pixel D is connected to control signal SL2D.

[0158] In pixel E of the first embodiment, the control terminal of the selection transistor SLT3 is connected to any one of the control signals SL3A to SL3D. The control signal to which the selection transistor SLT3 is connected depends on the column in pixel unit GU1 where pixel E is located. The selection transistor SLT3 of pixel E located in the same column as pixel A is connected to control signal SL3A. The selection transistor SLT3 of pixel E located in the same column as pixel B is connected to control signal SL3B. The selection transistor SLT3 of pixel E located in the same column as pixel C is connected to control signal SL3C. The selection transistor SLT3 of pixel E located in the same column as pixel D is connected to control signal SL3D.

[0159] In pixel E of the first embodiment, the control terminal of the selection transistor SLT4 is connected to any one of the control signals SL4A to SL4D. The control signal to which the selection transistor SLT4 is connected depends on the column in pixel unit GU1 where pixel E is located. The selection transistor SLT4 of pixel E located in the same column as pixel A is connected to control signal SL4A. The selection transistor SLT4 of pixel E located in the same column as pixel B is connected to control signal SL4B. The selection transistor SLT4 of pixel E located in the same column as pixel C is connected to control signal SL4C. The selection transistor SLT4 of pixel E located in the same column as pixel D is connected to control signal SL4D.

[0160] Figure 10 This is a diagram illustrating an example of a wiring pattern in a pixel array according to the first embodiment. In this diagram, i represents the row number.

[0161] In pixel unit GU1 of pixel array 11 shown in the figure, pixel A is located at the left end of the i-th row, i.e., at coordinate (1,1). Pixel B is located at the second position from the left in the (i+1)-th row, i.e., at coordinate (2,2). Pixel C is located at the third position from the left in the (i+2)-th row, i.e., at coordinate (3,3). Pixel D is located at the fourth position from the left in the (i+3)-th row, i.e., at coordinate (4,4). Pixel E is located in pixel unit GU1 at a different position than pixels A through D.

[0162] The wiring of the pixel array 11 in the first embodiment is basically the same as that of a conventional pixel array, but the wiring of the control signal SL is different.

[0163] The pixels configured in the i-th row have the following wiring: control signals SL1A[i] to SL4A[i] for the selection transistor SLT (SLT1 to SLT4) of pixel A, control signals SL1B[i] to SL4B[i] for the selection transistor SLT (SLT1 to SLT4) of pixel B, control signals SL1C[i] to SL4C[i] for the selection transistor SLT (SLT1 to SLT4) of pixel C, and control signals SL1D[i] to SL4D[i] for the selection transistor SLT (SLT1 to SLT4) of pixel D.

[0164] In the pixel configured in row (i+1), there are control signals SL1A[i+1] to SL4A[i+1] for the selection transistor SLT (SLT1 to SLT4) of pixel A, control signals SL1B[i+1] to SL4B[i+1] for the selection transistor SLT (SLT1 to SLT4) of pixel B, control signals SL1C[i+1] to SL4C[i+1] for the selection transistor SLT (SLT1 to SLT4) of pixel C, and control signals SL1D[i+1] to SL4D[i+1] for the selection transistor SLT (SLT1 to SLT4) of pixel D.

[0165] The pixels configured in row (i+2) have the following wiring: control signals SL1A[i+2] to SL4A[i+2] for the selection transistor SLT (SLT1 to SLT4) of pixel A, control signals SL1B[i+2] to SL4B[i+2] for the selection transistor SLT (SLT1 to SLT4) of pixel B, control signals SL1C[i+2] to SL4C[i+2] for the selection transistor SLT (SLT1 to SLT4) of pixel C, and control signals SL1D[i+2] to SL4D[i+2] for the selection transistor SLT (SLT1 to SLT4) of pixel D.

[0166] The pixels configured in row (i+3) have the following wiring: control signals SL1A[i+3] to SL4A[i+3] for the selection transistor SLT (SLT1 to SLT4) of pixel A, control signals SL1B[i+3] to SL4B[i+3] for the selection transistor SLT (SLT1 to SLT4) of pixel B, control signals SL1C[i+3] to SL4C[i+3] for the selection transistor SLT (SLT1 to SLT4) of pixel C, and control signals SL1D[i+3] to SL4D[i+3] for the selection transistor SLT (SLT1 to SLT4) of pixel D.

[0167] Figure 11 This is a timing diagram showing the pixel driving during the merging operation in the first embodiment. In this diagram, the horizontal axis represents time, and the vertical axis represents the waveform of the control signals. The control signals, from top to bottom, are control signals G1~G4, control signal GD, control signals RT1[i:i+3], RT2[i:i+3], RT3[i:i+3], RT4[i:i+3], control signals RTC1~RTC4, control signal SLnX[i+k], output signals PIXOUT1~PIXOUT4, and control signals CSL1~CSL4. In the control signals SL, the suffix n is an integer from 1 to 4, X is any one of A to E, and k is an integer from 0 to 3. i represents the row number.

[0168] During the merging operation, the pixel driving circuit 12 first fixes the control signal RT to the H (high level) state and fixes the reset transistors RST (RST1~RST4) of all pixels in the pixel unit GU1 to the on state.

[0169] In addition, the pixel driving circuit 12 fixes the control signals SL, which are different from the control signal SL1A[i], namely the control signals SL2A[i]~SL4A[i], SL1B[i]~SL4B[i], SL1C[i]~SL4C[i], and SL1D[i]~SL4D[i] to the L state in the i-th row.

[0170] In addition, in the (i+1)th row, the pixel driving circuit 12 fixes the control signals SL that are different from the control signal SL2B[i+1], namely the control signals SL1A[i+1]~SL4A[i+1], SL1B[i+1], SL3B[i+1]~SL4B[i+1], SL1C[i+1]~SL4C[i+1], and SL1D[i+1]~SL4D[i+1] to the L state.

[0171] In addition, in the (i+2)th row, the pixel driving circuit 12 fixes the control signals SL that are different from the control signal SL3C[i+2], namely the control signals SL1A[i+2]~SL4A[i+2], SL1B[i+2]~SL4B[i+2], SL1C[i+2]~SL2C[i+2], SL4C[i+2], SL1D[i+2]~SL4D[i+2] to the L state.

[0172] In addition, in the (i+3)th row, the pixel driving circuit 12 fixes the control signals SL that are different from the control signal SL4D[i+3], namely the control signals SL1A[i+3]~SL4A[i+3], SL1B[i+3]~SL4B[i+3], SL1C[i+3]~SL4C[i+3], SL1D[i+3]~SL3D[i+3] to the L state.

[0173] In addition, the pixel driving circuit 12 sets the control signal CSL (CSL1 to CSL4) to the L state and resets the output of the selection circuit CSEL.

[0174] During the period up to time T11, the pixel driving circuit 12, similar to conventional pixel driving, turns on the transfer transistors GT1 to GT4 via control signals G1 to G4, causing the charge storage section CS1 to accumulate charge. Furthermore, while the pixel driving circuit 12 is accumulating charge in the charge storage section CS1 to CS4, it turns off the charge discharge transistor DT via control signal GD.

[0175] At time T11, the pixel driving circuit 12 sets the control signals SL1A[i], SL2B[i+1], SL3C[i+2] and SL4D[i+3] to the H state.

[0176] Additionally, at time T11, control signals CSL1 to CSL4 are set to the H state (Active).

[0177] Therefore, the pixel value (output signal) corresponding to the charge stored in the charge storage section CS1, which is calculated by combining the values ​​from pixel A, is output to the output line PIXOUT1.

[0178] Additionally, a pixel value (output signal) corresponding to the charge stored in the charge storage section CS2, which is calculated by combining the values ​​from pixel B, is output to the output line PIXOUT2.

[0179] The pixel value (output signal) corresponding to the charge stored in the charge storage section CS3 is output from pixel C to the output line PIXOUT3.

[0180] The pixel value (output signal) corresponding to the charge stored in the charge storage section CS4 is output from pixel D to the output line PIXOUT4.

[0181] At time T12, the pixel driving circuit 12 sets the control signal RTC (RTC1 to RTC4) to state H, which resets the charge stored in the charge storage section CS (CS1 to CS4) in the pixel unit GU1.

[0182] (Regarding the second implementation method) Here, the second embodiment will be described. In the first embodiment described above, the number of control signals SL is four times that of the conventional pixel unit GU1, which may increase the wiring area. Based on this viewpoint, in this embodiment, the number of control signals SL is suppressed compared to the first embodiment, and the readout time is the same as that of the first embodiment.

[0183] In this embodiment, a control signal SLX is added to the control signals SL (SL1 to SL4) used to control the selection transistor SLT in the control pixel array 11. X is any one of A to D corresponding to the four types (pixel A to pixel D) in pixel 10.

[0184] Specifically, in addition to the four conventional control signals SL (SL1 to SL4) provided for each row of the pixel array 11, a control signal SLA connected to the control terminal of the selection transistor SLT1 for pixel A is added to the row where pixel A is located. In the row where pixel B is located, a control signal SLB connected to the control terminal of the selection transistor SLT2 for pixel B is added. In the row where pixel C is located, a control signal SLC connected to the control terminal of the selection transistor SLT3 for pixel C is added. In the row where pixel D is located, a control signal SLD connected to the control terminal of the selection transistor SLT4 for pixel D is added. Thus, the selection of the selection transistor SLT can be controlled for each column. Furthermore, in this embodiment, the number of control signals SL can be reduced to five, which is less than the number in the first embodiment (16).

[0185] Furthermore, the configuration of pixels 10 (pixels A to E) in the second embodiment is the same as that of conventional pixels (pixels A to E), except for the connection of the control signal SL.

[0186] Figure 12 This is a diagram showing an example of pixel A in the second embodiment.

[0187] like Figure 12 As shown, the basic structure of pixel A in the second embodiment is the same as that of the conventional pixel A, but the connection of the control signal (selection signal) of the selection transistor SLT1 is different.

[0188] In pixel A of the second embodiment, the control terminal of the selection transistor SLT1 is connected to the control signal SLA.

[0189] Figure 13 This is a diagram showing an example of pixel B in the second embodiment.

[0190] like Figure 13 As shown, the basic structure of pixel B in the second embodiment is the same as that of the conventional pixel B, but the connection of the control signal (selection signal) of the selection transistor SLT2 is different.

[0191] In pixel B of the second embodiment, the control terminal of the selection transistor SLT2 is connected to the control signal SLB.

[0192] Figure 14 This is a diagram showing an example of pixel C in the second embodiment.

[0193] like Figure 14 As shown, the basic structure of pixel C in the second embodiment is the same as that of the conventional pixel C, but the connection of the control signal (selection signal) of the selection transistor SLT3 is different.

[0194] In pixel C of the second embodiment, the control terminal of the selection transistor SLT3 is connected to the control signal SLC.

[0195] Figure 15 This is a diagram showing an example of pixel D in the second embodiment.

[0196] like Figure 15 As shown, the basic structure of pixel D in the second embodiment is the same as that of the conventional pixel D, but the connection of the control signal (selection signal) of the selection transistor SLT4 is different.

[0197] In pixel D of the second embodiment, the control terminal of the selection transistor SLT4 is connected to the control signal SLD.

[0198] Figure 16 This is a diagram showing an example of pixel E in the second embodiment.

[0199] like Figure 16 As shown, the pixel E in the second embodiment has the same structure as the conventional pixel E.

[0200] Figure 17 This is a diagram illustrating an example of a wiring pattern in a pixel array according to the second embodiment. In this diagram, i represents the row number.

[0201] In pixel unit GU1 of pixel array 11 shown in the figure, pixel A is located at the left end of the i-th row, i.e., at coordinate (1,1). Pixel B is located at the second position from the left in the (i+1)-th row, i.e., at coordinate (2,2). Pixel C is located at the third position from the left in the (i+2)-th row, i.e., at coordinate (3,3). Pixel D is located at the fourth position from the left in the (i+3)-th row, i.e., at coordinate (4,4). Pixel E is located in pixel unit GU1 at a different position than pixels A through D.

[0202] The wiring of the pixel array 11 in the second embodiment is basically the same as that of the conventional pixel array, but the wiring of the control signal SL is different.

[0203] A control signal SLA for the selection transistor SLT1 of pixel A is wired in the pixel arranged in the i-th row. In addition, the control signal SL for controlling the other selection transistors SLT2 to SLT4 of pixel A and the selection transistors SLT (SLT1 to SLT4) arranged in pixel E in the i-th row is the same as that for conventional pixels.

[0204] A control signal SLB for the selection transistor SLT2 of pixel B is wired in the pixel configured in row (i+1). Furthermore, the control signal SL for controlling the other selection transistors SLT1, SLT3 to SLT4 of pixel B, as well as the selection transistors SLT (SLT1 to SLT4) provided in pixel E configured in row (i+1) is the same as that for conventional pixels.

[0205] The control signal SLC for the selection transistor SLT3 of pixel C is wired in the pixel arranged in the (i+2) row. In addition, the control signal SL for controlling the other selection transistors SLT1 to SLT2 and SLT4 of pixel C, as well as the selection transistors SLT (SLT1 to SLT4) arranged in pixel E in the (i+2) row, is the same as that for conventional pixels.

[0206] The control signal SLD for the selection transistor SLT4 of pixel D is wired in the pixel arranged in the (i+3) row. In addition, the control signal SL for controlling the other selection transistors SLT1 to SLT2 and SLT4 of pixel D, as well as the selection transistors SLT (SLT1 to SLT4) arranged in pixel E in the (i+3) row, is the same as that for conventional pixels.

[0207] Figure 18 This is a timing diagram showing the pixel driving during the merging operation in the second embodiment. In this diagram, the horizontal axis represents time, and the vertical axis represents the waveform of the control signals. The control signals, from top to bottom, are control signals G1 to G4, control signal GD, control signals RT1[i:i+3], RT2[i:i+3], RT3[i:i+3], RT4[i:i+3], control signals RTC1 to RTC4, control signal SLn[i+k], SLA, SLB, SLC, SLD, output signals PIXOUT1 to PIXOUT4, and control signals CSL1 to CSL4. The suffix n of the control signal SL is an integer from 1 to 4, and k is an integer from 0 to 3. i represents the row number.

[0208] During the merging operation, the pixel driving circuit 12 first fixes the control signal RT to the H (high) state and fixes the reset transistors RST (RST1~RST4) of all pixels in the pixel unit GU1 to the on state.

[0209] In addition, the pixel driving circuit 12 fixes the control signals SL, which are different from the control signal SLA, i.e., control signals SL1[i] to SL4[i], to the L state in the i-th row.

[0210] In addition, the pixel driving circuit 12 fixes the control signal SL, which is different from the control signal SLB, i.e., the control signals SL1[i+1] to SL4[i+1], to the L state in the (i+1)th row.

[0211] In addition, the pixel driving circuit 12 fixes the control signals SL, which are different from the control signal SLC, namely the control signals SL1[i+2] to SL4[i+2], to the L state in the (i+2)th row.

[0212] In addition, the pixel driving circuit 12 fixes the control signals SL, which are different from the control signal SLD, namely the control signals SL1[i+3] to SL4[i+3], to the L state in the (i+3)th row.

[0213] In addition, the pixel driving circuit 12 sets the control signal CSL (CSL1 to CSL4) to the L state and resets the output of the selection circuit CSEL.

[0214] During the period up to time T21, the pixel driving circuit 12, similar to conventional pixel driving, turns on the transfer transistors GT1 to GT4 via control signals G1 to G4, causing the charge storage section CS1 to accumulate charge. Furthermore, while the pixel driving circuit 12 is accumulating charge in the charge storage section CS1 to CS4, it turns off the charge discharge transistor DT via control signal GD.

[0215] At time T21, the pixel driving circuit 12 sets the control signals SLA, SLB, SLC, and SLD to the H state.

[0216] Additionally, at time T21, control signals CSL1 to CSL4 are set to the H state (Active).

[0217] Therefore, the pixel value (output signal) corresponding to the charge stored in the charge storage section CS1, which is calculated by combining the values ​​from pixel A, is output to the output line PIXOUT1.

[0218] Additionally, a pixel value (output signal) corresponding to the charge stored in the charge storage section CS2, which is calculated by combining the values ​​from pixel B, is output to the output line PIXOUT2.

[0219] The pixel value (output signal) corresponding to the charge stored in the charge storage section CS3 is output from pixel C to the output line PIXOUT3.

[0220] The pixel value (output signal) corresponding to the charge stored in the charge storage section CS4 is output from pixel D to the output line PIXOUT4.

[0221] At time T22, the pixel driving circuit 12 sets the control signal RTC (RTC1 to RTC4) to state H, which resets the charge stored in the charge storage section CS (CS1 to CS4) in the pixel unit GU1.

[0222] The above embodiments are illustrated. Figure 3 As shown, pixels A, B, C, and D are arranged sequentially from the upper left end to the lower right end of pixel unit GU1. However, it is not limited to this.

[0223] use Figure 19 and Figure 20 This section describes examples of pixel configurations that can be used in the implementation and examples of pixel configurations that cannot be used.

[0224] Figure 19 This is a diagram illustrating an example of the pixel configuration of the pixel unit GU1 that can be used in the implementation.

[0225] The left side of the figure shows the same pixel arrangement as in the embodiment. That is, pixel A is placed at position coordinate (1,1), pixel B at position coordinate (2,2), pixel C at position coordinate (3,3), and pixel D at position coordinate (4,4). This arrangement can be used in this embodiment.

[0226] The figure shows an example of a configuration where pixels A, B, C, and D are arranged sequentially from the upper right to the lower left. Specifically, pixel A is located at coordinates (4,1), pixel B at coordinates (3,2), pixel C at coordinates (2,3), and pixel D at coordinates (1,4). This configuration can be used in this embodiment.

[0227] On the right side of the figure, pixel A is positioned at coordinates (2,1), pixel B at coordinates (1,2), pixel C at coordinates (4,3), and pixel D at coordinates (3,4). This configuration can be used in this embodiment.

[0228] Figure 20 This is a diagram illustrating an example of the pixel configuration of pixel unit GU1, which cannot be used in the implementation.

[0229] The left side of the figure shows an example of a configuration where pixels A, B, C, and D are arranged sequentially in the left-right direction. That is, pixel A is arranged at position coordinate (1,1), pixel B at position coordinate (2,1), pixel C at position coordinate (3,1), and pixel D at position coordinate (4,1). This configuration cannot be used in this embodiment.

[0230] The figure shows an example of a configuration where pixels A, B, C, and D are arranged sequentially in the vertical direction, on the left-center side. Specifically, pixel A is located at coordinate (1,1), pixel B at coordinate (1,2), pixel C at coordinate (1,3), and pixel D at coordinate (1,4). This configuration cannot be used in this embodiment.

[0231] The diagram shows a configuration example where at least two pixels from A to D are arranged in a left-right direction, located on the right-center side. Specifically, pixel A is positioned at coordinate (1,1), pixel B at coordinate (2,2), pixel C at coordinate (3,2), and pixel D at coordinate (4,4). This configuration cannot be used in this embodiment.

[0232] The right side of the figure shows an example of a configuration where at least two pixels from A to D are arranged vertically. Specifically, pixel A is positioned at coordinate (1,1), pixel B at coordinate (2,2), pixel C at coordinate (2,3), and pixel D at coordinate (4,4). This configuration cannot be used in this embodiment.

[0233] As described above, the distance image imaging element 1 of the embodiment includes a pixel array 11 in which a plurality of pixels 10 are arranged in a two-dimensional matrix, and a pixel driving circuit 12 for driving the pixels 10. Each pixel 10 includes: a photoelectric conversion element PD that generates a charge corresponding to incident light; m charge storage units CS that store charge, where m is an integer greater than or equal to 2, for example, m=4; and m selection transistors SLT that are respectively provided corresponding to the m charge storage units CS and output a voltage signal corresponding to the amount of charge stored in the charge storage units CS. In the pixel array 11, there is a pixel A (first pixel) that outputs a combined sum of output signals PIXOUT (specific voltage signals) corresponding to the amount of charge stored in one of the m charge storage units CS (first charge storage units) of the pixel during an m×m merging operation, and pixels B to D (second pixels) that do not output a combined sum of output signals PIXOUT (specific voltage signals).

[0234] The control terminal of SLT1 (the first selection transistor that outputs the sum of the first voltage signals) of the m selection transistors SLT in pixel A (the first pixel) and the control terminal of SLT1 (the first selection transistor) of the selection transistors SLT in pixels B to E (the second pixels) are connected to different selection signals.

[0235] For example, such as Figures 12 to 16As shown, the control terminal of the selection transistor SLT1 for pixel A is connected to the control signal SLA, while the control terminal of the selection transistor SLT1 for pixels B to E is connected to the control signal SL1.

[0236] Therefore, in the distance image camera element 1 of the embodiment, the selection transistor SLT can be controlled column by column, which can shorten the time required to read out the pixel signals of each of the multiple charge storage units when performing a merging operation.

[0237] Furthermore, in the distance image imaging element 1 of the embodiment, the control terminals of each of the m selection transistors SLT (for example, selection transistors SLT1 to SLT4 in the case of m=4) disposed in pixel A (first pixel) and the control terminals of each of the selection transistors SLT disposed in pixels 10 (pixels B to E) which are different from pixels A (first pixel) disposed in pixel array 11 are connected to different selection signals.

[0238] For example, such as Figures 5-6 As shown, the control terminal of the selection transistor SLT1 for pixel A is connected to the control signal SL1A, while the control terminal of the selection transistor SLT1 for pixel B is connected to the control signal SL1B.

[0239] Therefore, the distance image camera element 1 in the embodiment achieves the same effect as described above.

[0240] Furthermore, in the distance image camera element 1 of the embodiment, the pixel array 11 has at least m types of pixels 10 (e.g., pixels A to pixels D) that are driven differently in an m×m merging operation.

[0241] The m types of pixels 10 are pixels 10 that output the sum of voltage signals corresponding to the amount of charge stored in any one of the m charge storage sections CS of the pixel 10.

[0242] In each of the m types of pixels 10, the control terminal of the specific selection transistor that outputs the sum of the combined values ​​in the m selection transistors SLT of pixel 10 is connected to the control terminal of the selection transistor corresponding to the specific selection transistor in the m selection transistors SLT of other different types of pixels 10, and is connected to different selection signals.

[0243] For example, such as Figures 5-9As shown, the control terminal of the selection transistor SLT1 of pixel A is connected to the control signal SL1A, the control terminal of the selection transistor SLT1 of pixel B is connected to the control signal SL1B, the control terminal of the selection transistor SLT1 of pixel C is connected to the control signal SL1C, and the control terminal of the selection transistor SLT1 of pixel D is connected to the control signal SL1D.

[0244] Therefore, the distance image camera element 1 in the embodiment achieves the same effect as described above.

[0245] In addition, in the distance image camera element 1 of the embodiment, the pixel 10 has four charge storage units CS (charge storage units CS1 to CS4) and four selection transistors SLT (selection transistors SLT1 to SLT4).

[0246] The pixel array 11 includes at least four types of pixels 10 (pixel A to pixel D) that perform different drives in a 4×4 merging operation.

[0247] The four types of pixels 10 are: pixel 10-A (pixel A), which outputs a sum of first voltage signals corresponding to the amount of charge stored in the four charge storage units CS1 to CS4 of the pixel 10; pixel 10-B (pixel B), which outputs a sum of second voltage signals corresponding to the amount of charge stored in the charge storage unit CS2 (second charge storage unit); pixel 10-C (pixel C), which outputs a sum of third voltage signals corresponding to the amount of charge stored in the charge storage unit CS3 (third charge storage unit); and pixel 10-D (pixel D), which outputs a sum of fourth voltage signals corresponding to the amount of charge stored in the charge storage unit CS4 (fourth charge storage unit).

[0248] The control terminal of the selection transistor SLT1 (first selection transistor) for the output first voltage signal of pixel 10-A (pixel A) of type A is connected to the control terminal of the selection transistor SLT1 of pixel 10 (pixel B to pixel D) of a different type than type A, and is connected to different selection signals.

[0249] The control terminal of the selection transistor SLT2 (second selection transistor) for the output second voltage signal of pixel 10-B (pixel B) of type B is connected to the control terminal of the selection transistor SLT2 of pixel 10 (pixel A, pixel C to pixel D) of a different type than type B, and is connected to different selection signals.

[0250] The control terminal of the selection transistor SLT3 (third selection transistor) for the output third voltage signal of pixel 10-C (pixel C) of type C is connected to the control terminal of the selection transistor SLT3 of pixel 10 (pixel A to pixel B, pixel D) of a different type than type C, and is connected to different selection signals.

[0251] The control terminal of the selection transistor SLT4 (fourth selection transistor) for the output fourth voltage signal of pixel 10-D (pixel D) of type D and the control terminal of the selection transistor SLT4 for a different type of pixel 10 (pixel A to pixel C) are connected to different selection signals.

[0252] Therefore, the distance image camera element 1 in the embodiment achieves the same effect as described above.

[0253] In addition, in the distance image camera element 1 of the embodiment, the pixel 10 includes: m reset transistors RST, each corresponding to m charge storage units CS, which reset the charge storage units to a predetermined reset potential supplied from the power line; and m control transistors RS, each corresponding to the m reset transistors RST, connected between the reset transistors RST and the power line.

[0254] In pixel 10, the control transistor RS corresponding to a specific voltage signal (the signal that outputs the combined sum value) among the m control transistors RS is connected to the control wiring RT that can control the conduction state, and the remaining control transistors RST among the m control transistors RS that are different from the control transistor RS corresponding to the specific voltage signal are fixed in the non-conducting state.

[0255] For example, such as Figure 5 As shown, in pixel A, the control transistor RS1 (control transistor RS1 to RS4) of the four control transistors RS is connected to the control wiring RT1, which is capable of controlling the conduction state. The other control transistors SR (control transistor RS2 to RS4) of the four control transistors RS (control transistor RS1 to RS4) that are different from the control transistor RS1 corresponding to the first voltage signal are fixed in the non-conducting state.

[0256] Therefore, in the distance image camera element 1 of the embodiment, it is possible to merge and add, or eliminate the added charge, and to perform a merging operation.

[0257] As explained above, the distance image capturing device 100 of the embodiment includes a light source unit 2, a light receiving unit 3, and a distance image processing unit 4. The light source unit 2 irradiates a light pulse onto the subject OB. The light receiving unit 3 has a distance image capturing element 1. The distance image processing unit 4 controls the pixel driving circuit 12 to cause the charge accumulating units CS to accumulate charge, and calculates the distance to the subject OB based on the sum of the voltage signals corresponding to the amount of charge accumulated in each charge accumulating unit CS. Thus, in the distance image capturing device 100 of the embodiment, distance calculation can be performed within the sensor circuit (distance image capturing device 100), and the voltage signals corresponding to the amount of charge accumulated in any of the charge accumulating units CS are sequentially stored in a memory provided inside or outside the distance image capturing device 100. It is not necessary to calculate the distance after all the voltage signals used for distance calculation are collected, which can reduce the memory capacity and shorten the time required for distance calculation.

[0258] Furthermore, the present invention is not limited to the embodiments described above, and modifications can be made without departing from the spirit of the present invention.

[0259] For example, in the above embodiment, an example of pixel 10 having 4 charge storage units CS is described, but it is not limited to this. As long as there are 2 or more charge storage units CS, other numbers (m or less) of charge storage units CS may also be provided.

[0260] Furthermore, in the above embodiment, an example of pixel array 11 having 4 types of pixels 10 was described as an example of m types of pixels 10, but it is not limited to this.

[0261] For example, when performing the merging of (2×2) pixels, there may be at least two types of pixels 10 that output the combined sum of voltage signals corresponding to the amount of charge stored in each of the two charge storage units CS1 to CS2.

[0262] Alternatively, for example, when performing (3×3) pixel merging, at least three types of pixels 10 may be provided that output the combined sum of voltage signals corresponding to the amount of charge stored in each of the three charge storage units CS1 to CS3.

[0263] In addition, when merging 5 or more pixels, for example (5×5), at least 5 types of pixels 10 can be provided to output the sum of voltage signals corresponding to the amount of charge stored in each of the 5 charge storage units CS1 to CS5.

[0264] Furthermore, the above embodiments illustrate an example of a buried photodiode where the photoelectric conversion element PD is an embedded photodiode that generates and stores charge by photoelectric conversion of incident light, but it is not limited to this; the structure of the photoelectric conversion element PD can be arbitrary. For example, the photoelectric conversion element PD can be a PN photodiode with a structure that combines P-type and N-type semiconductors, or a PIN photodiode with an I-type semiconductor sandwiched between P-type and N-type semiconductors. Additionally, the photoelectric conversion element PD is not limited to a photodiode; for example, it can also be a grating-type photoelectric conversion element.

[0265] Furthermore, in the above embodiments, the examples described are NMOS transistors for the transfer transistor GT (GT1 to GT4), charge discharge transistor DT, reset transistor RST (RST1 to RST4), source follower transistor SF (SF1 to SF4), select transistor SLT (SLT1 to SLT4), and control transistor RS (RS1 to RS4), but it is not limited to this, and other transistors such as PMOS transistors may also be used.

[0266] All or part of the distance image capturing element 1 and the distance image capturing device 100 in the above embodiments can also be implemented by a computer. In this case, it can also be implemented by recording the program for implementing this function on a computer-readable recording medium, and having the computer system read and execute the program recorded on the recording medium. In addition, the "computer system" mentioned here includes hardware such as OS and peripheral devices. In addition, "computer-readable recording medium" refers to removable media such as floppy disks, optical disks, ROMs, CD-ROMs, etc., and storage devices such as hard disks built into the computer system. Furthermore, "computer-readable recording medium" can also include a medium that dynamically holds the program for a short period of time, such as a communication line in the case of transmitting the program via a network such as the Internet, or a communication line such as a telephone line, or a medium that holds the program for a certain period of time, such as volatile memory inside the computer system that serves as a server or client in this case. In addition, the above-mentioned program can be a program for implementing part of the above-mentioned function, or a program that can implement the above-mentioned function by combining with a program already recorded in the computer system, or a program implemented using a programmable logic device such as an FPGA.

[0267] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the specific configuration is not limited to these embodiments, and also includes designs, device configurations, correction processes, filtering processes, etc., that do not depart from the spirit of the present invention.

Claims

1. A distance image capturing element, comprising: A pixel array, consisting of multiple pixels arranged in a two-dimensional matrix; and Pixel driving circuit, drives the pixel. The pixel has the following characteristics: A photoelectric conversion element generates a charge corresponding to the incident light; m charge storage units, storing the charge, where m is an integer greater than or equal to 2; and m selection transistors are respectively arranged corresponding to m charge storage sections, and output voltage signals corresponding to the amount of charge stored in the charge storage sections. The pixel array includes a first pixel and a second pixel. In an m×m merging operation, the first pixel outputs a summed value of a specific voltage signal corresponding to the amount of charge stored in one of the m charge storage units of the pixel. The second pixel does not output the summed value of the specific voltage signal. The control terminals of the specific selection transistors that output the sum of the specific voltage signals in the m selection transistors of the first pixel and the control terminals of the specific selection transistors of the second pixel are connected to different selection signals.

2. The distance image capturing element according to claim 1, wherein, The control terminals of the m selection transistors located in the first pixel and the control terminals of the selection transistors located in the second pixel are connected to different selection signals.

3. The distance image capturing element according to claim 1, wherein, The pixel array has at least m types of pixels that are driven differently in an m×m merging operation. The pixel in m is the pixel that outputs the sum of voltage signals corresponding to the amount of charge stored in any one of the m charge storage sections of the pixel. In each of the m types of pixels, the control terminal of the specific selection transistor that outputs the summed value in the m selection transistors of the pixel is connected to the control terminal of the selection transistor corresponding to the specific selection transistor in the m selection transistors of other different types of pixels, and is connected to different selection signals.

4. The distance image capturing element according to claim 1, wherein, The pixel has the following characteristics: The four charge storage units; and The four selected transistors, The pixel array has at least four types of pixels that are driven differently in a 4×4 merging operation. The four types of pixels are: type A pixels that output a sum of first voltage signals corresponding to the amount of charge stored in the first charge storage unit of the four charge storage units of the pixel; type B pixels that output a sum of second voltage signals corresponding to the amount of charge stored in the second charge storage unit; type C pixels that output a sum of third voltage signals corresponding to the amount of charge stored in the third charge storage unit; and type D pixels that output a sum of fourth voltage signals corresponding to the amount of charge stored in the fourth charge storage unit. The control terminal of the first selection transistor that outputs the first voltage signal to the pixel of type A is connected to the control terminal of the first selection transistor of a pixel of a different type A, and to different selection signals. The control terminal of the second selection transistor that outputs the second voltage signal to the pixel of type B is connected to the control terminal of the second selection transistor of a pixel of a different type B via different selection signals. The control terminal of the third selection transistor that outputs the third voltage signal to the pixel of type C is connected to the control terminal of the third selection transistor of a pixel of a different type C via different selection signals. The control terminal of the fourth selection transistor that outputs the fourth voltage signal of the pixel of type D is connected to the control terminal of the fourth selection transistor of the pixel of a different type than type D, and is connected to different selection signals.

5. The distance image capturing element according to claim 1, wherein, The pixel has the following characteristics: m reset transistors, each corresponding to one of the m charge storage sections, reset the charge storage sections to a predetermined reset potential supplied from the power line; and m control transistors, corresponding to m reset transistors, are connected between the reset transistors and the power supply line. In the pixel, the control transistor corresponding to the specific voltage signal among the m control transistors is connected to a control wiring capable of controlling the conduction state, and the remaining control transistors among the m control transistors that are different from the control transistor corresponding to the specific voltage signal are fixed in a non-conducting state.

6. A distance image camera device, comprising: The light source irradiates the subject with light pulses; The light-receiving part includes the distance image capturing element as described in claim 1; and The distance image processing unit controls the pixel driving circuit to cause the charge storage section to store the charge respectively, and outputs a combined sum of voltage signals corresponding to the amount of charge stored by the charge storage section. Based on the combined sum of the values ​​corresponding to the charge storage sections, the distance to the subject is calculated.

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