Method for manufacturing alignment marks of a wafer, double-side alignment photolithography method and wafer

Abstract

The application discloses a manufacturing method of alignment marks of a wafer, a double-side alignment photolithography method and the wafer. The manufacturing method of the alignment marks comprises the following steps: cleaning the wafer; determining the shape and position of the alignment marks on the wafer; and vertically etching the wafer by using a plasma deep silicon etching process or a laser drilling process according to the shape and position of the alignment marks on the wafer, so as to form the up-and-down through type alignment marks on the wafer body. The technical scheme provided by the embodiment of the application can directly form the up-and-down through type alignment marks on the wafer body, visible light can directly pass through the wafer through the alignment marks, high-precision double-side alignment of the wafer is realized, and the precision of the photolithography process is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating alignment marks on a wafer, a photolithography method for double-sided alignment, and a wafer. Background Technology

[0002] With the rapid development of semiconductor technology, wafers, as an indispensable part of modern electronic devices, are widely used in the semiconductor field, and increasingly require alignment photolithography operations on both sides of thick silicon wafers.

[0003] Currently, when performing double-sided alignment photolithography on thick silicon wafers, especially those thicker than 775μm, conventional lithography machines' near-infrared light paths cannot penetrate the thick pure silicon wafers, resulting in limited alignment accuracy and the inability to directly identify the back-side pattern. Alignment methods relying on wafer notches and edge mechanical positioning have low accuracy and large overlay errors. Existing dedicated infrared lithography equipment is expensive and unsuitable for general mass production scenarios. Therefore, the inability to accurately align both sides during double-sided photolithography on thick silicon wafers has become a pressing technical problem that needs to be solved in the industry. Summary of the Invention

[0004] This invention provides a method for fabricating alignment marks on a wafer, a photolithography method for double-sided alignment, and a wafer, to solve the problem that the existing double-sided photolithography process on thick silicon wafers cannot achieve precise double-sided alignment, thereby realizing high-precision double-sided alignment photolithography.

[0005] According to one aspect of the present invention, a method for fabricating alignment marks on a wafer is provided, comprising: The wafer is cleaned; Determine the shape and position of the alignment marks on the wafer; Based on the shape and position of the alignment mark on the wafer, a plasma deep silicon etching process or a laser drilling process is used to vertically etch through the wafer to form a vertically penetrating alignment mark on the wafer body.

[0006] Optionally, when vertically etching the wafer using the plasma deep silicon etching process, the alignment mark is formed on the wafer by vertically etching the wafer using either plasma deep silicon etching or laser drilling, depending on the shape and position of the alignment mark. This process includes: An alignment mark pattern is formed in the non-device effective area of ​​the wafer according to the shape of the alignment mark and its position on the wafer; The alignment mark pattern is used to vertically etch the wafer using the plasma deep silicon etching process, forming a vertical alignment mark on the wafer body.

[0007] Optionally, forming an alignment mark pattern in the non-device effective area of ​​the wafer according to the shape and position of the alignment mark on the wafer includes: A hard mask layer is formed on the surface of the wafer; Photoresist is coated on the surface of the hard mask layer, and the alignment mark pattern is formed on the photoresist by exposure and development.

[0008] Optionally, the step of vertically etching the wafer using the plasma deep silicon etching process according to the alignment mark pattern to form a vertically penetrating alignment mark on the wafer body includes: The hard mask layer is etched using the alignment mark pattern to transfer the alignment mark pattern into the hard mask layer, and the photoresist layer is removed. The wafer is etched using a plasma deep silicon etching process, and the hard mask layer is removed to form a through-type alignment mark on the wafer body.

[0009] Optionally, the plasma deep silicon etching process includes an etching stage and a passivation stage, wherein the etching stage and the passivation stage are performed alternately.

[0010] Optionally, when using laser drilling to vertically etch the wafer, depending on the shape and position of the alignment mark on the wafer, plasma deep silicon etching or laser drilling is used to vertically etch the wafer to form a vertically penetrating alignment mark on the wafer body, including: A protective liquid is applied to the surface of the wafer; The wafer is slotted by laser drilling and the protective solution is cleaned to form vertical alignment marks on the wafer body.

[0011] Optionally, the alignment mark may be one or more, and the shape of the alignment mark may include a cross-shaped through hole, a rectangular through hole, or a circular through hole.

[0012] Optionally, visible light can pass directly through the alignment mark.

[0013] According to another aspect of the present invention, a photolithography method for double-sided alignment of a wafer is provided, comprising: A wafer is provided, and alignment marks are formed on the wafer using the wafer alignment mark fabrication method provided in any of the above embodiments; The wafer is placed face up in a lithography machine, which identifies the alignment marks from the front side of the wafer to perform lithography on the front side of the wafer. The wafer is flipped over, and the lithography machine identifies the alignment marks from the back side of the wafer to perform lithography on the back side of the wafer.

[0014] According to another aspect of the present invention, a wafer is provided in which alignment marks are fabricated using the wafer alignment mark fabrication method provided in any of the above embodiments.

[0015] The technical solution of this invention first determines the shape of the alignment mark and its position on the wafer, and then cleans the wafer. Next, based on the shape and position of the alignment mark on the wafer, a plasma deep silicon etching process or a laser drilling process is used to vertically etch through the cleaned wafer, forming a vertically penetrating alignment mark on the wafer body. By creating a vertically penetrating alignment mark in a non-device-active area at the wafer edge, visible light can directly pass through the wafer. The lithography machine can directly optically identify the same set of alignment marks from both the front and back sides, achieving high-precision double-sided alignment of thick wafers without the need for additional settings, thus reducing equipment costs. Furthermore, since the alignment mark is located in a non-device-active area at the wafer edge, it does not occupy chip area, and there is no need for wafer thinning, ensuring wafer strength.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for fabricating alignment marks on a wafer, as provided in an embodiment of the present invention; Figure 2 A flowchart illustrating another method for fabricating alignment marks on a wafer, as provided in an embodiment of the present invention; Figure 3 A flowchart illustrating another method for fabricating alignment marks on a wafer, as provided in an embodiment of the present invention; Figure 4 A process flow diagram for fabricating alignment marks on a wafer using plasma deep silicon etching is provided as an embodiment of the present invention. Figure 5 This is a schematic diagram of a structure for coating photoresist on a wafer according to an embodiment of the present invention; Figure 6 A flowchart illustrating another method for fabricating alignment marks on a wafer, as provided in an embodiment of the present invention; Figure 7A flowchart illustrating another method for fabricating alignment marks on a wafer, as provided in an embodiment of the present invention; Figure 8 A process flow diagram for fabricating alignment marks on a wafer using laser drilling technology is provided as an embodiment of the present invention. Figure 9 This is a schematic diagram of a structure for coating a protective liquid on a wafer, provided in an embodiment of the present invention; Figure 10 This is a flowchart of a photolithography method for double-sided alignment of a wafer, provided as an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a flowchart of a method for fabricating alignment marks on a wafer according to an embodiment of the present invention. This embodiment of the present invention can be applied to the fabrication of alignment marks on thick wafers.

[0022] like Figure 1 As shown, the method for fabricating alignment marks on a wafer provided in this embodiment of the invention includes: S110. Clean the wafer.

[0023] Specifically, in current semiconductor manufacturing processes, an increasing number of wafers require photolithography on both the front and back sides. During double-sided photolithography, alignment marks are used to lithographically pattern both sides of the wafer to ensure accurate patterning of the front and back images. However, for thicker wafers, such as those with a thickness of 500μm-1000μm, the difficulty of double-sided alignment photolithography is far greater than for wafers of ordinary thickness because light cannot penetrate the wafer. This invention provides a method for fabricating through-hole alignment marks, which can be used in double-sided photolithography processes for thick wafers. Before fabricating the alignment marks, the wafer needs to be cleaned to remove particulate contaminants, organic contaminants, and metal ion contaminants from its surface. In the alignment mark fabrication method provided by this invention, since through-holes or grooves need to be formed on the wafer, the cleanliness of the wafer surface has a significant impact on subsequent pattern definition and etching processes. If particulate contaminants are present on the wafer surface, it may lead to uneven photoresist coating, resulting in pinhole defects that hinder localized etching, causing bumps or incomplete etching on the via sidewalls, and affecting the clarity of the alignment marks. Therefore, before fabricating alignment marks, the wafer needs to be cleaned to ensure good adhesion of the photoresist to the wafer surface in subsequent processes and accurate transfer of the pattern during via etching, thereby improving the clarity of the alignment marks. For example, the wafer can be cleaned using plasma cleaning or ultrasonic cleaning with deionized water. Furthermore, the wafer needs to be dried after cleaning.

[0024] S120. Determine the shape and position of the alignment mark on the wafer.

[0025] Specifically, before fabricating alignment marks on the wafer, the shape and distribution of the alignment marks on the wafer need to be determined. A wafer can have one or more alignment marks, and these marks can be one or more of the following shapes: cross-shaped, rectangular, circular, L-shaped, T-shaped, I-shaped, concentric rings, or grid-like. The pattern of the wafer alignment marks can be determined according to the type of wafer. As for the distribution of the alignment marks on the wafer, they can be placed in the non-device-active area at the wafer edge, that is, the area on the wafer surface not used for fabricating semiconductor devices. For example, the alignment marks can be located in a ring-shaped area 0.5mm-10mm from the outer edge of the wafer. This area does not contain any functional chip patterns, and fabricating alignment marks in this area will not damage or affect the performance of functional devices on the wafer. When there are multiple alignment marks, they can be symmetrically distributed along the wafer edge.

[0026] S130. Based on the shape and position of the alignment mark on the wafer, a plasma deep silicon etching process or a laser drilling process is used to vertically etch through the wafer to form a vertical alignment mark on the wafer body.

[0027] Specifically, after determining the shape and distribution of the alignment marks on the wafer, plasma deep silicon etching or laser drilling can be used to vertically etch through the cleaned wafer, forming vertically penetrating alignment marks on the wafer body. These alignment marks need to penetrate the wafer, running through both the front and back sides, to achieve double-sided alignment during double-sided photolithography. The alignment marks can be formed on the wafer using either plasma deep silicon etching or laser drilling; both methods can achieve the technical effect of vertically penetrating wafers with a thickness of 500μm-1000μm.

[0028] The method for fabricating alignment marks on a wafer provided in this invention first determines the shape of the alignment marks and their location on the wafer, and then cleans the wafer. Next, based on the shape and position of the alignment marks on the wafer, a plasma deep silicon etching process or a laser drilling process is used to vertically etch through the cleaned wafer, forming vertically penetrating alignment marks on the wafer body. By fabricating vertically penetrating alignment marks in the non-device-active area at the wafer edge, visible light can directly pass through the wafer. The lithography machine can directly optically identify the same set of alignment marks from both the front and back sides, achieving high-precision double-sided alignment of thick wafers without the need for additional settings, thus reducing equipment costs. Furthermore, since the alignment marks are located in the non-device-active area at the wafer edge, they do not occupy chip area, and wafer thinning is unnecessary, ensuring wafer strength.

[0029] Optional, Figure 2 A flowchart illustrating another method for fabricating alignment marks on a wafer, provided as an embodiment of the present invention. Based on the above embodiments, see [link to related documentation]. Figure 2 The method for fabricating alignment marks on a wafer provided in this embodiment of the invention includes: S210. Clean the wafer.

[0030] S220. Determine the shape and position of the alignment marks on the wafer.

[0031] S230. An alignment mark pattern is formed in the non-device effective area of ​​the wafer according to the shape and position of the alignment mark on the wafer.

[0032] Specifically, when fabricating alignment marks on a wafer using plasma deep silicon etching, an alignment mark pattern consistent with the alignment mark needs to be formed at the corresponding position on the wafer first. After determining the shape and distribution of the alignment marks on the wafer, the alignment mark pattern needs to be exposed and developed at the corresponding position on the wafer. This involves transferring the already determined shape of the alignment mark to the surface of the wafer, forming a physical alignment mark pattern on the wafer surface, so that through-holes can be formed on the wafer subsequently. The alignment mark pattern matches the shape of the alignment mark, and the corresponding position on the wafer is the distribution position of the alignment mark on the wafer. This allows it to be located in the non-device area at the edge of the wafer, thus ensuring the integrity of the device area in the center of the wafer.

[0033] S240. Based on the alignment mark pattern, a plasma deep silicon etching process is used to vertically etch through the wafer to form a vertical alignment mark on the wafer body.

[0034] Specifically, after forming alignment mark patterns at corresponding positions on the wafer surface, plasma deep silicon etching (PDE) can be used to vertically etch through the wafer, creating vertically continuous alignment marks on the wafer body. PDE is a plasma-based dry etching technique. It involves introducing etching gas into a vacuum reaction chamber, generating plasma containing active particles under a high-frequency electric field. These active particles chemically react with the exposed silicon material to generate volatile products that are then removed, thus removing the silicon material. This process features high etching rate, good anisotropy, and high selectivity, making it particularly suitable for fabricating high aspect ratio silicon structures. It ensures the sharpness of the alignment mark edges without damaging the wafer.

[0035] Optional, Figure 3 A flowchart illustrating another method for fabricating alignment marks on a wafer according to an embodiment of the present invention. Figure 4 This invention provides a process flow diagram for fabricating alignment marks on wafers using plasma deep silicon etching. Figure 5 This is a schematic diagram illustrating the structure of coating photoresist on a wafer according to an embodiment of the present invention. Based on the above embodiment, see [link to embodiment]. Figures 3-5 The method for fabricating alignment marks on a wafer provided in this embodiment of the invention includes: S310, Clean the wafer.

[0036] For details, see Figure 4 As shown in step a1, a wafer 10 is provided, and the wafer 10 is cleaned and dried. The wafer 10 can be made of silicon-based material, which not only provides good support but also allows for the integration of key electronic components.

[0037] S320. Determine the shape and position of the alignment mark on the wafer.

[0038] S330, forming a hard mask layer on the surface of the wafer.

[0039] For details, see Figure 4 As shown in step a2, when preparing the through-type alignment mark S2 using plasma deep silicon etching, since the subsequent deep silicon etching needs to continue for a relatively long time, a hard mask layer 20 needs to be formed on the surface of the wafer 10 to ensure that the wafer 10 is not damaged during the etching process. The hard mask layer 20 is an inorganic thin film material formed by chemical vapor deposition, and its main components may include titanium nitride, silicon nitride, silicon dioxide, etc. The function of the hard mask layer 20 is to act as an intermediate medium, transferring the alignment mark pattern formed on the photoresist to its own surface in subsequent processes, and finally transferring the pattern to the wafer 10 during the deep silicon etching process to form a vertically through-type alignment mark on the wafer 10. The thickness of the hard mask layer 20 is not specifically limited in this embodiment of the invention and can be limited according to the actual situation.

[0040] S340. Photoresist is coated on the surface of the hard mask layer, and alignment mark patterns are formed on the photoresist by exposure and development.

[0041] For details, see Figure 4 As shown in steps a3 and a4, there can be two alignment marks S2 on the wafer 10, both located in the non-device active area at the edge of the wafer 10 and symmetrically arranged about the center line of the wafer. After forming the hard mask layer 10 on the surface of the wafer 10, a layer of photoresist 30 needs to be coated on the surface of the hard mask layer 200, such as... Figure 5As shown, a hard mask layer 20 and photoresist 30 are sequentially formed on wafer 10. Alignment mark patterns S1 are then formed on the photoresist 30 through exposure and development, serving as an intermediate medium for subsequent pattern transfer to wafer 10. After coating the photoresist 30, the wafer 10 is pre-baked, involving heating the wafer 10 coated with photoresist 30. After pre-baking, exposure is performed. The mask tool with the alignment mark pattern S1 is aligned with the wafer 10, and the photoresist 30 is exposed using ultraviolet light. During exposure, ultraviolet light passes through the transparent area of ​​the mask tool and irradiates the photoresist 30, causing changes in the chemical structure of the exposed areas of the photoresist 30. After exposure, the wafer 10 is placed in a developing solution for development, which selectively dissolves the photoresist 30 in the exposed areas. After development, an alignment mark pattern S1 is formed on the photoresist 30. This alignment mark pattern S1 is consistent with the determined alignment mark shape and is located in the non-device effective area at the edge of the wafer 10. After development, the wafer 10 needs to be post-baked to remove residual developer and moisture, further enhancing the adhesion of the photoresist 30 to the hard mask layer 20.

[0042] S350. Based on the alignment mark pattern, a plasma deep silicon etching process is used to vertically etch through the wafer to form a vertical alignment mark on the wafer body.

[0043] Optional, Figure 6 A flowchart illustrating another method for fabricating alignment marks on a wafer, provided as an embodiment of the present invention. Based on the above embodiments, see [link to related documentation]. Figures 4-6 The method for fabricating alignment marks on a wafer provided in this embodiment of the invention includes: S410, Clean the wafer.

[0044] S420. Determine the shape and position of the alignment marks on the wafer.

[0045] S430, forming a hard mask layer on the surface of the wafer.

[0046] S440. Photoresist is coated on the surface of the hard mask layer, and alignment mark patterns are formed on the photoresist by exposure and development.

[0047] S450: The hard mask layer is etched by aligning the marking pattern, the alignment marking pattern is transferred to the hard mask layer, and the photoresist layer is removed.

[0048] For details, see Figure 4As shown in steps a5 and a6, after forming the alignment mark pattern S1 on the photoresist 30 on the surface of the hard mask layer 20, the hard mask layer 20 is etched using the alignment mark pattern S1 formed on the photoresist 30 as a mask to transfer the alignment mark pattern S1 on the photoresist 30 into the hard mask layer 20. Then, the photoresist layer 30 remaining on the surface of the hard mask layer 20 is removed, preparing for subsequent deep silicon etching. After forming the alignment mark pattern S1 with the same shape as the alignment marks on the photoresist 30 through exposure and development processes, the exposed hard mask layer 20 is etched using the patterned photoresist 30 as a mask. During the etching process, the hard mask layer 20 in the area covered by the photoresist 30 is protected from etching, while the hard mask layer 20 in the area where the photoresist 30 is removed (i.e., the area of ​​the alignment mark pattern S1) is exposed to the etching environment and removed. After etching, a window consistent with the photoresist pattern S1 is formed on the hard mask layer 20, exposing the surface of the wafer 10 at the window location. The alignment mark pattern S1 is transferred from the photoresist layer 30 to the hard mask layer 20. After etching the hard mask layer 20, it is necessary to completely remove the photoresist 30 remaining on the surface of the hard mask layer 20. Dry or wet photoresist removal can be used to avoid the photoresist 30 affecting the alignment marks in plasma deep silicon etching. The etching method for the hard mask layer 20 is not specifically limited in this embodiment of the invention and can be selected according to the actual situation.

[0049] S460: The wafer is etched using plasma deep silicon etching process, and the hard mask layer is removed to form a through-type alignment mark on the wafer body.

[0050] For details, see Figure 4As shown in steps a7 and a8, after the alignment mark pattern S1 is transferred from the photoresist 30 to the hard mask layer 20, the patterned hard mask layer 20 is used as a blocking material. The wafer 10 is vertically etched downwards at the opening position of the hard mask layer 20 using a plasma deep silicon etching process until the entire wafer 10 is etched through. After the deep silicon etching is completed, the hard mask layer 20 remaining on the surface of the wafer 10 is removed, ultimately forming a vertically continuous alignment mark S2 on the wafer 10 body. The plasma deep silicon etching process includes an etching stage and a passivation stage, which are performed alternately. The etching stage is mainly used to etch downwards onto the wafer 10, while the passivation stage is mainly used to form a protective film on the sidewalls of the trenches formed after etching on the wafer 10. This protective film can prevent the sidewalls of the trenches from being further etched in the next etching stage. After deep silicon etching is completed, a through-type alignment mark S2 is formed at the corresponding position on wafer 10, and then the hard mask layer 20 remaining on the surface of wafer 10 is removed. After removing the hard mask layer 20, only the through-type alignment mark S2 formed by the wafer 10 body remains on the surface of wafer 10. This alignment mark S2 runs through the front and back sides of wafer 10, is transparent from top to bottom, has a clear outline, and can be directly passed through by visible light. The lithography machine can use visible light to perform optical recognition directly from the front and back sides, providing a high-precision alignment reference for subsequent double-sided alignment lithography.

[0051] Optional, Figure 7 A flowchart illustrating another method for fabricating alignment marks on a wafer according to an embodiment of the present invention. Figure 8 This invention provides a process flow diagram for fabricating alignment marks on wafers using laser drilling technology, as an embodiment of the present invention. Figure 9 This is a schematic diagram illustrating the structure of a protective liquid coating on a wafer, provided in an embodiment of the present invention. Based on the above embodiment, see... Figures 7-9 The method for fabricating alignment marks on a wafer provided in this embodiment of the invention includes: S510, Clean the wafer.

[0052] For details, see Figure 8 As shown in step b1, a wafer 10 is provided and then cleaned and dried.

[0053] S520, Determine the shape and position of the alignment marks on the wafer.

[0054] S530. Apply a protective liquid to the surface of the wafer.

[0055] For details, see Figure 8 Step b2 and Figure 9As shown, when preparing the through-type alignment mark S2 using laser drilling, a high-energy laser beam is used to directly irradiate the corresponding position on the wafer 10 to form the vertically penetrating alignment mark S2. Before laser drilling the wafer 10, a protective liquid 40 is coated on the surface of the wafer 10. This effectively protects other areas of the wafer 10 during the laser drilling process, and also disperses heat in a timely manner, preventing the thermal energy of the laser from spreading and causing the processing area to become too large. It also effectively prevents the debris after processing from splashing onto the surface of the wafer 10, preventing workpiece cracks, chipping, and surface scratches. The material of the protective liquid 40 is not specifically limited in this embodiment of the invention and can be set according to actual needs. For example, it can be a water-soluble protective liquid.

[0056] S540: The wafer is slotted by laser drilling and the protective solution is cleaned to form a through-type alignment mark on the wafer body.

[0057] For details, see Figure 8 As shown in steps b3 and b4, Figure 8 An example is shown where two alignment marks S2 are formed on wafer 10. After coating the surface of wafer 10 with a protective liquid 40, a groove can be made on the surface of wafer 10 using a laser drilling process, according to the shape and position of the alignment marks on the wafer, vertically penetrating the entire wafer. Subsequently, the protective liquid 40 and residues generated by laser processing are removed by cleaning, ultimately forming vertically penetrating alignment marks S2 on the wafer 10 body. After cleaning, the surface of wafer 10 is clean, retaining only the vertically penetrating alignment marks S2 on the wafer 10 body. These alignment marks S2 are located in the non-device effective area at the edge of wafer 10, penetrating the front and back sides of wafer 10, and are transparent from top to bottom with clear outlines, allowing visible light to pass directly through.

[0058] The wafer alignment mark fabrication method provided in this invention can form a through-type alignment mark on the wafer through plasma deep silicon etching or laser drilling. It has low manufacturing cost and simple process. It does not require growing oxide, nitride or epitaxial layers on the wafer surface, and does not require wafer thinning, thus achieving high-precision double-sided alignment of thick wafers.

[0059] This invention also provides a photolithography method for double-sided alignment of a wafer. Figure 10 This is a flowchart illustrating a photolithography method for double-sided alignment of a wafer, provided as an embodiment of the present invention. See also... Figure 10 The photolithography method for double-sided alignment of a wafer provided in this embodiment of the invention includes: S610. A wafer is provided, and alignment marks are formed on the wafer by a method for making alignment marks on the wafer.

[0060] Specifically, before performing photolithography on the wafer, it is necessary to first form vertical alignment marks on the wafer. The wafer alignment mark fabrication method provided in any of the above embodiments can be used to form vertical alignment marks on the wafer, so that the photolithography machine can accurately position itself during subsequent photolithography to perform photolithography on the front and back sides of the wafer using the same alignment marks.

[0061] S620. Place the wafer face up in the lithography machine. The lithography machine identifies the alignment mark from the front of the wafer to perform lithography on the front of the wafer.

[0062] Specifically, a wafer with pre-formed alignment marks is placed face up on the stage of a lithography machine. The alignment system of the lithography machine optically identifies the alignment marks from the front of the wafer, allowing visible light to pass directly through them. After identifying the alignment marks, the lithography machine uses their position as a reference to precisely align the circuit pattern on the photomask with the wafer. Once aligned, the lithography machine exposes the front of the wafer, transferring the pattern from the photomask onto the photoresist on the front of the wafer, thus completing the front-side lithography of the wafer.

[0063] S630, The wafer is flipped over, and the lithography machine identifies the alignment mark from the back of the wafer to perform lithography on the back of the wafer.

[0064] Specifically, after photolithography is completed on the front side of the wafer, the wafer is flipped over. Using the same set of through-type alignment marks as an alignment reference, photolithography exposure is performed on the back side of the wafer, thereby achieving high-precision overlay of the front and back patterns. After the front side photolithography is completed, the wafer is removed from the lithography machine stage and flipped over. The lithography machine identifies the same through-type alignment marks on the back side of the wafer. After alignment, the lithography machine exposes the back side of the wafer, transferring the back pattern from the photomask to the photoresist on the back side of the wafer. After exposure, subsequent processes such as development and etching can be performed, ultimately forming the desired pattern structure on both the front and back sides of the wafer.

[0065] The wafer double-sided alignment photolithography method provided in this embodiment of the invention uses the same alignment mark on the front and back sides of the wafer. The relative positional relationship between the front and back patterns is determined by the alignment mark. There is no cumulative error introduced by the conversion of the alignment mark or the separate production of different marks. The wafer alignment reliability is high, the alignment accuracy of the photolithography process is improved, and the alignment error caused by different alignment marks during the photolithography process is avoided, which significantly improves the photolithography accuracy of the wafer.

[0066] This invention also provides a wafer for fabricating alignment marks using the wafer alignment mark fabrication method provided in any of the above embodiments, which has the beneficial effects of the wafer alignment mark fabrication method provided in any of the above embodiments, and will not be repeated here.

[0067] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for fabricating alignment marks on a wafer, characterized in that, include: The wafer is cleaned; Determine the shape and position of the alignment marks on the wafer; Based on the shape and position of the alignment mark on the wafer, a plasma deep silicon etching process or a laser drilling process is used to vertically etch through the wafer to form a vertically penetrating alignment mark on the wafer body.

2. The method for making alignment marks according to claim 1, characterized in that, When the plasma deep silicon etching process is used to vertically etch the wafer, the alignment mark is formed on the wafer by using either plasma deep silicon etching or laser drilling, depending on the shape and position of the alignment mark. This process involves forming vertically penetrating alignment marks on the wafer body, including: An alignment mark pattern is formed in the non-device effective area of ​​the wafer according to the shape of the alignment mark and its position on the wafer; The alignment mark pattern is used to vertically etch the wafer using the plasma deep silicon etching process, forming a vertical alignment mark on the wafer body.

3. The method for making alignment marks according to claim 2, characterized in that, The step of forming an alignment mark pattern in the non-device effective area of ​​the wafer according to the shape and position of the alignment mark on the wafer includes: A hard mask layer is formed on the surface of the wafer; Photoresist is coated on the surface of the hard mask layer, and the alignment mark pattern is formed on the photoresist by exposure and development.

4. The method for making alignment marks according to claim 3, characterized in that, The step of vertically etching the wafer using the plasma deep silicon etching process according to the alignment mark pattern to form a vertically continuous alignment mark on the wafer body includes: The hard mask layer is etched using the alignment mark pattern to transfer the alignment mark pattern into the hard mask layer, and the photoresist layer is removed. The wafer is etched using a plasma deep silicon etching process, and the hard mask layer is removed to form a through-type alignment mark on the wafer body.

5. The method for making alignment marks according to claim 4, characterized in that, The plasma deep silicon etching process includes an etching stage and a passivation stage, wherein the etching stage and the passivation stage are performed alternately.

6. The method for making alignment marks according to claim 1, characterized in that, When vertically etching the wafer using laser drilling, the alignment mark is formed on the wafer by using either plasma deep silicon etching or laser drilling, depending on the shape and position of the alignment mark. This process creates a vertically penetrating alignment mark on the wafer body. A protective liquid is applied to the surface of the wafer; The wafer is slotted by laser drilling and the protective solution is cleaned to form vertical alignment marks on the wafer body.

7. The method for making alignment marks according to claim 1, characterized in that, The alignment mark may be one or more, and the shape of the alignment mark may include a cross-shaped through hole, a rectangular through hole, or a circular through hole.

8. The method for making alignment marks according to claim 1, characterized in that, Visible light can pass directly through the alignment mark.

9. A photolithography method for double-sided alignment of a wafer, characterized in that, include: A wafer is provided, and alignment marks are formed on the wafer by the method for fabricating alignment marks according to any one of claims 1-8; The wafer is placed face up in a lithography machine, which identifies the alignment marks from the front side of the wafer to perform lithography on the front side of the wafer. The wafer is flipped over, and the lithography machine identifies the alignment marks from the back side of the wafer to perform lithography on the back side of the wafer.

10. A wafer, characterized in that, Alignment marks are fabricated on the wafer using the method for fabricating alignment marks according to any one of claims 1-8.

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