Low-dropout linear voltage regulator and electronic device

Abstract

The application discloses a low-dropout linear voltage regulator and electronic equipment. The low-dropout linear voltage regulator is provided with a first transient response acceleration circuit and a second transient response acceleration circuit, which respectively provide an acceleration current to a control end of a power tube according to a first sensing current and a second sensing current; and a transistor size for transmitting the second sensing current in a second feedback branch is greater than a corresponding transistor size in a first feedback branch. Thus, the two feedback branches can respectively adapt to a smaller sensing current and a larger sensing current, so that the power tube can change the conduction state quickly when the load changes from light load to heavy load.

Description

Technical Field

[0001] This invention relates to the field of power management circuits, and particularly to a low dropout linear regulator and electronic device. Background Technology

[0002] Low dropout linear regulators are typically integrated into power management chips to convert input voltage into a stable output voltage. A typical low dropout linear regulator includes a power transistor and a main regulation loop. The main regulation loop adjusts the control voltage of the power transistor based on the relationship between the reference voltage and the output feedback voltage, thereby changing the transistor's conduction level and maintaining the output voltage within a predetermined range.

[0003] The load on a low-dropout linear regulator can change rapidly between small and large load currents. When the load current changes, the potential at the control terminal of the power transistor needs to be adjusted accordingly to regulate the current supplied by the power transistor to the load. Due to the parasitic capacitance at the control terminal of the power transistor and the limitation of the response speed of the main regulation loop by factors such as loop bandwidth, the conduction state of the power transistor may not change in time with the load change, causing the output voltage to overshoot, undershoot, or require a long time to recover stability.

[0004] For low-dropout linear regulators with a wide load current range, the requirements for current transfer devices differ depending on the load range. Therefore, existing low-dropout linear regulators struggle to achieve transient response across a wide load range. Summary of the Invention

[0005] The purpose of this invention is to provide a low-dropout linear regulator and electronic device to solve the problem that existing low-dropout linear regulators are unable to take into account transient response over a wide load range.

[0006] In a first aspect, this application provides a low-dropout linear regulator, including an input terminal, an output terminal, a power transistor, a main regulating loop, a first transient response acceleration circuit, and a second transient response acceleration circuit. The power transistor is connected between the input terminal and the output terminal. The main regulating loop is connected to both the output terminal and the control terminal of the power transistor, and is used to control the power transistor based on the feedback voltage and reference voltage at the output terminal. The first transient response acceleration circuit includes a first current sensing transistor and a first feedback branch. The first current sensing transistor is connected to the power transistor and is used to generate a first induced current based on the current flowing through the power transistor. The first feedback branch is used to provide a first acceleration current to the control terminal of the power transistor based on the first induced current. The second transient response acceleration circuit includes a second current sensing transistor and a second feedback branch. The second current sensing transistor is connected to the power transistor and is used to generate a second induced current based on the current flowing through the power transistor. The second feedback branch is used to provide a second acceleration current to the control terminal of the power transistor based on the second induced current. The size of the transistor in the second feedback branch used to transmit the second induced current is larger than the size of the transistor in the first feedback branch used to transmit the first induced current.

[0007] Secondly, this application provides an electronic device including any of the aforementioned low-dropout linear regulators.

[0008] This application includes a first transient response acceleration circuit and a second transient response acceleration circuit. These two circuits generate a first induced current and a second induced current based on the current flowing through the power transistor, respectively, and provide the first accelerating current and the second accelerating current to the control terminal of the power transistor. The transistor in the first feedback branch is suitable for transmitting a smaller induced current, while the transistor in the second feedback branch is larger and capable of transmitting a larger induced current. Therefore, the first and second feedback branches can jointly adjust the control terminal of the power transistor within different load ranges, reducing overshoot, undershoot, and recovery time of the output voltage after load changes. Attached Figure Description

[0009] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. The drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings.

[0010] Figure 1 A structural block diagram of a low-dropout linear regulator provided in this application;

[0011] Figure 2 A circuit diagram of a comparative low-dropout linear regulator provided in this application;

[0012] Figure 3 A circuit diagram of a low-dropout linear regulator provided in this application;

[0013] Figure 4A simulation waveform of the output voltage when the load current changes from light load to heavy load, provided in this application;

[0014] Figure 5 The output voltage simulation waveform diagram provided in this application is shown when the load current changes from heavy load to light load. Detailed Implementation

[0015] This invention provides a low dropout linear regulator and electronic device to solve the problem that existing low dropout linear regulators are unable to achieve transient response over a wide load range.

[0016] To make the objectives and technical solutions of the embodiments of the present invention clearer, the embodiments of the present invention will be fully described below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, not all embodiments. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention.

[0017] like Figure 1 As shown, in a first aspect, this application provides a low dropout linear regulator, including an input terminal, an output terminal, a power transistor Mn, a main voltage regulator loop 50, a first transient response acceleration circuit 10, and a second transient response acceleration circuit 20.

[0018] The power transistor Mn is connected between the input terminal and the output terminal;

[0019] The voltage regulation main loop 50 is connected to the output terminal and the control terminal of the power transistor Mn respectively, and is used to control the power transistor Mn according to the feedback voltage and reference voltage of the output terminal;

[0020] The first transient response acceleration circuit 10 includes a first current detection transistor Msen_1 and a first feedback branch 30. The first current detection transistor Msen_1 is connected to the power transistor Mn and is used to generate a first induced current based on the current flowing through the power transistor Mn. The first feedback branch 30 is used to provide a first acceleration current to the control terminal of the power transistor Mn based on the first induced current.

[0021] The second transient response acceleration circuit 20 includes a second current detection transistor Msen_2 and a second feedback branch 40. The second current detection transistor Msen_2 is connected to the power transistor Mn and is used to generate a second induced current based on the current flowing through the power transistor Mn. The second feedback branch 40 is used to provide a second acceleration current to the control terminal of the power transistor Mn based on the second induced current.

[0022] The size of the transistor in the second feedback branch 40 used to transmit the second induced current is larger than the size of the transistor in the first feedback branch 30 used to transmit the first induced current.

[0023] like Figure 2 As shown, the red portion represents a single first transient response acceleration circuit 10. The first current sensing transistor Msen_1 generates a first induced current based on the current flowing through the power transistor Mn. This induced current is transmitted through the branch containing the first transistor M1 to the seventh transistor M7 and acts on the control terminal of the power transistor Mn to accelerate the charging or discharging of the control terminal. When the load current is small, this light-load transient response acceleration circuit can respond quickly to load changes; however, when the load current increases, the first transistor M1 to the seventh transistor M7 may not be able to maintain normal operation due to insufficient operating voltage space, thus weakening the effect of the acceleration circuit in the heavy-load range. Figure 3 As shown, the red part is the first transient response acceleration circuit 10, i.e., the light-load transient response acceleration circuit; the blue part is the second transient response acceleration circuit 20, i.e., the heavy-load transient response acceleration circuit. The light-load transient response acceleration circuit provides a first accelerating current to the control terminal of the power transistor Mn based on the first induced current. The heavy-load transient response acceleration circuit provides a second accelerating current to the control terminal of the power transistor Mn based on the second induced current generated by the second current detection transistor Msen_2. Both acceleration circuits remain connected. Within the light-load range, the first accelerating current plays a major role, while the second accelerating current is relatively small. As the load current increases, the effect of the light-load transient response acceleration circuit gradually weakens, while the second accelerating current provided by the heavy-load transient response acceleration circuit increases and begins to play a major role, thus adapting to transient changes within different load ranges. Figure 3 As shown, the input terminal is used to receive the input voltage VIN_LDO, and the output terminal is used to provide the output voltage VOUT to the load. The power transistor Mn is connected between the input and output terminals. The control terminal of the power transistor Mn forms the gate control node VG, and the conduction level of the power transistor Mn changes with the potential of the gate control node VG.

[0024] The main voltage regulator loop 50 receives a reference voltage VREF0P5V and a feedback voltage VFB obtained from the output voltage VOUT. The main voltage regulator loop 50 changes the potential of the gate control node VG based on the difference between the reference voltage and the feedback voltage, keeping the output voltage VOUT near the corresponding target value. In this embodiment, the main voltage regulator loop 50 can be formed using a differential input branch, a current mirror branch, a cascaded transistor branch, and an output drive branch. The specific number of transistors, bias voltage, and compensation capacitor in the main voltage regulator loop 50 can be determined based on the input voltage, output voltage, and loop stability conditions; this application is not limited to any particular connection of the main voltage regulator loop 50.

[0025] The first transient response acceleration circuit 10 is connected to the power transistor Mn and generates a first induced current based on the current flowing through the power transistor Mn. The first feedback branch 30 receives the first induced current and provides a first acceleration current to the gate control node VG. When the load current changes, the first induced current changes accordingly, and the first feedback branch 30 charges or discharges the gate control node VG, causing the conduction level of the power transistor Mn to change before the main voltage regulator loop 50 completes subsequent regulation. The first feedback branch 30 can use a smaller transistor, resulting in a smaller parasitic capacitance inside the branch, thus making it suitable for transmitting a small-amplitude first induced current under light load conditions.

[0026] The second transient response acceleration circuit 20 is connected to the power transistor Mn and generates a second induced current based on the current flowing through the power transistor Mn. The second feedback branch 40 receives the second induced current and provides a second acceleration current to the gate control node VG. The transistor in the second feedback branch 40 used to transmit the second induced current is larger than the transistor in the first feedback branch 30 used to transmit the first induced current, so that the second feedback branch 40 still has sufficient current transmission capability and operating voltage margin when the second induced current is large.

[0027] In some embodiments, the size of the transistor can be expressed by the channel width, parallel exponent, or equivalent channel width-to-length ratio. The transistor in the first feedback branch 30 may, but is not limited to, have a channel width-to-length ratio of 2μm / 400nm or 4μm / 400nm, and the corresponding transistor in the second feedback branch 40 may, but is not limited to, have a channel width-to-length ratio of 64μm / 400nm. These dimensions are merely approximations, and the requirement is that the size of the corresponding transistor in the second feedback branch 40 is not less than N times the size of the transistor in the first feedback branch 30, where N is not less than 10. In other embodiments, other absolute sizes can be used, as long as the size of the transistor in the second feedback branch 40 carrying the second induced current is larger than the size of the transistor in the first feedback branch 30 carrying the first induced current. The specific size can be determined based on the maximum load current, process node, supply voltage, and allowable chip area.

[0028] Both the first transient response acceleration circuit 10 and the second transient response acceleration circuit 20 remain connected to the control terminal of the power transistor Mn. The second transient response acceleration circuit 20 does not need to be completely turned off under light load conditions, nor is it controlled by the overcurrent detection enable signal. When the load current is small, both the first induced current and the second induced current are small. Due to its small device size and small parasitic capacitance, the first feedback branch 30 establishes a response quickly, and the first accelerating current plays a major role in the regulation process of the gate control node VG. At this time, the second feedback branch 40 is still in the on state, but the amplitude of the second accelerating current is relatively small.

[0029] As the load current gradually increases, the smaller transistor in the first feedback branch 30 may approach the boundary of its operating voltage space, limiting the variation of the first accelerating current. Simultaneously, the second induced current increases, and the larger transistor in the second feedback branch 40 can still transmit the corresponding current. The second accelerating current plays a major role in the regulation of the gate control node VG. Therefore, the two feedback branches do not rely on discrete switching signals, but rather naturally share gate regulation under different load ranges through the differences in induced current amplitude and device size.

[0030] like Figure 4 As shown in the figure, this graph illustrates the output voltage change as the load current changes from a light load state to a heavy load state. The solid curve represents the output voltage VOUT without a transient response acceleration circuit, showing a significant voltage drop after a sudden increase in load current. The dotted curve represents the output voltage VOUT when only the first transient response acceleration circuit is operating; it accelerates the response during the light load phase, but the acceleration effect weakens after entering the heavy load range. The dashed curve represents the output voltage VOUT when both the first and second transient response acceleration circuits are operating; its voltage drop is smaller, and it recovers to a stable value more quickly. Figure 4 The lower section illustrates the change in load current from near a light load value to approximately 550mA. When the load current rapidly increases from a small value to a large value, the output voltage curve without a transient response acceleration circuit exhibits a significant drop and a long recovery process. Even with only a feedback branch suitable for light loads, the output voltage still shows a noticeable deviation after entering a larger load range. When the first feedback branch 30 and the second feedback branch 40 operate together, both the drop in output voltage and the recovery time are reduced.

[0031] like Figure 5 As shown in the figure, this graph illustrates the output voltage change when the load current changes from a heavy load state to a light load state. The solid curve represents the output voltage VOUT without the transient response acceleration circuit, where a large voltage overshoot occurs after the load current suddenly decreases. The dashed curve represents the output voltage VOUT when only the first transient response acceleration circuit is operating; since the effect of the first transient response acceleration circuit is limited within the heavy load range, its suppression of voltage overshoot is relatively small. The dotted line curve represents the output voltage VOUT when both the first and second transient response acceleration circuits are operating; its voltage overshoot amplitude is small, and it can recover to a stable value relatively quickly. Figure 5 The lower curve represents the change in load current from a larger value to a smaller value. When the load current rapidly decreases from a larger value to a smaller value, the original conduction level of the power transistor Mn will cause an overshoot in the output voltage. The first and second accelerating currents together change the potential of the gate control node VG, causing the power transistor Mn to decrease its conduction level more quickly. Figure 5The output voltage curve corresponding to the dual-branch operation shown returns to a stable value more quickly. Therefore, the first transient response acceleration circuit 10 and the second transient response acceleration circuit 20 can adapt to smaller and larger induced currents respectively, enabling the low-dropout linear regulator to maintain a short transient recovery process within the example load range of 0 to 500mA.

[0032] In other embodiments, the voltage polarities of the input terminal, output terminal, and power transistor Mn can be adjusted according to the application scenario, and the power transistor Mn can be a MOSFET suitable for the corresponding power supply polarity. The first feedback branch 30 and the second feedback branch 40 can directly provide accelerating current to the control terminal of the power transistor Mn, or they can provide accelerating current to the main loop output node connected to the control terminal. As long as both feedback branches can change the control terminal potential of the power transistor Mn according to the corresponding induced current, and the size of the relevant transistor in the second feedback branch 40 is larger than the size of the relevant transistor in the first feedback branch 30, the same working process as in this embodiment can be formed.

[0033] In one exemplary embodiment, the power transistor Mn, the first current detection transistor Msen_1, and the second current detection transistor Msen_2 each include a first terminal, a second terminal, and a control terminal;

[0034] The first end of the power transistor Mn is connected to the input end of the low dropout linear regulator, and the second end of the power transistor Mn is connected to the output end of the low dropout linear regulator.

[0035] The control terminals of the first current sensing transistor Msen_1 and the second current sensing transistor Msen_2 are both connected to the control terminal of the power transistor Mn. The second terminal voltages of the first current sensing transistor Msen_1 and the second terminal voltages of the second current sensing transistor Msen_2 are the same as the second terminal voltage of the power transistor Mn.

[0036] The first induced current has a first ratio with the current flowing through the power transistor Mn, and the second induced current has a second ratio with the current flowing through the power transistor Mn, wherein the second ratio is greater than the first ratio.

[0037] In this embodiment, the first end and the second end represent the two ends of the transistor's conductive path, and the control end represents the gate used to control the current of the conductive path.

[0038] The first terminal of power transistor Mn is connected to the input terminal, and the second terminal of power transistor Mn is connected to the output terminal. Figure 3In the N-type power transistor implementation shown, the first terminal of the power transistor Mn is connected to the input voltage VIN_LDO, the second terminal is connected to the output voltage VOUT, and the control terminal is connected to the gate control node VG. For implementations using other transistor types, the first and second terminals can correspond to different source-drain terminal names depending on the direction of the conduction current, but the power transistor Mn is still located between the input and output terminals.

[0039] The control terminals of both the first current sensing transistor Msen_1 and the second current sensing transistor Msen_2 are connected to the control terminal of the power transistor Mn, therefore all three transistors receive the same gate control voltage. The second terminal voltages of both the first and second current sensing transistors Msen_1 and Msen_2 are the same as the second terminal voltage of the power transistor Mn. In this embodiment, the second terminals of all three transistors are at the potential corresponding to the output voltage VOUT, making them have the same or similar gate-source voltages.

[0040] The first current sensing transistor Msen_1 and the second current sensing transistor Msen_2 can use the same transistor type and channel length as the power transistor Mn, with size differences created by channel width or parallel exponents. When the gate voltage and related terminal voltages are the same or close, the induced current flowing through the sensing transistors corresponds to the current flowing through the power transistor Mn according to the device size relationship. Therefore, the sensing transistors do not need to be connected in series in the main output path of the power transistor Mn to obtain the induced current representing the load current change.

[0041] The first induced current has a first ratio to the current flowing through the power transistor Mn, and the second induced current has a second ratio to the current flowing through the power transistor Mn, the second ratio being greater than the first ratio. In one specific embodiment, the dimensions of the first current sensing transistor Msen_1, the power transistor Mn, and the second current sensing transistor Msen_2 are in a ratio of 1:640:5, the first induced current is approximately 1 / 640 of the power transistor current, and the second induced current is approximately 5 / 640 of the power transistor current. This ratio is used to illustrate one feasible value and is not intended to exclude other ratios.

[0042] Taking an increase in load current from 0 to 50mA as an example, the magnitude of the first induced current can be in the range of 0 to approximately 80μA. The smaller first feedback branch 30 can transmit this current and change the gate control node VG more quickly. When the load current expands to around 500mA, the magnitude of the first induced current can reach approximately 800μA, and the smaller transistor in the first feedback branch 30 may lack sufficient operating voltage headroom. The second ratio is greater than the first ratio, making the second induced current more sensitive to heavy load changes, and it is transmitted by the larger second feedback branch 40.

[0043] In other embodiments, the first ratio and the second ratio can be determined based on the maximum output current of the power transistor Mn, the transmittable current of the first feedback branch 30 and the second feedback branch 40, and the allowable quiescent current. For example, the ratio can be changed by altering the parallel exponent of the first current sensing transistor Msen_1 and the second current sensing transistor Msen_2, or a current mirror ratio can be set after the sensing transistors to change the current fed into the corresponding feedback branch. Regardless of the method used, the second ratio remains greater than the first ratio, so that the second induced current received by the second feedback branch 40 is suitable for representing a larger load current.

[0044] The first current sensing transistor Msen_1 and the second current sensing transistor Msen_2 can be arranged near the power transistor Mn, using the same orientation and adjacent process regions to reduce the impact of temperature and manufacturing deviations on the current ratio. In some embodiments, the sensing transistors and the power transistor can share the gate interconnect and the output metal interconnect. In other embodiments, separate metal interconnects can be provided and connected at circuit nodes. All the above arrangements maintain the correspondence between the control terminal voltage and the second terminal voltage.

[0045] Through the aforementioned terminal relationships, the first induced current and the second induced current can change synchronously with the output current of the power transistor Mn without increasing a large series voltage drop in the main output path. The second ratio is greater than the first ratio, so that the first feedback branch 30 and the second feedback branch 40 receive induced currents of different magnitudes, thereby cooperating with the transistor size difference in Embodiment 1, so that the two feedback branches can adapt to light load and heavy load conditions respectively.

[0046] In one exemplary embodiment, the first feedback branch 30 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.

[0047] The second terminal of the first current sensing transistor Msen_1 is connected to the first terminal of the first transistor M1;

[0048] The first terminal of the second transistor M2 is connected to the output terminal, and the second terminal of the second transistor M2 is connected to the control terminal of the second transistor M2, the control terminal of the first transistor M1, and the first terminal of the fourth transistor M4, respectively.

[0049] The second terminal of the first transistor M1 is connected to the first terminal of the third transistor M3, the control terminal of the third transistor M3, the control terminal of the fourth transistor M4, and the control terminal of the fifth transistor M5, respectively.

[0050] The second terminal of the third transistor M3, the second terminal of the fourth transistor M4, and the second terminal of the fifth transistor M5 are all grounded;

[0051] The first terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6, the control terminal of the sixth transistor M6, and the control terminal of the seventh transistor M7, respectively.

[0052] The first terminal of the sixth transistor M6 and the first terminal of the seventh transistor M7 are both connected to the power supply terminal, and the second terminal of the seventh transistor M7 is connected to the control terminal of the power transistor Mn.

[0053] In this embodiment, the second terminal of the first current sensing transistor Msen_1 is connected to the first terminal of the first transistor M1. The first terminal of the second transistor M2 is connected to the output terminal, and the second terminal of the second transistor M2 is connected to the control terminal of the second transistor M2, the control terminal of the first transistor M1, and the first terminal of the fourth transistor M4. The second transistor M2 forms a reference node by connecting its control terminal to its second terminal, and provides the node potential to the control terminal of the first transistor M1.

[0054] The second terminal of the first transistor M1 is connected to the first terminal of the third transistor M3, the control terminal of the third transistor M3, the control terminal of the fourth transistor M4, and the control terminal of the fifth transistor M5, respectively. The control terminal of the third transistor M3 is connected to the first terminal, and the third transistor M3 and the fourth transistor M4 are driven by the same control potential. The second terminals of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all grounded.

[0055] The third transistor M3 and the fourth transistor M4 can form a current mirror branch to provide corresponding current between the relevant nodes of the first transistor M1 and the second transistor M2. The first transistor M1 and the second transistor M2 change the potential of the relevant nodes according to the output terminal potential and the first induced current, thereby limiting the operating terminal potential of the first current detection transistor Msen_1. As a result, the first current detection transistor Msen_1 can obtain the first induced current in a first proportion within the light load range.

[0056] The control terminal of the fifth transistor M5 receives the potential of the current mirror node where the third transistor M3 and the fourth transistor M4 are located. The first terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6, the control terminal of the sixth transistor M6, and the control terminal of the seventh transistor M7, respectively. The fifth transistor M5 converts the change in the current of the preceding stage into a change in the control potential of the sixth transistor M6 and the seventh transistor M7.

[0057] The first terminals of both the sixth transistor M6 and the seventh transistor M7 are connected to the power supply terminal, and the second terminal of the seventh transistor M7 is connected to the control terminal of the power transistor Mn. The control terminal of the sixth transistor M6 is connected to the second terminal to generate the control potential of the seventh transistor M7. The seventh transistor M7 provides a first accelerating current to the gate control node VG according to this control potential.

[0058] When the load current suddenly increases, the first induced current obtained by the first current sensing transistor Msen_1 increases, and the current and potential of the nodes where the first transistor M1 to the fifth transistor M5 are located change accordingly. The sixth transistor M6 and the seventh transistor M7 change the charging and discharging current of the gate control node VG, causing the power transistor Mn to change towards the conducting state of increasing output current. When the load current suddenly decreases, the above nodes change in the opposite direction, causing the power transistor Mn to change towards the state of decreasing output current. The specific direction of potential rise or fall is determined by the conduction type of the power transistor and the feedback transistor.

[0059] In one specific embodiment, the dimensions of the first transistor M1 and the second transistor M2 can be 4μm / 400nm, the dimensions of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 can be 2μm / 400nm, and the dimensions of the sixth transistor M6 and the seventh transistor M7 can be 4μm / 400nm. These smaller dimensions result in a smaller internal parasitic capacitance in the first feedback branch 30, making it suitable for fast response under light load conditions.

[0060] In other embodiments, the channel widths of the first transistor M1 through the seventh transistor M7 can be varied by the same multiple, or the required equivalent width can be formed by connecting multiple identical transistor units in parallel. The third transistor M3 and the fourth transistor M4 can be the same size, or they can be set according to a predetermined mirror ratio. The ratio of the sixth transistor M6 to the seventh transistor M7 can be determined based on the first accelerating current required by the gate control node VG.

[0061] When the load current increases to a heavier range, one or more of the first transistor M1 to the fourth transistor M4 may no longer be able to maintain their original operating range, and the transmission relationship of the first induced current weakens accordingly. This state is not caused by the control signal actively shutting down the first feedback branch 30, but is determined by the operating voltage space of the smaller device under a larger induced current. At this time, the second feedback branch 40 continues to provide the second accelerating current, thereby compensating for the current transmission limitation of the first feedback branch 30 in the heavy load range.

[0062] In one exemplary embodiment, the second transient response acceleration circuit 20 further includes an analog buffer, an eighth transistor M8, and a first bias current transistor;

[0063] The second terminal of the second current sensing transistor Msen_2 is connected to the output terminal of the low dropout linear regulator, and the first terminal of the second current sensing transistor Msen_2 is connected to the first input terminal of the analog buffer buff and the second terminal of the eighth transistor M8, respectively.

[0064] The second input terminal of the analog buffer buff is connected to the input terminal of the low dropout linear regulator, and the output terminal of the analog buffer buff is connected to the control terminal of the eighth transistor M8.

[0065] The first bias current transistor is connected between the second terminal of the eighth transistor M8 and ground, and the control terminal of the first bias current transistor is used to receive the bias voltage.

[0066] The analog buffer buff is used to control the eighth transistor M8 based on the first terminal voltage of the second current sensing transistor Msen_2 and the voltage of the input terminal, so that the first terminal voltage of the second current sensing transistor Msen_2 follows the voltage of the input terminal of the low dropout linear regulator.

[0067] In this embodiment, the second input terminal of the analog buffer is connected to the input terminal of the low-dropout linear regulator, receiving the input voltage VIN_LDO. The output terminal of the analog buffer is connected to the control terminal of the eighth transistor M8. The analog buffer detects the difference between the voltage at the first terminal of the second current sensing transistor Msen_2 and the input voltage VIN_LDO, and changes the potential of the control terminal of the eighth transistor M8 according to this difference.

[0068] The first bias current transistor is connected between the second terminal of the eighth transistor M8 and ground, and its control terminal receives the bias voltage vbn. The first bias current transistor provides bias current in the second current sensing branch, ensuring that the analog buffer buff and the eighth transistor M8 maintain a defined DC operating point even when the load current is small. The magnitude of the bias current can be determined based on the output range of the analog buffer, the transconductance of the eighth transistor M8, and the range of the second induced current.

[0069] The control terminal voltages of the power transistor Mn, the first current sensing transistor Msen_1, and the second current sensing transistor Msen_2 are the same, and their second terminal voltages are also the same. If the first terminal voltage of the second current sensing transistor Msen_2 is different from that of the power transistor Mn, then the voltage between their first and second terminals will be different. Even if the gate control voltage is the same, their conduction current may still deviate from the device size relationship due to factors such as channel length modulation.

[0070] The analog buffer (buff) and the eighth transistor (M8) form a closed-loop regulation. When the voltage at the first terminal of the second current sensing transistor (Msen_2) is lower than the input voltage (VIN_LDO), the analog buffer (buff) changes the control terminal potential of the eighth transistor (M8), causing a change in the current action of the eighth transistor (M8) on that node, pushing the node voltage closer to the input voltage (VIN_LDO). When the node voltage is higher than the input voltage (VIN_LDO), the regulation direction is reversed. After stabilization, the voltage at the first terminal of the second current sensing transistor (Msen_2) follows the input voltage.

[0071] In this embodiment, the first terminal of the second current sensing transistor Msen_2 corresponds to the sensing terminal that needs to be clamped, the input voltage VIN_LDO is the clamping reference voltage, and the eighth transistor M8 corresponds to the controlled current regulating device. Therefore, the control terminal voltage, the second terminal voltage, and the first terminal voltage of the second current sensing transistor Msen_2 and the power transistor Mn are all the same or close, and the second induced current can change according to the dimensional relationship between the second current sensing transistor Msen_2 and the power transistor Mn.

[0072] In some embodiments, the analog buffer can be formed using a differential input amplifier circuit and an output driving transistor, with the first input terminal and the second input terminal receiving the regulated node voltage and the reference node voltage, respectively. In other embodiments, the analog buffer can be a transconductance amplifier circuit, provided that its output can continuously control the eighth transistor M8 according to the difference between the two input voltages, so that the voltage at the first terminal of the second current sensing transistor Msen_2 follows the input voltage.

[0073] The first bias current transistor can be a single MOSFET controlled by the bias voltage, or it can be a current source branch composed of multiple transistors. If multiple transistors are used, the output resistance can be increased by connecting them in a common-source, common-gate configuration; if the supply voltage margin is small, a single transistor connection can also be used. Regardless of the specific form used, the first bias current transistor is used to establish the bias current in the branch containing the eighth transistor M8, rather than to selectively turn the second feedback branch 40 on or off.

[0074] The second transient response acceleration circuit 20 is always on. When the load current is small, the second induced current generated by the second current detection transistor Msen_2 is small, the analog buffer buff maintains the detection terminal voltage, and the second feedback branch 40 outputs a small second acceleration current. When the load current increases, the second induced current increases accordingly, and the eighth transistor M8 continues to maintain the detection terminal voltage under closed-loop control. The subsequent second feedback branch 40 receives the second induced current that can represent the change in heavy load current.

[0075] By simulating the buffer buff, the eighth transistor M8 and the first bias current transistor, the second current sensing transistor Msen_2 maintains the corresponding terminal voltage condition over a wide load range, reduces the deviation of the sensing current caused by the difference in the first terminal voltage, and enables the subsequent second feedback branch 40 to adjust the control terminal of the power transistor Mn according to the second induced current.

[0076] In one exemplary embodiment, the second feedback branch 40 includes a ninth transistor M9 and an eleventh transistor M11;

[0077] The first terminal of the eighth transistor M8 is connected to the second terminal of the ninth transistor M9, the control terminal of the ninth transistor M9, and the control terminal of the eleventh transistor M11, respectively.

[0078] The first terminal of the ninth transistor M9 and the first terminal of the eleventh transistor M11 are both connected to the power supply terminal.

[0079] The second terminal of the eleventh transistor M11 is connected to the control terminal of the power transistor Mn, and is used to output the second accelerating current according to the current mirror control signal generated by the ninth transistor M9.

[0080] In this embodiment, the control terminal of the ninth transistor M9 is connected to the second terminal, enabling the ninth transistor M9 to establish the potential of the mirror control node based on the second induced current transmitted by the eighth transistor M8. The control terminal of the eleventh transistor M11 is connected to the same mirror control node, therefore the eleventh transistor M11 generates a corresponding mirror current according to its size relationship with the ninth transistor M9.

[0081] The first terminal of the ninth transistor M9 and the first terminal of the eleventh transistor M11 are both connected to the power supply terminal. Figure 3 In the illustrated embodiment, the power supply terminal is VDD2P5V. The second terminal of the eleventh transistor M11 is connected to the control terminal of the power transistor Mn. The mirror current output by the eleventh transistor M11 forms the second accelerating current I_TRAN_BST and is sent to the gate control node VG.

[0082] When the load current increases, the second induced current of the second current sensing transistor Msen_2 increases, and the eighth transistor M8 transfers the corresponding current to the ninth transistor M9, causing the potential of the mirror control node to change accordingly. The second accelerating current output by the eleventh transistor M11 increases, causing the potential of the gate control node VG to change more quickly, and the current supplied by the power transistor Mn to the load increases.

[0083] When the load current decreases, the second induced current and the mirror control node potential change in opposite directions. The current effect of the eleventh transistor M11 on the gate control node VG decreases or changes accordingly, causing the power transistor Mn to reduce the current supplied to the output terminal. The specific charging and discharging directions are determined based on the conductivity types of the eleventh transistor M11 and the power transistor Mn. In this embodiment... Figure 3 The conductivity type shown is an example.

[0084] The branch containing the eleventh transistor M11 is always on, unaffected by the overcurrent detection enable signal EN_OC, and does not switch between on and off based on EN_OC. Under light load conditions, the second induced current is small, and the eleventh transistor M11 outputs a small second accelerating current; under heavy load conditions, the second induced current increases, and the eleventh transistor M11 outputs a larger second accelerating current. This continuous variation allows the second feedback branch 40 to gradually assume a larger gate regulation function according to the load current.

[0085] In one specific embodiment, the ninth transistor M9 and the eleventh transistor M11 can both have a size of 64μm / 400nm. This size is larger than the transistor size of 2μm / 400nm or 4μm / 400nm in the first feedback branch 30, enabling the ninth transistor M9 and the eleventh transistor M11 to continue operating under a larger second induced current.

[0086] In other embodiments, the ninth transistor M9 and the eleventh transistor M11 can be the same size, so that the second accelerating current is formed in a one-to-one relationship with the input current in the ninth transistor M9. Alternatively, they can be set to different sizes, so that the second accelerating current is amplified or reduced according to a predetermined ratio. The ninth transistor M9 and the eleventh transistor M11 can also be formed by multiple identical transistor cells connected in parallel to maintain cell consistency in the layout.

[0087] The second feedback branch 40 can also include a current-limiting transistor or a switching transistor between the second terminal of the eleventh transistor M11 and the gate control node VG, but this additional device does not change the relationship between the eleventh transistor M11 and the output of the second accelerating current according to the mirror control node. When the supply voltage space allows, the ninth transistor M9 and the eleventh transistor M11 can be connected with increased output resistance. When the supply voltage space is limited, a different configuration can be used. Figure 3 The simple current mirror connection is shown.

[0088] Thus, the eighth transistor M8 completes the transmission of the second induced current, the ninth transistor M9 forms a mirror control node, and the eleventh transistor M11 outputs the second accelerating current to the control terminal of the power transistor Mn. This current path enables the second transient response acceleration circuit 20 to directly change the charging and discharging process of the gate control node VG under heavy load conditions.

[0089] In one exemplary embodiment, the low-dropout linear regulator further includes an overcurrent detection enable branch and an overcurrent detection circuit.

[0090] The overcurrent detection enable branch is connected to the second transient response acceleration circuit 20 and is used to generate an overcurrent detection enable signal EN_OC based on the second induced current.

[0091] The overcurrent detection circuit is connected to the overcurrent detection enable branch and is used to start when the overcurrent detection enable signal EN_OC is valid, and to perform overcurrent detection based on the second induced current.

[0092] In this embodiment, the second induced current can represent the load current flowing through the power transistor Mn, and the second ratio is greater than the first ratio. Therefore, current information suitable for overload judgment can be obtained in the second transient response acceleration circuit 20. The overcurrent detection enable branch reuses this current information, eliminating the need to connect a separate sampling resistor in the main output path of the power transistor Mn, thereby avoiding additional output voltage drop.

[0093] The overcurrent detection enable signal EN_OC indicates that the load current has entered the range requiring overcurrent detection. EN_OC being active does not equate to an overcurrent event, nor does it directly control the second acceleration output branch containing the eleventh transistor M11. The eleventh transistor M11 remains on and continues to output the second acceleration current, while the overcurrent detection circuit begins comparing the corresponding detection voltage after EN_OC becomes active.

[0094] When the load current is small, the second induced current is less than the startup condition corresponding to the overcurrent detection enable branch, EN_OC remains invalid, and the overcurrent detection circuit can be in a non-operating or low-current state. Therefore, the complete overcurrent comparison branch does not need to continuously consume operating current during light load periods. As the load current increases, the second induced current reaches the startup condition, EN_OC becomes valid, and the overcurrent detection circuit enters the operating state.

[0095] The overcurrent detection circuit receives the overcurrent detection current generated by the second induced current and converts this current into at least two detection voltages for comparison. When the two detection voltages maintain a normal magnitude relationship, the overcurrent detection circuit outputs a state indicating that no overcurrent has occurred; when the load current continues to increase and reaches the overcurrent threshold, the magnitude relationship between the two detection voltages changes, and the overcurrent detection circuit outputs a valid overcurrent status signal OC_STATUS.

[0096] EN_OC corresponds to the first judgment stage, used to initiate overcurrent detection. OC_STATUS corresponds to the second judgment stage, used to indicate the overcurrent detection result. The initiation current of the first judgment stage can be lower than the final overcurrent threshold, allowing the overcurrent detection circuit to pre-establish an operating point when the load current approaches the overcurrent range. The two judgment stages share the current information in the second transient response acceleration circuit 20, but have different output signals and different uses.

[0097] In some embodiments, the overcurrent detection enable branch and the overcurrent detection circuit can be formed by an analog current branch, with EN_OC and OC_STATUS converted to logic levels via inverters. In other embodiments, a latch can be set after the analog compare output to keep OC_STATUS valid until the control circuit completes a reset. Whether to set a latch depends on the recovery method of the electronic device after an overcurrent event and does not change the fact that EN_OC is only used to initiate overcurrent detection.

[0098] After the overcurrent detection circuit is activated, it can continuously determine the load status based on the second induced current. If the load current decreases before reaching the final overcurrent threshold, the two detection voltages maintain a normal magnitude relationship, OC_STATUS remains invalid, and the power transistor Mn continues to be controlled by the main voltage regulator loop 50 and the two transient response acceleration circuits. If the load current reaches the overcurrent threshold, OC_STATUS becomes valid, and the subsequent control circuit performs a shutdown.

[0099] By setting the overcurrent detection enable signal and the overcurrent status signal separately, the second acceleration branch can operate continuously across the entire load range, while the overcurrent detection circuit only activates within a larger load range. This setting avoids mistaking heavy-load transient responses for overcurrent conditions and also prevents EN_OC from interfering with the normal acceleration function of the eleventh transistor M11.

[0100] In one exemplary embodiment, the second feedback branch 40 has a mirror control node for transmitting the second induced current;

[0101] The overcurrent detection enable branch includes the tenth transistor M10 and the second bias current transistor.

[0102] The first terminal of the tenth transistor M10 is connected to the power supply terminal, the control terminal of the tenth transistor M10 is connected to the mirror control node, and the second terminal of the tenth transistor M10 serves as an overcurrent detection enable terminal.

[0103] The second bias current transistor is connected between the overcurrent detection enable terminal and ground, and the control terminal of the second bias current transistor is used to receive the bias voltage.

[0104] The tenth transistor M10 generates a mirror current based on the voltage of the mirror control node. The mirror current and the bias current provided by the second bias current transistor together determine the level of the overcurrent detection enable terminal, so that the overcurrent detection enable terminal outputs the overcurrent detection enable signal EN_OC.

[0105] In this embodiment, the first terminal of the tenth transistor M10 is connected to the power supply terminal, and the second terminal of the tenth transistor M10 serves as an overcurrent detection enable terminal. The tenth transistor M10 generates a mirror current based on the voltage of the mirror control node. Since the mirror control node changes with the second induced current, the mirror current of the tenth transistor M10 also changes with the load current of the power transistor Mn.

[0106] The second bias current transistor is connected between the overcurrent detection enable terminal and ground, and its control terminal receives a bias voltage. In one specific embodiment, the control terminal of the second bias current transistor can receive the same bias voltage vbn as the control terminal of the first bias current transistor, so that the two bias branches are provided with control potentials by the same bias circuit. The second bias current transistor provides a reference current or a pull-down current at the overcurrent detection enable terminal.

[0107] The mirror current output by the tenth transistor M10 and the bias current provided by the second bias current transistor jointly determine the level of the overcurrent detection enable terminal. When the mirror current of the tenth transistor M10 is less than the reference current corresponding to the second bias current transistor, the overcurrent detection enable terminal remains at the first level, and EN_OC is invalid. When the mirror current of the tenth transistor M10 reaches or exceeds the corresponding condition, the overcurrent detection enable terminal switches to the second level, and EN_OC becomes valid.

[0108] The tenth transistor M10 and the second bias current transistor can be considered as a current comparison branch. This comparison does not require a separate differential comparator; instead, it utilizes two branches providing currents in opposite directions or of different magnitudes at the same node, causing the node potential to flip when a condition is met. An inverter or level-shaping circuit can be connected after the overcurrent detection enable terminal to obtain a logic signal suitable for controlling the overcurrent detection circuit.

[0109] In one specific embodiment, the channel size of the tenth transistor M10 can be 64μm / 400nm, and it uses the same transistor unit as the ninth transistor M9 and the eleventh transistor M11. The size and bias voltage of the second bias current transistor determine the reference current, which in turn determines the load current corresponding to the start of EN_OC. By changing the size or bias voltage of the second bias current transistor, the start point of overcurrent detection can be changed.

[0110] In other embodiments, the second bias current transistor can be replaced by a current mirror output branch that provides a fixed or adjustable reference current. The reference current can be generated by the chip's internal bias circuitry or compensated for based on process corner and temperature. Regardless of whether a single bias current transistor or a current mirror branch is used, EN_OC is determined by the reference current and the mirror current of the tenth transistor M10.

[0111] The mirror control node can also be connected to the control terminals of the eleventh transistor M11 and the subsequent twelfth transistor M12, causing the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 to generate mirror currents for overcurrent enable, transient acceleration, and overcurrent detection, respectively. The three output branches share the same mirror control node, but their output terminals are separate, so changes in the EN_OC level will not disconnect the branch containing the eleventh transistor M11.

[0112] Through the tenth transistor M10 and the second bias current transistor, the overcurrent detection enable terminal can generate EN_OC when the second induced current reaches the start-up condition. This start-up condition can be set before the final overcurrent threshold, so that the subsequent comparison branch has already entered normal operating state when an overcurrent judgment is needed.

[0113] In one exemplary embodiment, the overcurrent detection circuit includes a twelfth transistor M12, a first resistor branch, a second resistor branch, and a comparison unit.

[0114] The twelfth transistor M12 includes a first terminal, a second terminal, and a control terminal. The first terminal of the twelfth transistor M12 is connected to the power supply terminal, and the control terminal of the twelfth transistor M12 is connected to the mirror control node. The twelfth transistor M12 is used to output an overcurrent detection current according to the voltage of the mirror control node.

[0115] The first resistor branch and the second resistor branch are respectively used to generate a first detection voltage and a second detection voltage based on the overcurrent detection current;

[0116] The comparison unit is connected to the first resistor branch and the second resistor branch respectively, and is used to generate an overcurrent status signal OC_STATUS based on the magnitude relationship between the first detection voltage and the second detection voltage.

[0117] like Figure 3As shown, the twelfth transistor M12 includes a first terminal, a second terminal, and a control terminal. Its first terminal is connected to the power supply terminal, and its control terminal is connected to the mirror control node. The twelfth transistor M12 outputs an overcurrent detection current based on the voltage of the mirror control node. The mirror control node changes with the second induced current; therefore, the overcurrent detection current corresponds to the load current flowing through the power transistor Mn. In one specific embodiment, the twelfth transistor M12 can have a size of 64μm / 400nm, and its size is the same as or at a predetermined ratio to that of the ninth transistor M9.

[0118] The second terminal of the twelfth transistor M12 provides overcurrent detection current to the subsequent detection branch. Figure 3 This current can be represented as I_NET_OC. The overcurrent detection current participates in forming the first detection voltage of the first resistor branch and the second detection voltage of the second resistor branch. The first resistor branch and the second resistor branch have different equivalent resistances or different current distribution relationships, therefore the two detection voltages change differently with the overcurrent detection current.

[0119] The comparator unit is connected to the first resistor branch and the second resistor branch respectively, and receives the first and second detected voltages. The comparator unit generates an overcurrent status signal OC_STATUS based on the magnitude relationship between the two detected voltages. OC_STATUS is invalid when the two detected voltages maintain a normal magnitude relationship. OC_STATUS is valid when the magnitude relationship between the two detected voltages changes due to an increase in the overcurrent detection current.

[0120] The comparison unit may include a differential input stage, a gain output stage, and a level shaping stage. The differential input stage receives a first detection voltage and a second detection voltage, respectively, and generates an internal current or internal voltage representing the difference between the two. The gain output stage amplifies this difference. The level shaping stage converts the analog comparison result into OC_STATUS. Thus, the entire back end of M12 is an overcurrent detection circuit, which can contain both an amplification section and a comparison function.

[0121] In other embodiments, the comparator unit may employ a voltage comparator with two inputs, or an operational amplifier for comparison in open-loop mode. If the subsequent control circuitry can directly identify the analog level, a separate level shaping stage can be omitted. The specific transistor connections of the comparator unit can be determined based on the power supply voltage, the input common-mode range, and the required switching speed.

[0122] The first resistor branch and the second resistor branch can be directly connected to the second terminal of the twelfth transistor M12, or they can receive the overcurrent detection current generated by the twelfth transistor M12 through one or more current mirrors, switching transistors or bias transistors. Figure 3The back-end circuit shown can use multi-stage transistors to distribute I_NET_OC to the two detection nodes. This application primarily uses the relationship between two detection voltages formed based on the overcurrent detection current and compared by a comparison unit.

[0123] After EN_OC is enabled, the comparator and related bias branches enter the working state. At this time, the twelfth transistor M12 continuously outputs the overcurrent detection current corresponding to the second induced current. When the load current is only under heavy load but has not yet reached the overcurrent threshold, the first and second detection voltages maintain a normal relationship; when the load current continues to increase, the two detection nodes are affected by different equivalent resistances and current paths, and their magnitude relationship changes.

[0124] The twelfth transistor M12 shares a mirror control node with the eleventh transistor M11, but performs different functions. The eleventh transistor M11 provides the second accelerating current to the control terminal of the power transistor Mn, while the twelfth transistor M12 provides the overcurrent detection current to the overcurrent detection circuit. The placement of the twelfth transistor M12 does not replace the transient acceleration function of the eleventh transistor M11.

[0125] Through M12, two resistor branches, and a comparison unit, the overcurrent detection circuit converts the mirror current representing the load current into two comparable voltages and outputs OC_STATUS based on their relationship. This process enables overcurrent detection without altering the main output path of the power transistor Mn.

[0126] In one exemplary embodiment, the first resistor branch includes a plurality of resistors connected in series, and the second resistor branch includes a plurality of resistors connected in parallel, wherein the resistance values ​​of each resistor in the first resistor branch and the second resistor branch are the same.

[0127] The first ends of the first resistor branch and the second resistor branch are both connected to the power supply terminal, and the second ends of the first resistor branch and the second resistor branch are respectively connected to the two input terminals of the comparison unit.

[0128] When the current flowing through the power transistor Mn is less than the overcurrent threshold, the first detection voltage and the second detection voltage have a first magnitude relationship.

[0129] When the current flowing through the power transistor Mn reaches the overcurrent threshold, the first detection voltage and the second detection voltage have a second magnitude relationship that is different from the first magnitude relationship, and the comparison unit outputs a valid overcurrent status signal OC_STATUS;

[0130] The low-dropout linear regulator also includes a control circuit for controlling the power transistor Mn to turn off based on the valid overcurrent status signal OC_STATUS.

[0131] In this embodiment, multiple resistors in the first resistor branch are connected end-to-end, so that the equivalent resistance of the first resistor branch is the sum of the resistances of each individual resistor. In the second resistor branch, the two ends of multiple resistors are connected together, so that the equivalent resistance of the second resistor branch is less than the resistance of a single individual resistor. The first and second resistor branches can be connected in series and in parallel to achieve the desired ratio of equivalent resistance.

[0132] The first terminals of both the first and second resistor branches are connected to the power supply terminal, and the second terminals of both branches are connected to the two input terminals of the comparator unit, respectively. The second terminal of the first resistor branch forms the first detection voltage, and the second terminal of the second resistor branch forms the second detection voltage. An overcurrent detection current, or the current mirrored therefrom, acts on the two detection nodes, causing the two detection voltages to vary with the load current.

[0133] Using resistor units of the same resistance value to form series and parallel branches allows all resistors to use the same material, width, and basic layout unit, reducing proportional deviations caused by differences in size and manufacturing processes. The number of series units is increased when a larger equivalent resistance is needed, and the number of parallel units is increased when a smaller equivalent resistance is needed.

[0134] When the current flowing through the power transistor Mn is less than the overcurrent threshold, the first detection voltage and the second detection voltage have a first magnitude relationship. In one specific embodiment, the first detection voltage is less than the second detection voltage. The comparator outputs an invalid OC_STATUS based on this magnitude relationship, the control circuit does not perform overcurrent shutdown, and the power transistor Mn continues to be jointly controlled by the voltage regulation main loop 50, the first feedback branch 30, and the second feedback branch 40.

[0135] When the current flowing through the power transistor Mn reaches the overcurrent threshold, the overcurrent detection current increases, and the first and second detection voltages have a second magnitude relationship different from the first relationship. In one specific embodiment, the second detection voltage is less than the first detection voltage, that is, the magnitude order between the two detection voltages is reversed. The comparison unit outputs a valid OC_STATUS accordingly.

[0136] The control circuit turns off the power transistor Mn after receiving a valid OC_STATUS. For Figure 3 For the N-type power transistor shown, the control circuit can pull the gate control node VG to a potential that turns the power transistor off, or it can disconnect the driving of the gate control node VG by the main voltage regulator loop 50 and release the gate charge through the discharge transistor. For power transistors of other conductivity types, the control circuit drives the control terminal to the corresponding cutoff potential.

[0137] In some embodiments, the control circuit may keep power transistor Mn off while OC_STATUS is active. In other embodiments, the control circuit may re-detect the load state after a predetermined waiting time and allow power transistor Mn to resume operation after the overcurrent condition disappears. The recovery method may be determined by the control requirements of the electronic device, but in the event of an overcurrent, power transistor Mn is first turned off based on the active OC_STATUS.

[0138] The first and second magnitude relationships are not limited to fixed high and low directions, as long as they are different and can be distinguished by the comparison unit. Under different transistor polarities or resistor branch connection methods, the normal state can be that the first detection voltage is greater than the second detection voltage, and the overcurrent state can be that the first detection voltage is less than the second detection voltage. This embodiment uses the first and second magnitude relationships to cover the above-mentioned different polarities.

[0139] The overcurrent threshold can be determined by the mirror ratio of the twelfth transistor M12, the equivalent resistance of the first and second resistor branches, the relevant bias current, and the input offset of the comparator unit. During production testing, the overcurrent threshold can be changed using optional resistor units or adjustable bias current. The specific threshold should be higher than the normal heavy-load current range and lower than the dangerous current range allowed by the power transistor Mn and the load.

[0140] Therefore, the overcurrent detection enable branch first activates the overcurrent detection circuit when the load current enters a large range. M12 and the two resistor branches then form a comparable detection voltage. The comparison unit outputs OC_STATUS when the voltage relationship changes, and the control circuit turns off the power transistor Mn accordingly. This process is independent of the continuous transient acceleration process of the second feedback branch 40. Under heavy load conditions, the second feedback branch 40 can respond normally, and the shutdown is only performed when the overcurrent threshold is reached.

[0141] Secondly, this application also provides an electronic device, including the low-dropout linear regulator as described above.

[0142] Electronic devices may include a power input interface, a load circuit, and a low-dropout linear regulator. The input terminal of the low-dropout linear regulator is connected to the power input interface, and the output terminal is connected to the power supply terminal of the load circuit, used to convert the input voltage into a stable voltage required by the load circuit.

[0143] The load circuit can be a processor, memory, analog-to-digital converter, digital-to-analog converter, RF transceiver circuit, sensor interface, motor control circuit, or other circuit that generates load current that changes with operating conditions. Electronic devices can be mobile terminals, server components, vehicle control equipment, industrial control equipment, wearable devices, or sensor nodes. The above device types are only used to illustrate the usage of low-dropout linear regulators.

[0144] During electronic device operation, the load circuit can switch between standby, low-power, and operational states, causing the output current of the low-dropout linear regulator to vary between a small and a large value. The first transient response acceleration circuit 10 provides a first accelerating current to the control terminal of the power transistor Mn based on a first induced current, and the second transient response acceleration circuit 20 provides a second accelerating current to the control terminal of the power transistor Mn based on a second induced current.

[0145] When the load circuit transitions from standby to operating state, the load current increases rapidly. The first feedback branch 30 responds to the smaller induced current initially, while the second feedback branch 40 provides a larger second accelerating current as the second induced current increases. When the load circuit returns from operating state to standby state, the two feedback branches cause the power transistor Mn to decrease its conduction level more quickly, reducing output voltage overshoot.

[0146] Low-dropout linear regulators (LDLs) can be installed as independent power management chips on the circuit board of electronic devices, or they can be integrated into the same semiconductor chip as the load circuit. Multiple LDLs can be installed on the same chip to power the processor core, analog circuits, RF circuits, and memory circuits. Each LDL can employ different input / output voltage and load current ranges.

[0147] In one specific embodiment, the input voltage of the low-dropout linear regulator can be 2.5V, the reference voltage can be 0.5V, the output voltage can be set to approximately 1.1V based on the feedback resistor ratio, and the load current range can be 0 to 500mA. The above values ​​are consistent with... Figures 3 to 5 The circuit shown corresponds to the simulation conditions. In other embodiments, the input voltage, reference voltage, and feedback ratio can be varied according to the rated voltage of the load circuit.

[0148] When the electronic device adopts the overcurrent detection implementation method described above, the overcurrent detection enable branch generates EN_OC based on the second induced current. When EN_OC is valid, the overcurrent detection circuit determines whether the load current has reached the overcurrent threshold. If OC_STATUS is valid, the control circuit turns off the power transistor Mn, cutting off or limiting the continued power supply to the load circuit, thereby reducing the impact of continuous high current on the power transistor and the load circuit.

[0149] The electronic device may also include a main controller that can receive OC_STATUS and record overcurrent events. In some embodiments, the main controller re-enables the low-dropout linear regulator after a load fault has been cleared. In other embodiments, the main controller keeps the low-dropout linear regulator off until the electronic device is powered on again. The main controller's processing does not alter the internal process of the low-dropout linear regulator to turn off the power transistor Mn based on OC_STATUS.

[0150] In a low-dropout linear regulator, the power transistor Mn, the first current sensing transistor Msen_1, the second current sensing transistor Msen_2, and the first transistor M1 through the twelfth transistor M12 can be fabricated using the same semiconductor process. The resistor branches can use polysilicon resistors, diffused resistors, or metal resistors. When using identical resistor units to form series and parallel branches, each unit can be arranged adjacently on the chip and have the same surrounding environment.

[0151] By incorporating the aforementioned low-dropout linear regulator into the electronic device, the control terminal of the power transistor Mn receives an accelerating current corresponding to the load current when the load circuit varies between small and large loads. Furthermore, when the load current exceeds the allowable range, the power transistor Mn can be shut down via OC_STATUS. Therefore, this electronic device can maintain output power supply under wide load variation conditions and perform shutdown under overcurrent conditions.

[0152] For further details on the electronic equipment, please refer to the steps outlined above for the low-dropout linear regulator; these will not be repeated here.

[0153] It should also be noted that, in this specification, the terms "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily indicate a specific order between these entities or operations. The terms "include," "contain," and variations thereof indicate non-exclusive inclusion, meaning that a process, method, article, or apparatus that includes a list of elements may include not only the listed elements but also other elements not expressly listed or elements inherent to the process, method, article, or apparatus. Without further limitations, a technical solution defined by including one element does not exclude the presence of other identical elements.

[0154] The above description of the disclosed embodiments enables those skilled in the art to practice the invention. Modifications to these embodiments can be applied to other embodiments without departing from the principles and scope of the invention. Therefore, the invention is not limited to the specific embodiments shown herein, but should be accorded the scope consistent with the disclosure herein.

Claims

1. A low-dropout linear regulator, characterized in that, It includes input terminals, output terminals, power transistors, a main voltage regulator loop, a first transient response acceleration circuit, and a second transient response acceleration circuit; The power transistor is connected between the input terminal and the output terminal; The voltage regulation main loop is connected to the output terminal and the control terminal of the power transistor respectively, and is used to control the power transistor according to the feedback voltage and reference voltage of the output terminal; The first transient response acceleration circuit includes a first current detection tube and a first feedback branch. The first current detection tube is connected to the power tube and is used to generate a first induced current based on the current flowing through the power tube. The first feedback branch is used to provide a first acceleration current to the control terminal of the power tube based on the first induced current. The second transient response acceleration circuit includes a second current detection tube and a second feedback branch. The second current detection tube is connected to the power tube and is used to generate a second induced current based on the current flowing through the power tube. The second feedback branch is used to provide a second acceleration current to the control terminal of the power tube based on the second induced current. The size of the transistor used to transmit the second induced current in the second feedback branch is larger than the size of the transistor used to transmit the first induced current in the first feedback branch.

2. The low-dropout linear regulator according to claim 1, characterized in that, The power transistor, the first current detection transistor, and the second current detection transistor each include a first terminal, a second terminal, and a control terminal; The first end of the power transistor is connected to the input end of the low dropout linear regulator, and the second end of the power transistor is connected to the output end of the low dropout linear regulator. The control terminals of the first current sensing transistor and the second current sensing transistor are both connected to the control terminal of the power transistor, and the second terminal voltages of the first current sensing transistor and the second current sensing transistor are the same as the second terminal voltage of the power transistor. The first induced current has a first ratio to the current flowing through the power transistor, and the second induced current has a second ratio to the current flowing through the power transistor, wherein the second ratio is greater than the first ratio.

3. The low-dropout linear regulator according to claim 2, characterized in that, The first feedback branch includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The second end of the first current sensing tube is connected to the first end of the first transistor; The first terminal of the second transistor is connected to the output terminal, and the second terminal of the second transistor is connected to the control terminal of the second transistor, the control terminal of the first transistor, and the first terminal of the fourth transistor, respectively. The second terminal of the first transistor is connected to the first terminal of the third transistor, the control terminal of the third transistor, the control terminal of the fourth transistor, and the control terminal of the fifth transistor, respectively. The second terminal of the third transistor, the second terminal of the fourth transistor, and the second terminal of the fifth transistor are all grounded; The first terminal of the fifth transistor is connected to the second terminal of the sixth transistor, the control terminal of the sixth transistor, and the control terminal of the seventh transistor, respectively. The first terminal of the sixth transistor and the first terminal of the seventh transistor are both connected to the power supply terminal, and the second terminal of the seventh transistor is connected to the control terminal of the power transistor.

4. The low-dropout linear regulator according to claim 2, characterized in that, The second transient response acceleration circuit also includes an analog buffer, an eighth transistor, and a first bias current transistor; The second end of the second current sensing tube is connected to the output end of the low dropout linear regulator, and the first end of the second current sensing tube is connected to the first input end of the analog buffer and the second end of the eighth transistor, respectively. The second input terminal of the analog buffer is connected to the input terminal of the low dropout linear regulator, and the output terminal of the analog buffer is connected to the control terminal of the eighth transistor. The first bias current transistor is connected between the second terminal of the eighth transistor and ground, and the control terminal of the first bias current transistor is used to receive the bias voltage. The analog buffer is used to control the eighth transistor based on the first terminal voltage of the second current sensing transistor and the voltage at the input terminal, so that the first terminal voltage of the second current sensing transistor follows the voltage at the input terminal of the low dropout linear regulator.

5. The low-dropout linear regulator according to claim 4, characterized in that, The second feedback branch includes the ninth transistor and the eleventh transistor; The first terminal of the eighth transistor is connected to the second terminal of the ninth transistor, the control terminal of the ninth transistor, and the control terminal of the eleventh transistor, respectively. The first terminal of the ninth transistor and the first terminal of the eleventh transistor are both connected to the power supply terminal. The second terminal of the eleventh transistor is connected to the control terminal of the power transistor, and is used to output the second accelerating current according to the current mirror control signal generated by the ninth transistor.

6. The low-dropout linear regulator according to any one of claims 2 to 5, characterized in that, The low-dropout linear regulator also includes an overcurrent detection enable branch and an overcurrent detection circuit. The overcurrent detection enable branch is connected to the second transient response acceleration circuit and is used to generate an overcurrent detection enable signal based on the second induced current. The overcurrent detection circuit is connected to the overcurrent detection enable branch and is used to start when the overcurrent detection enable signal is valid, and to perform overcurrent detection based on the second induced current.

7. The low-dropout linear regulator according to claim 6, characterized in that, The second feedback branch has a mirror control node for transmitting the second induced current; The overcurrent detection enable branch includes a tenth transistor and a second bias current transistor. The first terminal of the tenth transistor is connected to the power supply terminal, the control terminal of the tenth transistor is connected to the mirror control node, and the second terminal of the tenth transistor serves as an overcurrent detection enable terminal. The second bias current transistor is connected between the overcurrent detection enable terminal and ground, and the control terminal of the second bias current transistor is used to receive the bias voltage. The tenth transistor generates a mirror current based on the voltage of the mirror control node. The mirror current and the bias current provided by the second bias current transistor together determine the level of the overcurrent detection enable terminal, so that the overcurrent detection enable terminal outputs the overcurrent detection enable signal.

8. The low-dropout linear regulator according to claim 7, characterized in that, The overcurrent detection circuit includes a twelfth transistor, a first resistor branch, a second resistor branch, and a comparison unit; The twelfth transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the twelfth transistor is connected to the power supply terminal, and the control terminal of the twelfth transistor is connected to the mirror control node. The twelfth transistor is used to output an overcurrent detection current according to the voltage of the mirror control node. The first resistor branch and the second resistor branch are respectively used to generate a first detection voltage and a second detection voltage based on the overcurrent detection current; The comparison unit is connected to the first resistor branch and the second resistor branch respectively, and is used to generate an overcurrent state signal based on the magnitude relationship between the first detection voltage and the second detection voltage.

9. The low-dropout linear regulator according to claim 8, characterized in that, The first resistor branch includes multiple resistors connected in series, and the second resistor branch includes multiple resistors connected in parallel. The resistance values ​​of each resistor in the first resistor branch and the second resistor branch are the same. The first ends of the first resistor branch and the second resistor branch are both connected to the power supply terminal, and the second ends of the first resistor branch and the second resistor branch are respectively connected to the two input terminals of the comparison unit. When the current flowing through the power transistor is less than the overcurrent threshold, the first detection voltage and the second detection voltage have a first magnitude relationship. When the current flowing through the power transistor reaches the overcurrent threshold, the first detection voltage and the second detection voltage have a second magnitude relationship that is different from the first magnitude relationship, and the comparison unit outputs a valid overcurrent state signal; The low-dropout linear regulator also includes a control circuit for controlling the power transistor to turn off based on a valid overcurrent state signal.

10. An electronic device, characterized in that, Including the low dropout linear regulator as described in any one of claims 1-9.

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