Controller circuit applied to switching voltage regulator and control method thereof

Abstract

A controller circuit for a switching regulator and a control method thereof. The controller circuit includes a constant on-time setting circuit and a delay time setting circuit. The constant on-time setting circuit is configured to adaptively adjust a constant on-time control setting, wherein a turn-on time of an upper bridge power switch of the switching regulator depends on the constant on-time control setting. The delay time setting circuit is configured to adaptively adjust a delay time control setting during a period in which the constant on-time control setting is assigned a minimum constant on-time control value allowed by the switching regulator, wherein a delay time applied to a turn-off time point of a lower bridge power switch of the switching regulator depends on the delay time control setting.

Description

Technical Field

[0001] This invention relates to the design of switching regulators, and more particularly to a method and apparatus for controlling adaptive charge-recovery in switching regulators. Background Technology

[0002] With the advancement of technology, various electronic products have emerged and are widely used in daily life. Generally, electronic products require switching regulators to provide operating power. A switching regulator is a buck converter that can convert high DC voltage to low and stable DC voltage to meet the normal operating requirements of electronic products. Switching regulators can be used in audio devices such as Bluetooth headsets. When the output voltage of a switching regulator is provided to a light load (or extremely light load), the switching frequency F of the switching regulator... SW A lower frequency may result in audible power noise, affecting the user's auditory experience. To maintain the switching frequency F under light (or very light) load conditions... SW Above the audio frequency band (i.e., F) SW For frequencies above 20kHz, a common solution is to add a dummy load to the output node of the switching regulator. However, adding a dummy load causes energy loss, resulting in reduced efficiency under light (or very light) load conditions. Summary of the Invention

[0003] One of the objectives of this invention is to provide a method and apparatus for controlling adaptive charge recovery in a switching regulator.

[0004] In one embodiment of the present invention, a controller circuit for a switching regulator is disclosed. The controller circuit includes a constant on-time setting circuit and a delay time setting circuit. The constant on-time setting circuit adaptively adjusts a constant on-time control setting, wherein an on-time of an upper-bridge power switch of the switching regulator depends on the constant on-time control setting. The delay time setting circuit adaptively adjusts a delay time control setting during a period in which the constant on-time control setting is applied to a minimum allowable constant on-time control value for the switching regulator, wherein a delay time applied to a closing time of a lower-bridge power switch of the switching regulator depends on the delay time control setting.

[0005] In one embodiment of the present invention, a method for controlling a switching regulator is disclosed. The method includes: adaptively adjusting a constant on-time control setting, wherein an on-time of an upper-bridge power switch of the switching regulator depends on the constant on-time control setting; and adaptively adjusting a delay time control setting during a period in which the constant on-time control setting is assigned a minimum allowable constant on-time control value for the switching regulator, wherein a delay time applied to a closing time of a lower-bridge power switch of the switching regulator depends on the delay time control setting.

[0006] The controller circuit of this invention supports multiple control schemes, including the traditional ACOT control scheme and the CB control scheme proposed in this invention. The CB control scheme proposed in this invention will be activated when specific conditions are met. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a switching voltage regulator according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of normal COT voltage regulation operation and CB mode voltage regulation operation according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of a counter-based adaptive adjustment algorithm used in the controller circuit of an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of the controller circuit of a switching regulator according to an embodiment of the present invention.

[0011] Figure 5 This is a flowchart of a method for controlling a switching voltage regulator according to an embodiment of the present invention.

[0012] [Symbol Explanation]

[0013] 100: Switching voltage regulator

[0014] 102: Feedback Circuit

[0015] 104, 400: Controller circuit

[0016] 106, 108: Body diodes

[0017] 110: ACOT control scheme

[0018] 112: CB Control Scheme

[0019] 402: COT setting circuit

[0020] 404: Delay time setting circuit

[0021] 406: Decision Circuit

[0022] 408: On-time generator

[0023] 410, 412, 422: Comparators

[0024] 414: Controllable delay circuit (labeled "ZC delay")

[0025] 416: Multiplexer

[0026] 418: Power Switch Controller

[0027] 420: Current source

[0028] V IN Input voltage

[0029] V OUT Output voltage

[0030] GND: Grounding voltage

[0031] LX, LX2: Switch nodes

[0032] L: Inductance

[0033] I L Inductor current

[0034] V LX V C : Voltage

[0035] UG: Upper Bridge Power Switch

[0036] LG: Downbridge power switch

[0037] C O Output capacitor

[0038] V FB Feedback voltage

[0039] V REF VREF_CIP: Reference voltage

[0040] CS1: COT Control Settings

[0041] CS2: Delay Time Control Settings

[0042] R1, R2: Resistors

[0043] V DIFF ZC: Comparator output

[0044] VDSET, VRST: Control Input

[0045] 28uS_CLK: Fixed clock

[0046] C1, C2, C3: Capacitors

[0047] SW1, SW2: Switches

[0048] T ON On-time

[0049] OFF LG Closing time point

[0050] T D Delay time

[0051] T HIZ HiZ Time

[0052] I peak Peak current

[0053] I NEG Negative peak current

[0054] Cot_min: Minimum COT control value

[0055] S502, S504, S506, S508, S510, S512, S514, S516, S518, S520: Steps Detailed Implementation

[0056] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0057] Figure 1 This is a schematic diagram of a switching voltage regulator according to an embodiment of the present invention. The switching voltage regulator 100 is a voltage converter, such as a buck converter. In this embodiment, the switching voltage regulator 100 is designed to switch the input voltage V... IN Converted to output voltage VOUT (For example, V) OUT < V IN Input voltage V IN It can be powered by a battery or similar source. Output voltage V OUT Provided to a load device (not shown), which can be any electronic device that consumes electrical energy. The switching regulator (e.g., a buck converter) 100 includes an inductor L, a high-side power switch UG, a low-side power switch LG, a feedback circuit 102, and an output capacitor C. O and controller circuitry (e.g., buck controller) 104.

[0058] The upper-bridge power switch UG can be implemented using a P-channel metal-oxide-semiconductor (PMOS) transistor, and the lower-bridge power switch LG can be implemented using an N-channel metal-oxide-semiconductor (NMOS) transistor. Due to the inherent characteristics of PMOS transistors, the upper-bridge power switch UG has a body diode 106, whose anode is coupled to the drain and whose cathode is coupled to the source. Due to the inherent characteristics of NMOS transistors, the lower-bridge power switch LG has a body diode 108, whose anode is coupled to the source and whose cathode is coupled to the drain. The upper-bridge power switch UG and the lower-bridge power switch LG are connected in series at a first voltage node (e.g., input voltage V). IN Specifically, the upper bridge power switch UG is coupled between the first voltage node (e.g., ground voltage GND) and the second voltage node. IN The inductor L is coupled between the switching node LX and the lower bridge power switch LG, while the lower bridge power switch LG is coupled between the switching node LX and the second voltage node (e.g., ground voltage GND). The inductor L has a first end coupled to the switching node LX and a second end coupled to another switching node LX2. When the inductor current I... L Along the positive direction When energy is transferred to the load device by flowing water, the inductor current I flowing through the inductor L is... L It is defined as having positive polarity. When the inductor current IL flows in the reverse direction... Flow (and positive) When the flow direction is opposite, the inductor current I flowing through inductor L is... LIt is defined as having negative polarity.

[0059] Controller circuit 104 is used to control the ON / OFF state of each of the upper bridge power switch UG and the lower bridge power switch LG, so as to control the output voltage V. OUT Voltage regulation is performed. Feedback circuit 102 is used to regulate the output voltage V of the switching regulator 100. OUT To generate feedback voltage V FB In this embodiment, the feedback circuit 102 is implemented by a voltage divider circuit, which has a voltage divider circuit connected in series with the output voltage V. OUT Resistors R1 and R2 are connected between the input terminal and the reference terminal (e.g., ground voltage GND), and the resistance values ​​of resistors R1 and R2 can be set according to actual needs. Feedback circuit 102 is used to monitor the output voltage V. OUT A voltage divider is used to generate a divided voltage, which is then used as the feedback voltage V. FB and the feedback voltage V FB Provided to controller circuit 104. Due to feedback voltage V FB With output voltage V OUT The two are positively correlated, therefore the controller circuit 104 can determine the output voltage V. OUT The instantaneous state. Or, the feedback voltage V. FB It can also be directly determined by the output voltage V OUT Setting. In short, the feedback voltage V FB It can be derived from any source of output voltage V OUT The voltage signal is used for setting. The controller circuit 104 can also receive voltage V at the switching node LX. LX The ON state of the upper bridge power switch UG can be determined based on the feedback voltage V. FB ( or This is triggered by [the voltage V]. The OFF state of the lower bridge power switch LG can be determined based on the voltage V. LX To trigger.

[0060] The switching regulator 100 can employ an adaptive constant on-time (ACOT) control scheme in discontinuous current mode (DCM). In this embodiment, the controller circuit 104 can support multiple control schemes, including the conventional ACOT control scheme 110 and the charge back (CB) control scheme 112 proposed in this invention. The CB control scheme 112 proposed in this invention will be activated when specific conditions are met.

[0061] Figure 2 This is a schematic diagram of normal constant on-time (COT) voltage regulation operation and CB mode voltage regulation operation according to an embodiment of the present invention. Assume the output voltage V... OUT The feedback voltage V is used as the required feedback voltage for the controller circuit (e.g., buck controller) 104. FB For normal COT voltage regulation operation, the controller circuit 104 will adjust the feedback voltage V. FB With reference voltage V REF (This is compared to the target voltage level of the regulator output.) When the output voltage V OUT Below the reference voltage V REF At this time, the controller circuit 104 will turn on the upper bridge power switch UG to initiate a voltage regulation operation. The ACOT control scheme 110 has a COT control setting CS1, which is set to control the on-time T of the upper bridge power switch UG. ON During the conduction time T ON Upon expiration, controller circuit 104 turns off the upper bridge power switch UG and turns on the lower bridge power switch LG. Controller circuit 104 will then adjust the voltage V... LX Compare with the ground voltage GND. When the voltage V continues to drop... LX When the ground voltage GND is reached, this indicates that the inductor current I... L It is zero (that is, I). L = 0mA), the controller circuit 104 will OFF at the turn-off time. LG (that is, V) LX At the point when V = 0V, the lower bridge power switch LG is turned off. Since both the upper bridge power switch UG and the lower bridge power switch LG are off and the inductor current I... L When the impedance is zero, the switching regulator 100 will enter a high-impedance (high-Z, hereinafter referred to as "HiZ") state.

[0062] Next, the controller circuit 104 will send the feedback voltage V FB With reference voltage V REF (This is compared to the target voltage level output by the regulator.) When the output voltage V OUT Again below the reference voltage V REF At this time, the controller circuit 104 will turn on the upper bridge power switch UG to initiate another voltage regulation operation. The controller circuit 104 detects the HiZ time T between the previous voltage regulation operation and the current voltage regulation operation. HIZ Greater than a threshold (e.g., 37µs), this indicates a switching frequency F SW Approaching the upper limit of the audio frequency band, controller circuit 104 activates CB control scheme 112. It should be noted that the threshold of 37µs here is merely illustrative and not intended to limit the invention. When the HiZ time T... HIZ When the threshold is reached, it indicates a switching frequency F higher than the audio frequency band. SW We are now approaching the upper limit of the audio frequency band (e.g., 20kHz). In practice, the threshold setting may depend on actual design considerations.

[0063] During the conduction time T ON Upon expiration, controller circuit 104 will turn off the upper bridge power switch UG and turn on the lower bridge power switch LG. Controller circuit 104 will then adjust the voltage V. LX Compare with the ground voltage GND. As the voltage V gradually decreases... LX When the ground voltage GND is reached, this indicates that the inductor current I... L It is zero (that is, I). L = 0mA), at this time, the CB control scheme 112 will not turn off the lower bridge power switch LG, thus allowing the inductor current I L Reverse the polarity and increase its current magnitude. CB control scheme 112 has a delay time control setting CS2, which is set to control the OFF point applied to the lower bridge power switch LG. LG Delay time T D Therefore, due to the delay time T D Because of this, the inductor current I L It will become a negative inductor current. When the delay time T... DUpon expiration, controller circuit 104 shuts down the lower bridge power switch LG. After the lower bridge power switch LG is shut down, the negative inductor current flows back to the power source (e.g., battery) through the body diode 106 of the upper bridge power switch UG, thereby returning excess energy (i.e., excess charge) to the power source (e.g., battery). It is important to note that both the upper bridge power switch UG and the lower bridge power switch LG are shut down by controller circuit 104, and the body diode 106 of the shut-down upper bridge power switch UG is forward biased to conduct the negative inductor current from inductor L back to the power source (e.g., battery). When the inductor current I... L When both the upper bridge power switch UG and the lower bridge power switch LG are off, the value becomes zero (i.e., I). L When the voltage drops to 0mA, the switching regulator 100 will re-enter the HiZ state.

[0064] The CB control scheme 112 proposed in this invention will be enabled when certain conditions are met. For example, unless the HiZ time T between the previous voltage regulation operation and the current voltage regulation operation is met. HIZ The value is greater than the threshold (e.g., 37µs) and the COT control setting CS1 is given the minimum COT control value (which corresponds to the minimum peak current I of the inductor L that the switching regulator 100 can allow due to its own hardware limitations). peak Otherwise, the switching regulator 100 will not enter CB mode. Furthermore, the CB control scheme 112 proposed in this invention will be disabled when certain conditions are met. For example, unless the delay time control setting CS2 is assigned a minimum delay time control value (which corresponds to the minimum delay time that the switching regulator 100 can allow, such as T...), the CB mode will not be activated. D = 0us), otherwise the switching regulator 100 will not exit CB mode. Specifically, the COT control setting CS1 is determined by the maximum COT control value (which corresponds to the maximum peak current I of the inductor L that the switching regulator 100 can allow due to its hardware limitations). peak The initialization or reset is performed by , and the delay time control setting CS2 is based on the minimum delay time control value (which corresponds to the minimum delay time that the switching regulator 100 can allow, for example, T). D = 0us) to initialize or reset.

[0065] In this embodiment, the controller circuit 104 employs a counter-based adaptive adjustment algorithm to adaptively adjust the COT control setting CS1 and the delay time control setting CS2. For example, while the COT control setting CS1 is given the minimum COT control value allowed by the switching regulator 100, the delay time control setting CS2 is adaptively adjusted. Therefore, the delay time control setting CS2 is a control code that is adjusted by an adjustment value (e.g., +1 or -1) each time a CB mode voltage regulation operation is performed. Figure 3 This is a schematic diagram of the counter-based adaptive adjustment algorithm used in the controller circuit 104 of an embodiment of the present invention. When the switching frequency F SW If the HiZ time exceeds 37µs due to the threshold, the virtual load will be periodically activated at a fixed clock frequency, along with a positive peak current I. peak This will be reduced by adaptively adjusting (decreasing) the COT control setting CS1. Once the positive peak current I... peak Since the COT control setting CS1 has been reduced to its minimum value by assigning the minimum COT control value Cot_min, and the HiZ time is still greater than 37us, the ZC delay time will begin to gradually increase, resulting in the negative peak current I of the inductor. NEG The current increases until a balance is reached between the load and the inductor current. The following section, with accompanying diagrams, provides a more detailed description of the counter-based adaptive adjustment algorithm.

[0066] Figure 4 This is a schematic diagram of the controller circuit of a switching regulator according to an embodiment of the present invention. Figure 1 The controller circuit 104 shown can be implemented using controller circuit 400. Controller circuit 400 includes a COT setting circuit 402, a delay time setting circuit 404, a decision circuit 406, an on-time generator 408, comparators 410 and 412, a controllable delay circuit (labeled "ZC delay") 414, a multiplexer 416, and a power switch controller 418. The COT setting circuit 402 is used to adaptively adjust the COT control setting CS1, wherein the on-time T of the upper bridge power switch UG of the switching regulator 100... ONDepending on the COT control setting CS1, the delay time setting circuit 404 is used to adaptively adjust the delay time control setting CS2 during the period when the COT control setting CS1 of the switching regulator 100 is given the minimum COT control value allowed by the switching regulator 100, wherein the off-time point OFF of the lower bridge power switch LG of the switching regulator 100 is applied. LG Delay time T D Depending on the delay time control setting CS2, the decision circuit 406 monitors the HiZ time T between two consecutive voltage regulation operations. HIZ The decision circuit 406 asserts the control signal CB_MODE (CB_MODE = 1) to enable CB mode. The decision circuit 406 can function as both a normal mode controller and a CB mode controller; for example, the decision circuit 406 can also monitor the HiZ time T. HIZ The COT setting circuit 402 and the delay time setting circuit 404 are used to adjust one or both of the COT control setting CS1 and the delay time control setting CS2. When the delay time control setting CS2 decreases to the minimum value corresponding to the minimum delay time (e.g., T...), the delay time control setting CS2 is adjusted. D When the voltage drops to 0µs, the switching regulator 100 will exit CB mode.

[0067] When CB mode is not in operation (i.e., CB_MODE = 0), multiplexer 416 will select the comparator output V of comparator 412. DIFF The control input VDSET is used as the control input for the power switch controller 418. The control input VDSET determines the turn-on time of the upper bridge power switch UG; specifically, the control input VDSET controls whether to initiate a primary voltage regulation operation of the output voltage VOUT. When the feedback voltage V... FB Higher than the reference voltage V REF When the control input VDSET is low, the upper bridge power switch UG will not be turned on. However, when the feedback voltage V... FB Below the reference voltage V REF When the control input DSET is high, the upper bridge power switch UG will be turned on. When CB mode is in operation (i.e., CB_MODE = 1), the multiplexer 416 selects a fixed clock 28µs_CLK (i.e., a 35kHz clock with a period of 28µs) as the control input VDSET of the power switch controller 418. Therefore, in CB mode, the upper bridge power switch UG will be turned on periodically at a fixed clock frequency.

[0068] The on-time generator 408 generates the control input VRST to the power switch controller 418. The control input VRST determines the off-time of the upper bridge power switch UG and the on-time of the lower bridge power switch LG. Specifically, the on-time T of the upper bridge power switch UG... ON The on-time is determined by both the control input VDSET and the control input VRST. For example, the on-time generator 408 may include a current source 420, multiple capacitors (e.g., C1, C2, and C3), multiple switches (e.g., SW1 and SW2), and a comparator 422. The current source 420 provides a reference current. The on / off state of each of switches SW1 and SW2 is controlled by the COT control setting CS1. When the COT control setting CS1 is given the maximum COT control value, both switches SW1 and SW2 will be turned on, causing voltage V to... C It has the longest charging time. When the COT control setting CS1 is given the minimum COT control value, both switches SW1 and SW2 will be turned off, causing the voltage V to... C It has the shortest charging time. When the COT control setting CS1 is assigned a medium COT control value, only one of switches SW1 and SW2 will be turned on, causing the voltage V to... C It has an intermediate charging time. When the voltage V C When the voltage is below the reference voltage VREF_CIP, the control input VRST is at a high logic level, the upper bridge power switch UG will not be turned off, and the lower bridge power switch LG will not be turned on. However, when the voltage V... C When the voltage is higher than the reference voltage VREF_CIP, the control input VRST is at a low logic level, the upper bridge power switch UG will be turned off, and the lower bridge power switch LG will be turned on.

[0069] Comparator 410 converts voltage V LX The voltage is compared with the ground voltage GND to set the comparator output ZC. The comparator output ZC determines the off-time of the lower bridge power switch LG. LG Specifically, when the voltage V LX When the ground voltage GND is reached, the comparator output ZC is set to instruct the lower bridge power switch LG to turn off. When CB mode is not in operation (i.e., CB_MODE = 0), the controllable delay circuit 414 directly bypasses the comparator output ZC to the power switch controller 418 without applying any delay time. When CB mode is in operation (i.e., CB_MODE = 1), the controllable delay circuit 414 applies a delay time T to the comparator output ZC before it reaches the power switch controller 418. DIn other words, under CB mode, the off-time of the lower bridge power switch LG is OFF. LG It will be delayed by the controllable delay circuit 414, and the delay time T D It is controlled by the delay time control setting CS2.

[0070] Please refer to this as well. Figure 5 and Figure 4 . Figure 5 This is a flowchart of a method for controlling a switching voltage regulator according to an embodiment of the present invention. For example, this method can be... Figure 4 The controller circuit 400 shown is used in this circuit. If a substantially similar result can be obtained, the steps do not necessarily need to be followed exactly. Figure 5 The operations are performed in the order shown. In step S502, the controller circuit 400 performs ACOT control in DCM mode. In step S504, the decision circuit 406 checks the HiZ time T between the previous voltage regulation operation and the current voltage regulation operation. HIZ Is it greater than the threshold TH1 (e.g., TH1 = 37us)? If the HiZ time T HIZ If the value is greater than the threshold TH1 (e.g., TH1 = 37µs), this indicates that the switching frequency F... SW If the frequency band is approaching its upper limit, the decision circuit 406 checks whether the COT control setting CS1 is assigned the minimum COT control value (step S506). If the COT control setting CS1 is not assigned the minimum COT control value, the decision circuit 406 instructs the COT setting circuit 402 to decrease the COT control setting CS1 (e.g., COT control code = COT control code - 1) to reduce the positive peak current I of the current voltage regulation operation. peak (Step S508). If the COT control setting CS1 has been assigned the minimum COT control value, the decision circuit 406 instructs the delay time setting circuit 404 to increase the delay time control setting CS2 (e.g., ZC delay time = ZC delay time + 1) to increase the negative peak current I of the current regulated operation. NEG (Step S510).

[0071] If step S504 determines the HiZ time T between the previous voltage regulation operation and the current voltage regulation operation... HIZ If the value is not greater than the threshold TH1 (e.g., TH1 = 37µs), the process proceeds to step S512. In step S512, the decision circuit 406 checks the HiZ time T between the previous voltage regulation operation and the current voltage regulation operation. HIZ Is it less than the threshold TH2 (e.g., TH2 = 20us)? If the HiZ time T HIZIf the current is less than the threshold TH2 (e.g., TH2 = 20µs), indicating that the load device has suddenly become a heavy load requiring high power, then the decision circuit 406 instructs the COT setting circuit 402 to reset the COT control setting CS1 and instructs the delay time setting circuit 404 to reset the delay time control setting CS2. In step S514, the COT setting circuit 402 resets the COT control setting CS1 to the maximum COT control value allowed by the switching regulator 100 to select the maximum positive peak current for the current regulation operation, and the delay time setting circuit 404 resets the delay time control setting CS2 to the minimum delay time control value allowed by the switching regulator 100 to select the minimum negative peak current (e.g., I0). NEG = 0mA) for current voltage regulation operation.

[0072] If step S512 determines the HiZ time T HIZ Not less than the threshold TH2 (e.g., TH2 = 20us), which means the HiZ time T HIZ If the value is between threshold TH1 and threshold TH2, the process proceeds to step S516. In step S516, the decision circuit 406 checks whether the delay time control setting CS2 is assigned a minimum delay time control value. If the delay time control setting CS2 is assigned a minimum delay time control value, the decision circuit 406 instructs the COT setting circuit 402 to increase the COT control setting CS1 (e.g., COT control code = COT control code + 1) to increase the positive peak current I of the current regulated operation. peak (Step S518) Specifically, the iteration of step S518 can make the positive peak current I... peak The current gradually approaches the maximum positive peak current. If the delay time control setting CS2 has not yet been assigned a minimum delay time control value, the decision circuit 406 instructs the delay time setting circuit 404 to reduce the delay time control setting CS2 (e.g., ZC delay time = ZC delay time - 1) to reduce the negative peak current I of the current regulated operation. NEG (Step S520) Specifically, the iteration of step S520 can make the negative peak current I... NEG It gradually approaches the minimum negative peak current.

[0073] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A controller circuit for a switching voltage regulator, comprising: A constant on-time setting circuit is used to adaptively adjust the constant on-time control setting, wherein the on-time of the upper bridge power switch of the switching regulator depends on the constant on-time control setting; and A delay time setting circuit is used to adaptively adjust the delay time control setting during the period when the constant on-time control setting is given the minimum constant on-time control value allowed by the switching regulator, wherein the delay time applied to the off-time of the lower bridge power switch of the switching regulator depends on the delay time control setting.

2. The controller circuit as described in claim 1, further comprising: The decision circuit is used to check whether the high impedance time between the previous voltage regulation operation and the current voltage regulation operation is greater than a threshold. When the high impedance time is greater than the threshold, one of the constant on-time control setting and the delay time control setting will be adjusted.

3. The controller circuit of claim 2, wherein the high impedance time is greater than the threshold, and the constant on-time setting circuit is used to reduce the constant on-time control setting when the constant on-time control setting is not assigned the minimum constant on-time control value.

4. The controller circuit of claim 2, wherein the high impedance time is greater than the threshold, and the delay time setting circuit is used to increase the delay time control setting when the constant on-time control is given the minimum constant on-time control value.

5. The controller circuit as described in claim 1, further comprising: The decision circuit is used to check whether the high impedance time between the previous voltage regulation operation and the current voltage regulation operation is less than a threshold. When the high impedance time is less than the threshold, both the constant conduction time control setting and the delay time control setting will be adjusted.

6. The controller circuit of claim 5, wherein the high impedance time is less than the threshold, the constant on-time setting circuit is used to reset the constant on-time control setting to the maximum constant on-time control value allowed by the switching regulator, and the delay time setting circuit is used to reset the delay time control setting to the minimum delay time control value allowed by the switching regulator.

7. The controller circuit as claimed in claim 1, further comprising: The decision circuit is used to check whether the high impedance time between the previous voltage regulation operation and the current voltage regulation operation is greater than a first threshold, and to check whether the high impedance time between the previous voltage regulation operation and the current voltage regulation operation is less than a second threshold. When the high impedance time is not greater than the first threshold and not less than the second threshold, one of the constant on-time control setting and the delay time control setting will be adjusted.

8. The controller circuit of claim 7, wherein the high impedance time is not greater than the first threshold and not less than the second threshold, and the constant on-time setting circuit is used to increase the constant on-time control setting when the delay time control setting is given the minimum delay time control value allowed by the switching regulator.

9. The controller circuit of claim 7, wherein the high impedance time is not greater than the first threshold and not less than the second threshold, and the delay time setting circuit is used to reduce the delay time control setting when the delay time control setting is not assigned the minimum delay time control value allowed by the switching regulator.

10. The controller circuit of claim 1, wherein the delay time setting circuit is configured to periodically adjust the delay time control setting during the period in which the constant on-time control setting is assigned the minimum constant on-time control value.

11. A method for controlling a switching voltage regulator, comprising: The constant on-time control setting is adaptively adjusted, wherein the on-time of the upper bridge power switch of the switching regulator depends on the constant on-time control setting; and During the period when the constant on-time control setting is given the minimum constant on-time control value allowed by the switching regulator, the delay time control setting is adaptively adjusted, wherein the delay time applied to the off-time of the lower bridge power switch of the switching regulator depends on the delay time control setting.

12. The method of claim 11, further comprising: Check whether the high-impedance time between the previous voltage regulation operation and the current voltage regulation operation is greater than the threshold; and Since the high impedance time is greater than the threshold, adjust one of the constant on-time control setting and the delay time control setting.

13. The method of claim 12, wherein the step of adjusting one of the constant on-time control setting and the delay time control setting comprises: Since the constant on-time control setting has not been assigned the minimum constant on-time control value, the constant on-time control setting is reduced.

14. The method of claim 12, wherein the step of adjusting one of the constant on-time control setting and the delay time control setting comprises: Since the constant on-time control should be assigned the minimum constant on-time control value, the delay time control setting is increased.

15. The method of claim 11, further comprising: Check whether the high-impedance time between the previous voltage regulation operation and the current voltage regulation operation is less than the threshold; and Since the high impedance time is less than the threshold, adjust the constant on-time control setting and the delay time control setting.

16. The method of claim 15, wherein the step of adjusting the constant on-time control setting and the delay time control setting comprises: The constant on-time control setting is reset to the maximum constant on-time control value allowed by the switching regulator; and Reset the delay time control setting to the minimum delay time control value allowed by the switching regulator.

17. The method of claim 11, further comprising: Check whether the high impedance time between the previous voltage regulation operation and the current voltage regulation operation is greater than the first threshold. Check whether the high impedance time between the previous voltage regulation operation and the current voltage regulation operation is less than the second threshold; and When the high impedance time is not greater than the first threshold and not less than the second threshold, adjust one of the constant on-time control setting and the delay time control setting.

18. The method of claim 17, wherein the step of adjusting one of the constant on-time control setting and the delay time control setting comprises: The constant on-time control setting is increased because the delay time control setting is assigned the minimum delay time control value allowed by the switching regulator.

19. The method of claim 17, wherein the step of adjusting one of the constant on-time control setting and the delay time control setting comprises: If the delay time control setting is not assigned the minimum delay time control value allowed by the switching regulator, the delay time control setting should be reduced.

20. The method of claim 11, wherein during the period during which the constant on-time control setting is assigned the minimum constant on-time control value, the delay time control setting is periodically adjusted.

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