synchronization circuit

Abstract

The present disclosure relates to a synchronous circuit. The present disclosure relates to a synchronous circuit comprising a plurality of flip-flops and providing an updated output at each first type edge of a first clock signal. A first circuit comprises a first flip-flop of the plurality of flip-flops, synchronized on a first type edge of a second clock signal having a frequency that is half of the first clock signal. The first circuit provides an updated first output at each first type edge of the second clock signal. A second circuit comprises a second flip-flop of the plurality of flip-flops, synchronized on a second type edge of the second clock signal. The second circuit provides an updated second output at each second type edge of the second clock signal. A combining circuit receives the first output and the second output and provides an output of the synchronous circuit.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. FR2503061, filed on March 25, 2025, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic circuits, and in particular to integrated circuits. More specifically, this disclosure relates to synchronous electronic circuits. Background Technology

[0004] In known synchronous circuits, the clock signal is distributed to multiple synchronous flip-flops, typically D flip-flops, which are synchronized on the edges of the clock signal (usually edges of the same type as the clock signal, such as rising edges).

[0005] In such a known synchronous circuit, each of a plurality of flip-flops updates its output with data present in its data input at each edge (e.g., rising edge) of the same type of clock signal received from its synchronous input. This allows the circuit to provide updated output data at each such edge of the clock signal.

[0006] Since all the flip-flops in a plurality of flip-flops are updated on the same type of edge of the clock signal, all of these flip-flops have power consumption peaks on each of these edges, which causes a drop in the supply voltage of the flip-flops.

[0007] Furthermore, in such known circuits, power consumption is related to the frequency of the clock signal. Therefore, reducing the frequency of the clock signal allows for a reduction in the circuit's power consumption. However, when the circuit must process input data from another circuit or must provide output data to another circuit, it may not be possible to reduce the frequency of the clock signal.

[0008] There is a need for a synchronization circuit with multiple flip-flops that overcomes all or some of the drawbacks of known synchronization circuits with multiple flip-flops synchronized on the same type of edge of a clock signal, and provides updated output data at each of these edges. Summary of the Invention

[0009] One embodiment addresses all or some of the drawbacks of known circuits having multiple flip-flops that are synchronized on the same type of edge of a clock signal and provide updated output data at each of these edges.

[0010] One embodiment provides a synchronization circuit including a plurality of flip-flops and configured to provide an updated output at each edge of a first type of edge of a first clock signal. The synchronization circuit includes a first circuit comprising a first flip-flop of the plurality of flip-flops, the first flip-flop being synchronized with and updated on a first type of edge of a second clock signal having a frequency equal to half the frequency of the first clock signal, the first circuit being configured to provide an updated first output at each edge of the first type of edge of the second clock signal. The synchronization circuit also includes a second circuit comprising a second flip-flop of the plurality of flip-flops, the second flip-flop being synchronized with and updated on a second type of edge of the second clock signal, the second circuit being configured to provide an updated second output at each edge of the second type of edge of the second clock signal. The synchronization circuit further includes combinational logic circuitry receiving the first and second outputs and configured to provide an output of the synchronization circuit based on the first and second outputs.

[0011] According to one embodiment, the number of first triggers is equal to the number of second triggers.

[0012] According to one embodiment, the first circuit includes more than one first flip-flop, and the second circuit includes more than one second flip-flop.

[0013] According to one embodiment, the first circuit and the second circuit each have the same function.

[0014] According to one embodiment, each first trigger is configured to maintain its output between two consecutive updates of the first trigger, and each second trigger is configured to maintain its output between two consecutive updates of the second trigger.

[0015] According to one embodiment, a first flip-flop is connected in series in a first circuit, and a second flip-flop is connected in series in a second circuit.

[0016] According to one embodiment, the first output is determined by at least one output of the first flip-flop, and the second output is determined by at least one output of the second flip-flop.

[0017] According to one embodiment, the synchronization circuit is a synchronization counter.

[0018] According to one embodiment, the first circuit is a first synchronous counter, the second circuit is a second synchronous counter, and the combinational logic circuit is an adder circuit configured to add the first output and the second output and provide an output of the synchronous circuit equal to the sum of the two outputs.

[0019] According to one embodiment, for each first flip-flop, the first circuit includes circuitry that provides an input to the first flip-flop based on at least one of the outputs of the first flip-flop, the at least one output including the output of the first flip-flop; and for each second flip-flop, the second circuit includes circuitry that provides an input to the second flip-flop based on at least one of the outputs of the second flip-flop, the at least one output including the output of the second flip-flop.

[0020] According to one embodiment, the synchronization circuit is a shift register.

[0021] According to one embodiment, the first circuit is a first shift register, the second circuit is a second shift register, and the combinational logic circuit is configured to provide an output of a synchronization circuit equal to a first output of the first circuit when the second clock signal is in a state following each edge of a second type of edge of the second clock signal, and to provide an output of a synchronization circuit equal to a second output of the second circuit when the second clock signal is in a state following each edge of a first type of edge of the second clock signal.

[0022] According to one embodiment, first flip-flops are connected in series, the first of the first flip-flops having an input to receive an input of a synchronization circuit, and each of the other first flip-flops having an input connected to the output of the preceding first flip-flop, and the last of the first flip-flops having an output to provide a first output; and second flip-flops are connected in series, the first of the second flip-flops having an input to receive an input of a synchronization circuit, and each of the other second flip-flops having an input connected to the output of the preceding second flip-flop, and the last of the second flip-flops having an output to provide a second output.

[0023] Another embodiment provides a system comprising: a transmitting circuit configured to provide updated first data at each edge of a first type of edge of a first clock signal; a receiving circuit configured to receive updated second data at each edge of the first type of edge of the first clock signal; and the aforementioned synchronization circuit, which is a synchronous shift register. Attached Figure Description

[0024] The foregoing features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, in which specific embodiments are given by way of example rather than limitation, and in which:

[0025] Figure 1 An example of a synchronous circuit with multiple flip-flops is shown.

[0026] Figure 2 It shows Figure 1 The shortcomings of the circuit.

[0027] Figure 3 An embodiment of the synchronization circuit is shown.

[0028] Figure 4 It shows the relationship with Figure 1 Compared to the operation of the circuit Figure 3 The operation of the circuit.

[0029] Figure 5 It shows Figure 3 The advantages of this circuit.

[0030] Figure 6 It shows the relationship with Figure 1 Examples of synchronous circuits of the type described above.

[0031] Figure 7 It shows the relationship with Figure 3 Examples of synchronous circuits of the relevant description type.

[0032] Figure 8 It shows the relationship with Figure 6 Compared to the operation of the circuit Figure 7 The operation of the circuit.

[0033] Figure 9 It shows the relationship with Figure 1 Another example of a synchronous circuit of the type described above.

[0034] Figure 10 It shows the relationship with Figure 3 Another example of a synchronous circuit of the type described above.

[0035] Figure 11 It shows the relationship with Figure 9 Compared to the operation of the circuit Figure 10 The operation of the circuit. Detailed Implementation

[0036] Similar features are indicated by similar reference numerals in the various figures. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0037] For clarity, only those operations and elements useful for understanding the embodiments described herein are shown and described in detail.

[0038] Unless otherwise indicated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0039] In the following disclosure, unless otherwise indicated, references to absolute positional qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative positional qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.) refer to the orientation shown in the accompanying drawings.

[0040] Unless otherwise specified, the expressions “approximately,” “about,” “substantially,” and “on the order of magnitude” indicate within 10% or 10°, and preferably within 5% or 5°.

[0041] Figure 1 An example of synchronous circuit 1 is illustrated schematically using a block diagram.

[0042] Circuit 1 includes a plurality of synchronous flip-flops 100, preferably D flip-flops 100. Although not in Figure 1 As shown, all triggers 100 are supplied with the same power supply voltage Vdd.

[0043] Each flip-flop 100 includes a data input D, a data output Q, and a synchronization input C. The data input D is configured to receive input data bits of the flip-flop 100. The data output Q is configured to provide output data bits of the flip-flop 100. The synchronization input C is configured to receive a clock signal. The flip-flop 100 is configured to update its output Q with its input D at each edge of the same type (e.g., at each rising edge) of the clock signal received by its synchronization input C (copying its input D onto its output Q). The flip-flop 100 is also configured to maintain or remember its output Q between two consecutive updates of the output.

[0044] In circuit 1, all flip-flops 100 are configured to update their respective output Q at each edge of the same type (e.g., the rising edge) of the clock signal clk. For example, in Figure 1 In this circuit, all synchronous inputs C are sensitive to rising edges, and synchronous inputs C receive the signal clk.

[0045] The flip-flops 100 of circuit 1 are connected in series. In other words, each flip-flop 100 in the series-coupled sequence, except for the first one, receives input data at its input D that is at least partially determined by the output data of the preceding flip-flop 100 in the sequence. The first flip-flop in the series-coupled sequence receives input data at its input D that is at least partially determined by the input data IN of circuit 1 or its own output data. Therefore, when the input of the first flip-flop 100 in the sequence is determined by the output Q of that flip-flop 100, the input IN may not exist.

[0046] exist Figure 1In the example, circuit 1 includes an associated circuit 102 for each flip-flop 100, which provides input data to the flip-flop 100.

[0047] Circuit 102 is a combinational logic circuit, or in other words, it does not include any flip-flops, latches, or storage elements.

[0048] In another example not shown, the flip-flops 100 are connected in series, and for each flip-flop 100 in the series-connected sequence except for the first flip-flop, the input D of the flip-flop 100 is connected to the output Q of the previous flip-flop 100 in the sequence, so that each circuit 102 corresponds to a simple connection line.

[0049] Circuit 1 is configured to provide updated output data OUT at each edge of the same type of clock signal clk (e.g., at each rising edge). Circuit 1 is also configured to keep its output OUT stable between two consecutive updates of its output OUT, or in other words, between two consecutive edges of the same type of signal clk.

[0050] The output OUT can be determined by the output Q of the last trigger 100 in the sequence of triggers 100. For example, the output OUT is the output Q of the last trigger 100.

[0051] Alternatively, the output OUT can be determined by at least one of the outputs Q of the flip-flop 100, for example, by all the outputs Q of the flip-flop 100. For example, the output OUT is a cascade of the outputs Q of the flip-flop 100.

[0052] As an example, circuit 1 could be a synchronous shift register. As another example, circuit 1 could be a synchronous counter. As a further example, circuit 1 could be a linear feedback shift register (LFSR). More generally, circuit 1 could be any circuit based on a synchronous shift register or a synchronous counter.

[0053] As mentioned earlier, the power consumption of circuit 1 is related to the frequency of the clock signal clk. In fact, the higher the frequency of the clock signal clk, the higher the power consumption.

[0054] When it is desirable to reduce power consumption, those skilled in the art may consider reducing the frequency of the signal clk. However, when circuit 1 is part of an electronic system and receives an input IN updated at a first frequency from another circuit of the system and / or provides an output OUT updated at a first frequency to another circuit of the system, reducing the frequency of the signal clk relative to the first frequency will cause the system to malfunction.

[0055] Figure 2 It shows Figure 1 The operation of circuit 1. More specifically, Figure 2This represents the signal clk of circuit 1 and the power supply voltage Vdd of the flip-flop 100 in circuit 1. Figure 2 In the example, the output OUT is updated at each rising edge of the signal clk and is maintained between two consecutive updates.

[0056] More specifically, curve 200 shows the evolution of voltage Vdd relative to nominal value Vdd-nom when circuit 1 includes N flip-flops 100, where N is an integer greater than or equal to 2, curve 202 shows the evolution of voltage Vdd when circuit 1 includes 2·N flip-flops 100, and curve 204 shows the evolution of voltage Vdd when circuit 1 includes 3·N flip-flops 100.

[0057] like Figure 2 As can be seen, at each rising edge of the signal clk, the voltage Vdd drops because the flip-flop 100 draws power to update its output Q. The higher the number of flip-flops 100 in circuit 1, the greater the voltage drop.

[0058] like Figure 2 As can also be seen, at each falling edge of the signal clk, the voltage Vdd also decreases, but to a lesser extent than at the rising edge. This decrease in voltage Vdd is, for example, caused by the propagation of the clock edge through the clock tree.

[0059] This drop in voltage Vdd can impair the performance of circuit 1 and the system comprising circuit 1. In fact, besides flip-flop 100, signal clk is typically supplied to many other flip-flops similar to flip-flop 100 via a clock tree including delay units to ensure that all flip-flops receive the edge of signal clk simultaneously. However, changes in voltage Vdd, particularly a drop in voltage Vdd, alter the delay introduced by each delay unit of the clock tree. This causes an imbalance in the propagation of signal clk within the clock tree and may lead to failure of circuit 1 or the system comprising circuit 1.

[0060] Therefore, it is necessary to reduce the drop in voltage Vdd at the rising edge of signal clk, especially when output OUT is updated at each rising edge of signal clk.

[0061] Figure 3 An embodiment of the synchronization circuit 3 is shown.

[0062] Synchronization circuit 3 is configured, similar to circuit 1, to provide an updated output OUT1 at each edge of the same type as the clock signal clk (e.g., at each rising edge of the signal clk). Circuit 3 is also configured to keep its output OUT1 stable between two consecutive updates, or in other words, to keep its output OUT1 stable between two consecutive rising edges of the signal clk.

[0063] Synchronization circuit 3 includes multiple reference circuits. Figure 1 The described flip-flop 100 is the same as flip-flops 300 and 320, except that they are not sensitive to the rising edge of the signal clk, or in other words, they are not configured to update their respective output Q at each rising edge of the signal clk.

[0064] More specifically, circuit 3 includes circuit 30 and circuit 32, circuit 30 including a portion of the plurality of flip-flops of circuit 3, and circuit 32 including another portion of the plurality of flip-flops of circuit 3, the flip-flops of circuit 30 and 32 being labeled 300 and 320, respectively.

[0065] Preferably, circuit 30 (or 32) includes more than one flip-flop 300 (or 320).

[0066] Preferably, the number of flip-flops 300 is equal to the number of flip-flops 320. For example, to implement a synchronous shift register whose shift between input and output is equal to 2·N+1 cycles of the signal clk, where N is a strictly positive integer, each of circuits 30 and 32 has N flip-flops, and the remaining flip-flops are added to the input IN or output OUT of circuit 3 and synchronized with the clock signal clk. As another example, to implement a synchronous shift register whose shift between input and output is equal to 2·N cycles of the signal clk, each of circuits 30 and 32 has N flip-flops. As yet another example, when circuit 3 implements a synchronous counter, the number of flip-flops in each of circuits 30 and 32 is the same.

[0067] Flip-flops 300 are synchronized with, or sensitive to, the first type of edge of clock signal clk / 2, which has a frequency equal to half the frequency of clock signal clk. In other words, each flip-flop 300 is configured to update its output Q with its input D at each first type of edge of signal clk / 2. Each flip-flop 300 is also configured to hold its output Q between two consecutive updates of its output Q, or in other words, to hold its output Q between two consecutive first type of edges of signal clk / 2.

[0068] Flip-flops 320 are synchronized with, or sensitive to, the second type of edge of the clock signal clk / 2. In other words, each flip-flop 320 is configured to update its output Q with its input D at each second type of edge of the signal clk / 2. Each flip-flop 320 is also configured to hold its output Q between two consecutive updates of its output Q, or in other words, to hold its output Q between two consecutive second type of edges of the signal clk / 2.

[0069] Each edge of the first type of signal clk / 2 is synchronized with the corresponding edge of signal clk, and each edge of the second type of signal clk / 2 is also synchronized with the corresponding edge of signal clk. The edges of signal clk are synchronized with the first and second types of edges of signal clk / 2, and these edges are of the same type, such as rising edges. The output OUT1 of circuit 3 is updated on each of these edges.

[0070] exist Figure 3 In the example, the first type of edge of signal clk / 2 is a rising edge, and the second type of edge of signal clk / 2 is a falling edge.

[0071] exist Figure 3 In the example, the synchronization input C of each flip-flop 300 and 320 is sensitive to the rising edge of the signal received at that input. Therefore, in this example, each flip-flop 300 receives the signal clk / 2 at its input C, and each flip-flop 320 receives the two's complement of the signal clk / 2 at its input C, which... Figure 3 The winning bid is Nclk / 2.

[0072] In an alternative example not shown, the synchronization input C of each flip-flop 300 may be sensitive to the falling edge of the signal received by that input, and / or the synchronization input C of each flip-flop 320 may be sensitive to the falling edge of the signal received by that input. This will allow those skilled in the art to adapt the signals received by the synchronization input C of flip-flop 300 and / or the signals received by the synchronization input C of flip-flop 320 such that flip-flop 300 is updated on a first type of edge of signal clk / 2 and flip-flop 320 is updated on a second type of edge of signal clk / 2.

[0073] According to one embodiment, the flip-flops 300 (or 320) of circuit 30 (or 32) are series coupled. In other words, each flip-flop 300 (or 320) in the series-coupled sequence, except for the first one, receives input data at its input D that is at least partially determined by the output data of the preceding flip-flop 300 (or 320) in the sequence. The first of the series-coupled flip-flops 300 (or 320) receives input data at its input D that is at least partially determined by the input data IN of circuit 3 or by its own output data. Therefore, when the input of the first flip-flop 300 (or 320) in the sequence is determined by the output Q of that flip-flop 300 (or 320), the input IN may not exist.

[0074] exist Figure 3In the example, flip-flops 300 (or 320) are series-coupled, and circuit 30 (or 32) includes an associated circuit 302 (or 322) for each flip-flop 300 (or 320), which provides the input data for that flip-flop 300 (or 320). For example, for each flip-flop 300 (or 320) in the sequence except the first one, the circuit 302 (or 322) associated with that flip-flop 300 (or 320) is configured to determine the input data of that flip-flop based at least in part on the output data of the preceding flip-flop 300 (or 320) in the sequence. For example, the circuit 302 (or 322) associated with the first of the series-coupled flip-flops 300 (or 320) is configured to determine the input data of that flip-flop based at least in part on the input data IN of circuit 3 or the output data of that flip-flop.

[0075] Circuits 302 and 322 are combinational logic circuits, or in other words, they do not include any flip-flops, latches, or storage elements.

[0076] In another example not shown, flip-flops 300 (or 320) are connected in series, and for each flip-flop 300 (or 320) in the series-connected sequence except for the first one, the input D of the flip-flop 300 (or 320) is connected to the output Q of the previous flip-flop 300 (or 320) in the sequence, and each circuit 302 (or 322) corresponds to a simple connection line.

[0077] Circuit 30 (or 32) is configured to provide output data OUT' (or OUT”) updated at each edge of the first type (or second type) of the clock signal clk / 2. For example, circuit 30 (or 32) is configured to provide output data OUT' (or OUT”) updated at each rising edge (or each falling edge) of the signal clk / 2.

[0078] Circuit 30 (or 32) is also configured to keep the output stable between two consecutive updates of its output OUT' (or OUT") . Specifically, the output OUT' (or OUT") is never updated on the second type (or first type) edge of the signal clk / 2.

[0079] The output OUT' can be determined by the output Q of the last flip-flop 300 in the sequence of flip-flops 300. For example, output OUT' is the output bit of the last flip-flop 300. Similarly, the output OUT" can be determined by the output Q of the last flip-flop 320 in the sequence of flip-flops 320. For example, output OUT" is the output bit of the last flip-flop 320.

[0080] Alternatively, output OUT' can be determined by at least one of the outputs Q of flip-flop 300, for example, by all the outputs Q of flip-flop 300. For example, output OUT' is a cascade of the outputs Q of flip-flop 300. Similarly, output OUT' can be determined by at least one of the outputs Q of flip-flop 320, for example, by all the outputs Q of flip-flop 320. For example, output OUT' is a cascade of the outputs Q of flip-flop 320.

[0081] Preferably, the two circuits 30 and 32 have the same function. For example, both circuits 30 and 32 are synchronous shift registers. As another example, both circuits 30 and 32 are synchronous counters. As yet another example, both circuits 30 and 32 are part of a linear feedback shift register.

[0082] although Figure 3 Although not shown in the diagram, all flip-flops 300 and 320 are powered by the same supply voltage Vdd.

[0083] Circuit 3 also includes combinational logic circuit 34. Circuit 34 receives the outputs OUT' and OUT' of the corresponding circuits 30 and 32, and is configured to provide the output OUT1 of circuit 3 based on the received outputs OUT' and OUT'. Circuit 34 is preferably purely combinational logic circuit and therefore does not include any storage elements such as flip-flops or latches.

[0084] Figure 4 Explained with Figure 1 Compared to the operation of circuit 1 Figure 3 The operation of the circuit.

[0085] More specifically, Figure 4 An example of how the following signal evolves with time t is shown: clock signal clk; Figure 1 The output OUT of circuit 1; clock signal clk / 2; Figure 3 The output OUT' of circuit 30; Figure 3 The output OUT of circuit 32; and Figure 3 The output OUT1 of circuit 3.

[0086] exist Figure 4 In the example, circuit 1 is configured to update its output OUT at each rising edge of signal clk, circuit 30 is configured to update its output OUT' at each rising edge of signal clk / 2, and circuit 32 is configured to update its output OUT' at each falling edge of signal clk / 2. Additionally, in Figure 4 In this context, the rising edge of signal clk / 2 is synchronized with the corresponding rising edge of signal clk. For example, although... Figure 3Although not shown, circuit 3 may include a divider that receives signal clk and provides signal clk / 2, for example, by an inverter circuit that receives signal clk / 2 from circuit 3.

[0087] Before time t0, outputs OUT, OUT', OUT” and OUT1 have values ​​v0, v0', v0” and v0 respectively. The value v0 of output OUT1 is determined by circuit 34 based on the values ​​v0' and v0”, and is equal to the value v0 of output OUT.

[0088] At time t0, both signals clk and clk / 2 change from low to high. The rising edge of signal clk causes output OUT to be updated to the value v1, and the rising edge of signal clk / 2 causes output OUT' to be updated to the value v1'. Output OUT" remains at its current value v0". Then, the value OUT1 changes from the value v0 determined by values ​​v0' and v0" to the value v1 determined by values ​​v1' and v0"".

[0089] At time t1 after time t0, signal clk changes from low to high, and signal clk / 2 changes from high to low. The rising edge of signal clk causes output OUT to be updated to value v2, and the falling edge of signal clk / 2 causes output OUT" to be updated to value v1", while output OUT' remains at its current value v1'. Then, value OUT1 changes from value v1, determined by values ​​v1' and v0" to value v2, determined by values ​​v1' and v1" respectively.

[0090] At time t2, following time t1, both signals clk and clk / 2 change from low to high. The rising edge of signal clk causes output OUT to be updated to value v3, and the rising edge of signal clk / 2 causes output OUT' to be updated to value v2', while output OUT" remains at its current value v1. Value OUT1 changes from value v2 to value v3, determined by values ​​v2' and v1".

[0091] At time t3, after time t2, signal clk changes from low to high, and signal clk / 2 changes from high to low. The rising edge of signal clk causes output OUT to be updated to value v4, and the falling edge of signal clk / 2 causes output OUT" to be updated to value v2", while output OUT' remains at its current value v2'. Value OUT1 changes from value v3 to value v4, determined by values ​​v2' and v2"".

[0092] At time t4, after time t3, both signals clk and clk / 2 change from low to high. The rising edge of signal clk causes output OUT to be updated to value v5, and the rising edge of signal clk / 2 causes output OUT' to be updated to value v3', while output OUT" remains at its current value v2. Value OUT1 changes from value v4 to value v5, which is determined by values ​​v3' and v2".

[0093] At time t5, after time t4, signal clk changes from low to high, and signal clk / 2 changes from high to low. The rising edge of signal clk causes output OUT to be updated to value v6, and the falling edge of signal clk / 2 causes output OUT" to be updated to value v3", while output OUT' remains at its current value v3'. Value OUT1 changes from value v5 to value v6, determined by values ​​v3' and v3" respectively.

[0094] like Figure 4 As can be seen, similar to output OUT, output OUT1 is updated at each rising edge of signal clk. Furthermore, at each rising edge of signal clk, both outputs OUT and OUT1 are updated to the same value. Therefore, circuits 1 and 3 have the same output signals OUT and OUT1.

[0095] However, in circuit 3, the updates of flip-flops 300 and 320 occur at a frequency twice as low as the update frequency of flip-flop 100 in circuit 1. Therefore, the power consumption of circuit 3 is reduced relative to that of circuit 1.

[0096] Figure 5 Explained with Figure 1 Compared to circuit 1 Figure 3 The advantages of circuit 3. More specifically, Figure 5 This represents the signal clk of circuit 1, the signal clk / 2 of circuit 3, and the power supply voltage Vdd of flip-flops 300 and 320 in circuit 3. Figure 5 In the example, output OUT' is updated at each rising edge of signal clk / 2 and not at the falling edge of signal clk / 2, while output OUT" is updated at each falling edge of signal clk / 2 and not at the rising edge of signal clk / 2.

[0097] More specifically, curve 500 shows the relationship between the total number N of flip-flops 300 and 320 included in circuit 3 and the corresponding... Figure 2Curve 200 shows the evolution of voltage Vdd relative to the nominal value Vdd-nom when the number N of flip-flops 100 in circuit 3 is equal. Curve 502 shows the evolution of voltage Vdd when the total number of flip-flops 300 and 320 included in circuit 3 is equal to 2·N. Curve 504 shows the evolution of voltage Vdd when the total number of flip-flops 300 and 320 included in circuit 3 is equal to 3·N.

[0098] like Figure 5 As can be seen, at each rising edge of the signal clk / 2, the voltage Vdd drops because the flip-flop 300 draws power to update its output Q. The higher the number of flip-flops 300 in circuit 3, the greater the voltage drop.

[0099] However, for the same number N flip-flops in circuits 1 and 3, the voltage drop ΔVdd in circuit 3 at each rising edge of signal clk / 2 is lower than that in circuit 3. Figure 2 The voltage drop ΔVdd at each rising edge of the signal clk in circuit 1 shown is ΔVdd.

[0100] This is due to the fact that in circuit 3, only flip-flop 300 is updated at each rising edge of signal clk / 2, while in circuit 1, all flip-flops 100 are updated at each rising edge of signal clk.

[0101] Furthermore, at each falling edge of the signal clk, the voltage Vdd in circuit 3 does not decrease because neither of the flip-flops 300 nor 320 is updated at that edge.

[0102] like Figure 5 As can also be seen in the diagram, at each falling edge of the signal clk / 2, the voltage Vdd drops as the flip-flop 320 draws power to update its output Q. The higher the number of flip-flops 320 in circuit 3, the greater the voltage drop.

[0103] However, for the same number of N flip-flops in circuits 1 and 3, the voltage drop ΔVdd at each falling edge of signal clk / 2 in circuit 3 is lower than that in circuit 3. Figure 2 The voltage drop ΔVdd at each rising edge of the signal clk in circuit 1 shown is ΔVdd.

[0104] This is due to the fact that in circuit 3, only flip-flop 320 is updated at each falling edge of signal clk / 2, while in circuit 1, all flip-flops 100 are updated at each rising edge of signal clk.

[0105] In fact, in circuit 3, for a given number of N flip-flops 300 and 320, the voltage drop at each rising edge of signal clk / 2 is substantially similar to the voltage drop at each falling edge of signal clk / 2, and these voltage drops are lower than the voltage drop at each rising edge of signal clk in circuit 1 with N flip-flops 100.

[0106] Therefore, compared with the corresponding circuit 1, circuit 3 advantageously allows for a reduction in the voltage drop of the supply voltage Vdd.

[0107] The advantages of power consumption and voltage drop ΔVdd described above for circuit 3 compared to circuit 1 also apply when the total number of flip-flops in circuit 3 is greater than the number of flip-flops in circuit 1, for example, when the total number of flip-flops in circuit 3 is equal to the number of flip-flops in circuit 1 plus one or two. For example, when both circuits 1 and 3 are implemented as synchronous counters that count to the same number, the number of flip-flops in circuit 3 can be two more than the number of flip-flops in circuit 1.

[0108] Figure 6 Synchronization circuit 1 is shown as an example, where circuit 1 is a synchronous counter.

[0109] exist Figure 6 In the example, trigger 100 is updated at each rising edge of signal clk and maintains its respective output between two consecutive rising edges of signal clk.

[0110] exist Figure 6 In the example, circuit 1 includes four flip-flops 100 connected in series. The first flip-flop 100 in the sequence of flip-flops 100 (located in...) Figure 6 The first flip-flop (left side) receives input D1 and provides output Q1. The second flip-flop 100 receives input D2 and provides output Q2. The third flip-flop 100 receives input D3 and provides output Q3. The fourth or final flip-flop 100 receives input D4 and provides output Q4.

[0111] In this example, circuit 1 is a synchronous counter, and the output OUT of circuit 1 is a cascade of outputs Q1, Q2, Q3 and Q4.

[0112] In this example, circuit 1 is a synchronous counter that does not receive any input IN.

[0113] In one exemplary embodiment, a first circuit 102 receives output Q1 and provides an input D1 equal to the Boolean NOT of output Q1. A second circuit 102 receives outputs Q1 and Q2 and provides an input D2 equal to the Boolean XOR of outputs Q1 and Q2. A third circuit 102 receives outputs Q1, Q2, and Q3 and provides an input D3 equal to the Boolean XOR of output Q3 with the Boolean AND of outputs Q1 and Q2. A fourth circuit 102 receives outputs Q1, Q2, Q3, and Q4 and provides an input D4 equal to the Boolean XOR of output Q4 with the Boolean AND of outputs Q1, Q2, and Q3.

[0114] Figure 7 Synchronization circuit 3 is shown as an example, where circuit 3 is a synchronous counter. Unless otherwise stated, this applies to... Figure 3 All descriptions provided in Circuit 3 also apply to... Figure 7 Circuit 3 in the diagram.

[0115] When circuit 3 is a synchronous counter, circuits 30 and 32 are two synchronous counters, for example, they are identical to each other. Furthermore, circuit 34 is preferably an adder circuit configured to add outputs OUT' and OUT" and provide an output OUT1 equal to the sum of outputs OUT' and OUT".

[0116] For example, circuit 30 includes, for each flip-flop 300, circuit 302 associated with and configured to provide input data to the flip-flop 300 based on at least one of the outputs of the flip-flop 300, the at least one output including the output of the flip-flop 300 associated with circuit 302. Similarly, circuit 32 includes, for each flip-flop 320, circuit 322 associated with and configured to provide input data to the flip-flop 320 based on at least one of the outputs of the flip-flop 320, the at least one output including the output of the flip-flop 320 associated with circuit 322.

[0117] exist Figure 7 In the example, synchronization counter 3 is configured to count at least to the value of the previous one. Figure 6 The synchronous counter 1 has the same maximum value. Therefore, in this example, circuit 3 includes six flip-flops, more specifically, three series-coupled flip-flops 300 in circuit 30 and three series-coupled flip-flops 320 in circuit 32.

[0118] In circuit 30, the first flip-flop 300 in the sequence of flip-flops 300 (located in...) Figure 7The first circuit (left side) receives input D1' and provides output Q1'. The second circuit (left side) receives input D2' and provides output Q2'. The third or final circuit (right side) receives input D3' and provides output Q3'. For example, the first circuit (right side) receives output Q1' and provides input D1' equal to the Boolean NOT of Q1'. The second circuit (right side) receives outputs Q1' and Q2' and provides input D2' equal to the Boolean XOR of Q1' and Q2'. The third circuit (right side) receives outputs Q1', Q2', and Q3' and provides input D3' equal to the Boolean XOR of Q3' with the Boolean AND of Q1' and Q2'.

[0119] In circuit 32, the first flip-flop 320 in the sequence of flip-flops 320 (located in...) Figure 7 The first circuit (left side) receives input D1" and provides output Q1". The second circuit (left side) receives input D2" and provides output Q2". The third or final circuit (right side) receives input D3" and provides output Q3". For example, the first circuit (right side) receives output Q1" and provides input D1" which is a Boolean NOT of Q1". The second circuit (right side) receives outputs Q1" and Q2" and provides input D2" which is a Boolean XOR of Q1" and Q2". The third circuit (right side) receives outputs Q1", Q2" and Q3" and provides input D3" which is a Boolean XOR of Q3" with Q1" and Q2".

[0120] In this example, circuit 3 is a synchronous counter, the output OUT' of circuit 30 is a cascade of outputs Q1', Q2' and Q3', and the output OUT" of circuit 32 is a cascade of outputs Q1" and Q2" and Q3".

[0121] In this example, circuit 3 is a synchronous counter, and circuit 3 does not receive any input IN, therefore its circuits 30 and 32 also do not receive any input IN.

[0122] Figure 8 It shows the relationship with Figure 6 Compared to the operation of circuit 1 Figure 7 The operation of circuit 3.

[0123] More specifically, Figure 8 An example of how the following signal evolves with time t is shown: clock signal clk; Figure 6 The output OUT of circuit 1; clock signal clk / 2; Figure 7 The output OUT' of circuit 30; Figure 7 The output OUT of circuit 32; and Figure 7 The output OUT1 of circuit 3.

[0124] exist Figure 8The diagram shows the updates of signals OUT, OUT', OUT" and OUT1 with respect to the corresponding edges of signals clk and clk / 2, in a delayed manner. Figure 4 The differences shown are as follows.

[0125] exist Figure 8 In the example, circuit 1 is configured to update its output OUT at each rising edge of signal clk, circuit 30 is configured to update its output OUT' at each rising edge of signal clk / 2, and circuit 32 is configured to update its output OUT' at each falling edge of signal clk / 2. Furthermore, to better compare the operation of circuits 1 and 3, in Figure 8 In this context, the rising edge of signal clk / 2 is synchronized with the rising edge of signal clk. Figure 8 In the example, eight consecutive rising edges of the signal clk are shown and labeled as t0, t1, t2, t3, t4, t5, t6 and t7.

[0126] Before time t0, the outputs OUT, OUT', OUT” and OUT1 have values ​​of 0, 0, 0 and 0 respectively. The value of output OUT1 is 0, which is equal to the sum of the values ​​of output OUT' and OUT”, and is also equal to the value of output OUT.

[0127] At time t0, the rising edge of signal clk causes output OUT to be updated to the value 1, and the rising edge of signal clk / 2 causes output OUT' to be updated to the value 1, while output OUT" remains at its current value 0. Therefore, output OUT1 changes from value 0 to value 1, which is equal to the sum of the values ​​1 and 0 of outputs OUT' and OUT" respectively.

[0128] At time t1 after time t0, the rising edge of signal clk causes output OUT to be updated to value 2, and the falling edge of signal clk / 2 causes output OUT” to be updated to value 1, while output OUT' remains at its current value 1. Therefore, output OUT1 changes from value 1 to value 2, which is equal to the sum of the values ​​1 and 1 of outputs OUT' and OUT” respectively.

[0129] At time t2, after time t1, the rising edge of signal clk causes output OUT to be updated to value 3, and the rising edge of signal clk / 2 causes output OUT' to be updated to value 2, while output OUT" remains at its current value 1. Therefore, output OUT1 changes from value 2 to value 3, which is equal to the sum of the values ​​2 and 1 of outputs OUT' and OUT" respectively.

[0130] At time t3, after time t2, the rising edge of signal clk causes output OUT to be updated to value 4, and the falling edge of signal clk / 2 causes output OUT” to be updated to value 2, while output OUT' remains at its current value 2. Therefore, output OUT1 changes from value 3 to value 4, which is equal to the sum of the values ​​2 and 2 of outputs OUT' and OUT” respectively.

[0131] At time t4, after time t3, the rising edge of signal clk causes output OUT to be updated to value 5, and the rising edge of signal clk / 2 causes output OUT' to be updated to value 3, while output OUT" remains at its current value 2. Therefore, output OUT1 changes from value 4 to value 5, which is equal to the sum of the values ​​3 and 2 of outputs OUT' and OUT" respectively.

[0132] At time t5, after time t4, the rising edge of signal clk causes output OUT to be updated to value 6, and the falling edge of signal clk / 2 causes output OUT” to be updated to value 3, while output OUT' remains at its current value 3. Therefore, output OUT1 changes from value 5 to value 6, which is equal to the sum of the values ​​3 and 3 of outputs OUT' and OUT” respectively.

[0133] At time t6, after time t5, the rising edge of signal clk causes output OUT to be updated to value 7, and the rising edge of signal clk / 2 causes output OUT' to be updated to value 4, while output OUT" remains at its current value 3. Therefore, output OUT1 changes from value 6 to value 7, which is equal to the sum of the values ​​4 and 3 of outputs OUT' and OUT" respectively.

[0134] At time t7, after time t6, the rising edge of signal clk causes output OUT to be updated to value 8, and the falling edge of signal clk / 2 causes output OUT” to be updated to value 4, while output OUT' remains at its current value 4. Therefore, output OUT1 changes from value 7 to value 8, which is equal to the sum of the values ​​4 and 4 of outputs OUT' and OUT” respectively.

[0135] like Figure 8 As can be seen, output OUT1 is updated at each rising edge of signal clk, similar to output OUT. Therefore, circuits 1 and 3 have the same output signals OUT and OUT1.

[0136] also, Figure 7 The power consumption of circuit 3 is lower than Figure 6 The power consumption of circuit 1, and Figure 7 The maximum drop in voltage Vdd in circuit 3 is less than Figure 6 The maximum drop in voltage Vdd in circuit 1.

[0137] Figure 9Synchronization circuit 1 is shown as an example, where circuit 1 is a synchronous shift register.

[0138] exist Figure 9 In the example, triggers 100 are updated at each rising edge of signal clk, and their respective outputs remain at their current value between two consecutive updates, or in other words, between two consecutive rising edges of signal clk.

[0139] exist Figure 9 In the example, circuit 1 includes four flip-flops 100 connected in series. The first flip-flop 100 in the sequence of flip-flops 100 (located in...) Figure 9 The first flip-flop (left side) receives the input IN of the receiving circuit 1 and provides the output Q1. The second flip-flop 100 receives the output Q1 as its input data and provides the output Q2. The third flip-flop 100 receives the output Q2 as its input data and provides the output Q3. The fourth or final flip-flop 100 receives the output Q3 as its input data and provides the output Q4.

[0140] In this example, circuit 1 is a synchronous shift register, and the output OUT of circuit 1 is the output Q4 of the last flip-flop 100 in the series of flip-flops.

[0141] In this example, circuit 1 is a synchronous shift register that receives input IN.

[0142] For example, the first flip-flop 100 in the sequence of flip-flops 100 connected in series (located in...) Figure 9 The circuit 102 associated with the flip-flop 100 (on the left side of the sequence) corresponds to the connection line between the input D and the input IN of the flip-flop 100. For each flip-flop 100 in the sequence other than the first flip-flop, the circuit 102 associated with the flip-flop 100 corresponds to the connection line between the input D of the flip-flop 100 and the output Q of the previous flip-flop 100 in the sequence.

[0143] Figure 10 Synchronization circuit 3 is shown as an example, where circuit 3 is a synchronous shift register.

[0144] When circuit 3 is a synchronous shift register, circuits 30 and 32 are two synchronous shift registers, preferably identical to each other. Furthermore, circuit 34 is, for example, a selection circuit configured to selectively select output OUT' or output OUT" based on the state of signal clk / 2. For example, combinational logic circuit 34 is configured to provide output OUT1 equal to output OUT' after each edge of signal clk / 2 corresponding to the update of output OUT" and before the next edge of signal clk / 2, and to provide output OUT1 equal to output OUT" after each edge of signal clk / 2 corresponding to the update of output OUT' and before the next edge of signal clk / 2.

[0145] exist Figure 10 In the example, synchronous shift register 3 provides output OUT1, which is offset by the number of cycles of the signal clk relative to the input IN of circuit 3. Figure 9 The output OUT of circuit 1 is offset by the same number of cycles relative to the input IN of circuit 1. Therefore, in this example, circuit 3 includes four flip-flops, more specifically, two flip-flops 300 connected in series in circuit 30 and two flip-flops 320 connected in series in circuit 32.

[0146] In circuit 30, flip-flops 300 are connected in series. The first flip-flop 300 in the sequence (in...) Figure 10 The flip-flop 300 located on the left receives the input IN of circuit 3 at its input D. Each subsequent flip-flop 300 receives the output Q of the previous flip-flop 300 at its input D. The output OUT' corresponds to the last flip-flop 300 (located on the left). Figure 10 The output is located on the right side.

[0147] In circuit 32, flip-flops 320 are connected in series. The first flip-flop 320 in the sequence (in...) Figure 10 The flip-flop 320 located on the left receives the input IN of circuit 3 at its input D. Each subsequent flip-flop 320 receives the output Q of the previous flip-flop 320 at its input D. The output OUT corresponds to the last flip-flop 320 (located on the left). Figure 10 The output is located on the right side.

[0148] exist Figure 10 In the example circuit 30, the first flip-flop 300 receives the signal IN at its input D and provides the output Q1', and the second or last flip-flop 300 receives the output Q1' at its input D and provides the output Q2', with the signal OUT' being the output Q2'. Each circuit 302 corresponds to the connection line between the input D of the associated flip-flop 300 and the input IN (for the first flip-flop 300) or the output Q of the previous flip-flop 300.

[0149] exist Figure 10 In the example circuit 32, the first flip-flop 320 receives the signal IN at its input D and provides the output Q1", and the second or last flip-flop 320 receives the output Q1" at its input D and provides the output Q2", and the signal OUT" is the output Q2". Each circuit 322 corresponds to the connection line between the input D of the associated flip-flop 320 and the input IN (for the first flip-flop 320) or the output Q of the previous flip-flop 320.

[0150] exist Figure 10 In the example, flip-flop 300 is updated at each rising edge of signal clk / 2, and flip-flop 320 is updated at each falling edge of signal clk / 2. Circuit 34 provides output OUT1 equal to output OUT' when signal clk / 2 is low, and provides output OUT1 equal to output OUT" when signal clk / 2 is high.

[0151] Figure 11 It shows the relationship with Figure 9 Compared to the operation of circuit 1 Figure 10 The operation of circuit 3.

[0152] More specifically, Figure 11 The following example illustrates the evolution of a signal over time t: applied to Figure 9 Circuit 1 and Figure 10 The input signal IN of circuit 3; the clock signal clk; Figure 9 The output of circuit 1 is OUT (or Q4); the clock signal is clk / 2; Figure 10 The output OUT' (or Q2') of circuit 30; Figure 10 The output of circuit 32 is OUT" (or Q2"); and Figure 10 The output OUT1 of circuit 3.

[0153] exist Figure 11 In the diagram, the updates of signals OUT, OUT', OUT" and OUT1 are shown with a delay relative to the corresponding edges of signals clk and clk / 2, which is consistent with... Figure 4 The differences are represented in the text.

[0154] exist Figure 11 In the example, circuit 1 is configured to update its output OUT at each rising edge of signal clk, circuit 30 is configured to update its output OUT' at each rising edge of signal clk / 2, and circuit 32 is configured to update its output OUT" at each falling edge of signal clk / 2. Furthermore, to better compare the operation of circuits 1 and 3, in Figure 11 Each rising edge of the signal clk / 2 is synchronized with the corresponding rising edge of the signal clk.

[0155] exist Figure 11 The example shows eleven consecutive rising edges of the signal clk, labeled as t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, and t10.

[0156] At time t0, corresponding to the rising edge of signal clk / 2, the input signal IN has a value V0. Because... Figure 9 Circuit 1 includes four flip-flops 100, therefore the output OUT of circuit 1 is updated to the value V0 at time t3. Furthermore, since circuit 30 is a synchronous shift register including two flip-flops 300 synchronized on the rising edge of signal clk / 2, the output OUT' is updated to the value V0 at time t2 corresponding to the rising edge following the rising edge of signal clk / 2 at time t0. Output OUT' remains at value V0 until its next update.

[0157] At time t1, which is after time t0 and corresponds to the falling edge of signal clk / 2, the input signal IN has a value V1. Figure 9 The output OUT of circuit 1 is updated to the value V1 at time t4. Furthermore, since circuit 32 is a synchronous shift register comprising two flip-flops 320 synchronized on the falling edge of signal clk / 2, the output OUT" is updated to the value V1 at time t3, corresponding to the falling edge following the falling edge of signal clk / 2 at time t1. Output OUT" remains at value V1 until its next update.

[0158] At time t2, which corresponds to the rising edge of signal clk / 2, the input signal IN has a value V2. Figure 9 The output OUT of circuit 1 is updated to the value V2 at time t5. Furthermore, the output OUT' is updated to the value V2 at time t4, corresponding to the rising edge following the rising edge of the signal clk / 2 at time t2. Output OUT' remains at the value V2 until its next update.

[0159] At time t3, which is after time t2 and corresponds to the falling edge of signal clk / 2, the input signal IN has a value of V3. Figure 9 The output OUT of circuit 1 is updated to the value V3 at time t6. Furthermore, the output OUT" is updated to the value V3 at time t5, corresponding to the falling edge following the falling edge of the signal clk / 2 at time t3. The output OUT" remains at the value V3 until its next update.

[0160] At time t4, which is after time t3 and corresponds to the rising edge of signal clk / 2, the input signal IN has the value V4. Figure 9The output OUT of circuit 1 is updated to the value V4 at time t7. Furthermore, the output OUT' is updated to the value V4 at time t6, corresponding to the rising edge following the rising edge of the signal clk / 2 at time t4. Output OUT' remains at the value V4 until its next update.

[0161] At time t5, which is after time t4 and corresponds to the falling edge of signal clk / 2, the input signal IN has a value of V5. Figure 9 The output OUT of circuit 1 is updated to the value V5 at time t8. Furthermore, the output OUT” is updated to the value V5 at time t7, corresponding to the falling edge of signal clk / 2 after the falling edge at time t5. The output OUT” remains at the value V5 until its next update.

[0162] At time t6, which is after time t5 and corresponds to the rising edge of signal clk / 2, the input signal IN has the value V6. Figure 9 The output OUT of circuit 1 is updated to the value V6 at time t9. Furthermore, the output OUT' is updated to the value V6 at time t8, corresponding to the rising edge of the signal clk / 2 after the rising edge at time t6. Output OUT' remains at the value V6 until its next update.

[0163] At time t7, which is after time t6 and corresponds to the falling edge of signal clk / 2, the input signal IN has a value of V7. Figure 9 The output OUT of circuit 1 is updated to the value V7 at time t10. Furthermore, the output OUT” is updated to the value V7 at time t9, corresponding to the falling edge of the signal clk / 2 after the falling edge at time t7. The output OUT” remains at the value V7 until its next update.

[0164] Furthermore, between times t3 and t4, t5 and t6, t7 and t8, and t9 and t10, signal clk / 2 is low, therefore circuit 34 provides output OUT1, which is equal to output OUT'. Conversely, between times t4 and t5, t6 and t7, and t8 and t9, signal clk / 2 is high, therefore circuit 34 provides output OUT1, which is equal to output OUT'.

[0165] As a result, output OUT1 has the value V0 between times t3 and t4, the value V1 between times t4 and t5, the value V2 between times t5 and t6, the value V3 between times t6 and t7, the value V4 between times t7 and t8, the value V5 between times t8 and t9, the value V6 between times t9 and t10, and the value V7 after time t10.

[0166] If possible Figure 11As can be seen, similar to output OUT, output OUT1 is updated at each rising edge of signal clk. Therefore, circuits 1 and 3 have the same output signals OUT and OUT1.

[0167] also, Figure 10 The power consumption of circuit 3 is lower than Figure 9 The power consumption of circuit 1, and Figure 10 The maximum drop in voltage Vdd in circuit 3 is less than Figure 9 The maximum drop in voltage Vdd in circuit 1.

[0168] Although not shown in the figure, the synchronous shift register 3 may be part of an electronic system or device including transmitting and receiving circuitry. The transmitting circuitry is configured to provide first data updated at each first-type edge of a clock signal clk, the frequency of which is twice the frequency of a signal clk / 2. The receiving circuitry is configured to receive second data updated at each first-type edge of the clock signal clk. In such a system, the shift register 3 is configured, for example, to receive the first data and provide the second data by shifting the first data in time.

[0169] Already referenced Figure 6 and Figure 9 Described Figure 3 Two specific examples of circuit 3 are a synchronous counter and a synchronous shift register. Those skilled in the art can implement other circuits with... Figure 3 Circuit 3 has the structure of Circuit 3, but provides other functions such as a linear feedback shift register.

[0170] Furthermore, in all the examples described above, the first type edge that causes the trigger 300 of circuit 30 to update due to signal clk / 2 and the second type edge that causes the trigger 320 of circuit 32 to update due to signal clk / 2 are rising and falling edges, respectively. Those skilled in the art can adapt this specification and examples to the case where the first type edge is a falling edge and the second type edge is a rising edge.

[0171] In the previous comparison between circuits 1 and 3, the output OUT of circuit 1 is updated at each first-type edge of signal clk, the output OUT' is updated at each first-type edge of signal clk / 2, the frequency of which is half the frequency of signal clk, and the output OUT" is updated at each second-type edge of signal clk / 2. In this configuration, the power consumption and voltage drop ΔVdd in circuit 3 are lower than those in circuit 1. However, it is also possible that in circuit 3, the output OUT' is updated at each first-type edge of signal clk, and the output OUT" is updated at each second-type edge of signal clk. In this case, the rate at which the output OUT1 of circuit 3 is updated is twice as fast as the rate at which the output of the corresponding circuit 1, synchronized on the first-type edges of signal clk, is updated. In other words, in this configuration, instead of improving power consumption and reducing voltage drop in the clock tree, the time resolution of circuit 3 is increased by twice that of the corresponding circuit 1. For example, if circuits 1 and 3 both implement shift registers, then shift register 3 processes input data and provides updated output data at twice the rate of shift register 1. Similarly, if circuits 1 and 3 both implement counters, then counter 3 counts at twice the rate of counter 1.

[0172] Various embodiments and variations have been described. Those skilled in the art will recognize that certain features of these embodiments can be combined, and other variations will readily arise. In particular, the total number of flip-flops 300 and 320 in the example of circuit 3 described above may differ from the number explicitly described above.

[0173] Finally, based on the functional descriptions provided above (especially regarding the implementations of circuits 302, 322, and 34), those skilled in the art can implement the actual implementations of the embodiments and variations described herein.

Claims

1. A synchronization circuit, comprising: Multiple flip-flops are configured to provide an updated output at each first type edge of a first clock signal; A first circuit includes a first flip-flop of the plurality of flip-flops, the first flip-flop being synchronized and updated on a first type edge of a second clock signal, the second clock signal having a frequency equal to half the frequency of the first clock signal, the first circuit being configured to provide a first output updated at each first type edge of the second clock signal; The second circuit includes a second flip-flop among the plurality of flip-flops, the second flip-flop being synchronized and updated on a second type edge of the second clock signal, and the second circuit is configured to provide a second output that is updated at each second type edge of the second clock signal; as well as A combinational logic circuit that receives the first output and the second output, and is configured to provide the output of the synchronization circuit based on the first output and the second output.

2. The synchronization circuit according to claim 1, wherein the number of first flip-flops is equal to the number of second flip-flops.

3. The synchronization circuit according to claim 1, wherein the first circuit includes more than one first flip-flop, and the second circuit includes more than one second flip-flop.

4. The synchronization circuit according to claim 1, wherein the first circuit and the second circuit each have the same function.

5. The synchronization circuit of claim 1, wherein each first flip-flop is configured to maintain its output between every two updates of the first flip-flop, and each second flip-flop is configured to maintain its output between every two updates of the second flip-flop.

6. The synchronization circuit according to claim 1, wherein the first flip-flop is connected in series in the first circuit, and the second flip-flop is connected in series in the second circuit.

7. The synchronization circuit according to claim 1, wherein the first output is determined by at least one output of the first flip-flops, and the second output is determined by at least one output of the second flip-flops.

8. The synchronization circuit according to claim 1, wherein the synchronization circuit is a synchronization counter.

9. The synchronization circuit of claim 8, wherein the first circuit is a first synchronization counter, the second synchronization circuit is a second synchronization counter, and the combinational logic circuit is an adder circuit configured to add the first output and the second output and provide an output of the synchronization circuit equal to the result of the addition.

10. The synchronization circuit according to claim 8, wherein: For each first flip-flop, the first circuit includes circuitry that provides an input to the first flip-flop based on at least one of the outputs of the first flip-flop, the at least one output including the output of the first flip-flop; and For each second flip-flop, the second circuit includes circuitry that provides an input to the second flip-flop based on at least one of the outputs of the second flip-flop, the at least one output including the output of the second flip-flop.

11. The synchronization circuit according to claim 1, wherein the synchronization circuit is a shift register.

12. The synchronization circuit of claim 11, wherein the first circuit is a first shift register, the second circuit is a second shift register, and the combinational logic circuit is configured to provide an output of the synchronization circuit equal to a first output of the first circuit when the second clock signal is in a state following each second type edge of the second clock signal, and to provide an output of the synchronization circuit equal to a second output of the second circuit when the second clock signal is in a state following each first type edge of the second clock signal.

13. The synchronization circuit according to claim 12, wherein: The first flip-flops are connected in series, the first of the first flip-flops has an input that receives the input of the synchronization circuit, and each of the other first flip-flops has an input that is connected to the output of the previous first flip-flop, and the last of the first flip-flops has an output that provides the first output; and The second flip-flops are connected in series, the first of the second flip-flops has an input that receives the input of the synchronization circuit, and each of the other second flip-flops has an input that connects to the output of the previous second flip-flop, and the last of the second flip-flops has an output that provides the second output.

14. A system comprising: The transmitting circuit is configured to provide updated first data at each first type edge of the first clock signal; The receiving circuit is configured to receive updated second data at each first type edge of the first clock signal; as well as A synchronization circuit, configured to receive the first data and provide the second data by shifting the first data, the synchronization circuit comprising: Multiple flip-flops are configured to provide an updated output at each first type edge of the first clock signal; A first circuit includes a first flip-flop of the plurality of flip-flops, the first flip-flop being synchronized and updated on a first type edge of a second clock signal, the second clock signal having a frequency equal to half the frequency of the first clock signal, the first circuit being configured to provide an updated first output at each first type edge of the second clock signal; A second circuit includes a second flip-flop among the plurality of flip-flops, the second flip-flop being synchronized and updated on a second type edge of the second clock signal, and the second circuit being configured to provide an updated second output at each second type edge of the second clock signal; and A combinational logic circuit that receives the first output and the second output and is configured to provide the output of the synchronization circuit based on the first output and the second output.

15. The system of claim 14, wherein the first circuit includes more than one first flip-flop, and the second circuit includes more than one second flip-flop.

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