Computing device

Abstract

The embodiment of the application provides a kind of computing device, it is related to computing technical field.The computing device includes box, backplate and computing node.The box includes at least one first installation site, each first installation site is used to supply one functional node, each first installation site can be inserted different types of functional node.Backplate is fixedly connected with the box, and first installation site is opposite to backplate.Backplate includes first high-speed signal connection structure and second high-speed signal connection structure corresponding to first installation site.First high-speed signal connection structure is electrically connected with computing node, and second high-speed signal connection structure is electrically connected with first high-speed signal connection structure.Second high-speed signal connection structure is used to be inserted with the functional node of corresponding first installation site insertion connection.This way, the reconfiguration of computing device is more flexible, and it is convenient to adjust the configuration of computing device according to the change of business demand.

Description

Technical Field

[0001] This application relates to the field of computing technology, and more particularly to a computing device. Background Technology

[0002] Computing devices such as servers and computers may include components such as processors, motherboards, internal components, memory, and computing accelerator cards. In related technologies, these components are typically located on the motherboard and interact with each other through it. However, due to constantly changing business needs, the flexibility of reconfiguring computing devices in these technologies is poor, making it difficult to adjust the configuration of computing devices flexibly according to changes in business requirements. Summary of the Invention

[0003] This application provides a computing device that is highly flexible in its configuration, allowing for adjustments to the device's configuration based on changes in business needs.

[0004] This application provides a computing device, which includes a housing, a backplane, and computing nodes.

[0005] The enclosure includes at least one first mounting position, each first mounting position is used for inserting a functional node, and each first mounting position can insert different types of functional nodes. The back panel is fixedly connected to the enclosure, and the first mounting positions are opposite to the back panel.

[0006] The backplane includes a first high-speed signal connection structure and a second high-speed signal connection structure corresponding to the first mounting position. The first high-speed signal connection structure is electrically connected to the computing node, and the second high-speed signal connection structure is electrically connected to the first high-speed signal connection structure. The second high-speed signal connection structure is used to connect to the functional node inserted in the corresponding first mounting position, so that the computing node and the functional node can realize data transmission through the first high-speed signal connection structure and the second high-speed signal connection structure.

[0007] The computing device provided in this application embodiment allows for configuration changes when necessary. It allows for the insertion of a target-configuration functional node into an empty first mounting position, or the replacement of the original functional node in the first mounting position with the target-configuration functional node. After insertion into the first mounting position, the functional node connects to a second high-speed signal connection structure. The functional node can transmit data with the computing node through the high-speed signal channel formed by the second and first high-speed signal connection structures, thereby enabling configuration changes. This flexibility allows for adjustments to the computing device configuration based on changes in business requirements. Furthermore, the hardware configuration of the functional nodes is highly flexible. By adding, removing, or replacing functional nodes, specific hardware can be added, removed, or replaced according to business needs. This facilitates on-demand adjustments to the computing device configuration, minimizing hardware idleness and configuration waste, and promoting full utilization of the configuration.

[0008] In some possible implementations, the enclosure includes at least two first mounting positions. The back panel also includes third high-speed signal connection structures corresponding to the first mounting positions, with each first mounting position corresponding to m third high-speed signal connection structures, where m = n - 1, and n is the number of first mounting positions.

[0009] Each first mounting position corresponds to any one third high-speed signal connection structure, which is electrically connected to a third high-speed signal connection structure corresponding to another first mounting position, so that m third high-speed signal connection structures corresponding to any one first mounting position are electrically connected to a third high-speed signal connection structure corresponding to another first mounting position. The third high-speed signal connection structure is used to connect to the functional node inserted in the corresponding first mounting position, so that any two functional nodes inserted in different first mounting positions can realize data transmission through the third high-speed signal connection structure.

[0010] In this way, the enclosure can accommodate at least two functional nodes, enabling the computing device to have good reconfiguration capabilities. Furthermore, it facilitates interconnection between functional nodes inserted in different first mounting positions, allowing data transmission between these nodes via a high-speed signal channel formed by two interconnected third high-speed signal connection structures. This results in high data transmission efficiency between functional nodes inserted in different first mounting positions, further enhancing the computing device's reconfiguration capabilities.

[0011] In some possible implementations, the backplane further includes a first low-speed signal connection structure and a second low-speed signal connection structure corresponding to the first mounting position. The first low-speed signal connection structure is electrically connected to the computing node, and the second low-speed signal connection structure is electrically connected to the first low-speed signal connection structure. The second low-speed signal connection structure is used to connect to a functional node inserted in the corresponding first mounting position, so that the computing node and the functional node can transmit data through the first low-speed signal connection structure and the second low-speed signal connection structure.

[0012] In this way, the functional node inserted in the first mounting position can transmit data with the computing node through the low-speed signal channel formed by the second low-speed signal connection structure and the first low-speed signal connection structure, so as to realize functions such as managing the functional node and connecting the functional node to the local area network.

[0013] In some possible implementations, the computing device also includes a functional node, with at least one functional node inserted in a first mounting position.

[0014] The functional node includes a fourth high-speed signal connection structure. The fourth high-speed signal connection structure of the functional node is connected to the second high-speed signal connection structure corresponding to the first mounting position of the functional node. The computing node can realize data transmission through the first high-speed signal connection structure, the second high-speed signal connection structure and the fourth high-speed signal connection structure.

[0015] This facilitates the electrical connection between the functional nodes and the second high-speed signal connection structure, thereby enabling the modification of the computing device by inserting functional nodes. Devices within the functional nodes can transmit data or disconnect from the computing node by switching their connection to the fourth high-speed signal connection structure.

[0016] In some possible implementations, the functional node further includes m fifth high-speed signal connection structures. Any one of the fifth high-speed signal connection structures of the functional node is connected to a third high-speed signal connection structure corresponding to the first mounting position of the functional node, enabling data transmission between one fifth high-speed signal connection structure of the functional node and a fifth high-speed signal connection structure of another functional node via the third high-speed signal connection structure.

[0017] This facilitates the electrical connection between the functional nodes and the m third high-speed signal connection structures corresponding to the first mounting positions where the functional nodes are inserted, thereby enabling data transmission between functional nodes inserted in different first mounting positions. Devices within a functional node can transmit or disconnect data with other functional nodes by connecting or disconnecting from each fifth high-speed signal connection structure.

[0018] In some possible implementations, the functional node further includes a third low-speed signal connection structure. This third low-speed signal connection structure of the functional node is connected to the second low-speed signal connection structure corresponding to the first mounting position on the functional node. The computing node can then transmit data through the first and second low-speed signal connection structures on the backplane and the third low-speed signal connection structure.

[0019] This facilitates the electrical connection between the functional node and the second low-speed signal connection structure, thereby enabling the management of the functional node and the connection of the functional node to the local area network.

[0020] In some possible implementations, at least one functional node is a first computing acceleration node. The first computing acceleration node further includes a first computing acceleration card, which is electrically connected to a fourth high-speed signal connection structure via a cable. Data transmission between the first computing acceleration card and the computing node is achieved through the fourth high-speed signal connection structure, the second high-speed signal connection structure, and the first high-speed signal connection structure. When the computing device includes multiple first computing acceleration nodes, the first computing acceleration cards of different first computing acceleration nodes achieve data transmission with the computing node through the fourth high-speed signal connection structure, the second high-speed signal connection structure, the first high-speed signal connection structure, and the computing node.

[0021] In this way, the first computing accelerator card can perform efficient data transmission with the computing nodes, providing computing acceleration functionality. When a computing device includes multiple first computing accelerator nodes, data transmission can be performed between the first computing accelerator cards of different nodes, enabling the computing device to have better computing acceleration performance. The first computing accelerator card is electrically connected to the fourth high-speed signal connection structure via cables, allowing for flexible placement of the first computing accelerator card and reducing the thickness of the first computing accelerator node.

[0022] In some possible implementations, at least one functional node is a second computing acceleration node. The second computing acceleration node further includes a second computing acceleration card and a first switching board. The second computing acceleration card is electrically connected to the first switching board via a cable. This electrical connection allows for more flexible placement of the second computing acceleration card, which helps reduce the thickness of the second computing acceleration node. When the second computing acceleration node includes multiple second computing acceleration cards, these cards can interact through the first switching board, facilitating efficient utilization of each card.

[0023] In some examples where at least one functional node is a second computing acceleration node, the first switching board is electrically connected to the fourth high-speed signal connection structure, and the second computing acceleration card and the computing node achieve data transmission through the first switching board, the fourth high-speed signal connection structure, the second high-speed signal connection structure and the first high-speed signal connection structure.

[0024] In this way, the second computing accelerator card can transmit data with the computing node and provide computing acceleration functionality. When the second computing accelerator node includes multiple second computing accelerator cards, the computing node can transmit data with each of the second computing accelerator cards through the switching of the first switching board, which is beneficial for making full use of each second computing accelerator card.

[0025] In some examples where at least one functional node is a second computing acceleration node, the first switching board is electrically connected to the fifth high-speed signal connection structure of the second computing acceleration node. When the computing device includes multiple functional nodes, the second computing acceleration card of the second computing acceleration node and other functional nodes achieve data transmission through the first switching board, the fifth high-speed signal connection structure and the third high-speed signal connection structure.

[0026] In this way, the second computing accelerator card can transmit data with other functional nodes and provide computing acceleration functions to them. Through the switching of the first switching board, other functional nodes can transmit data with each of the second computing accelerator cards, which is conducive to making full use of each second computing accelerator card.

[0027] For example, the first switching board is electrically connected to the fourth and fifth high-speed signal connection structures, enabling the second computing accelerator card to transmit data with computing nodes and other functional nodes through the first switching board, thus providing computing acceleration functionality to the computing nodes and other functional nodes. Through the switching of the first switching board, computing nodes and other functional nodes can transmit data with each of the second computing accelerator cards, resulting in high utilization efficiency of each second computing accelerator card.

[0028] In some possible implementations, at least one functional node is a first storage node, and the first storage node further includes a first memory. The first memory is electrically connected to a fourth high-speed signal connection structure via a cable. Data transmission between the first memory and the computing node is achieved through the fourth high-speed signal connection structure, the second high-speed signal connection structure, and the first high-speed signal connection structure.

[0029] In this way, the first memory can transmit data with the computing node and provide storage functionality for the computing node. The first memory is electrically connected to the fourth high-speed signal connection structure via cables, which allows for more flexible placement of the first memory and helps to reduce the thickness of the first memory node.

[0030] In some possible implementations, at least one functional node is a second storage node, which further includes a second memory and a second switching board. The second memory is electrically connected to the second switching board via a cable. This electrical connection allows for more flexible arrangement of the second memory, which helps reduce the thickness of the second storage node. When the second storage node includes multiple second memories, these memories can interact through the second switching board, facilitating efficient utilization of each memory.

[0031] In some examples where at least one functional node is a second storage node, the second switching board is electrically connected to the fourth high-speed signal connection structure, and the second memory and the computing node achieve data transmission through the second switching board, the fourth high-speed signal connection structure, the second high-speed signal connection structure and the first high-speed signal connection structure.

[0032] In this way, the second memory can transmit data with the compute node and provide storage functionality for the compute node. When the second storage node includes multiple second memories, the compute node can transmit data with each second memory through the switching of the second switching board, which is beneficial for making full use of each second memory.

[0033] In some examples where at least one functional node is a second storage node, the second switching board is electrically connected to the fifth high-speed signal connection structure of the second storage node. When the computing device includes multiple functional nodes, the second memory of the second storage node and other functional nodes achieve data transmission through the second switching board, the fifth high-speed signal connection structure and the third high-speed signal connection structure.

[0034] In this way, the second memory can transmit data with other functional nodes and provide storage functionality for them. Through the switching on the second switching board, other functional nodes can transmit data with each of the second memories, facilitating full utilization of each second memory.

[0035] For example, the second switching board is electrically connected to the fourth and fifth high-speed signal connection structures, enabling the second memory to transmit data with computing nodes and other functional nodes via the second switching board, thus providing storage functionality for the computing nodes and other functional nodes. Through the switching of the second switching board, computing nodes and other functional nodes can transmit data with each of the second memories, resulting in high utilization efficiency of each second memory.

[0036] In some possible implementations, at least one functional node is a third storage node, which further includes a third memory and a fourth memory corresponding to the fifth high-speed signal connection structure of the third storage node. The third memory is electrically connected to the fourth high-speed signal connection structure via a cable, and data transmission between the third memory and the computing node is achieved through the fourth high-speed signal connection structure, the second high-speed signal connection structure, and the first high-speed signal connection structure. The fourth memory is electrically connected to the corresponding fifth high-speed signal connection structure via a cable. When the computing device includes multiple functional nodes, the fourth memory of the third storage node and other functional nodes achieve data transmission through the fifth high-speed signal connection structure and the third high-speed signal connection structure.

[0037] In this way, the third memory can transmit data with the computing node and provide storage functionality for it. The fourth memory can transmit data with other functional nodes and provide storage functionality for them. The third memory is electrically connected to the fourth high-speed signal connection structure via cables, and the fourth memory is electrically connected to the corresponding fifth high-speed signal connection structure via cables. This allows for flexible arrangement of the third and fourth memories and helps reduce the thickness of the third memory node.

[0038] In some possible implementations, at least one functional node is a memory node, and the memory node further includes a first memory. The first memory is electrically connected to a fourth high-speed signal connection structure via a cable. Data transmission between the first memory and the computing node is achieved through the fourth high-speed signal connection structure, the second high-speed signal connection structure, and the first high-speed signal connection structure.

[0039] In this way, the first memory can transmit data with the compute node and provide memory functionality to the compute node. The first memory is electrically connected to the fourth high-speed signal connection structure via cables, which allows for more flexible placement of the first memory and helps to reduce the thickness of the memory node.

[0040] In some possible implementations, at least one functional node is an extended computing node. The extended computing node also includes a first central processing unit and a first motherboard. The first central processing unit is located on the first motherboard and is electrically connected to the first motherboard. By inserting the extended computing node, it is convenient to build a hyperconverged architecture, and the cost of building a hyperconverged architecture is relatively low.

[0041] In some examples where at least one functional node is an extended computing node, the first motherboard is electrically connected to the third low-speed signal connection structure of the extended computing node, and the first central processing unit of the extended computing node and the computing node achieve data transmission through the first motherboard, the third low-speed signal connection structure, the second low-speed signal connection structure of the backplane, and the first low-speed signal connection structure of the backplane.

[0042] In this way, the first central processing unit can transmit data with the computing node through the third low-speed signal connection structure, so as to facilitate access to the local area network through the computing node.

[0043] In some examples where at least one functional node is an extended computing node, the first motherboard is electrically connected to the fifth high-speed signal connection structure of the extended computing node. When the computing device includes multiple functional nodes, the first central processing unit of the extended computing node and other functional nodes achieve data transmission through the first motherboard, the fifth high-speed signal connection structure and the third high-speed signal connection structure.

[0044] In this way, the first central processing unit can transmit data with other functional nodes through the fifth high-speed signal connection structure. The first central processing unit can call the configuration of other functional nodes, which is convenient for building a hyper-converged architecture with other functional nodes, enabling computing devices to have high performance and more efficient use of configuration.

[0045] In some possible implementations, the computing node includes a first signal enhancement board, a second motherboard, and a processing module. The processing module is disposed on and electrically connected to the second motherboard, the second motherboard is electrically connected to the first signal enhancement board, and a first high-speed signal connection structure is electrically connected to the first signal enhancement board, enabling the processing module and the functional node to transmit data through the second motherboard, the first signal enhancement board, the first high-speed signal connection structure, and the second high-speed signal connection structure.

[0046] In this way, by enhancing the signal through the first signal enhancement board, the data transmission performance between the processing module and the functional nodes can be improved, which is conducive to the efficient invocation of the functional node configuration by the processing module. Attached Figure Description

[0047] Figure 1 A schematic diagram of a computing device provided in an embodiment of this application;

[0048] Figure 2 A schematic diagram of yet another computing device provided in an embodiment of this application;

[0049] Figure 3 A schematic diagram of yet another computing device provided in an embodiment of this application;

[0050] Figure 4 A schematic diagram of a backplate provided in an embodiment of this application;

[0051] Figure 5 A topology diagram of a backplane provided in an embodiment of this application;

[0052] Figure 6 A schematic diagram of yet another computing device provided in an embodiment of this application;

[0053] Figure 7 A schematic diagram of yet another computing device provided in an embodiment of this application;

[0054] Figure 8 A schematic diagram of yet another computing device provided in an embodiment of this application;

[0055] Figure 9 A schematic diagram of a functional node provided in an embodiment of this application;

[0056] Figure 10 A topology diagram of a first computing acceleration node provided in an embodiment of this application;

[0057] Figure 11 A topology diagram of a second computing acceleration node provided in an embodiment of this application;

[0058] Figure 12 A topology diagram of a first storage node provided in an embodiment of this application;

[0059] Figure 13 A topology diagram of a second storage node provided in an embodiment of this application;

[0060] Figure 14 A topology diagram of a third storage node provided in an embodiment of this application;

[0061] Figure 15 A memory node topology diagram provided in an embodiment of this application;

[0062] Figure 16 A topology diagram of an extended computing node is provided in an embodiment of this application;

[0063] Figure 17 A topology diagram of a computing device provided in an embodiment of this application;

[0064] Figure 18 This application provides another topology diagram of a computing device.

[0065] Figure 19 This application provides another topology diagram of a computing device.

[0066] Figure 20 This application provides another topology diagram of a computing device.

[0067] Figure 21 This application provides another topology diagram of a computing device.

[0068] Figure 22 This application provides another topology diagram of a computing device.

[0069] Figure 23This application provides another topology diagram of a computing device.

[0070] Figure 24 This application provides another topology diagram of a computing device.

[0071] Figure 25 This is a topology diagram of another computing device provided in an embodiment of this application.

[0072] Explanation of reference numerals in the attached figures:

[0073] 100. Box body;

[0074] 200. Back panel;

[0075] 300. Compute nodes;

[0076] 400, Functional Node; 400a, First Computation Acceleration Node; 400b, Second Computation Acceleration Node; 400c, First Storage Node; 400d, Second Storage Node; 400e, Third Storage Node; 400f, Memory Node; 400g, Extended Computation Node;

[0077] A1, First mounting position; A2, Second mounting position;

[0078] J1, First high-speed signal connection structure; J2, Second high-speed signal connection structure; J3, Third high-speed signal connection structure; J4, Fourth high-speed signal connection structure; J5, Fifth high-speed signal connection structure; J6, First low-speed signal connection structure; J7, Second low-speed signal connection structure; J8, Third low-speed signal connection structure;

[0079] G1, First computing accelerator card; G2, Second computing accelerator card;

[0080] S1, First memory; S2, Second memory; S3, Third memory; S4, Fourth memory;

[0081] M1, the first memory;

[0082] C1, First Central Processing Unit; C2, Second Central Processing Unit; C3, Third Central Processing Unit;

[0083] B1, First switching board; B2, Second switching board; B3, First mainboard; B4, Second signal enhancement board; B5, Second mainboard; B6, First signal enhancement board;

[0084] x, first direction; y, second direction; z, third direction. Detailed Implementation

[0085] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0086] This application provides a computing device that can be used in scenarios such as offices and conference rooms. This computing device may include, but is not limited to, servers, computers, etc. For example, the computing device may be a workstation.

[0087] Figure 1 This is a schematic diagram of a computing device provided in an embodiment of this application. In the diagram, the x-direction is a first direction, the y-direction is a second direction, and the z-direction is a third direction. The first direction is the depth direction of the computing device, also known as the front-to-back direction. The second direction is the width direction of the computing device, also known as the left-to-right direction. The third direction is the height direction of the computing device, also known as the up-down direction.

[0088] like Figure 1 As shown in the embodiments of this application, the computing device includes a chassis, which includes a housing 100. The housing 100 can accommodate and support other components of the computing device, and the housing 100 can protect the accommodated components.

[0089] Figure 2 This is a schematic diagram of yet another computing device provided in an embodiment of this application. Figure 3 This is a schematic diagram of yet another computing device provided in an embodiment of this application. Figure 4 This is a schematic diagram of a backplate provided in an embodiment of this application. Figure 5 This is a topology diagram of a backplane provided in an embodiment of this application. Figure 2 The diagram shown illustrates the insertion and removal of functional node 400 at the first mounting position A1. Figure 5 The connection structure within the same dashed box is the connection structure corresponding to the same first mounting position A1.

[0090] like Figure 2 As shown in the embodiment of this application, the computing device further includes a computing node 300, which is capable of general computing. The chassis also includes a backplate 200, which is fixedly connected to the enclosure 100. The enclosure 100 includes a second mounting position A2 and at least one first mounting position A1. The computing node 300 is disposed at the second mounting position A2. The first mounting position A1 is opposite to the backplate 200, and each first mounting position A1 is used to insert one functional node 400. Each first mounting position A1 can insert different types of functional nodes 400.

[0091] For example, the configurations of functional nodes 400 of different types are different.

[0092] like Figures 3-5As shown, the backplane 200 includes a first high-speed signal connection structure J1 and a second high-speed signal connection structure J2 corresponding to the first mounting position A1.

[0093] The first high-speed signal connection structure J1 is electrically connected to the computing node 300, and the second high-speed signal connection structure J2 is electrically connected to the first high-speed signal connection structure J1 to realize data transmission between the second high-speed signal connection structure J2 and the computing node 300.

[0094] The second high-speed signal connection structure J2 is used to connect with the functional node 400 inserted in the corresponding first mounting position A1 to realize data transmission between the second high-speed signal connection structure J2 and the inserted functional node 400, so that the computing node 300 and the functional node 400 can realize data transmission through the first high-speed signal connection structure J1 and the second high-speed signal connection structure J2.

[0095] In this way, when the configuration of the computing device needs to be changed, the target configuration functional node 400 can be inserted into the empty first mounting position A1 as needed, or the original functional node 400 inserted in the first mounting position A1 can be replaced with the target configuration functional node 400. After the functional node 400 is inserted into the first mounting position A1, it is connected to the second high-speed signal connection structure J2. The functional node 400 can transmit data with the computing node 300 through the high-speed signal channel formed by the second high-speed signal connection structure J2 and the first high-speed signal connection structure J1, thereby realizing the reconfiguration of the computing device. In this way, the reconfiguration of the computing device is more flexible, and it is easy to adjust the configuration of the computing device according to changes in business needs. In addition, the hardware configuration of the functional node 400 is more flexible. By adding, removing, or replacing the functional node 400, certain specific hardware can be added, removed, or replaced according to business needs. This facilitates flexible adjustment of the computing device configuration as needed, making it less likely to have idle hardware or wasted configuration, and promoting full utilization of the configuration.

[0096] The second high-speed signal connection structure J2 can be plugged into any type of functional node 400 inserted in the corresponding first mounting position A1, and the second high-speed signal connection structure J2 can transmit data with the plugged-in functional node 400.

[0097] For example, the functional node 400 is different in size from the compute node 300.

[0098] For example, the configuration of function node 400 is different from that of compute node 300.

[0099] For example, different types of functional nodes 400 have the same size.

[0100] In some examples, compute node 300 can be a general-purpose compute node used for general computing.

[0101] In some examples, compute node 300 can perform heterogeneous computing in addition to general computing.

[0102] For example, the computing device may include a functional node 400, that is, at least one first mounting position A1 is in which a functional node 400 is inserted. The computing device may also not include a functional node 400, that is, all first mounting positions A1 are in an unoccupied state, and no functional node 400 is inserted in any of the first mounting positions A1.

[0103] For example, the first mounting position A1 is a slot structure located on one side of the housing 100 in a first direction, and the back plate 200 is located on one side of the first mounting position A1 in the first direction. Specifically, the first mounting position A1 is a slot structure located on the front side of the housing 100, and the back plate 200 is located behind the first mounting position A1. The first mounting position A1 is opposite to the back plate 200 along the first direction.

[0104] For example, the first mounting position A1 and the computing node 300 are located on the same side of the back panel 200 in the first direction. Specifically, the first mounting position A1 and the computing node 300 are both located in front of the back panel 200.

[0105] For example, computing node 300 is positioned above the first mounting position A1.

[0106] For example, the second mounting position A2 is a slot structure located on the side of the housing 100 where the first mounting position A1 is provided. Specifically, the second mounting position A2 is a slot structure located on the front side of the housing 100. The computing node 300 can be inserted into the second mounting position A2 and connected to the back plate 200.

[0107] For example, each first mounting position A1 may correspond to one or more second high-speed signal connection structures J2. The functional node 400 inserted into the first mounting position A1 may be inserted into one or more second high-speed signal connection structures J2.

[0108] For example, computing node 300 may be electrically connected to one or more first high-speed signal connection structures J1.

[0109] In some examples, the backplane 200 may include a first high-speed signal connection structure J1 corresponding to the second high-speed signal connection structure J2, wherein the second high-speed signal connection structure J2 is electrically connected to the corresponding first high-speed signal connection structure J1 so as to be electrically connected to the computing node 300 through the corresponding first high-speed signal connection structure J1.

[0110] In some examples, multiple second high-speed signal connection structures J2 can be electrically connected to the same first high-speed signal connection structure J1 to be electrically connected to the computing node 300 through the same first high-speed signal connection structure J1.

[0111] For example, the second high-speed signal connection structure J2 is electrically connected to the first high-speed signal connection structure J1 via a cable.

[0112] For example, the first high-speed signal connection structure J1 and the second high-speed signal connection structure J2 can be high-speed signal connectors or high-speed signal connection terminal groups.

[0113] like Figure 2 , Figure 3 As shown, in some examples, the enclosure 100 has at least two first mounting positions A1, which allows at least two functional nodes 400 to be installed in the enclosure 100, thereby enabling the computing device to have better reconfiguration performance.

[0114] Each first mounting position A1 is in the same relative position as the corresponding second high-speed signal connection structure J2, so that the functional node 400 can be inserted into any first mounting position A1 and connected to the corresponding second high-speed signal connection structure J2.

[0115] For example, multiple first mounting positions A1 are arranged along the height direction of the computing device.

[0116] For example, the enclosure 100 may have four first mounting positions A1 arranged in a row along the height direction of the computing device.

[0117] like Figures 3-5 As shown, in some examples where the housing 100 has at least two first mounting positions A1, the back panel 200 also includes a third high-speed signal connection structure J3 corresponding to the first mounting position A1, with each first mounting position A1 corresponding to m third high-speed signal connection structures J3, where m = n - 1 and n is the number of first mounting positions A1.

[0118] Each first mounting position A1 corresponds to any one third high-speed signal connection structure J3, which is electrically connected to another third high-speed signal connection structure J3 corresponding to another first mounting position A1. This allows m third high-speed signal connection structures J3 corresponding to any one first mounting position A1 to be electrically connected to another third high-speed signal connection structure J3 corresponding to another first mounting position A1. The third high-speed signal connection structure J3 is used to connect to the functional node 400 inserted in the corresponding first mounting position A1, so as to realize data transmission between the third high-speed signal connection structure J3 and the connected functional node 400. This allows any two different functional nodes 400 inserted in the first mounting positions A1 to achieve data transmission through the third high-speed signal connection structure J3.

[0119] This facilitates the interconnection between functional nodes 400 inserted in different first mounting positions A1, allowing data transmission between functional nodes 400 inserted in different first mounting positions A1 through a high-speed signal channel formed by two interconnected third high-speed signal connection structures J3. The data transmission efficiency between functional nodes 400 inserted in different first mounting positions A1 is high, enabling the computing device to have better reconfiguration performance.

[0120] Any third high-speed signal connection structure J3 corresponding to any first mounting position A1 is electrically connected to other third high-speed signal connection structures J3 corresponding to other first mounting positions A1, and any two third high-speed signal connection structures J3 corresponding to any first mounting position A1 are electrically connected to other two different third high-speed signal connection structures J3 corresponding to other first mounting positions A1.

[0121] The third high-speed signal connection structure J3 can be plugged into any type of functional node 400 inserted in the corresponding first mounting position A1, and the third high-speed signal connection structure J3 can transmit data with the plugged-in functional node 400.

[0122] Each first mounting position A1 is in the same relative position as the corresponding third high-speed signal connection structure J3, so that the functional node 400 can be inserted into any first mounting position A1 and connected to the corresponding third high-speed signal connection structure J3.

[0123] For example, the third high-speed signal connection structure J3 can be a high-speed signal connector or a high-speed signal connection terminal block.

[0124] For example, any m third high-speed signal connection structures J3 corresponding to any first mounting position A1 are electrically connected to one third high-speed signal connection structure J3 corresponding to another first mounting position A1 via cables.

[0125] For example, the enclosure 100 may have four first mounting positions A1, namely, first mounting position one, first mounting position two, first mounting position three, and first mounting position four. Each first mounting position A1 corresponds to three third high-speed signal connection structures J3, namely, a first high-speed interconnect structure, a second high-speed interconnect structure, and a third high-speed interconnect structure. The first high-speed interconnect structure corresponding to first mounting position one is electrically connected to the first high-speed interconnect structure corresponding to first mounting position two; the second high-speed interconnect structure corresponding to first mounting position one is electrically connected to the first high-speed interconnect structure corresponding to first mounting position three; and the third high-speed interconnect structure corresponding to first mounting position one is electrically connected to the first high-speed interconnect structure corresponding to first mounting position four. The second high-speed interconnect structure corresponding to first mounting position two is electrically connected to the second high-speed interconnect structure corresponding to first mounting position three; the third high-speed interconnect structure corresponding to first mounting position two is electrically connected to the second high-speed interconnect structure corresponding to first mounting position four; and the third high-speed interconnect structure corresponding to first mounting position three is electrically connected to the third high-speed interconnect structure corresponding to first mounting position four.

[0126] like Figures 3-5 As shown, in some possible implementations, the backplane 200 further includes a first low-speed signal connection structure J6 and a second low-speed signal connection structure J7 corresponding to the first mounting position A1.

[0127] The first low-speed signal connection structure J6 is electrically connected to the computing node 300, and the second low-speed signal connection structure J7 is electrically connected to the first low-speed signal connection structure J6 to realize data transmission between the second low-speed signal connection structure J7 and the computing node 300.

[0128] The second low-speed signal connection structure J7 is used to connect with the functional node 400 inserted in the corresponding first mounting position A1 to realize data transmission between the second low-speed signal connection structure J7 and the inserted functional node 400, so that the computing node 300 and the functional node 400 can realize data transmission through the first low-speed signal connection structure J6 and the second low-speed signal connection structure J7.

[0129] In this way, the functional node 400 inserted in the first mounting position A1 can transmit data with the computing node 300 through the low-speed signal channel formed by the second low-speed signal connection structure J7 and the first low-speed signal connection structure J6, so as to realize the management of the functional node 400 and the connection of the functional node 400 to the local area network.

[0130] In some examples, compute node 300 can manage functional node 400 through a first low-speed signal connection structure J6 and a second low-speed signal connection structure J7.

[0131] In some examples, functional node 400 can access the local area network through a first low-speed signal connection structure J6, a second low-speed signal connection structure J7, and computing node 300.

[0132] The second low-speed signal connection structure J7 can be plugged into any type of functional node 400 inserted in the corresponding first mounting position A1, and the second low-speed signal connection structure J7 can transmit data with the plugged-in functional node 400.

[0133] Each first mounting position A1 is in the same relative position as the corresponding second low-speed signal connection structure J7, so that the functional node 400 can be inserted into any first mounting position A1 and connected to the corresponding second low-speed signal connection structure J7.

[0134] For example, each first mounting position A1 may correspond to one or more second low-speed signal connection structures J7. The functional node 400 inserted into the first mounting position A1 may be connected to one or more second low-speed signal connection structures J7.

[0135] For example, computing node 300 may be electrically connected to one or more first low-speed signal connection structures J6.

[0136] In some examples, the backplane 200 may include a first low-speed signal connection structure J6 corresponding to the second low-speed signal connection structure J7, wherein the second low-speed signal connection structure J7 is electrically connected to the corresponding first low-speed signal connection structure J6 to be electrically connected to the computing node 300 through the corresponding first low-speed signal connection structure J6.

[0137] In some examples, multiple second low-speed signal connection structures J7 can be electrically connected to the same first low-speed signal connection structure J6 to be electrically connected to the computing node 300 through the same first low-speed signal connection structure J6.

[0138] For example, the second low-speed signal connection structure J7 is electrically connected to the first low-speed signal connection structure J6 via a cable.

[0139] For example, the first low-speed signal connection structure J6 and the second low-speed signal connection structure J7 can be a low-speed signal connector or a low-speed signal connection terminal group.

[0140] Figure 6 This is a schematic diagram of another computing device provided in an embodiment of this application.

[0141] like Figure 6 As shown, in some possible implementations, the computing device includes a functional node 400, with at least one first mounting position A1 in which the functional node 400 is inserted.

[0142] This allows for a wider range of configurations for computing devices, enabling them to achieve higher performance.

[0143] When the enclosure 100 has multiple first mounting positions A1, the number and type of the inserted functional nodes 400 can be adjusted according to the configuration required by the computing device.

[0144] For example, the housing 100 has a plurality of first mounting positions A1, some of which have a functional node 400 inserted in them, and some of which are empty (without a functional node 400 inserted).

[0145] In some examples, the housing 100 has multiple first mounting positions A1, one of which is equipped with a functional node 400, while the other first mounting positions A1 are empty.

[0146] Figure 7 This is a schematic diagram of another computing device provided in an embodiment of this application.

[0147] like Figure 7 As shown, in some examples, the housing 100 has multiple first mounting positions A1, at least two of which are equipped with functional nodes 400, and some of the first mounting positions A1 are empty.

[0148] Figure 8 This is a schematic diagram of another computing device provided in an embodiment of this application.

[0149] like Figure 8 As shown, in some examples, a functional node 400 is inserted in each first mounting position A1.

[0150] For example, functional node 400 includes a housing, and a first mounting position A1 is used for housing insertion. Different types of functional nodes 400 have housings of the same size.

[0151] Figure 9 This is a schematic diagram of a functional node provided in an embodiment of this application.

[0152] like Figure 9 As shown, in some possible implementations, the functional node 400 further includes a fourth high-speed signal connection structure J4. The fourth high-speed signal connection structure J4 of the functional node 400 is connected to the second high-speed signal connection structure J2 corresponding to the first mounting position A1 of the functional node 400. The second high-speed signal connection structure J2 and the connected fourth high-speed signal connection structure J4 transmit data. The computing node 300 can realize data transmission through the first high-speed signal connection structure J1, the second high-speed signal connection structure J2 and the fourth high-speed signal connection structure J4.

[0153] This facilitates the electrical connection between functional node 400 and the second high-speed signal connection structure J2, thereby enabling the modification of the computing device by inserting functional node 400. Devices within functional node 400 can transmit data or disconnect from computing node 300 by switching on or off with the fourth high-speed signal connection structure J4.

[0154] For example, the fourth high-speed signal connection structure J4 is located at one end of the housing facing the back plate 200.

[0155] For example, the fourth high-speed signal connection structure J4 of different types of functional nodes 400 is in the same relative position as the housing.

[0156] For example, the number of fourth high-speed signal connection structures J4 of functional node 400 is the same as the number of second high-speed signal connection structures J2 corresponding to the first mounting position A1 inserted in functional node 400, and they correspond one-to-one. The fourth high-speed signal connection structure J4 is inserted into the corresponding second high-speed signal connection structure J2.

[0157] For example, the fourth high-speed signal connection structure J4 can be a high-speed signal connector or a high-speed signal connection terminal block.

[0158] like Figure 9 As shown, in some possible implementations, functional node 400 further includes m fifth high-speed signal connection structures J5. Any fifth high-speed signal connection structure J5 of functional node 400 is connected to a third high-speed signal connection structure J3 corresponding to the first mounting position A1 of functional node 400. The third high-speed signal connection structure J3 transmits data with the connected fifth high-speed signal connection structure J5, enabling data transmission between one fifth high-speed signal connection structure J5 of functional node 400 and another fifth high-speed signal connection structure J5 of another functional node 400 via the third high-speed signal connection structure J3.

[0159] This facilitates the electrical connection between functional node 400 and the m third high-speed signal connection structures J3 corresponding to the first mounting position A1 where functional node 400 is inserted, thereby enabling data transmission between functional nodes 400 inserted in different first mounting positions A1. Devices within functional node 400 can achieve data transmission or disconnection with other functional nodes 400 by connecting or disconnecting from each fifth high-speed signal connection structure J5.

[0160] Any two fifth high-speed signal connection structures J5 of functional node 400 are connected to two different third high-speed signal connection structures J3 corresponding to the first mounting position A1 inserted into functional node 400.

[0161] For example, the fifth high-speed signal connection structure J5 is located at one end of the housing facing the back plate 200.

[0162] For example, the fifth high-speed signal connection structure J5 of different types of functional nodes 400 is in the same relative position as the housing.

[0163] For example, the fifth high-speed signal connection structure J5 of the functional node 400 corresponds one-to-one with the third high-speed signal connection structure J3 corresponding to the first mounting position A1 of the functional node 400, and the fifth high-speed signal connection structure J5 is connected to the corresponding third high-speed signal connection structure J3.

[0164] For example, the fifth high-speed signal connection structure J5 can be a high-speed signal connector or a high-speed signal connection terminal block.

[0165] like Figure 9 As shown, in some possible implementations, functional node 400 further includes a third low-speed signal connection structure J8. The third low-speed signal connection structure J8 of functional node 400 is connected to the second low-speed signal connection structure J7 corresponding to the first mounting position A1 of functional node 400. The second low-speed signal connection structure J7 and the connected third low-speed signal connection structure J8 transmit data. Computation node 300 can achieve data transmission through the first low-speed signal connection structure J6, the second low-speed signal connection structure J7, and the third low-speed signal connection structure J8 on the backplane 200.

[0166] This facilitates the electrical connection between the functional node 400 and the second low-speed signal connection structure J7, thereby enabling the management of the functional node 400 and the connection of the functional node 400 to the local area network.

[0167] For example, the third low-speed signal connection structure J8 is located at one end of the housing facing the back plate 200.

[0168] For example, the third low-speed signal connection structure J8 of different types of functional nodes 400 is in the same relative position as the housing.

[0169] For example, the number of third low-speed signal connection structures J8 of functional node 400 is the same as the number of second low-speed signal connection structures J7 corresponding to the first mounting position A1 inserted in functional node 400, and they correspond one-to-one. The third low-speed signal connection structure J8 is inserted into the corresponding second low-speed signal connection structure J7.

[0170] For example, the third low-speed signal connection structure J8 can be a low-speed signal connector or a low-speed signal connection terminal group.

[0171] Figure 10 A topology diagram of a first computing acceleration node provided in an embodiment of this application.

[0172] like Figure 10 As shown, exemplarily, one type of functional node 400 is a first computing acceleration node 400a, meaning that each first mounting position A1 can accommodate a first computing acceleration node 400a. The first computing acceleration node 400a also includes a first computing acceleration card G1, which is electrically connected to a fourth high-speed signal connection structure J4 via a cable to enable data transmission between the first computing acceleration card G1 and the fourth high-speed signal connection structure J4. Data transmission between the first computing acceleration card G1 and the computing node 300 is achieved through the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2, and the first high-speed signal connection structure J1. When the computing device includes multiple first computing acceleration nodes 400a, the first computing acceleration cards G1 of different first computing acceleration nodes 400a achieve data transmission with the computing node 300 through the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2, the first high-speed signal connection structure J1, and the computing node 300.

[0173] In this way, the first computing acceleration card G1 can perform efficient data transmission with the computing node 300, providing computing acceleration functionality to the computing node 300. When the computing device includes multiple first computing acceleration nodes 400a, the first computing acceleration cards G1 of different first computing acceleration nodes 400a can transmit data, enabling the computing device to have better computing acceleration performance. The first computing acceleration card G1 is electrically connected to the fourth high-speed signal connection structure J4 via a cable, allowing for more flexible placement of the first computing acceleration card G1 and facilitating a reduction in the thickness of the first computing acceleration node 400a.

[0174] For example, the first computing accelerator card G1 can be a GPU accelerator card.

[0175] For example, the first computing acceleration card G1 is disposed within the housing of the first computing acceleration node 400a.

[0176] For example, the first computing acceleration node 400a includes a plurality of first computing acceleration cards G1, which are stacked along the thickness direction of the first computing acceleration node 400a.

[0177] For example, each fourth high-speed signal connection structure J4 can be electrically connected to one or more first computing accelerator cards G1, and the number of first computing accelerator cards G1 electrically connected to different fourth high-speed signal connection structures J4 can be the same or different.

[0178] For example, different first computing accelerator cards G1 can be electrically connected to the same or different fourth high-speed signal connection structures J4. For instance, multiple first computing accelerator cards G1 can be electrically connected to the same fourth high-speed signal connection structure J4.

[0179] In some examples, the number of first computing acceleration cards G1 and fourth high-speed signal connection structures J4 of the first computing acceleration node 400a are equal and correspond one-to-one, and the first computing acceleration card G1 is electrically connected to the corresponding fourth high-speed signal connection structure J4.

[0180] Figure 11 This is a topology diagram of a second computing acceleration node provided in an embodiment of this application.

[0181] like Figure 11 As shown, for example, one type of functional node 400 is a second computing acceleration node 400b, that is, each first mounting position A1 can be used to insert the second computing acceleration node 400b.

[0182] The second computing acceleration node 400b also includes a second computing acceleration card G2 and a first switching board B1. The second computing acceleration card G2 is electrically connected to the first switching board B1 via a cable, which allows for more flexible placement of the second computing acceleration card G2 and helps reduce the thickness of the second computing acceleration node 400b. When the second computing acceleration node 400b includes multiple second computing acceleration cards G2, the multiple second computing acceleration cards G2 can interact through the first switching board B1, which facilitates the efficient utilization of each second computing acceleration card G2.

[0183] In some examples where at least one functional node 400 is a second computing acceleration node 400b, the first switching board B1 is electrically connected to the fourth high-speed signal connection structure J4 to realize data transmission between the second computing acceleration card G2 and the fourth high-speed signal connection structure J4. The second computing acceleration card G2 and the computing node 300 realize data transmission through the first switching board B1, the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2 and the first high-speed signal connection structure J1.

[0184] In this way, the second computing accelerator card G2 can transmit data with the computing node 300 and provide computing acceleration functionality to the computing node 300. When the second computing accelerator node 400b includes multiple second computing accelerator cards G2, the computing node 300 can transmit data with each second computing accelerator card G2 through the switching of the first switching board B1, which is beneficial to make full use of each second computing accelerator card G2.

[0185] In some examples where at least one functional node 400 is a second computing acceleration node 400b, the first switching board B1 is electrically connected to the fifth high-speed signal J5 connection structure of the second computing acceleration node 400b to realize data transmission between the second computing acceleration card G2 and the fifth high-speed signal connection structure J5. When the computing device includes multiple functional nodes 400, the second computing acceleration card G2 of the second computing acceleration node 400b and other functional nodes 400 realize data transmission through the first switching board B1, the fifth high-speed signal connection structure J5, and the third high-speed signal connection structure J3.

[0186] In this way, the second computing accelerator card G2 can transmit data with other functional nodes 400 and provide computing acceleration functions to them. Through the switching of the first switching board B1, other functional nodes 400 can transmit data with each of the second computing accelerator cards G2, which is beneficial to make full use of each of the second computing accelerator cards G2.

[0187] For example, the first switching board B1 is electrically connected to the fourth high-speed signal connection structure J4 and the fifth high-speed signal connection structure J5 to realize data transmission between the second computing accelerator card G2 and the fourth high-speed signal connection structure J4 and the fifth high-speed signal connection structure J5. This allows the second computing accelerator card G2 to transmit data with the computing node 300 and other functional nodes 400 through the first switching board B1, providing computing acceleration functions for the computing node 300 and other functional nodes 400. Through the switching of the first switching board B1, the computing node 300 and other functional nodes 400 can transmit data with each of the second computing accelerator cards G2, resulting in high utilization efficiency of each of the second computing accelerator cards G2.

[0188] For example, the second computing accelerator card G2 can be a GPU accelerator card.

[0189] For example, the second computing accelerator card G2 is disposed within the housing of the second computing accelerator node 400b.

[0190] For example, the second computing acceleration node 400b includes a plurality of second computing acceleration cards G2, which are stacked along the thickness direction of the second computing acceleration node 400b.

[0191] For example, each fourth high-speed signal connection structure J4 of the second computing acceleration node 400b is electrically connected to all the second computing acceleration cards G2 of the second computing acceleration node 400b through the first switching board B1 of the second computing acceleration node 400b, enabling each fourth high-speed signal connection structure J4 of the second computing acceleration node 400b to perform data transmission with all the second computing acceleration cards G2 of the second computing acceleration node 400b. Each fifth high-speed signal connection structure J5 of the second computing acceleration node 400b is electrically connected to all the second computing acceleration cards G2 of the second computing acceleration node 400b through the first switching board B1 of the second computing acceleration node 400b, enabling each fifth high-speed signal connection structure J5 of the second computing acceleration node 400b to perform data transmission with all the second computing acceleration cards G2 of the second computing acceleration node 400b.

[0192] Figure 12 This is a topology diagram of a first storage node provided in an embodiment of this application.

[0193] like Figure 12 As shown, exemplarily, one type of functional node 400 is a first storage node 400c, meaning that each first mounting position A1 can be used to insert the first storage node 400c. The first storage node 400c also includes a first memory S1, which is electrically connected to a fourth high-speed signal connection structure J4 via a cable to realize data transmission between the first memory S1 and the fourth high-speed signal connection structure J4. Data transmission between the first memory S1 and the computing node 300 is achieved through the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2, and the first high-speed signal connection structure J1.

[0194] In this way, the first memory S1 can transmit data with the computing node 300 and provide storage functionality for the computing node 300. The first memory S1 is electrically connected to the fourth high-speed signal connection structure J4 via a cable, which allows for more flexible arrangement of the first memory S1 and helps to reduce the thickness of the first storage node 400c.

[0195] For example, the first memory S1 can be a hard disk.

[0196] For example, the first memory S1 is disposed within the housing of the first storage node 400c.

[0197] For example, the first storage node 400c includes a plurality of first memories S1, which are stacked along the thickness direction of the first storage node 400c.

[0198] For example, each fourth high-speed signal connection structure J4 can be electrically connected to one or more first memories S1, and the number of first memories S1 electrically connected to different fourth high-speed signal connection structures J4 can be the same or different.

[0199] For example, different first memories S1 can be electrically connected to the same or different fourth high-speed signal connection structures J4. For instance, multiple first memories S1 can be electrically connected to the same fourth high-speed signal connection structure J4.

[0200] In some examples, each fourth high-speed signal connection structure J4 of the first storage node 400c corresponds to one or more first memories S1, and the fourth high-speed signal connection structure J4 is electrically connected to the corresponding first memory S1. Different fourth high-speed signal connection structures J4 are connected to different first memories S1. For example, each fourth high-speed signal connection structure J4 of the first storage node 400c corresponds to one first memory S1, and the number of fourth high-speed signal connection structures J4 of the first storage node 400c is equal to the number of first memories S1.

[0201] Figure 13 This is a topology diagram of a second storage node provided in an embodiment of this application.

[0202] like Figure 13 As shown, for example, one type of functional node 400 is a second storage node 400d, that is, each first mounting bit A1 can be used to insert the second storage node 400d.

[0203] The second storage node 400d also includes a second memory S2 and a second switching board B2. The second memory S2 is electrically connected to the second switching board B2 via a cable. This connection allows for more flexible arrangement of the second memory S2, which helps reduce the thickness of the second storage node 400d. When the second storage node 400d includes multiple second memories S2, these memories can interact through the second switching board B2, facilitating efficient utilization of each memory S2.

[0204] In some examples where at least one functional node 400 is the second storage node 400d, the second switching board B2 is electrically connected to the fourth high-speed signal connection structure J4 to realize data transmission between the second memory S2 and the fourth high-speed signal connection structure J4. Data transmission between the second memory S2 and the computing node 300 is achieved through the second switching board B2, the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2 and the first high-speed signal connection structure J1.

[0205] In this way, the second memory S2 can transmit data with the computing node 300, providing storage functionality for the computing node 300. When the second storage node 400d includes multiple second memories S2, the computing node 300 can transmit data with each of the second memories S2 through the switching on the second switching board B2, which facilitates full utilization of each second memory S2.

[0206] In some examples where at least one functional node 400 is a second storage node 400d, the second switching board B2 is electrically connected to the fifth high-speed signal connection structure J5 of the second storage node 400d to enable data transmission between the second memory S2 and the fifth high-speed signal connection structure J5. When the computing device includes multiple functional nodes 400, the second memory S2 of the second storage node 400d transmits data to other functional nodes 400 through the second switching board B2, the fifth high-speed signal connection structure J5, and the third high-speed signal connection structure J3.

[0207] In this way, the second memory S2 can transmit data with other functional nodes 400 and provide storage functions for them. Through the switching on the second switching board B2, other functional nodes 400 can transmit data with each of the second memories S2, which is beneficial for making full use of each of the second memories S2.

[0208] For example, the second switching board B2 is electrically connected to the fourth high-speed signal connection structure J4 and the fifth high-speed signal connection structure J5 to realize data transmission between the second memory S2 and the fourth high-speed signal connection structure J4 and the fifth high-speed signal connection structure J5. This allows the second memory S2 to transmit data with the computing node 300 and other functional nodes 400 through the second switching board B2, providing storage functionality for the computing node 300 and other functional nodes 400. Through the switching of the second switching board B2, the computing node 300 and other functional nodes 400 can transmit data with each of the second memories S2, resulting in high utilization efficiency of each second memory S2.

[0209] For example, the second memory S2 can be a hard disk.

[0210] For example, the second memory S2 is disposed within the housing of the second memory node 400d.

[0211] For example, the second storage node 400d includes a plurality of second memories S2, which are stacked along the thickness direction of the second storage node 400d.

[0212] For example, each fourth high-speed signal connection structure J4 of the second storage node 400d is electrically connected to all the second memories S2 of the second storage node 400d through the second switching board B2 of the second storage node 400d, enabling each fourth high-speed signal connection structure J4 of the second storage node 400d to transmit data with all the second memories S2 of the second storage node 400d. Each fifth high-speed signal connection structure J5 of the second storage node 400d is connected to all the second memories S2 of the second storage node 400d through the second switching board B2 of the second storage node 400d, enabling each fifth high-speed signal connection structure J5 of the second storage node 400d to transmit data with all the second memories S2 of the second storage node 400d.

[0213] Figure 14 This is a topology diagram of a third storage node provided in an embodiment of this application.

[0214] like Figure 14 As shown, one type of functional node 400 is a third storage node 400e, meaning that each first mounting position A1 can accommodate a third storage node 400e. The third storage node 400e also includes a third memory S3 and a fourth memory S4 corresponding to the fifth high-speed signal connection structure J5 of the third storage node 400e. The third memory S3 is electrically connected to the fourth high-speed signal connection structure J4 via a cable to achieve data transmission between the third memory S3 and the fourth high-speed signal connection structure J4. Data transmission between the third memory S3 and the computing node 300 is achieved through the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2, and the first high-speed signal connection structure J1. The fourth memory S4 is electrically connected to the corresponding fifth high-speed signal connection structure J5 via a cable to achieve data transmission between the fourth memory S4 and the corresponding fifth high-speed signal connection structure J5. When the computing device includes multiple functional nodes 400, the fourth memory S4 of the third storage node 400e and other functional nodes 400 achieve data transmission through the fifth high-speed signal connection structure J5 and the third high-speed signal connection structure J3.

[0215] In this way, the third memory S3 can transmit data with the computing node 300 and provide storage functionality for the computing node 300. The fourth memory S4 can transmit data with other functional nodes 400 and provide storage functionality for them. The third memory S3 is electrically connected to the fourth high-speed signal connection structure J4 via a cable, and the fourth memory S4 is electrically connected to the corresponding fifth high-speed signal connection structure J5 via a cable. This allows for flexible arrangement of the third memory S3 and the fourth memory S4, which helps to reduce the thickness of the third storage node 400e.

[0216] For example, the third memory S3 and the fourth memory S4 can be hard disks.

[0217] For example, the third memory S3 and the fourth memory S4 are located within the housing of the third storage node 400e.

[0218] For example, the third memory S3 and the fourth memory S4 can be stacked along the thickness direction of the third memory node 400e.

[0219] For example, the third storage node 400e may include one or more third memories S3 and one or more fourth memories S4.

[0220] For example, each fourth high-speed signal connection structure J4 can be electrically connected to one or more third memories S3, and the number of third memories S3 electrically connected to different fourth high-speed signal connection structures J4 can be the same or different.

[0221] For example, different third memories S3 can be electrically connected to the same or different fourth high-speed signal connection structures J4. For instance, multiple third memories S3 can be electrically connected to the same fourth high-speed signal connection structure J4.

[0222] In some examples, each fourth high-speed signal connection structure J4 of the third storage node 400e corresponds to one or more third memories S3, and the fourth high-speed signal connection structure J4 is electrically connected to the corresponding third memory S3. Different fourth high-speed signal connection structures J4 are connected to different third memories S3. For example, each fourth high-speed signal connection structure J4 of the third storage node 400e corresponds to one third memory S3, and the number of fourth high-speed signal connection structures J4 of the third storage node 400e is equal to the number of third memories S3.

[0223] For example, each fifth high-speed signal connection structure J5 can be electrically connected to one or more fourth memories S4, and the number of fourth memories S4 electrically connected to different fifth high-speed signal connection structures J5 can be the same or different.

[0224] In some examples, each fifth high-speed signal connection structure J5 of the third storage node 400e corresponds to one or more fourth memories S4. The fifth high-speed signal connection structure J5 is electrically connected to the corresponding fourth memory S4, and different fifth high-speed signal connection structures J5 are connected to different fourth memories S4. For example, each fifth high-speed signal connection structure J5 of the third storage node 400e corresponds to one fourth memory S4, and the number of fifth high-speed signal connection structures J5 of the third storage node 400e is equal to the number of fourth memories S4.

[0225] Figure 15This is a memory node topology diagram provided in an embodiment of this application.

[0226] like Figure 15 As shown, one type of functional node 400 is a memory node 400f, meaning that each first mounting position A1 can accommodate a memory node 400f. The memory node 400f also includes a first memory M1, which is electrically connected to a fourth high-speed signal connection structure J4 via a cable to enable data transmission between the first memory M1 and the fourth high-speed signal connection structure J4. Data transmission between the first memory M1 and the computing node 300 is achieved through the fourth high-speed signal connection structure J4, the second high-speed signal connection structure J2, and the first high-speed signal connection structure J1.

[0227] In this way, the first memory M1 can transmit data with the computing node 300 and provide memory functionality to the computing node 300. The first memory M1 is electrically connected to the fourth high-speed signal connection structure J4 via a cable, which allows for more flexible placement of the first memory M1 and helps to reduce the thickness of the memory node 400f.

[0228] For example, the first memory M1 is located inside the housing of memory node 400f.

[0229] For example, memory node 400f includes a plurality of first memory modules M1, which are stacked along the thickness direction of memory node 400f.

[0230] For example, each fourth high-speed signal connection structure J4 can be electrically connected to one or more first memory M1s, and the number of first memory M1s electrically connected to different fourth high-speed signal connection structures J4 can be the same or different.

[0231] For example, different first memory modules M1 can be electrically connected to the same or different fourth high-speed signal connection structures J4. For instance, multiple first memory modules M1 can be electrically connected to the same fourth high-speed signal connection structure J4.

[0232] In some examples, each fourth high-speed signal connection structure J4 of memory node 400f corresponds to one or more first memory modules M1, and the fourth high-speed signal connection structure J4 is electrically connected to the corresponding first memory module M1. Different fourth high-speed signal connection structures J4 are connected to different first memory modules M1. For example, each fourth high-speed signal connection structure J4 of memory node 400f corresponds to one first memory module M1, and the number of fourth high-speed signal connection structures J4 of memory node 400f is equal to the number of first memory modules M1.

[0233] Figure 16 This is a topology diagram of an extended computing node provided in an embodiment of this application.

[0234] like Figure 16 As shown, one type of functional node 400 is an extended compute node 400g, meaning that each first mounting position A1 can accommodate an extended compute node 400g. The extended compute node 400g also includes a first central processing unit C1 and a first motherboard B3. The first central processing unit C1 is located on and electrically connected to the first motherboard B3. By installing the extended compute node 400g, it is convenient to build a hyperconverged architecture, and the cost of building a hyperconverged architecture is relatively low.

[0235] In some examples where at least one functional node 400 is an extended computing node 400g, the first motherboard B3 is electrically connected to the third low-speed signal connection structure J8 of the extended computing node 400g to enable data transmission between the first central processing unit C1 and the third low-speed signal connection structure J8. Data transmission between the first central processing unit C1 of the extended computing node 400g and the computing node 300 is achieved through the first motherboard B3, the third low-speed signal connection structure J8, the second low-speed signal connection structure J7 of the backplane 200, and the first low-speed signal connection structure J6 of the backplane 200.

[0236] In this way, the first central processing unit C1 can transmit data with the computing node 300 through the third low-speed signal connection structure J8, so as to access the local area network through the computing node 300.

[0237] In some examples where at least one functional node 400 is an extended computing node 400g, the first motherboard B3 is electrically connected to the fifth high-speed signal connection structure J5 of the extended computing node 400g to enable data transmission between the first central processing unit C1 and the fifth high-speed signal connection structure J5. When the computing device includes multiple functional nodes 400, the first central processing unit C1 of the extended computing node 400g and other functional nodes 400 achieve data transmission through the first motherboard B3, the fifth high-speed signal connection structure J5, and the third high-speed signal connection structure J3.

[0238] In this way, the first central processing unit C1 can transmit data with other functional nodes 400 through the fifth high-speed signal connection structure J5. The first central processing unit C1 can call the configuration of other functional nodes 400, which is convenient for building a hyper-converged architecture with other functional nodes 400, enabling the computing device to have high performance and more efficient use of configuration.

[0239] For example, the extended compute node 400g can be used for general computing.

[0240] For example, the first central processing unit C1 is housed within the casing of the extended computing node 400g.

[0241] In some examples, the extended computing node 400g also includes a second signal enhancement board B4, which is disposed within the housing of the extended computing node 400g. The first motherboard B3 is electrically connected to the second signal enhancement board B4. The second signal enhancement board B4 is electrically connected to the third low-speed signal connection structure J8 of the extended computing node 400g. The first motherboard B3 is electrically connected to the third low-speed signal connection structure J8 via the second signal enhancement board B4, enabling the first central processing unit C1 and the computing node 300 to transmit data through the first motherboard B3, the second signal enhancement board B4, the third low-speed signal connection structure J8, the second low-speed signal connection structure J7, and the first low-speed signal connection structure J6. The second signal enhancement board B4 is electrically connected to the fifth high-speed signal connection structure J5 of the extended computing node 400g. The first motherboard B3 is electrically connected to the fifth high-speed signal connection structure J5 via the second signal enhancement board B4, enabling the first central processing unit C1 and other functional nodes 400 to transmit data through the first motherboard B3, the second signal enhancement board B4, the fifth high-speed signal connection structure J5, and the third high-speed signal connection structure J3.

[0242] In some examples, the fourth high-speed signal connection structure J4 of the extended compute node 400g can be disconnected from the first central processing unit C1.

[0243] In some examples, the extended compute node 400g may also include a second memory disposed within the housing of the extended compute node 400g. The second memory is electrically connected to the first central processing unit C1 and provides memory functionality to the first central processing unit C1. For example, the second memory may be electrically connected to the first central processing unit C1 via a first motherboard B3.

[0244] In some examples, the extended compute node 400g may also include a fifth memory disposed within the housing of the extended compute node 400g, electrically connected to the first central processing unit C1, and capable of providing storage functionality for the first central processing unit C1. For example, the fifth memory may be electrically connected to the first central processing unit C1 via a first motherboard B3.

[0245] In some examples, the extended computing node 400g may also include a first baseboard management controller, which is electrically connected to a first motherboard B3. The first baseboard management controller can transmit data with a first central processing unit C1 through the first motherboard B3, and can manage the extended computing node 400g. The first baseboard management controller is electrically connected to a third low-speed signal connection structure J8 of the extended computing node 400g through the first motherboard B3.

[0246] Figure 17 This is a topology diagram of a computing device provided in an embodiment of this application.

[0247] like Figure 17 As shown, in some examples, computing node 300 includes a first signal enhancement board B6, a second main board B5, and a processing module. The processing module is located on and electrically connected to the second main board B5. The second main board B5 is electrically connected to the first signal enhancement board B6, and a first high-speed signal connection structure J1 is electrically connected to the first signal enhancement board B6, enabling data transmission between the processing module and functional node 400 through the second main board B5, the first signal enhancement board B6, the first high-speed signal connection structure J1, and the second high-speed signal connection structure J2.

[0248] In this way, by enhancing the signal through the first signal enhancement board B6, the processing module and the functional node 400 can have better data transmission performance, which is conducive to the efficient calling of the configuration of the functional node 400 by the processing module.

[0249] For example, the processing modules include a second central processing unit C2 and a third central processing unit C3, which are located on and electrically connected to the second motherboard B5. The second central processing unit C2 and the third central processing unit C3 are electrically connected through the second motherboard B5 to realize data transmission.

[0250] For example, the computing node 300 may further include a second baseboard management controller, which is electrically connected to the first signal enhancement board B6 and the first low-speed signal connection structure J6 is electrically connected to the first signal enhancement board B6, so that the second baseboard management controller and the functional node 400 can transmit data through the first signal enhancement board B6, the first low-speed signal connection structure J6 and the second low-speed signal connection structure J7, and the second baseboard management controller can manage the functional node 400.

[0251] For example, the computing node 300 may further include a local area network (LAN) switch board for connecting the computing device to the LAN. The LAN switch board is electrically connected to a first low-speed signal connection structure J6, enabling data transmission between the LAN switch board and the functional node 400 via the first low-speed signal connection structure J6 and the second low-speed signal connection structure J7, thereby facilitating the connection of the functional node 400 to the LAN.

[0252] For example, the computing node 300 may also include a third memory, which is located on and electrically connected to the second motherboard B5. The third memory is electrically connected to the processing module through the second motherboard B5 and can provide memory functionality for the processing module.

[0253] For example, the computing node 300 may also include a sixth memory electrically connected to the second motherboard B5 to be electrically connected to the processing module via the second motherboard B5, the sixth memory being able to provide storage functionality for the processing module.

[0254] Figure 18 This is a topology diagram of another computing device provided in an embodiment of this application.

[0255] like Figure 18 As shown, in some possible implementations, at least one functional node 400 of the computing device is a first computing acceleration node 400a, that is, at least one first mounting position A1 is provided with a first computing acceleration node 400a, which can provide computing acceleration function for computing node 300.

[0256] In some examples where the housing 100 has multiple first mounting positions A1, all the first mounting positions A1 can be used to insert a first computing acceleration node 400a.

[0257] For example, different first computing acceleration nodes 400a can transmit data through computing node 300.

[0258] Figure 19 This is a topology diagram of another computing device provided in an embodiment of this application.

[0259] like Figure 19 As shown, in some possible implementations, at least one functional node 400 of the computing device is a second computing acceleration node 400b, that is, at least one first mounting position A1 is provided with a second computing acceleration node 400b, which can provide computing acceleration functions for computing node 300 and other functional nodes 400.

[0260] In some examples where the housing 100 has multiple first mounting positions A1, all of the first mounting positions A1 can be used to insert a second computing acceleration node 400b.

[0261] In an example where multiple second computing acceleration nodes 400b are inserted inside the housing 100, different second computing acceleration nodes 400b can transmit data through an interconnecting third high-speed signal connection structure J3.

[0262] Figure 20 This is a topology diagram of another computing device provided in an embodiment of this application.

[0263] like Figure 20As shown, in some possible implementations, at least one functional node 400 of the computing device is a first computing acceleration node 400a, and at least one functional node 400 is a second computing acceleration node 400b. That is, at least one first mounting position A1 is in which a first computing acceleration node 400a is inserted, and at least one first mounting position A1 is in which a second computing acceleration node 400b is inserted. For example, the housing 100 has four first mounting positions A1, of which two first mounting positions A1 are in which first computing acceleration nodes 400a are inserted, and two first mounting positions A1 are in which second computing acceleration nodes 400b are inserted.

[0264] Figure 21 This is a topology diagram of another computing device provided in an embodiment of this application.

[0265] like Figure 21 As shown, in some possible implementations, at least one functional node 400 of the computing device is an extended computing node 400g, that is, an extended computing node 400g is inserted in at least one first mounting position A1, and the extended computing node 400g and the computing node 300 can call the configuration of other inserted functional nodes 400.

[0266] For example, some functional nodes 400 of the computing device are extended computing nodes 400g, and some functional nodes 400 are not extended computing nodes 400g.

[0267] For example, some functional nodes 400 of the computing device are extended computing nodes 400g, and some functional nodes 400 are second computing acceleration nodes 400b. That is, some first mounting positions A1 are fitted with extended computing nodes 400g, and some first mounting positions A1 are fitted with second computing acceleration nodes 400b. The second computing acceleration nodes 400b can provide computing acceleration functions for computing nodes 300 and extended computing nodes 400g. For example, the housing 100 has four first mounting positions A1, of which two first mounting positions A1 are fitted with extended computing nodes 400g, and two first mounting positions A1 are fitted with second computing acceleration nodes 400b.

[0268] For example, the third low-speed signal connection structure J8 of the extended computing node 400g can be electrically connected to the local area network switch board through the plug-in first low-speed signal connection structure J6, so as to connect the extended computing node 400g to the local area network.

[0269] Figure 22 This is a topology diagram of another computing device provided in an embodiment of this application.

[0270] like Figure 22As shown, in some possible implementations, at least one functional node 400 of the computing device is a memory node 400f, that is, at least one first mounting position A1 is provided with a memory node 400f, which can provide memory functionality for the computing node 300.

[0271] In some examples where the housing 100 has multiple first mounting positions A1, all the first mounting positions A1 can be used to insert a first computing acceleration node 400a.

[0272] like Figure 22 As shown, in some examples where the enclosure 100 has multiple first mounting positions A1, some functional nodes 400 of the computing device are memory nodes 400f and some functional nodes 400 are not memory nodes 400f.

[0273] For example, some functional nodes 400 of the computing device are memory nodes 400f and some functional nodes 400 are second computing acceleration nodes 400b. For instance, the housing 100 has four first mounting positions A1, one of which houses a memory node 400f and the other three of which house second computing acceleration nodes 400b.

[0274] Figure 23 This is a topology diagram of another computing device provided in an embodiment of this application.

[0275] like Figure 23 As shown, in some possible implementations, at least one functional node 400 of the computing device is a first storage node 400c, that is, at least one first mounting position A1 is provided with a first storage node 400c.

[0276] In some examples where the enclosure 100 has multiple first mounting positions A1, all of the first mounting positions A1 can be used to insert a first storage node 400c.

[0277] like Figure 23 As shown, in some examples where the enclosure 100 has multiple first mounting positions A1, some functional nodes 400 of the computing device are first storage nodes 400c, and some functional nodes 400 are not first storage nodes 400c.

[0278] For example, some functional nodes 400 of the computing device are first storage nodes 400c and some functional nodes 400 are second computing acceleration nodes 400b. For instance, the enclosure 100 has four first mounting positions A1, one of which houses the first storage node 400c and the other three of which house the second computing acceleration nodes 400b.

[0279] Figure 24This is a topology diagram of another computing device provided in an embodiment of this application.

[0280] like Figure 24 As shown, in some possible implementations, at least one functional node 400 of the computing device is a second storage node 400d, that is, at least one first mounting position A1 is provided with a second storage node 400d.

[0281] In some examples where the enclosure 100 has multiple first mounting positions A1, some functional nodes 400 of the computing device are second storage nodes 400d, and some functional nodes 400 are not second storage nodes 400d.

[0282] For example, some functional nodes 400 of the computing device are second storage nodes 400d and some functional nodes 400 are second computing acceleration nodes 400b. For instance, the enclosure 100 has four first mounting positions A1, one of which houses the second storage node 400d and the other three of which house the second computing acceleration nodes 400b.

[0283] Figure 25 This is a topology diagram of another computing device provided in an embodiment of this application.

[0284] like Figure 25 As shown, in some possible implementations, at least one functional node 400 of the computing device is a third storage node 400e, that is, at least one first mounting position A1 is provided with a third storage node 400e.

[0285] In some examples where the enclosure 100 has multiple first mounting positions A1, some functional nodes 400 of the computing device are third storage nodes 400e, and some functional nodes 400 are not third storage nodes 400e.

[0286] For example, some functional nodes 400 of the computing device are third storage nodes 400e and some functional nodes 400 are second computing acceleration nodes 400b. For instance, the enclosure 100 has four first mounting positions A1, one of which houses the third storage node 400e and the other three of which house the second computing acceleration nodes 400b.

[0287] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0288] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0289] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although the embodiments of this application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A computing device, characterized in that, It includes a housing (100), a back panel (200), and computing nodes (300); The housing (100) includes at least one first mounting position (A1), each first mounting position (A1) is used for inserting a functional node (400), and each first mounting position (A1) is capable of inserting different types of the functional node (400). The back panel (200) is fixedly connected to the housing (100), and the first mounting position (A1) is opposite to the back panel (200); The backplate (200) includes a first high-speed signal connection structure (J1) and a second high-speed signal connection structure (J2) corresponding to the first mounting position (A1). The first high-speed signal connection structure (J1) is electrically connected to the computing node (300), and the second high-speed signal connection structure (J2) is electrically connected to the first high-speed signal connection structure (J1). The second high-speed signal connection structure (J2) is used to connect to the functional node (400) inserted in the corresponding first mounting position (A1), so that the computing node (300) and the functional node (400) can realize data transmission through the first high-speed signal connection structure (J1) and the second high-speed signal connection structure (J2).

2. The computing device according to claim 1, characterized in that, The housing (100) includes at least two of the first mounting positions (A1); The backplate (200) also includes a third high-speed signal connection structure (J3) corresponding to the first mounting position (A1), and each first mounting position (A1) corresponds to m third high-speed signal connection structures (J3), where m = n - 1, and n is the number of first mounting positions (A1); Each of the first mounting positions (A1) corresponds to any one of the third high-speed signal connection structures (J3) and is electrically connected to another third high-speed signal connection structure (J3) corresponding to another first mounting position (A1), so that m third high-speed signal connection structures (J3) corresponding to any one first mounting position (A1) are electrically connected to another third high-speed signal connection structure (J3) corresponding to another first mounting position (A1). The third high-speed signal connection structure (J3) is used to connect to the functional node (400) inserted in the corresponding first mounting position (A1), so that the functional nodes (400) inserted in any two different first mounting positions (A1) can realize data transmission through the third high-speed signal connection structure (J3).

3. The computing device according to claim 1 or 2, characterized in that, The backplate (200) also includes a first low-speed signal connection structure (J6) and a second low-speed signal connection structure (J7) corresponding to the first mounting position (A1). The first low-speed signal connection structure (J6) is electrically connected to the computing node (300), and the second low-speed signal connection structure (J7) is electrically connected to the first low-speed signal connection structure (J6). The second low-speed signal connection structure (J7) is used to connect to the functional node (400) inserted in the corresponding first mounting position (A1), so that the computing node (300) and the functional node (400) can realize data transmission through the first low-speed signal connection structure (J6) and the second low-speed signal connection structure (J7).

4. The computing device according to any one of claims 1-3, characterized in that, It also includes the aforementioned functional node (400); The functional node (400) is inserted in at least one of the first mounting positions (A1). The functional node (400) includes a fourth high-speed signal connection structure (J4). The fourth high-speed signal connection structure (J4) of the functional node (400) is connected to the second high-speed signal connection structure (J2) corresponding to the first mounting position (A1) of the functional node (400). The computing node (300) can realize data transmission with the fourth high-speed signal connection structure (J4) through the first high-speed signal connection structure (J1) and the second high-speed signal connection structure (J2).

5. The computing device according to claim 4, characterized in that, The functional node (400) also includes m fifth high-speed signal connection structures (J5); Any of the fifth high-speed signal connection structures (J5) of the functional node (400) is connected to a third high-speed signal connection structure (J3) corresponding to the first mounting position (A1) of the functional node (400), so that one of the fifth high-speed signal connection structures (J5) of the functional node (400) and another fifth high-speed signal connection structure (J5) of the functional node (400) can realize data transmission through the third high-speed signal connection structure (J3).

6. The computing device according to claim 4 or 5, characterized in that, The functional node (400) also includes a third low-speed signal connection structure (J8); The third low-speed signal connection structure (J8) of the functional node (400) is connected to the second low-speed signal connection structure (J7) corresponding to the first mounting position (A1) of the functional node (400). The computing node (300) can realize data transmission through the first low-speed signal connection structure (J6) and the second low-speed signal connection structure (J7) of the backplane (200) and the third low-speed signal connection structure (J8).

7. The computing device according to any one of claims 4-6, characterized in that, At least one of the functional nodes (400) is a first computing acceleration node (400a). The first computing acceleration node (400a) further includes a first computing acceleration card (G1). The first computing acceleration card (G1) is electrically connected to the fourth high-speed signal connection structure (J4) via a cable. The first computing acceleration card (G1) and the computing node (300) realize data transmission through the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2), and the first high-speed signal connection structure (J1). When the computing device includes multiple first computing acceleration nodes (400a), the first computing acceleration cards (G1) of different first computing acceleration nodes (400a) realize data transmission through the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2), the first high-speed signal connection structure (J1) and the computing node (300).

8. The computing device according to any one of claims 4-7, characterized in that, At least one of the functional nodes (400) is a second computing acceleration node (400b), and the second computing acceleration node (400b) further includes a second computing acceleration card (G2) and a first switching board (B1). The second computing acceleration card (G2) is electrically connected to the first switching board (B1) via a cable. The first switching board (B1) is electrically connected to the fourth high-speed signal connection structure (J4), and the second computing accelerator card (G2) and the computing node (300) realize data transmission through the first switching board (B1), the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2) and the first high-speed signal connection structure (J1); and / or, the first switching board (B1) is electrically connected to the fifth high-speed signal connection structure (J5) of the second computing accelerator node (400b). When the computing device includes multiple functional nodes (400), the second computing accelerator card (G2) of the second computing accelerator node (400b) and other functional nodes (400) realize data transmission through the first switching board (B1), the fifth high-speed signal connection structure (J5) and the third high-speed signal connection structure (J3).

9. The computing device according to any one of claims 4-8, characterized in that, At least one of the functional nodes (400) is a first storage node (400c), and the first storage node (400c) further includes a first memory (S1). The first memory (S1) is electrically connected to the fourth high-speed signal connection structure (J4) via a cable. The first memory (S1) and the computing node (300) realize data transmission through the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2) and the first high-speed signal connection structure (J1).

10. The computing device according to any one of claims 4-9, characterized in that, At least one of the functional nodes (400) is a second storage node (400d), and the second storage node (400d) further includes a second memory (S2) and a second switching board (B2), wherein the second memory (S2) is electrically connected to the second switching board (B2) via a cable; The second switching board (B2) is electrically connected to the fourth high-speed signal connection structure (J4), and the second memory (S2) and the computing node (300) realize data transmission through the second switching board (B2), the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2) and the first high-speed signal connection structure (J1); and / or, the second switching board (B2) is electrically connected to the fifth high-speed signal connection structure (J5) of the second storage node (400d). When the computing device includes multiple functional nodes (400), the second memory (S2) of the second storage node (400d) and other functional nodes (400) realize data transmission through the second switching board (B2), the fifth high-speed signal connection structure (J5) and the third high-speed signal connection structure (J3).

11. The computing device according to any one of claims 4-10, characterized in that, At least one of the functional nodes (400) is a third storage node (400e), and the third storage node (400e) further includes a third memory (S3) and a fourth memory (S4) corresponding to the fifth high-speed signal connection structure (J5) of the third storage node (400e). The third memory (S3) is electrically connected to the fourth high-speed signal connection structure (J4) via a cable. The third memory (S3) and the computing node (300) realize data transmission through the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2) and the first high-speed signal connection structure (J1). The fourth memory (S4) is electrically connected to the corresponding fifth high-speed signal connection structure (J5) via a cable. When the computing device includes multiple functional nodes (400), the fourth memory (S4) of the third storage node (400e) and other functional nodes (400) realize data transmission through the fifth high-speed signal connection structure (J5) and the third high-speed signal connection structure (J3).

12. The computing device according to any one of claims 4-11, characterized in that, At least one of the functional nodes (400) is a memory node (400f), and the memory node (400f) further includes a first memory (M1). The first memory (M1) is electrically connected to the fourth high-speed signal connection structure (J4) via a cable. The first memory (M1) and the computing node (300) realize data transmission through the fourth high-speed signal connection structure (J4), the second high-speed signal connection structure (J2) and the first high-speed signal connection structure (J1).

13. The computing device according to any one of claims 5-12, characterized in that, At least one of the functional nodes (400) is an extended computing node (400g), and the extended computing node (400g) further includes a first central processing unit (C1) and a first motherboard (B3), wherein the first central processing unit (C1) is disposed on the first motherboard (B3) and electrically connected to the first motherboard (B3); The first motherboard (B3) is electrically connected to the third low-speed signal connection structure (J8) of the extended computing node (400g). The first central processing unit (C1) of the extended computing node (400g) and the computing node (300) achieve data transmission through the first motherboard (B3), the third low-speed signal connection structure (J8), the second low-speed signal connection structure (J7) of the backplane (200), and the first low-speed signal connection structure (J6) of the backplane (200). And / or, the first motherboard (B3) is electrically connected to the fifth high-speed signal connection structure (J5) of the extended computing node (400g). When the computing device includes multiple functional nodes (400), the first central processing unit (C1) of the extended computing node (400g) and other functional nodes (400) achieve data transmission through the first motherboard (B3), the fifth high-speed signal connection structure (J5), and the third high-speed signal connection structure (J3).

14. The computing device according to any one of claims 1-13, characterized in that, The computing node (300) includes a first signal enhancement board (B6), a second motherboard (B5), and a processing module; The processing module is located on the second motherboard (B5) and electrically connected to the second motherboard (B5). The second motherboard (B5) is electrically connected to the first signal enhancement board (B6). The first high-speed signal connection structure (J1) is electrically connected to the first signal enhancement board (B6), so that the processing module and the functional node (400) can realize data transmission through the second motherboard (B5), the first signal enhancement board (B6), the first high-speed signal connection structure (J1) and the second high-speed signal connection structure (J2).

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