Apparatus and method for frequency-aware intelligent power management

Abstract

The present disclosure relates to apparatuses and methods for frequency-aware intelligent power management. For example, an example processor includes a plurality of cores; a power management circuit to control power consumption of the plurality of cores according to a first power control mode or a second power control mode, the power management circuit to enter the second power control mode when a frequency of a core of the plurality of cores has fallen below a specified minimum frequency; the power management circuit to control power consumption of the core by adjusting a voltage and frequency of the core in the first power control mode; and the power management circuit to control power consumption of the core in the second power control mode by reducing a dynamic capacitance (C dyn ) associated with the core when the frequency of the core is below the specified minimum frequency.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of computer processors. More specifically, the embodiments relate to apparatus and methods for frequency-aware intelligent power management. Background Technology

[0002] As the number of cores in each new generation of processors continues to increase, the Thermal Design Power (TDP) specification remains relatively stable or even decreases to achieve lower operating costs, longer battery life, and / or meet platform power requirements. In some cases, the processor's base frequency (the "guaranteed" frequency at P1 performance) can be reduced to meet specific TDP specifications. This may result in a lower P1 frequency than its predecessor, reducing SKU market competitiveness or leading to SKU cancellation. Furthermore, as P1 requirements become increasingly stringent, the number of processors meeting both TDP and base frequency requirements decreases, potentially leading to lower-than-expected manufacturing yields. Summary of the Invention

[0003] One aspect of this disclosure provides a processor, including: a plurality of cores; a power management circuit for controlling the power consumption of the plurality of cores according to a first power control mode or a second power control mode, wherein the power management circuit enters the second power control mode when the frequency of a core among the plurality of cores has dropped below a specified minimum frequency; the power management circuit is configured to control the power consumption of the cores in the first power control mode by adjusting the voltage and frequency of the cores; and the power management circuit is configured to control the power consumption of the cores in the second power control mode by reducing the dynamic capacitance (C) associated with the cores. dyn This is used to control the power consumption of the core.

[0004] One aspect of this disclosure provides a machine-readable medium storing program code thereon, which, when executed by a power management circuit, causes the power management circuit to perform operations including: controlling the power consumption of a plurality of cores according to a first power control mode or a second power control mode, wherein entering the second power control mode when the frequency of a core among the plurality of cores has dropped below a specified minimum frequency; adjusting the voltage and frequency of the core in the first power control mode to control the power consumption of the core; and reducing the dynamic capacitance (C) associated with the core in the second power control mode. dyn To control power consumption.

[0005] One aspect of this disclosure provides a method comprising: controlling the power consumption of a plurality of cores by a power management circuit according to a first power control mode or a second power control mode, wherein entering the second power control mode when the frequency of a core among the plurality of cores has dropped below a specified minimum frequency; adjusting the voltage and frequency of the cores in the first power control mode to control the power consumption of the cores; and reducing the dynamic capacitance (C) associated with the cores in the second power control mode. dyn To control power consumption. Attached Figure Description

[0006] A better understanding of the invention will be obtained from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 The diagram illustrates an example computer system architecture.

[0007] Figure 2 The diagram illustrates a processor that includes multiple cores.

[0008] Figure 3(A) illustrates the multiple stages of the pipeline treatment.

[0009] Figure 3(B) illustrates details of one embodiment of the core.

[0010] Figure 4 An execution circuit according to one embodiment is illustrated.

[0011] Figure 5 An example of a register architecture is illustrated.

[0012] Figure 6 The illustration shows an example of an instruction format.

[0013] Figure 7 The illustration depicts an addressing technique according to one embodiment.

[0014] Figure 8 An example of an instruction prefix is ​​illustrated.

[0015] Figures 9(A)-9(D) The illustration shows an example of how to use the prefixed R, X, and B fields.

[0016] Figures 10(A)-10(B) An example of a second instruction prefix is ​​illustrated.

[0017] Figure 11 The illustration shows the payload byte of one embodiment of the instruction prefix.

[0018] Figure 12 The diagram illustrates the implementation of instruction conversion and binary translation.

[0019] Figure 13This is a block diagram of a system according to an embodiment of the present invention.

[0020] Figure 14 The illustration shows a slice-based deaggregation architecture that can be implemented thereon according to embodiments of the present invention.

[0021] Figure 15 Additional details of one embodiment of a slice-based de-aggregation architecture are illustrated.

[0022] Figure 16 The diagram illustrates communication between power units according to some embodiments. Figure 17 The illustration shows the arrangement of temperature sensors according to some embodiments.

[0023] Figure 18 The diagram illustrates an example architecture that includes an efficiency core cluster and a performance core cluster.

[0024] Figure 19 The diagram illustrates another example architecture that includes an efficiency core cluster, a performance core cluster, and an accelerator cluster.

[0025] Figure 20A The diagram illustrates power and voltage management in existing implementations.

[0026] Figure 20B The illustration depicts power and voltage management according to an embodiment of the present invention.

[0027] Figure 21 The diagram illustrates a power management circuit according to an embodiment of the present invention.

[0028] Figure 22 The diagram illustrates the transition between dynamic capacitor control mode and dynamic voltage and frequency regulation control mode.

[0029] Figure 23 The illustration shows the dynamic capacitor control logic according to an embodiment of the present invention.

[0030] Figure 24 The diagram illustrates several operating steps corresponding to the dynamic capacitor control mode.

[0031] Figure 25 The illustration shows a method according to an embodiment of the present invention. Detailed Implementation

[0032] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to those skilled in the art that embodiments of the invention may be implemented without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.

[0033] Exemplary Computer Architecture Exemplary computer architectures are described in detail below. Other system designs and configurations known in the art for laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In summary, a wide variety of systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally suitable.

[0034] Figure 1 An embodiment of an exemplary system is illustrated. The multiprocessor system 100 is a point-to-point interconnect system and includes a plurality of processors, including a first processor 170 and a second processor 180 coupled via a point-to-point interconnect 150. In some embodiments, the first processor 170 and the second processor 180 are homogeneous. In some embodiments, the first processor 170 and the second processor 180 are heterogeneous.

[0035] Processors 170 and 180 are shown to include integrated memory controller (IMC) unit circuitry 172 and 182, respectively. Processor 170 also includes point-to-point (PP) interfaces 176 and 178 as part of its interconnect controller unit; similarly, the second processor 180 includes PP interfaces 186 and 188. Processors 170 and 180 can exchange information via point-to-point (PP) interface 150 using PP interface circuitry 178 and 188. IMCs 172 and 182 couple processors 170 and 180 to their respective memories, namely memories 132 and 134, which may be part of the main memory locally attached to each processor.

[0036] Processors 170 and 180 can each exchange information with chipset 190 via individual PP interconnects 152 and 154 using point-to-point interface circuits 176, 194, 186, and 198, respectively. Chipset 190 can optionally exchange information with coprocessor 138 via high-performance interface 192. In some embodiments, coprocessor 138 is a dedicated processor, such as a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, etc.

[0037] A shared cache (not shown) may be included in either processor 170, 180, or outside of both processors but connected to the processors via a PP interconnect, such that local cache information of either or both processors may be stored in the shared cache when the processors are in a low-power mode.

[0038] Chipset 190 may be coupled to a first interconnect 116 via interface 196. In some embodiments, the first interconnect 116 may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Fast Interconnect or another I / O interconnect. In some embodiments, one of the interconnects is coupled to a power control unit (PCU) 117, which may include circuitry, software, and / or firmware to perform power management operations with respect to processors 170, 180, and / or coprocessor 138. PCU 117 provides control information to a voltage regulator to cause the voltage regulator to generate an appropriate regulated voltage. PCU 117 also provides control information to control the generated operating voltage. In various embodiments, PCU 117 may include various power management logic units (circuitry) to perform hardware-based power management. This power management may be entirely processor-controlled (e.g., controlled by various processor hardware and may be triggered by workload and / or power constraints, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0039] PCU 117 is illustrated as logic separate from processor 170 and / or processor 180. In other cases, PCU 117 may execute on one or more given cores (not shown) of processor 170 or 180. In some cases, PCU 117 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code (sometimes called P-code). In still other embodiments, the power management operations to be performed by PCU 117 may be implemented externally to the processor, for example, by means of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other embodiments, the power management operations to be performed by PCU 117 may be implemented within the BIOS or other system software.

[0040] Various I / O devices 114 may be coupled to a first interconnect 116 and an interconnect (bus) bridge 118 that couples the first interconnect 116 to a second interconnect 120. In some embodiments, one or more additional processors 115, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array (FPGA), or any other processor, are coupled to the first interconnect 116. In some embodiments, the second interconnect 120 may be a low pin count (LPC) interconnect. Various devices may be coupled to the second interconnect 120, including, for example, a keyboard and / or mouse 122, a communication device 127, and memory cell circuitry 128. Memory cell circuitry 128 may be a disk drive or other mass storage device, and in some embodiments, it may include instruction / code and data 130. Additionally, audio I / O 124 may be coupled to the second interconnect 120. Note that other architectures besides the point-to-point architecture described above are also possible. For example, a system such as the multi-processor system 100 can implement a multi-drop interconnect or other such architecture, rather than a point-to-point architecture.

[0041] Exemplary core architecture, processor, and computer architecture Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, these core implementations can include: 1) general-purpose ordered cores for general computing purposes; 2) high-performance general-purpose out-of-order cores for general computing purposes; and 3) dedicated cores primarily for graphics and / or scientific (throughput) computing purposes. Different processor implementations can include: 1) CPUs, including one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores for general computing purposes; and 2) coprocessors, including one or more dedicated cores primarily for graphics and / or scientific (throughput) purposes. Such different processors lead to different computer system architectures, which may include: 1) coprocessors and CPUs on separate chips; 2) coprocessors and CPUs on separate dies within the same package; 3) coprocessors and CPUs on the same die (in this case, such coprocessors are sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or dedicated cores); and 4) systems-on-a-chip (SoCs) that may include the aforementioned coprocessors and additional functionality on the same die as the described CPU (sometimes referred to as application cores or application processors). An exemplary core architecture is described next, followed by a description of exemplary processors and computer architectures.

[0042] Figure 2 A block diagram of an embodiment of processor 200 is illustrated. This processor may have more than one core, may have an integrated memory controller, and may have integrated graphics. Solid-line boxes illustrate processor 200 having a single core 202A, system agent 210, and a set of one or more interconnect controller unit circuits 216, while optionally added dashed-line boxes illustrate alternative processor 200 having multiple cores 202(A)-(N), a set of one or more integrated memory control unit circuits 214 and dedicated logic 208 from the system agent unit circuits 210, and a set of one or more interconnect controller unit circuits 216. Note that processor 200 may be… Figure 1 One of the processors 170 or 180 or the coprocessor 138 or 115.

[0043] Therefore, different implementations of processor 200 may include: 1) a CPU, where dedicated logic 208 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 202(A)-(N) are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 202(A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 202(A)-(N) are a large number of general-purpose ordered cores. Thus, processor 200 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit circuit), a high-throughput many-integrated-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. The processor 200 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a number of process technologies, such as BiCMOS, CMOS or NMOS.

[0044] The memory hierarchy includes one or more levels of cache cell circuitry 204(A)-(N) within cores 202(A)-(N), a group or one or more shared cache cell circuitry 206, and external memory (not shown) coupled to the group of integrated memory controller cell circuitry 214. The group of one or more shared cache cell circuitry 206 may include one or more intermediate level caches (e.g., level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), such as the last level cache (LLC), and / or combinations thereof. While in some embodiments a ring-based interconnect network circuitry 212 interconnects dedicated logic 208 (e.g., integrated graphics logic), the group of shared cache cell circuitry 206, and system proxy cell circuitry 210, alternative embodiments use any number of known techniques to interconnect such cells. In some embodiments, consistency is maintained between one or more of the shared cache cell circuitry 206 and cores 202(A)-(N).

[0045] In some embodiments, one or more of the cores 202(A)-(N) are capable of multithreaded processing. The system proxy unit circuitry 210 includes those components that coordinate and operate the cores 202(A)-(N). The system proxy unit circuitry 210 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of the cores 202(A)-(N) and / or dedicated logic 208 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0046] Cores 202(A)-(N) can be homogeneous or heterogeneous in terms of their instruction sets; that is, two or more cores 202(A)-(N) may be able to execute the same instruction set, while other cores may be able to execute only a subset of that instruction set or a different instruction set.

[0047] Exemplary Core Architecture Ordered and disordered core diagram Figure 3(A) is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention. Figure 3(B) is a block diagram illustrating both an exemplary embodiment of an ordered architecture core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core according to an embodiment of the present invention. Figures 3(A)-3(B) The solid boxes in the diagram illustrate ordered pipelines and ordered kernels, while the optional dashed boxes illustrate register renaming, out-of-order issue / execution pipelines, and kernels. Since ordered aspects are a subset of out-of-order aspects, out-of-order aspects will be described.

[0048] In Figure 3(A), processor pipeline 300 includes a fetch phase 302, an optional length decoding phase 304, a decoding phase 306, an optional allocation phase 308, an optional renaming phase 310, a scheduling (also known as dispatch or dispatch) phase 312, an optional register read / memory read phase 314, an execution phase 316, a write-back / memory write phase 318, an optional exception handling phase 322, and an optional commit phase 324. One or more operations can be performed in each of these processor pipeline phases. For example, during fetch phase 302, one or more instructions are fetched from instruction memory; during decoding phase 306, the fetched one or more instructions can be decoded; an address using a forwarding register port (e.g., a load store unit (LSU) address) can be generated; and branch forwarding (e.g., an immediate offset or a link register (LR)) can be performed. In one embodiment, decoding phase 306 and register read / memory read phase 314 can be combined into a single pipeline phase. In one embodiment, during execution phase 316, decoded instructions may be executed, LSU address / data pipelined to the Advanced Microcontroller Bus (AHB) interface may be executed, multiplication and addition operations may be executed, arithmetic operations with branching results may be executed, and so on.

[0049] As an example, the exemplary register renaming, out-of-order issue / execution core architecture can implement pipeline 300 as follows: 1) Instruction fetch 338 executes fetch and length decoding stages 302 and 304; 2) Decoding unit circuit 340 executes decoding stage 306; 3) Rename / allocator unit circuit 352 executes allocation stage 308 and rename stage 310; 4) Scheduler unit circuit 356 executes scheduling stage 312; 5) Physical register file unit circuit 358 and memory unit circuit 370 execute register read / memory read stage 314; execution cluster 360 executes execution stage 316; 6) Memory unit circuit 370 and physical register file unit circuit 358 execute write-back / memory write stage 318; 7) Various units (unit circuits) may be involved in exception handling stage 322; and 8) Deferral unit circuit 354 and physical register file unit circuit 358 execute commit stage 324.

[0050] Figure 3(B) shows that processor core 390 includes front-end unit circuitry 330 coupled to execution engine unit circuitry 350, and both are coupled to memory unit circuitry 370. Core 390 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 390 can be a dedicated core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0051] Front-end unit circuitry 330 may include branch prediction unit circuitry 332 coupled to instruction cache unit circuitry 334, which is coupled to translation lookaside buffer (TLB) 336, which is coupled to instruction fetch unit circuitry 338, which is coupled to decode unit circuitry 340. In one embodiment, instruction cache unit circuitry 334 is included in memory unit circuitry 370 instead of front-end unit circuitry 330. Decoding unit circuitry 340 (or decoder) may decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as outputs, which are decoded from, or otherwise reflect, or derived from the original instruction. Decoding unit circuitry 340 may also include address generation unit circuitry (AGU, not shown). In one embodiment, AGU uses forwarded register ports to generate LSU addresses and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). Various mechanisms can be used to implement the decoding unit circuit 340. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROMs), and so on. In one embodiment, core 390 includes a microcode ROM (not shown) or other medium that stores microcode for certain macro instructions (e.g., in the decoding unit circuit 340 or otherwise within the front-end unit circuit 330). In one embodiment, the decoding unit circuit 340 includes micro-ops or an operation cache (not shown) to retain / cacherate decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 300. The decoding unit circuit 340 may be coupled to the rename / allocator unit circuit 352 in the execution engine unit circuit 350.

[0052] The execution engine circuitry 350 includes a renaming / allocator unit circuitry 352, which is coupled to a retirement unit circuitry 354 and a set of one or more scheduler circuits 356. The scheduler circuits 356 represent any number of different schedulers, including reservation stations, central instruction windows, etc. In some embodiments, the scheduler circuitry 356 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an arithmetic generation unit (AGU) scheduler / scheduling circuit, an AGU queue, etc. One or more scheduler circuits 356 are coupled to one or more physical register file circuits 358. Each of the physical register file circuits 358 represents one or more physical register files, which store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, physical register file unit circuitry 358 includes vector register file unit circuitry, write mask register file unit circuitry, and scalar register file unit circuitry. These register files can provide architectural vector registers, vector mask registers, general-purpose registers, and so on. Physical register file unit circuitry 358 overlaps with retirement unit circuitry 354 (also referred to as a retirement queue or decommissioning queue) to illustrate various methods that can be used to implement register renaming and out-of-order execution (e.g., utilizing one or more reorder buffers (ROBs) and one or more retirement register files; utilizing one or more future heaps, one or more history buffers, and one or more retirement register files; utilizing register maps and register pools; etc.). Retirement unit circuitry 354 and one or more physical register file circuitry 358 are coupled to one or more execution clusters 360. One or more execution clusters 360 include a set of one or more execution unit circuitry 362 and a set of one or more memory access circuitry 364. Execution unit circuit 362 can perform various arithmetic, logical, floating-point, or other types of operations (e.g., shift, addition, subtraction, multiplication) on various types of data (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). While some embodiments may include several execution units or execution unit circuits dedicated to a particular function or set of functions, other embodiments may include only one execution unit circuit or multiple execution units / execution unit circuits that perform all functions.Scheduler circuitry 356, physical register file unit circuitry 358, and execution clusters (one or more) 360 are shown as potentially multiple, as some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each with its own scheduler circuitry, physical register file unit circuitry, and / or execution clusters—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of this pipeline has memory access unit circuitry 364). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be issued / executed out of order, while the rest are ordered.

[0053] In some embodiments, the execution engine unit circuit 350 can perform load memory unit (LSU) address / data pipelined to the Advanced Microcontroller Bus (AHB) interface (not shown), as well as address phase and write-back, data phase load, store, and branch.

[0054] The set of memory access circuitry 364 is coupled to memory cell circuitry 370, which includes data TLB cell circuitry 372, which is coupled to data cache circuitry 374, which is coupled to Level 2 (L2) cache circuitry 376. In one exemplary embodiment, memory access cell circuitry 364 may include load cell circuitry, memory address cell circuitry, and memory data cell circuitry, each of which is coupled to data TLB circuitry 372 in memory cell circuitry 370. Instruction cache circuitry 334 is further coupled to Level 2 (L2) cache cell circuitry 376 in memory cell circuitry 370. In one embodiment, instruction cache 334 and data cache 374 are combined into a single instruction and data cache (not shown) in L2 cache cell circuitry 376, Level 3 (L3) cache cell circuitry (not shown), and / or main memory. L2 cache cell circuitry 376 is coupled to one or more other levels of cache and ultimately coupled to main memory.

[0055] Core 390 may support one or more instruction sets (e.g., x86 instruction set (with some extensions added with newer versions); MIPS instruction set; ARM instruction set (with optional additional extensions, such as NEON)), including one or more instructions described herein. In one embodiment, core 390 includes logic to support compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using compressed data.

[0056] Exemplary execution unit circuit Figure 4 An embodiment of the execution unit circuitry is illustrated, such as execution unit circuitry 362 of FIG. 3(B). As shown, execution unit circuitry 362 may include one or more ALU circuits 401, vector / SIMD unit circuitry 403, load / store unit circuitry 405, and / or branch / jump unit circuitry 407. ALU circuitry 401 performs integer arithmetic and / or Boolean operations. Vector / SIMD unit circuitry 403 performs vector / SIMD operations on compressed data (e.g., SIMD / vector registers). Load / store unit circuitry 405 executes load and store instructions to load data from memory into registers or store data from registers into memory. Load / store unit circuitry 405 may also generate addresses. Branch / jump unit circuitry 407 causes a branch or jump to a memory address depending on the instruction. Floating-point unit (FPU) circuitry 409 performs floating-point arithmetic. The width of execution unit circuitry 362 varies depending on the embodiment and may range from 16 bits to 1024 bits. In some embodiments, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0057] Exemplary Register Architecture Figure 5 This is a block diagram of a register architecture 500 according to some embodiments. As shown, there is a vector / SIMD register 510 with a width ranging from 128 bits to 1024 bits. In some embodiments, the vector / SIMD register 510 is physically 512 bits, and depending on the mapping, only some of the lower bits are used. For example, in some embodiments, the vector / SIMD register 510 is a 512-bit ZMM register: the lower 256 bits are used for the YMM register, and the lower 128 bits are used for the XMM register. Therefore, register overriding exists. In some embodiments, the vector length field is selected between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length; scalar operations are performed at the lowest-order data element position in the ZMM / YMM / XMM registers; higher-order data element positions are either kept the same as before the instruction or are zeroed, depending on the embodiment.

[0058] In some embodiments, register architecture 500 includes write mask / predicate register 515. For example, in some embodiments, there are eight write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16-bit, 32-bit, 64-bit, or 128-bit in size. Write mask / predicate register 515 may allow merging (e.g., allowing any set of elements in the destination to be unupdated during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some embodiments, each data element position in a given write mask / predicate register 515 corresponds to a data element position in the destination. In other embodiments, write mask / predicate register 515 is scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits for each 64-bit vector element).

[0059] The register architecture 500 includes multiple general-purpose registers 525. These registers can be 16-bit, 32-bit, 64-bit, etc., and can be used for scalar operations. In some embodiments, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0060] In some embodiments, register architecture 500 includes a scalar floating-point register 545, which is used for scalar floating-point operations on 32 / 64 / 80-bit floating-point data extended with the x87 instruction set, or as an MMX register to perform operations on 64-bit compressed integer data, and to store operation objects for some operations performed between the MMX and XMM registers.

[0061] One or more flag registers 540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 540 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some embodiments, one or more flag registers 540 are referred to as program status and control registers.

[0062] Segment register 520 contains segment points for accessing memory. In some embodiments, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0063] The machine-specific register (MSR) 535 controls and reports processor performance. Most MSR 535 handles system-related functions and is not accessible to applications. The machine check register 560 consists of control, status, and error reporting MSRs used for detecting and reporting hardware errors.

[0064] One or more instruction pointer registers 530 store instruction pointer values. One or more control registers 555 (e.g., CR0-CR4) determine the operating mode of the processor (e.g., processors 170, 180, 138, 115, and / or 200) and the characteristics of the currently executing task. Debug register 550 controls and allows monitoring of debug operations on the processor or core.

[0065] Memory management register 565 specifies the location of data structures used in protected-mode memory management. These registers may include the GDTR, IDRT, task register, and LDTR register.

[0066] Alternative embodiments of the invention may use wider or narrower registers. Furthermore, alternative embodiments of the invention may use more, fewer, or different register files and registers.

[0067] Instruction set An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) to specify the operation to be performed (e.g., opcode) and the operand(s) to be performed on, and / or other data fields(e.g., mask), etc. Some instruction formats are further decomposed through the definition of instruction templates (or subformats). For example, an instruction template for a given instruction format may be defined as having different subsets of the fields of that instruction format (the included fields are usually in the same order, but at least some have different bit positions because fewer fields are included) and / or may be defined as having given fields interpreted in different ways. Thus, each instruction in an ISA is expressed using a given instruction format (and, if defined, as a given instruction template in the instruction templates of that instruction format) and includes fields for specifying the operation and operand. For example, an exemplary ADD instruction has a specific opcode and instruction format, which includes an opcode field to specify the opcode and an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field for selecting the specific operand.

[0068] Exemplary instruction format Implementations of the instructions(s) described herein may be carried out in various formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Implementations of the instructions(s)(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0069] Figure 6 An embodiment of the instruction format is illustrated. As shown, an instruction may include multiple components, including but not limited to one or more fields, for: one or more prefixes 601, opcode 603, addressing information 605 (e.g., register identifier, memory addressing information, etc.), offset value 607, and / or immediate value 609. Note that some instructions utilize some or all of the fields of this format, while other instructions may only use the fields of opcode 603. In some embodiments, the illustrated order is the order in which these fields are to be encoded; however, it should be understood that in other embodiments, these fields may be encoded in a different order, combined, etc.

[0070] One or more prefix fields 601 modify instructions when used. In some embodiments, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.) to provide section control (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.) to perform bus locking operations, and / or change the operand (e.g., 0x66) and address size (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes can be considered "traditional" prefixes. Other prefixes (one or more examples of which are detailed herein) indicate and / or provide further capabilities, such as specifying particular registers, etc. These other prefixes typically follow "traditional" prefixes.

[0071] The opcode field 603 is used to at least partially define the operation to be performed when the instruction is decoded. In some embodiments, the length of the major opcode encoded in the opcode field 603 is 1, 2, or 3 bytes. In other embodiments, the major opcode can be of different lengths. An additional 3-bit opcode field is sometimes encoded in another field.

[0072] Address field 605 is used to address one or more operands of an instruction, such as a location in memory or one or more registers. Figure 7An embodiment of addressing field 605 is illustrated. This illustration shows an optional ModR / M byte 702 and an optional Scale, Index, Base (SIB) byte 704. The ModR / M byte 702 and SIB byte 704 are used to encode up to two operands of an instruction, each operand being a direct register or an effective memory address. Note that each of these fields is optional; that is, not all instructions include one or more of these fields. The MOD R / M byte 702 includes the MOD field 742, the register field 744, and the R / M field 746.

[0073] The content of the MOD field 742 distinguishes between memory access and non-memory access modes. In some embodiments, when the value of the MOD field 742 is b11, register direct addressing mode is used; otherwise, register indirect addressing is used.

[0074] Register field 744 may encode a destination register operand or a source register operand, or may encode an opcode extension, and may not be used to encode any instruction operand. The contents of register index field 744 directly specify or generate by address the location of the specified source or destination operand (in a register or in memory). In some embodiments, register field 744 is supplemented with additional bits from a prefix (e.g., prefix 601) to allow for larger addressing.

[0075] The R / M field 746 can be used to encode instruction operands that reference memory addresses, or it can be used to encode destination register operands or source register operands. Note that in some embodiments, the R / M field 746 can be combined with the MOD field 742 to specify the addressing mode.

[0076] SIB byte 704 includes a scaling field 752, an index field 754, and a base field 756 for address generation. The scaling field 752 indicates a scaling factor. The index field 754 specifies the index register to be used. In some embodiments, the index field 754 is padded with extra bits from a prefix (e.g., prefix 601) to allow for larger addressing. The base field 756 specifies the base address register to be used. In some embodiments, the base field 756 is padded with extra bits from a prefix (e.g., prefix 601) to allow for larger addressing. In practice, the content of the scaling field 752 allows scaling the content of the index field 754 for memory address generation (e.g., for addresses using 2...). 缩放 *Address generation of index + base address.

[0077] Some addressing schemes use bitwise shifts to generate memory addresses. For example, they can be based on 2缩放 Memory addresses are generated using methods such as *index + base address + offset, index * scaling + offset, r / m + offset, instruction pointer (RIP / EIP) + offset, register + offset, etc. The offset can be a value of 1 byte, 2 bytes, 4 bytes, etc. In some embodiments, the offset field 607 provides this value. Furthermore, in some embodiments, the offset factor usage is encoded in the MOD field of the addressing field 605, indicating a compressed offset scheme for which the offset value is calculated by multiplying disp8 by a scaling factor N, which is determined based on the vector length, the value of b bits, and the size of the instruction input elements. This offset value is stored in the offset field 607.

[0078] In some embodiments, the immediate number field 609 specifies an immediate value for the instruction. The immediate value can be encoded as a 1-byte value, a 2-byte value, a 4-byte value, and so on.

[0079] Figure 8 An embodiment of the first prefix 601(A) is illustrated. In some embodiments, the first prefix 601(A) is an embodiment of the REX prefix. Instructions using this prefix can specify general-purpose registers, 64-bit compact data registers (e.g., single instruction, multiple data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0080] Instructions using the first prefix 601(A) can specify up to three registers using 3-bit fields, depending on the format: 1) using the reg field 744 and the R / M field 746 of Mod R / M byte 702; 2) using Mod R / M byte 702 with SIB byte 704, including using the reg field 744 and the base field 756 and the index field 754; or 3) using the register field of the opcode.

[0081] In the first prefix 601(A), bits 7:4 are set to 0100. Bit 3 (W) can be used to determine the operand size, but may not determine the operand width independently. Therefore, when W = 0, the operand size is determined by the code segment descriptor (CS.D), while when W = 1, the operand size is 64 bits.

[0082] Note that adding another bit allows addressing 16(2) 4 The MOD R / M reg field 744 and MOD R / MR / M field 746 can each address 8 registers, while the individual MOD R / M reg field 744 and MOD R / MR / M field 746 can each address 8 registers.

[0083] In the first prefix 601(A), bit position 2(R) can be an extension of the MOD R / M reg field 744, and can be used to modify the ModR / M reg field 744 when this field encodes a general-purpose register, a 64-bit compressed data register (e.g., an SSE register), or a control or debug register. R is ignored when the Mod R / M byte 702 specifies another register or defines an extended opcode.

[0084] Bit position 1 (X) X bits can modify SIB byte index field 754.

[0085] Bit position B (B) B can modify the base address in Mod R / MR / M field 746 or SIB byte base address field 756; or it can modify the opcode register field used to access general-purpose registers (e.g., general-purpose register 525).

[0086] Figures 9(A)-(D) illustrate embodiments of how the R, X, and B fields of the first prefix 601(A) are used. Figure 9(A) illustrates that when SIB byte 704 is not used for memory addressing, the R and B from the first prefix 601(A) are used to extend the reg field 744 and R / M field 746 of the MOD R / M byte 702. Figure 9(B) illustrates that when SIB byte 704 is not used, the R and B from the first prefix 601(A) are used to extend the reg field 744 and R / M field 746 of the MOD R / M byte 702 (register-to-register addressing). Figure 9(B) illustrates that when SIB byte 704 is used for memory addressing, the R, X, and B from the first prefix 601(A) are used to extend the reg field 744, as well as the index field 754 and the base address field 756 of the MOD R / M byte 702. Figure 9(D) illustrates that when the register is encoded in opcode 603, the B from the first prefix 601(A) is used to extend the reg field 744 of the MOD R / M byte 702.

[0087] Figures 10(A)-(B) illustrate embodiments of the second prefix 601(B). In some embodiments, the second prefix 601(B) is an embodiment of the VEX prefix. The second prefix 601(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD register 510) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 601(B) provides a syntax for three operands (or more). For example, the previous two-operand instructions performed operations such as A = A + B, which overwrote the source operands. The use of the second prefix 601(B) enables operands to perform non-destructive operations, such as A = B + C.

[0088] In some embodiments, the second prefix 601(B) has two forms—a two-byte form and a three-byte form. The two-byte second prefix 601(B) is primarily used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 601(B) provides a compact replacement for the first prefix 601(A) and 3-byte opcode instructions.

[0089] Figure 10(A) illustrates an embodiment of the two-byte form of the second prefix 601(B). In one example, format field 1001 (byte 0 1003) contains the value C5H. In another example, byte 1 1005 includes the value “R” in bit [7]. This value is the complement of the same value of the first prefix 601(A). Bit [2] is used to specify the length (L) of the vector (where the value of 0 is a scalar or a 128-bit vector, and the value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensions equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). The bits [6:3] shown as vvvv can be used to: 1) encode the first source register operand, which is specified in reverse (ones complement) form, for instructions with two or more source operands; 2) encode the destination register operand, which is specified in ones complement form, for some vector shift; or 3) not encode any operand, in which case the field is reserved and should contain a value such as 1111b.

[0090] Instructions using this prefix can use the Mod R / MR / M field 746 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0091] Instructions using this prefix can use the Mod R / M reg field 744 to encode either the destination register operand or the source register operand, and are treated as an opcode extension, rather than being used to encode any instruction operand.

[0092] For instruction syntax supporting four operands, vvvv, Mod R / MR / M field 746, and Mod R / M reg field 744 encode three of the four operands. Then bits [7:4] of immediate value 609 are used to encode the third source register operand.

[0093] Figure 10(B) illustrates an embodiment of the three-byte form of the second prefix 601(B). In one example, format field 1011 (byte 0 1013) contains the value C4H. Byte 1 1015 includes “R”, “X”, and “B” in bits [7:5], which are complements of the same values ​​of the first prefix 601(A). Bits [4:0] of byte 1 1015 (shown as mmmmm) include content to encode one or more implicit preamble opcode bytes as needed. For example, 00001 means 0FH preamble opcode, 00010 means 0F38H preamble opcode, 00011 means 0F3AH preamble opcode, and so on.

[0094] Bits [7] of byte 2 1017 are used similarly to W of the first prefix 601(A), including to help determine the size of the operand that can be promoted. Bit [2] is used to specify the length (L) of the vector (where the value of 0 is a scalar or a 128-bit vector, and the value of 1 is a 256-bit vector). Bits [1:0] provide opcode extensions equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3] shown as vvvv can be used to: 1) encode the first source register operand, which is specified in reverse (ones complement) form, valid for instructions with two or more source operands; 2) encode the destination register operand, which is specified in ones complement form, for some vector shift; or 3) not encode any operand, in which case the field is reserved and should contain a value, such as 1111b.

[0095] Instructions using this prefix can use the Mod R / MR / M field 746 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0096] Instructions using this prefix can use the Mod R / M reg field 744 to encode either the destination register operand or the source register operand, and are treated as an opcode extension, rather than being used to encode any instruction operand.

[0097] For instruction syntax supporting four operands, vvvv, Mod R / MR / M field 746, and Mod R / M reg field 744 encode three of the four operands. Then bits [7:4] of immediate value 609 are used to encode the third source register operand.

[0098] Figure 11 An embodiment of the third prefix 601(C) is illustrated. In some embodiments, the first prefix 601(A) is an embodiment of the EVEX prefix. The third prefix 601(C) is a four-byte prefix.

[0099] The third prefix 601(C) enables the encoding of 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some embodiments, write masks / operation masks are used (see the discussion of registers in the previous figures, e.g.) Figure 5 Or predicted instructions utilize this prefix. The operation mask register allows for conditional processing or selection control. Operation mask instructions—whose source / destination operation object is the operation mask register and treats the contents of the operation mask register as a single value—are encoded using the second prefix 601(B).

[0100] The third prefix 601(C) can encode instruction class-specific features (e.g., a compact instruction with "load + operation" semantics can support embedded broadcast functionality, a floating-point instruction with rounding semantics can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics can support "suppress all exceptions" functionality, and so on).

[0101] The first byte of the third prefix 601(C) is the format field 1111, which in one example has a value of 62H. The subsequent bytes are called payload bytes 1115-1119, and together they form the 24-bit value of P[23:0], which provides specific capabilities in the form of one or more fields (detailed here).

[0102] In some embodiments, P[1:0] of payload byte 1119 is identical to the two lower mmmm bits. In some embodiments, P[3:2] is reserved. Bit P[4] (R') allows access to the high 16 vector register set when combined with P[7] and ModR / M reg field 744. P[6] also provides access to the high 16 vector registers when SIB type addressing is not required. P[7:5] consists of R, X, and B, which are the operand specifier modifier bits for vector registers, general-purpose registers, and memory addressing, and when combined with ModR / M register field 744 and ModR / MR / M field 746, allows access to the next set of 8 registers beyond the lower 8 registers. P[9:8] provides opcode extrapolation equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). P

[10] is a fixed value of 1 in some embodiments. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand specified in inverse (ones complement) form, valid for instructions with two or more source operands; 2) encode a destination register operand specified in ones complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a value such as 1111b.

[0103] P

[15] is similar to W in the first prefix 601(A) and the second prefix 611(B), and can be used as an opcode extension bit or an operand size boost.

[0104] P[18:16] specifies the index of the register in the operation mask (write mask) register (e.g., write mask / predicate register 515). In one embodiment of the invention, the specific value aaa = 000 has special behavior, implying that no operation mask is used for a particular instruction (this can be implemented in various ways, including using a hard-wired operation mask to all one or hardware that bypasses the masking hardware). When merged, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic and enhanced operations); in another embodiment, the old value of each element with a corresponding mask bit of 0 is preserved in the destination. In contrast, when the zero-reset vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic and enhanced operations); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operations performed (i.e., the span of the modified elements, from the first to the last); however, the modified elements do not necessarily have to be contiguous. Thus, the operation mask field allows for some vector operations, including load, store, arithmetic, logic, etc. While an embodiment of the invention has been described in which the content of the operation mask field selects the operation mask to be used from among several operation mask registers (thus the content of the operation mask field indirectly identifies the mask to be performed), alternative embodiments, as a substitute or addition, allow the mask to be written directly to the content of the field to specify the mask to be performed.

[0105] P

[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax that allows access to the high 16 vector registers using P

[19] . P

[20] encodes various functions that differ across different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0106] The table below details exemplary embodiments of register encoding in instructions using the third prefix 601(C).

[0107]

[0108] Table 2: Encoding Register Specify in 32-bit Mode

[0109] Table 3: Operation Mask Register Specifier Encoding Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as a digital signal processor (DSP), microcontroller, application-specific integrated circuit (ASIC), or microprocessor.

[0110] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. Assembly or machine language can also be used if desired. In fact, the mechanisms described in this article are not limited to any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0111] The mechanisms disclosed herein can be implemented using hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code that execute on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0112] One or more aspects of at least one embodiment may be implemented by representative instructions representing various logics within a processor, stored on a machine-readable medium, which, when read by a machine, cause the machine-made logic to perform the techniques described herein. This representation, referred to as an "IP core," may be stored on a tangible machine-readable medium and provided to various customer or manufacturing facilities for loading into the manufacturing machine that actually manufactures the logic or processor.

[0113] Such machine-readable storage media may include, but are not limited to, non-transitory tangible arrangements of articles made or formed by a machine or device, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions.

[0114] Therefore, embodiments of the present invention also include a non-transitory tangible machine-readable medium containing instructions or design data, such as a Hardware Description Language (HDL), that defines the features of the structures, circuits, devices, processors, and / or systems described herein. Such embodiments may also be referred to as program products.

[0115] Simulation (including binary translation, code transformation, etc.) In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off-processor, or partially on-processor and partially off-processor.

[0116] Figure 12The block diagram contrasts, according to certain implementations, the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 12 A program of high-level language 1202 is shown to be compiled using a first ISA compiler 1204 to generate first ISA binary code 1206, which can be natively executed by a processor 1216 having at least one first instruction set core. A processor 1216 having at least one first ISA instruction set core means any processor that can perform substantially the same function as an Intel® processor having at least one first ISA instruction set core by compatiblely executing or otherwise processing (1) a substantial portion of the instruction set of the first ISA instruction set core or (2) a version of object code of an application or other software targeted to run on an Intel processor having at least one first ISA instruction set core, so as to achieve substantially the same results as a processor having at least one first ISA instruction set core. The first ISA compiler 1204 means a compiler operable to generate the first ISA binary code 1206 (e.g., object code), which can be executed on a processor 1216 having at least one first ISA instruction set core with or without additional linking processing.

[0117] Similarly, Figure 12 A program in high-level language 1202 is shown to be compiled using an alternative instruction set compiler 1208 to generate alternative instruction set binary code 1210, which can be natively executed by a processor 1214 without a first ISA instruction set core. An instruction converter 1212 is used to translate the first ISA binary code 1206 into code that can be natively executed by a processor 1214 without a first ISA instruction set core. This translated code is unlikely to be identical to the alternative instruction set binary code 1210, as an instruction converter capable of doing so would be difficult to manufacture; however, the translated code will implement general operations and consist of instructions from the alternative instruction set. Thus, the instruction converter 1212 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation, or any other process, allows a processor or other electronic device without a first ISA instruction set processor or core to execute the first ISA binary code 1206.

[0118] While the following embodiments are described with reference to a specific integrated circuit, such as an integrated circuit in a computing platform or processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy savings. For example, the disclosed embodiments are not limited to any particular type of computer system. That is, the disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower servers, rack servers, blade servers, microservers, etc.), communication systems, storage systems, desktop computers of any configuration, laptops, notebook computers, to tablet computers (including 2:1 tablet devices, phablets, etc.), and can also be used in other devices such as handheld devices, systems-on-chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can typically include microcontrollers, digital signal processors (DSPs), network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system capable of performing the functions and operations taught below. Additionally, embodiments can be implemented in mobile terminals with standard voice capabilities, such as mobile phones, smartphones, and tablets, and / or in non-mobile terminals without standard wireless voice communication capabilities, such as many wearable devices, tablets, laptops, desktop computers, microservers, servers, and so on. Furthermore, the apparatuses, methods, and systems described herein are not limited to physical computing devices but may also involve software optimizations.

[0119] Now for reference Figure 13 A block diagram of a portion of a system according to an embodiment of the present invention is shown. Figure 13 As shown, system 1300 may include various components, including processor 1310, which is a multi-core processor as shown. Processor 1310 may be coupled to power supply source 1350 via external voltage regulator 1360, which may perform a first voltage conversion to provide a main regulated voltage to processor 1310.

[0120] As can be seen, the processor 1310 can be a single-die processor comprising multiple cores 1320a-1320n. Furthermore, each core can be associated with an integrated voltage regulator (IVR) 1325a-1325n, which receives a master regulated voltage and generates an operating voltage to be supplied to one or more agents of the processor associated with that IVR. Therefore, an IVR implementation can be provided to allow fine-grained control of voltage, and thus allow fine-grained control of the power and performance of each individual core. In this way, each core can operate at independent voltage and frequency, which provides great flexibility and offers a wide range of opportunities to balance power consumption and performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated by the IVR and supplied only to those components in the group. During power management, a given power plane of one IVR can be powered down or de-energized when the processor is placed in a low-power state, while another power plane of another IVR remains active or fully powered.

[0121] Still referencing Figure 13 Additional components may reside within the processor, including input / output interface 1332, another interface 1334, and an integrated memory controller 1336. It can be seen that each of these components may be powered by another integrated voltage regulator 1325x. In one embodiment, interface 1332 may be enabled for Intel® Quick Path Interconnect (QPI) interconnect, which provides a point-to-point (PtP) link in a cache coherence protocol comprising multiple layers, including a physical layer, a link layer, and a protocol layer. Furthermore, interface 1334 may communicate via the Peripheral Component Interconnect Express (PCIe™) protocol.

[0122] A power control unit (PCU) 1338 is also shown, which may include hardware, software, and / or firmware to perform power management operations with respect to processor 1310. It can be seen that PCU 1338 provides control information to an external voltage regulator 1360 via a digital interface to cause the voltage regulator to generate an appropriate regulated voltage. PCU 1338 also provides control information to an IVR 1325 via another digital interface to control the generated operating voltage (or to disable the corresponding IVR in a low-power mode). In various embodiments, PCU 1338 may include various power management logic units to perform hardware-based power management. This power management may be entirely processor-controlled (e.g., controlled by various processor hardware and may be triggered by workload and / or power constraints, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0123] In this embodiment, PCU 1338 may be configured to dynamically determine hardware feedback information regarding the performance and energy efficiency capabilities of hardware circuitry such as core 1320, and provide an interface to enable this information to be communicated to the OS scheduler for making better scheduling decisions. To this end, PCU 1338 may be configured to determine and store this information, either internally within PCU 1338 or in another storage device of system 1300.

[0124] In addition, although Figure 13 The illustration shows an implementation where the PCU 1338 is a separate processing engine (which can be implemented as a microcontroller), but it's important to understand that in some cases, in addition to or replacing a dedicated power controller, each core may include a power control agent or be associated with a power control agent to more autonomously and independently control power consumption. In some cases, a hierarchical power management architecture may be provided, in which the PCU 1338 and the corresponding power management agent associated with each core 1320 communicate.

[0125] Although not shown for ease of illustration, it should be understood that additional components, such as non-core logic, and other components such as internal memory, for example, one or more levels of the cache memory hierarchy, may exist within the processor 1310. Furthermore, although in Figure 13 The implementation is illustrated using an integrated voltage regulator, but the embodiments are not limited to this.

[0126] The processor described herein can utilize a power management technique that is independent of and complementary to operating system-based power management (OSPM) mechanisms. According to one example OSPM technique, the processor can operate in various performance states or levels (so-called P states, i.e., from P0 to PN). Generally, the P1 performance state corresponds to the highest guaranteed performance state that the OS can request. In addition to this P1 state, the OS can also request higher performance states, i.e., the P0 state. This P0 state can thus be an opportunistic or enhanced mode state, in which the processor hardware can configure the processor or at least some of its components to operate at frequencies higher than the guaranteed frequency, when power and / or thermal budget are available. In many implementations, the processor may include multiple so-called bin frequencies exceeding the maximum guaranteed frequency up to the maximum peak frequency of a particular processor, which are burned in or otherwise written into the processor during manufacturing. Furthermore, according to an OSPM mechanism, the processor can operate in various power states or levels. Regarding power states, the OSPM mechanism can specify different power states, generally referred to as C states, C0, C1 to Cn. When a core is active, it operates in the C0 state, and when a core is idle, it can be placed in a core low-power state, also known as a core non-zero C state (e.g., C1-C6 states), where each C state is at a lower power level (thus C6 is a lower low-power state than C1, and so on).

[0127] It is important to understand that many different types of power management techniques can be used individually or in combination in different implementations. As a representative example, a power controller can manage the power of a processor using some form of dynamic voltage frequency scaling (DVFS), in which the operating voltage and / or operating frequency of one or more cores or other processor logic can be dynamically controlled to reduce power consumption in certain situations. In one example, enhanced Intel SpeedStep™ technology, available from Intel Corporation in Santa Clara, California, can be used to perform DVFS to provide optimal performance at the lowest possible power consumption level. In another example, Intel TurboBoost™ technology can be used to perform DVFS so that one or more cores or other computing engines can operate at frequencies higher than guaranteed based on conditions such as workload and availability.

[0128] Another power management technique that can be used in some examples is the dynamic switching of workloads between different computing engines. For example, a processor may include asymmetric cores or other processing engines operating at different power levels, allowing one or more workloads to be dynamically switched to execute on lower-power cores or other computing engines in power-constrained situations. Another exemplary power management technique is hardware duty cycling (HDC), which allows cores and / or other computing engines to be periodically enabled and disabled according to duty cycles, enabling one or more cores to be inactive during inactive periods of a duty cycle and active during active periods of a duty cycle.

[0129] Examples of heterogeneous architectures Figure 14 An example of a processor with a disaggregated architecture is illustrated, comprising a SoC tile 1410, a CPU tile 1415, a GPU tile 1405, and an I / O tile 1420 integrated on a common base tile 1490 coupled to a package substrate. In some embodiments, each tile includes a separate die or chip that communicates with other dies / chips via horizontal and / or vertical interconnects (e.g., through-silicon vias). The SoC tile 1410 includes a memory controller to couple the processor to system memory 1450 and provides various other SoC-level functions, such as various IP blocks, a display engine, and a consistent structural interconnect between low-power IP blocks that remain operational even when the processor enters a low-power state.

[0130] Some embodiments implement a distributed power management architecture comprising multiple power management units (P-units) 1430-1433 distributed across different dies 1405, 1410, 1415, and 1420. In some implementations, the P-units 1430-1433 are configured as a hierarchical power management subsystem, wherein a single P-unit (e.g., P-unit 1430 on SoC die 1410 in several examples described herein) operates as a supervisory P-unit, which collects and evaluates power management metrics provided from the other P-units 1431-1433 to make package-level power management decisions and determine the power / performance state (e.g., frequency and voltage of each IP block) to be operated for each die and / or individual IP block.

[0131] Supervisory P-cell 1430 communicates power / performance status to other P-cells 1431-1433, which implement power / performance status locally on each respective chip. In some implementations, the package-wide power management decisions of supervisory P-cell 1430 include those involving core parking and / or core merging, as described herein.

[0132] An operating system (OS) and / or other supervisory firmware (FW) or software (SW) 1470 may communicate with the supervisory P-unit 1430 to exchange power management status information and power management requests (e.g., "hints" as described herein). A hardware boot unit 1414 and an association table may be implemented in the supervisory P-unit 1430 and / or the SoC chip 1410. In some implementations described herein, communication between the OS / supervisory FW / SW 1470 and the P-unit 1430 occurs via a mailbox register or a set of mailbox registers. In some embodiments, a baseboard management controller (BMC) or other system controller may exchange power control messages with the supervisory P-unit 1430 via these mailbox registers or another set of mailbox registers.

[0133] Figure 15 Additional details of one embodiment of CPU chip 1415 are illustrated. CPU chip 1415 includes a heterogeneous core set comprising efficiency cores (E cores) arranged in two E core clusters 1510-1511 and multiple performance cores (P cores) 1520-1521. Some embodiments of SoC chip 1410 include: a set of E cores 1512-1513; and a memory controller 1515 for coupling the processor to system memory 1450 (e.g., DDR DRAM memory, HBM memory, etc.). Similarly, GPU chip 1405 includes multiple graphics cores 1507-1508 that can be managed in the same manner as the P cores and E cores described herein.

[0134] The E-cores in the E-core cluster 1510-1511 and the SoC chip 1410 are physically smaller (multiple E-cores are fitted into the physical die space of the P-cores), designed to maximize CPU efficiency (measured in performance per watt) and are typically used for scalable multi-threaded performance. The E-cores work in conjunction with the P-cores 1520-1521 to accelerate tasks that tend to consume a large number of cores. The E-cores are optimized to efficiently run background tasks, and therefore, smaller tasks are often offloaded to the E-cores (e.g., handling Discord or antivirus software) – leaving the P-cores 1520-1521 idle to drive high-performance tasks such as gaming or 3D rendering.

[0135] The P-cores 1520-1521 are physically larger and are high-performance cores tuned for high turbo frequencies and high instructions per cycle (IPC), and are particularly well-suited for handling heavy single-threaded tasks. In some embodiments, the P-cores are also capable of hyper-threading (i.e., running multiple software threads concurrently).

[0136] In the illustrated embodiment, different P units 1515-1516 are associated with each E-core cluster 1510-1511 to manage power consumption within each corresponding E-core cluster in response to messages from the supervisory P unit 1530, and to transmit power usage metrics to the supervisory P unit 1530. Similarly, different P units 1525-1526 are associated with each P core 1520-1521 to manage the power / performance of the corresponding P core in response to the supervisory P unit 1530, and to collect power usage metrics and transmit them to the supervisory P unit 1530.

[0137] In one embodiment, local P units 1515-1516 and 1525-1526 manage power locally by independently adjusting the frequency / voltage levels for each E-core cluster 1510-1511 and P-core 1520-1521, respectively. For example, P units 1515-1516 control digital linear voltage regulators (DLVRs) and / or fully integrated voltage regulators (FIVRs) to independently manage the frequency / voltage applied to each E-core within the E-core cluster 1510-1511. Similarly, P units 1525-1526 control another set of DLVRs and / or FIVRs to independently manage the frequency / voltage applied to each P-core 1520-1521. Graphics cores 1507-1508 and / or E-cores 1512-1513 can be similarly controlled via DLVRs / FIVRs. In these implementations, the frequency / voltage associated with a first core can be dynamically and independently adjusted—that is, without affecting the frequency / voltage of one or more other cores. Dynamic and independent control of individual E-cores / P-cores provides processor-wide dynamic voltage and frequency scaling (DVFS) controlled by the supervisory P-unit 1530.

[0138] like Figure 16 As shown, in some implementations, the supervisory P-unit 1530 and other P-units 1515 in the processor communicate via a private structure 1647. The supervisory P-unit 1530 sends power management messages to the other P-units 1515 via a transmit (TX) mailbox 1630 and receives messages from the other P-units via a receive (RX) mailbox 1631. Each other P-unit (e.g., P-unit 1515 shown for simplicity) includes a TX mailbox 1616 for sending messages and an RX mailbox 1617 for receiving messages.

[0139] In some embodiments, P units 1530, 1515 include a microcontroller or processor for executing firmware 1635, 1636, respectively, to perform the power management operations described herein. For example, supervisory firmware 1635, executed by supervisory P unit 1530, specifies operations such as transmitting a message sent to TX mailbox 1630 and then to RX mailbox 1617 of P unit 1515 via private structure 1647. Here, "mailbox" may refer to a specified register or memory location, or a driver executed in kernel space. Upon receiving a message, RX mailbox 1617 may save relevant portions of the message to memory 1618 (e.g., a region in local memory or system memory), the contents of which are accessible by P unit 1515 executing a copy of its firmware 1636 (which may be the same as or different from the firmware 1635 executed by supervisory P unit 1530).

[0140] In response to receiving a message, the P unit 1515 executing firmware 1636 acknowledges receipt of the message by sending an acknowledgment (Ack) message to the supervisor 1530 via the TX mailbox 1616. This acknowledgment message is transmitted to the RX mailbox 1631 via structure 1647 and may be stored in memory 1632 (e.g., a region in local memory or system memory). The supervisor P unit 1530 (executing firmware 1635) accesses memory 1632 to read and evaluate the message to be processed, thereby determining subsequent operational procedures.

[0141] In various embodiments, the supervisory P-unit 1530 can be accessed via a common structure 1646 through other system components such as a global agent 1655 (e.g., a platform supervisor agent, such as a BMC). In some embodiments, the common structure 1646 and the private structure 1647 are the same structure. In some embodiments, the supervisory P-unit 1530 can also be accessed by a software driver 1650 (e.g., a software driver 1650 operable within an OS or other supervisory FW / SW 1470) via a main structure 1645 and / or an application programming interface (API) 1640. In some embodiments, a single structure is used instead of Figure 16 The three independent structures shown are 1645-1647.

[0142] Figure 17The illustration shows an example SoC where temperature sensors 1712-1713, associated with each P-core 1520-1521, and temperature sensors 1714-1715, associated with each E-core cluster 1510-1511, report temperature measurements to the corresponding local P-units 1525-1526 and 1515-1516. Local P-units 1525-1526 and 1515-1516 can dynamically adjust local power consumption based on the temperature measurements and / or pass the temperature measurements to the supervisory P-unit 1530 (previously combined with...). Figure 15 (Description) The supervisory P-cell makes package-range power management decisions based at least in part on temperature measurements.

[0143] Similarly, temperature sensor 1741 associated with GPU chip 1405 reports temperature readings to local P-unit 1431, and temperature sensor 1710 associated with accelerator 1425 reports its temperature readings to local P-unit 1401. The two P-units 1431 and 1401 can dynamically adjust local power consumption based on these measurements and / or send temperature measurements to supervisory P-unit 1530 for package-wide power management decisions. In the example shown, temperature sensor 1731 on SoC chip 1410 reports temperature measurements directly to the supervisory P-unit.

[0144] However, it should be noted that the basic principles of this invention are not limited to the depolymerization system architecture or Figure 17 The specific de-aggregation architecture is illustrated in the diagram. Furthermore, embodiments of the invention described herein do not require a hierarchical power management subsystem (e.g., having a supervisory P-cell and multiple local P-cells).

[0145] Figure 18 The illustration shows an example implementation of SoC 1890, which includes a compute die 1851 having an efficiency core cluster 1812 and a performance core cluster 1814. The efficiency core cluster 1812 includes multiple efficiency cores 1815-1818 and a shared cache 1819, and the performance core cluster 1814 includes multiple performance cores 1825-1828 and a shared cache 1829. The I / O and control die 1850 includes input / output (I / O) interface circuitry 1841 and power management circuitry 1832, which has scheduling support circuitry 1830 for generating scheduling cues 1844 based on current power, temperature, and workload conditions 1881 and current region allocation 1834 as described herein. The efficiency core cluster 1812 and performance core cluster 1814 are coupled to memory 1802 (e.g., DRAM system memory) via a consistency structure and cache 1808 (e.g., last-level cache (LLC)) and memory controller 1804.

[0146] The computing die 1851 can be coupled to the I / O and control die 1850 via die-to-die interconnects (e.g., interconnects provided by an embedded multi-die interconnect bridge (EMIB)). Although Figure 18 The multi-die implementation is shown, but the basic principle of the present invention can be implemented on a single-die processor or on a multi-die processor with more than two dies.

[0147] In some implementations, the power management circuitry 1832 on the I / O and control die 1850 is a supervisory power manager (e.g., supervisory P-cell 1530 as described above). The power management circuitry 1832 makes SoC-wide power management decisions based at least in part on information provided by the computing die power manager 1831, which performs local power management for the computing die 1851.

[0148] As previously described, scheduling support circuitry 1830 communicates with scheduler 1880, which schedules multiple tasks 1881-1884 on efficiency core cluster 1812 and / or performance core cluster 1814 according to the techniques described herein. In some embodiments, scheduler 1880 is provided in an operating system or other supervisory software or firmware. Based on current conditions related to the characteristics of power, temperature, and / or workload 1881, scheduling support hardware 1830 provides scheduler 1880 with hints 1844 (e.g., scheduling recommendations) related to task placement on performance cluster 1812 and efficiency cluster 1814. Although scheduling support circuitry 1830 is shown as part of power management circuitry 1832, scheduling support circuitry 1830 and power management circuitry 1832 may be separate but interconnected circuit blocks on I / O and control die 1850.

[0149] In some implementations, power management circuitry 1832 determines a maximum achievable performance requirement 1887 based on one or more specified EPB values ​​1888, which may be stored in a control register (e.g., an MSR). When efficiency cluster 1812 is able to meet the maximum achievable performance requirement 1887 based on one or more energy / performance bias values ​​1888, power management circuitry 1832 assigns efficiency core cluster 1812, but not performance core cluster 1814, to a performance region. Scheduling support circuitry 1830 or power management circuitry 1832 generates a corresponding region allocation 1834, which maps efficiency core cluster 1812 and performance core cluster 1814 to different regions based on the current energy / performance bias value 1888 and the corresponding maximum achievable performance requirement 1887 (e.g., as indicated in one or more MSRs).

[0150] As an example and not a limitation, regions may include performance regions for performance-oriented tasks, efficiency regions for efficiency-oriented tasks, and multi-threaded regions for multi-threaded tasks. Scheduling support circuitry 1830 or power management circuitry 1832 may map efficiency cluster 1812 or performance cluster 1814 to performance regions based on the current(one or more) efficiency / performance bias values ​​1888 and / or the maximum achievable performance 1887. In one particular implementation, efficiency cluster 1812 is mapped to an efficiency region regardless of the efficiency / performance bias values ​​1888, and performance cluster 1814 is mapped to a multi-threaded region. However, in other embodiments, the cluster-to-region mapping is dynamic, allowing any cluster to be mapped to any defined region.

[0151] In some implementations, the EPB value 1888 is based on a normalized sliding scale (e.g., between 0 and 15), where relatively large values ​​indicate an energy bias and relatively low values ​​indicate a performance bias. In some embodiments, an EPB threshold 1889 is indicated in a control register (e.g., another MSR). EPB values ​​1888 greater than or equal to this threshold are considered energy-biased, and EPB values ​​less than this threshold are considered performance-biased. The mapping between clusters and regions is then performed accordingly (e.g., as shown in Table 6).

[0152] The techniques described in this article can be applied to SoC architectures with more than two types of computing clusters. For example, in Figure 19 In this process, an accelerator cluster 1820, comprising a set of accelerator cores 1835-1838 and a cache 1839, is integrated within a compute die 1851. The accelerator cores 1835-1838 can be graphics cores, neural processing unit (NPU) cores (e.g., for performing machine learning operations such as matrix multiplication), tensor processing cores, data compression cores, or any other core type used for accelerating operations.

[0153] In these implementations, the accelerator cluster 1820 can be mapped to a specific region, at least in part, based on one or more EPB values ​​1888 and / or the maximum achievable performance 1887. For example, where the EPB value indicates a performance preference, the accelerator cluster 1820 can be mapped to a performance region and / or a multi-threaded region. In some embodiments, another region, such as a second performance region or acceleration region, is defined, which is enabled and mapped to the accelerator cluster 1820 for certain types of workloads. As previously described, the scheduling support circuitry 1830 can then convey the region allocation 1834 as a prompt 1844 to the scheduler 1880, which responsively schedules tasks 1881-1884 based on the region allocation 1834.

[0154] As mentioned earlier, recent processor generations with a larger core count typically need to operate at a lower or similar Thermal Design Power (TDP) specification compared to earlier generations. Power control processes, such as those based on Operating Average Power Limits (RAPL), Power Limit 1 (PL1), and Power Limit 2 (PL2), maintain the processor's average power consumption below the specified TDP by adjusting the voltage and frequency of one or more processor components (e.g., cores and non-cores). For example, as power increases, the RAPL control loop reduces the frequency of one or more processor components to keep the average power consumption within the TDP limit. However, the need to operate at lower power levels reduces the processor's ability to reliably reach guaranteed frequencies and, in extreme cases, may result in processors operating below manufacturing specifications.

[0155] To mitigate this problem, the implementation scheme manages the dynamic capacitance (C) dyn This is achieved to guarantee minimum frequency operation, thereby reducing the high C values ​​that typically operate at or near the P1 frequency (also known as the guaranteed maximum frequency). dyn The application's power consumption, and enables lower C dyn Value-related applications can run without restrictions and without performance impact.

[0156] Dynamic capacitance C of circuit blocks such as the core dyn This is related to workload and can be correlated with instructions per cycle (IPC) using formulas that take into account the electrical characteristics of various cores in the SoC. Typically, the average power consumption of an active processor core can be determined using the following formula: P core = C dyn * V 2 * f, where V and f represent the operating voltage and frequency of the corresponding core, respectively.

[0157] To overcome the above limitations, the embodiment uses C dyn Controls regulate power while maintaining frequency at V. min Frequency (fV) min (For example, the frequency corresponding to the minimum defined voltage or the user-defined frequency specified via the MSR). These embodiments perform frequency and voltage scaling until fV is reached. min Subsequently, intelligent C was implemented in the core. dyn Control (also referred to in this paper as intelligent throttling (INTRO)) is used to reduce power. Since the frequency will never drop below fV... min Therefore, these embodiments address the negative impact on the fundamental frequency (P1 frequency) and the aforementioned deficiencies in binning yield.

[0158] Figure 20AThe diagram illustrates the difference between C and no C. dyn The scaling implementation frequency corresponds to a curve of power and voltage levels, and Figure 20B The illustration shows a diagram with C according to an embodiment of the present invention. dyn Scaling power and voltage levels at the same frequency in 2005. Specifying minimum power level in 2010 and minimum voltage level in 2011. Figure 20A -B is indicated by the corresponding dashed horizontal line.

[0159] Depending on the implementation, Dynamic Voltage and Frequency Scaling (DVFS) is used to reduce power until the frequency reaches fvmin 2015. This effectively reduces power because V in this region... 2 Dominant (i.e., according to) P core = C dyn * V 2 * f At this point, the corresponding core frequency remains at fvmin 2015, and the core dynamic capacitance C... dyn It is scaled down to reduce power.

[0160] Below fvmin, since the voltage is flat, C dyn - The frequency tradeoff is 1:1. In these implementations, C is modified... dyn Instead of frequency, first use C, which is predicted to be the most effective. dyn Reduction techniques (e.g., with an IPC:C ratio of approximately 1:1) dyn (Weigh the options), and then use a more aggressive C if necessary. dyn Reduce technology. The most effective C dyn The reduction technology uses intelligent C associated with the core. dyn Control is predictive (e.g., configured at least in part based on the manufacturability criteria described herein). Depending on these implementations, for high C... dyn For applications, sacrificing some performance is acceptable, as long as the rest are at a lower C++ level. dyn Applications (which represent most general-purpose applications) can operate without restrictions. These implementations guarantee a deterministic core operating point at frequencies greater than or equal to fvmin, while ensuring appropriate power reduction for TDP-constrained scenarios.

[0161] Figure 21 The illustration shows an example embodiment including multiple cores 2115, on which the intelligent C as described herein is implemented. dynControl. Power management code 2131, executing on power management circuitry 2132, collects power-related operational data 2110 from processor cores 2115, including current (I) data collected by current sensing circuitry associated with each core. Various cores 2115 and / or power management circuitry 2132 can be configured according to the intelligent C described herein. dyn The control mechanism is configured. As an example, not a limitation, C... dyn Control mechanisms may include throttling of the following: Speculative Depth Control (SDC), aggressiveness of branch prediction, aggressiveness of prefetcher, greedy allocation / retreat, power virus protection (PVP), and micro-operation (uop) processing. However, it should be noted that the basic principles of this invention are not limited to use with intelligent C. dyn Any specific throttling scheme under control.

[0162] In some embodiments, the most effective throttling technique or combination of throttling techniques is determined to provide optimal IPC:C. dyn Trade-offs. The most effective throttling techniques or combinations can be determined by testing different throttling schemes against different cores (and / or other circuit blocks) using different types of workloads. One or more of the most effective throttling techniques can be determined by testing and / or dynamically at runtime (e.g., using feedback to continuously evaluate the efficiency of each throttling technique for a given core or other circuit block).

[0163] In the example shown, core C0 2116 receives the Running Average Power Limit (RAPL) frequency limit from power management circuitry 2132. In some implementations, the RAPL frequency limit is stored in one or more control registers of power management circuitry 2132 (e.g., a specific operating point WP register, such as WP1 register in this example). Power management circuitry 2132 implements DVFS to reach a target frequency until it reaches fvmin 2115. In response to the frequency dropping below fvmin 2115, the core (or other circuit block) employs the intelligent C described herein. dyn A control mechanism is used to reduce power while maintaining the frequency at fvmin 2115 or higher.

[0164] In some embodiments, intelligent C dyn Control is achieved using a periodic proportional-integral-derivative (PID) controller 2150, which employs a most efficient IPC:C ratio. dyn Weigh the choice of one or more throttling techniques to reduce C dyn The PID controller 2150 may include a state machine and may be implemented in hardware, software / firmware, or any combination thereof.

[0165] In some embodiments, the PID controller 2150 is configured with a frequency setpoint fvmin and a PID feedback channel, which includes a RAPL forced frequency output from operating power management code 2131 (e.g., P code, A code, etc.). In the illustrated example, the RAPL forced frequency is indicated by C0.WP1.f (i.e., indicating the operating point 1 frequency for core 0). The output 2130 of the periodic PID controller 2150 is input to operating point calculation circuit 2120, which responsively determines the current operating point and corresponding operating frequency of core 2115. Thus, in the illustrated example, as the power used by core C0 is fed through C... dyn Control decreases, and the RAPL feedback loop should recover. When the RAPL limit equals fvmin, this means the core's C... dyn The correct limits have been set.

[0166] When C dyn When control is initiated, one throttling scheme involves controlling the speculative rate of micro-operations (e.g., the aggressiveness of branch depth) rather than forcibly stopping micro-operation execution. Here, "more aggressive" means less speculative, which results in lower C. dyn (i.e., lower IPC). Alternatively (or alternatively), branch prediction speculation can be reduced until C is satisfied. dyn (Frequency) target. If C is still not achieved. dyn The goal is to force throttling of micro-operation execution as needed to achieve C. dyn The goal is to achieve the desired result. Other throttling techniques (e.g., greedy retirement / allocation or dynamic width control) can also be applied to effectively reduce C. dyn .

[0167] In some embodiments, C dyn Reduce the aggressiveness of the target being used for dynamically setting configurations, and core C dyn The threshold is used to enforce the maximum allowed C of the core. dyn (For example, adjusting the core execution rhythm by using PID control as described in this article). Mechanisms such as branch speculation control and dynamic width control effectively reduce C dyn To recover from IPC loss. When operating point calculation is activated, select a specific type of C. dyn Forced implementation (e.g., DVFS based on the nonlinear region of the voltage-frequency (VF) curve, or using the VF curve below F). min (INTRO pattern of linear regions).

[0168] In some embodiments, the output 2130 of the periodic PID controller 2150 is a PVP threshold, which is tuned by the operating point calculator 2120 to limit the core C. dyn To meet the WP1 frequency. Maximum Cdyn The threshold can be enforced by throttling the IPC, for example, by increasing the aggressiveness of speculative depth control and using proportional-only control of the PID controller 2150.

[0169] According to some embodiments, C is performed as follows: dyn Control. When the operating point frequency WP1.f is less than the minimum frequency value, C should be reduced. dyn Therefore, as described herein, instruction processing (e.g., IPC) is limited. When WP1.f is greater than the minimum frequency value, C can be increased. dyn Therefore, restrictions on instruction processing are lifted. When WP1.f equals the minimum frequency value, this is C. dyn The convergence point that matches the core budget.

[0170] In some embodiments, one or more fuses or other persistent on-chip memory are configured to define minFreq (e.g., shared by all licenses of the processor) to reflect the transition point between the linear and nonlinear regions of the VF curve. Table 8 shows an example fuse definition for IA_VMIN_RATIO, which is encoded with 7 bits to indicate the minimum frequency defined for operation in normal operating mode.

[0171]

[0172] Table 8 Some embodiments also support software / firmware configuration settings to change the persistence definition. For example, one or more MSR registers or other control registers can be updated via the topology-aware register and PM capsule interface (TPMI) to set the minimum guaranteed frequency (e.g., to a value different from the value indicated by one or more fuse persistence indicators).

[0173] As mentioned earlier, this article describes the intelligent C dyn Control / intelligent throttling (INTRO) can be implemented at least in part in power management code 2131 (e.g., in P code, A code, or a combination thereof). PM code 2131 can reduce C during each WP1 update. dyn Or frequency. In a particular embodiment, code P performs a WP1 update, and code A responsively reduces C. dyn Or frequency. If WP1.frequency is less than the Fvmin threshold, then aggressive C can be initiated. dynSubsequent evaluations can determine whether WP1.Frequency remains below the VMIN_RATIO fuse value. PM code 2131 (e.g., P code) periodically evaluates the RAPL budget on the slow loop and adjusts WP1.Frequency accordingly. For example, if power rises above the RAPL threshold, PM code 2131 decreases WP1.Frequency. If power falls below the RAPL threshold, PM code 2131 increases WP1.Frequency.

[0174] When frequency has a linear effect on power based on the VF curve (i.e., the voltage flat region), reducing speculative aggression will yield more performance than reducing frequency. As an example, and not a limitation, Table 9 shows data collected from one implementation demonstrating IPC and Cp values ​​for speculative depth control against the SPEC CPU 2017 benchmark workload (Spec17 GCC8). dyn Impact:

[0175] Table 9 Therefore, intelligent C based on inference depth dyn Control provides a larger C than IPC dyn This reduces the frequency, thereby increasing instructions per second (IPS) at the Fvmin frequency of 2015. For different throttling schemes, IPC:C dyn The impact will vary, but will result in significant yield improvements during manufacturing. Performance losses, if any, will be limited to high C-frequency operation near P1n (i.e., n cores running at P1). dyn Workloads. All other workloads will run without restrictions.

[0176] When the frequency is limited by the Vmin ratio (Fmin), speculative aggression can be reduced (e.g., via core management firmware) to decrease the gap between the power budget and the current core power. Subsequently, if the frequency remains below the minimum frequency, the execution of micro-operations can be throttled to reduce C... dyn Reduce to an appropriate level. When the frequency is limited by Vmin_ratio(Fmin), it will enter C. dyn Control mode / INTRO mode. In some embodiments, this means reducing or increasing C. dyn And wait for WP1 feedback signal before proceeding to the next step.

[0177] Figure 22 The diagram shows C. dyn The switching between Control Mode 2201 and DVFS Mode 2200 (also known as Power Virus Control (PVC) Mode), C dynControl mode 2201 executes as described in this document: Intelligent C dyn In DVFS mode 2200, dynamic adjustments to core frequency and voltage are performed to reduce power consumption. When the operating point 1 (WP1) frequency drops below the defined Vmin ratio (i.e., below Fvmin 2015), a transition from DVFS mode 2200 to C... dyn Switching between control modes 2201.

[0178] In C dyn In control mode 2201, Speculation Depth Control (SDC) is initiated at level 0 (L0). If the WP1 frequency remains at or below the Vmin ratio at SDCL0, the SDC level is progressively increased, resulting in more aggressive speculation depth control (i.e., less speculation). If the highest SDC level is reached (SDL=3 in the example) and the WP1 frequency is still at or below the Vmin ratio, the PVP threshold is reduced proportionally.

[0179] When the WP1 frequency rises above the Vmin ratio, if C dyn Once the level and SDC level have been minimized, you can switch back to DVFS mode 2200. In DVFS mode, C can be increased or decreased as described in this article. dyn Level. In some embodiments, when WP1.f is less than Vmin_Ratio (e.g., Fvmin 2015), the power management code (e.g., A code, P code, etc.) continues to decrease C. dyn The level will increase until it reaches a defined minimum. Otherwise, it will increase C. dyn The level reaches the defined maximum value, then enters the normal PVP / DVFS mode. If in C... dyn If WP1.f is less than Vmin_Ratio at level 0, the power management code will progressively increase the SDC level (gradually reducing speculative operations) until it reaches its highest level. Otherwise (e.g., if WP1.f reaches Vmin_Ratio), it will progressively decrease the SDC level until it reaches the lowest level, and then move to C. dyn Level knob (i.e., and enter DVFS mode 2130). If at the highest SDC level (e.g., C... dyn If WP1.f is less than Vmin_Ratio at Level 0 / SDC Level 3, the power management code will begin to proportionally reduce the PVP threshold by an amount equal to [missing value]. Until a difference of approximately ±3% is reached. Otherwise, it will increase the threshold proportionally by an amount of [missing value]. This continues until a difference of approximately ±3% is reached. In these embodiments, each action is performed only after the WP1 update.

[0180] Therefore, when the WP1 frequency is below the Vmin ratio threshold, a transition from DVFS mode (also known as PVC mode) to C occurs. dyn Switching to (entering) the control mode (also known as INTRO mode). From C dyn Switching back to DVFS mode (exit) from control mode is only possible in C. dyn This occurs after the control mode gradually transitions back to the entry state. For example, when in SDC3, C dyn Control mode switched back to C dyn Level 0: SDC3 → SDC2 → … SDC0 → C dyn Level 0 → DVFS / PVC mode. This is done to avoid oscillations between the two modes.

[0181] Figure 23 The diagram illustrates an example C operable according to a Finite State Machine (FSM) 2315. dyn Control logic 2310, this state machine is in state C dyn The above operations are performed in control mode 2320. FSM 2315 generates a control signal 2350 to the operating point (WP) calculation circuit 2340, which indicates that the update 2322 in response to WP1 is maintained at C. dyn Control mode 2320 will switch to DVFS mode 2130. In response, WP calculation circuit 2340 outputs the next operating point (WP) and other variables described herein, such as the PVP threshold (e.g., Fvmin 2015) and the next SDC level.

[0182] Figure 24 The diagram shows C dyn In one embodiment of control mode 2320, the steps represent downward and upward transitions. Starting from step 2410, in C, which is shared by all licenses... dyn At this point, when the WP1 frequency is less than Vmin_Ratio, additional steps 2410 can be taken sequentially through the previously described Speculation Depth Control (SDC) levels (i.e., speculation decreases as the step moves down, from SDC0 to SDC3). If the WP1 frequency is less than Vmin_Ratio at SDC3, the power management code progressively lowers the PVP threshold, proceeding down to step 2420. An upward step movement occurs at any point where the WP1 frequency reaches or rises above Vmin_Ratio—ultimately returning to DVFS mode 2130.

[0183] Table 10 illustrates an example configuration register (CORE_PMA_CR_CONFIG_10) with an enable bit that can be set to enable the intelligent throttling techniques described herein. Table 11 illustrates an example performance limit register (PMSB_PCU_CR_ACP_PERF_LIMIT) with an enable bit that can be set to enable performance limiting based on the Vmin ratio (see, for example, Table 8).

[0184]

[0185] Table 10

[0186] Table 11 refer to Figure 25 At 2500, starting from DVFS mode (also known as PVC mode), if the current operating point frequency (e.g., WP1) drops below fvmin (determined at 2501), then at 2502, the Cdyn control mode is initialized and progressively enters one or more speculative depth control (SDC) levels. If the frequency does not remain below fvmin (determined at 2503), then at 2510, the speculative depth control operation progressively moves down the SDC level (e.g., … SDC2 → SDC1 → SDC0) until DVFS mode (2500) is reached.

[0187] If the frequency remains below fvmin (determined at 2503), and if the final SDC level (e.g., SDC3) has been reached (determined at 2504), the PVP threshold is progressively reduced at 2505 until the current operating point frequency is greater than or equal to fvmin. As previously mentioned, in some embodiments, the power management code will begin to proportionally reduce the PVP threshold by an amount that is... This continues until a difference of approximately ±3% is reached. When the current WP frequency reaches fvmin, it enters the highest SDC level (e.g., SDC3), and the SDC level continues to gradually decrease at 2510 until the lowest SDC level (e.g., SDC0) is reached, at which point it enters DVFS mode at 2500. It is assumed here that the WP frequency remains below fvmin at each SDC level. If the final SDC level is not reached at 2504, the next SDC level is entered at 2506, and the process returns to 2502.

[0188] The embodiments of the invention described herein address the problem associated with performance degradation in processor generation P1n, thereby ensuring operation within defined TDP specifications and improving overall manufacturing yield.

[0189] The example computer architecture is described in detail below. Other system designs and configurations known in the art for laptops, desktop and handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, de-aggregation servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, various systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are often appropriate.

[0190] The embodiments disclosed herein (e.g., mechanism embodiments) can be implemented in hardware, software, firmware, or a combination thereof. The embodiments of this disclosure can be implemented as a computer program or program code that executes on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0191] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0192] The program code can be implemented using a high-level procedural or object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented using assembly or machine language. In fact, the mechanisms described in this article are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0193] One or more aspects of at least one embodiment can be implemented by representative instructions stored on a machine-readable medium, which represent various logics within a processor that, when read by a machine, cause the machine to manufacture the logic to perform the techniques described herein. Such a representation (referred to as an "IP core") can be stored on a tangible machine-readable medium and provided to various customers or manufacturers for loading into a manufacturing machine that actually manufactures the logic or processor.

[0194] Such machine-readable storage media may include, but are not limited to, non-transitory arrangements of tangible articles made or formed by a machine or device, including storage media such as hard disks, any other type of disk (including floppy disks, optical disks, read-only compressed disk storage (CD-ROM), rewritable compressed disk (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) (e.g., dynamic random access memory (DRAM)), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM)), magnetic cards or optical cards, or any other type of media suitable for storing electronic instructions.

[0195] Therefore, embodiments of this disclosure also include non-transitory, tangible machine-readable media containing instructions or design data (e.g., hardware description language (HDL)) that define the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0196] Example The following are example implementations of different embodiments of the present invention.

[0197] Example 1. A processor, comprising: a plurality of cores; a power management circuit for controlling the power consumption of the plurality of cores according to a first power control mode or a second power control mode, the power management circuit entering the second power control mode when the frequency of a core among the plurality of cores has dropped below a specified minimum frequency; the power management circuit for controlling the power consumption of the cores in the first power control mode by adjusting the voltage and frequency of the cores; and the power management circuit for controlling the power consumption of the cores in the second power control mode by reducing the dynamic capacitance (C) associated with the core when the frequency of the core is below the specified minimum frequency. dyn This is used to control the power consumption of the core.

[0198] Example 2. A processor as described in Example 1, wherein, when in the second power control mode, the power management circuitry controls instruction processing parameters to reduce the CPU usage associated with the core. dyn .

[0199] Example 3. A processor as described in Example 1 or 2, wherein the instruction processing parameters include one or more of the following: speculative control level, power virus protection (PVP) threshold, branch prediction aggressiveness level, prefetcher aggressiveness level, greedy allocation / retreat operation, and micro-operation processing constraints.

[0200] Example 4. A processor as described in any one of Examples 1-3, wherein each speculative control level is associated with a corresponding maximum speculative rate, which is used to reduce the C++ core associated with the core. dyn .

[0201] Example 5. A processor as described in any one of Examples 1-4, wherein the power management circuitry is configured to progressively increase the speculative control level until the core operates at the specified minimum frequency.

[0202] Example 6. A processor as described in any one of Examples 1-5, wherein the power management circuitry is configured to progressively reduce the speculative control level while the core operates at or above the specified minimum frequency.

[0203] Example 7. A processor as described in any one of Examples 1-6, wherein the power management circuitry is configured to enter the first power control mode when the core operates at the specified minimum frequency or higher at the minimum speculative control level.

[0204] Example 8. A processor as described in any one of Examples 1-7, wherein the power management circuitry is configured to perform dynamic voltage and frequency scaling (DVFS) in the first control mode to regulate the voltage and frequency of the core.

[0205] Example 9. A processor as described in any one of Examples 1-8, wherein the power management circuitry is configured to progressively increase the speculative control level until a maximum speculative control level is reached; and the power management circuitry is configured to proportionally decrease the power virus protection threshold until the core frequency is equal to or greater than the specified minimum frequency.

[0206] Example 10. A machine-readable medium having stored program code thereon, the program code, when executed by a power management circuit, causing the power management circuit to perform operations, the operations including: controlling the power consumption of a plurality of cores by the power management circuit according to a first power control mode or a second power control mode, wherein entering the second power control mode when the frequency of a core among the plurality of cores has dropped below a specified minimum frequency; adjusting the voltage and frequency of the core in the first power control mode to control the power consumption of the core; and in the second power control mode, reducing the dynamic capacitance (C) associated with the core when the frequency of the core is below the specified minimum frequency. dyn To control power consumption.

[0207] Example 11. A machine-readable medium as described in Example 10, wherein, when in the second power control mode, in response to the program code, the power management circuitry controls instruction processing parameters to reduce the C associated with the core. dyn .

[0208] Example 12. A machine-readable medium as described in Example 10 or 11, wherein the instruction processing parameters include one or more of the following: speculative control level, power virus protection (PVP) threshold, branch prediction aggressiveness level, prefetcher aggressiveness level, greedy allocation / retreat operation, and micro-operation processing constraints.

[0209] Example 13. A machine-readable medium as described in any one of Examples 10-12, wherein each speculation control level is associated with a corresponding maximum speculation rate, the maximum speculation rate being used to reduce the C associated with the core. dyn .

[0210] Example 14. A machine-readable medium as described in any one of Examples 10-13, wherein, in response to the program code, the power management circuitry is configured to progressively increase the speculative control level until the core operates at the specified minimum frequency.

[0211] Example 15. A machine-readable medium as described in any one of Examples 10-14, wherein, in response to the program code, the power management circuitry is configured to progressively reduce the speculative control level while the core operates at or above the specified minimum frequency.

[0212] Example 16. A machine-readable medium as described in any one of Examples 10-15, wherein, in response to the program code, the power management circuitry is configured to enter the first power control mode when the core operates at the specified minimum frequency or higher at the minimum speculative control level.

[0213] Example 17. A machine-readable medium as described in any one of Examples 10-16, wherein, in response to the program code, the power management circuitry is configured to perform dynamic voltage and frequency scaling (DVFS) in the first control mode to regulate the voltage and frequency of the core.

[0214] Example 18. A machine-readable medium as described in any one of Examples 10-17, wherein, in response to the program code, the power management circuitry is configured to progressively increase the speculative control level until a maximum speculative control level is reached, and the power management circuitry is configured to proportionally decrease the power virus protection threshold until the core frequency is equal to or greater than the specified minimum frequency.

[0215] Example 19. A method comprising: controlling the power consumption of a plurality of cores according to a first power control mode or a second power control mode by a power management circuit, wherein entering the second power control mode when the frequency of a core among the plurality of cores has dropped below a specified minimum frequency; adjusting the voltage and frequency of the cores in the first power control mode to control the power consumption of the cores; and in the second power control mode, reducing a dynamic capacitance (C) associated with the core when the frequency of the core is below the specified minimum frequency. dyn To control power consumption.

[0216] Example 20. The method as described in Example 19, wherein, when in the second power control mode, the power management circuitry controls command processing parameters to reduce the C associated with the core. dyn .

[0217] The embodiments of the invention described herein improve performance at the same power level or energy consumption rate as existing implementations, or provide equivalent performance at a lower power level compared to existing implementations, thereby improving performance or extending the operating time of computing devices with the same battery life. In one particular implementation, these embodiments improve performance by approximately 60% while maintaining the same power level as existing implementations.

[0218] Embodiments of the present invention may include the various steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by a specific hardware component containing hard-wired logic for performing these steps, or by any combination of a programmable computer component and a custom hardware component.

[0219] As described herein, instructions can refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform a specific operation or have a predetermined function, or to software instructions stored in memory embodied in a non-transitory computer-readable medium. Therefore, the techniques illustrated in the figures can be implemented using code and data stored on and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer-machine-readable media to store and communicate (internal and / or with other electronic devices via a network) code and data. Computer-machine-readable media can be, for example, non-transitory computer-machine-readable storage media (e.g., disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transitory computer-machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagation signals—e.g., carrier waves, infrared signals, digital signals, etc.).

[0220] Furthermore, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. This coupling of the processors with other components is typically achieved via one or more buses and bridges (also known as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on one or more processors of that electronic device. Of course, one or more portions of embodiments of the invention can be implemented using different combinations of software, firmware, and / or hardware.

[0221] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without some of these specific details. In some cases, well-known structures and functions have not been described in detail to avoid obscuring the subject matter of the invention. Therefore, the scope and spirit of the invention should be determined based on the appended claims.

[0222] The embodiments of the invention described herein improve performance at the same power level or energy consumption rate as existing implementations, or provide equivalent performance at a lower power level compared to existing implementations, thereby improving performance or extending the operating time of computing devices with the same battery life. In one particular implementation, these embodiments improve performance by approximately 60% while maintaining the same power level as existing implementations.

[0223] Embodiments of the present invention may include the various steps described above. These steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform these steps. Alternatively, these steps may be performed by a specific hardware component containing hard-wired logic for performing these steps, or by any combination of a programmable computer component and a custom hardware component.

[0224] As described herein, instructions can refer to a specific configuration of hardware, such as an application-specific integrated circuit (ASIC) configured to perform a specific operation or have a predetermined function, or they can refer to software instructions stored in memory embodied in a non-transitory computer-readable medium. Therefore, the techniques illustrated in the figures can be implemented using code and data stored on and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). Such electronic devices use computer-machine-readable media to store and communicate (internal and / or with other electronic devices via a network) code and data, such as non-transitory computer-machine-readable storage media (e.g., disks; optical disks; random access memory; read-only memory; flash memory devices; phase-change memory) and transient computer-machine-readable communication media (e.g., electrical, optical, acoustic, or other forms of propagation signals—e.g., carrier waves, infrared signals, digital signals, etc.).

[0225] Furthermore, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. This coupling of the set of processors with other components is typically achieved via one or more buses and bridges (also known as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on one or more processors of that electronic device. Of course, one or more portions of embodiments of the invention can be implemented using different combinations of software, firmware, and / or hardware.

[0226] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without some of these specific details. In some cases, well-known structures and functions have not been described in detail to avoid obscuring the subject matter of the invention. Therefore, the scope and spirit of the invention should be determined based on the appended claims.

Claims

1. A processor, comprising: Multiple cores; A power management circuit is used to control the power consumption of the plurality of cores according to a first power control mode or a second power control mode, wherein the power management circuit enters the second power control mode when the frequency of one of the plurality of cores has dropped below a specified minimum frequency. The power management circuit is used to control the power consumption of the core by adjusting the voltage and frequency of the core in the first power control mode; and The power management circuitry is used in the second power control mode to reduce the dynamic capacitance (C) associated with the core. dyn This is used to control the power consumption of the core.

2. The processor as claimed in claim 1, wherein, When in the second power control mode, the power management circuit controls command processing parameters to reduce the C-value associated with the core. dyn .

3. The processor as claimed in claim 2, wherein, The instruction processing parameters include one or more of the following: speculative control level, power virus protection (PVP) threshold, branch prediction aggressiveness level, prefetcher aggressiveness level, greedy allocation / retreat operation, and micro-operation processing constraints.

4. The processor as claimed in claim 3, wherein, Each speculative control level is associated with a corresponding maximum speculative rate, which will be used to reduce the C associated with the core. dyn .

5. The processor as claimed in claim 4, wherein, The power management circuitry is used to progressively increase the speculative control level until the core operates at the specified minimum frequency.

6. The processor of claim 5, wherein, The power management circuitry is used to progressively reduce the speculative control level while the core operates at or above the specified minimum frequency.

7. The processor of claim 6, wherein, The power management circuitry is configured to enter the first power control mode when the core operates at the minimum speculative control level at or above the specified minimum frequency.

8. The processor as claimed in any one of claims 1 to 7, wherein, The power management circuitry is used to perform dynamic voltage and frequency scaling (DVFS) in the first control mode to adjust the voltage and frequency of the core.

9. The processor as claimed in any one of claims 4 to 8, wherein, The power management circuit is used to gradually increase the speculative control level until the maximum speculative control level is reached; the power management circuit is used to proportionally decrease the power virus protection threshold until the core frequency is equal to or greater than the specified minimum frequency.

10. A machine-readable medium having program code stored thereon, the program code, when executed by a power management circuit, causing the power management circuit to perform an operation, the operation comprising: The power management circuit controls the power consumption of multiple cores according to a first power control mode or a second power control mode, wherein when the frequency of one of the multiple cores has dropped below a specified minimum frequency, the second power control mode is entered. In the first power control mode, the voltage and frequency of the core are adjusted to control the power consumption of the core; and In the second power control mode, the dynamic capacitance (C) associated with the core is reduced. dyn To control power consumption.

11. The machine-readable medium of claim 10, wherein, When in the second power control mode, in response to the program code, the power management circuit controls instruction processing parameters to reduce the C associated with the core. dyn .

12. The machine-readable medium of claim 11, wherein, The instruction processing parameters include one or more of the following: speculative control level, power virus protection (PVP) threshold, branch prediction aggressiveness level, prefetcher aggressiveness level, greedy allocation / retreat operation, and micro-operation processing constraints.

13. The machine-readable medium of claim 12, wherein, Each speculative control level is associated with a corresponding maximum speculative rate, which will be used to reduce the C associated with the core. dyn .

14. The machine-readable medium of claim 13, wherein, In response to the program code, the power management circuitry is used to progressively increase the speculative control level until the core operates at the specified minimum frequency.

15. The machine-readable medium of claim 14, wherein, In response to the program code, the power management circuitry is configured to progressively reduce the speculative control level while the core operates at or above the specified minimum frequency.

16. The machine-readable medium of claim 15, wherein, In response to the program code, the power management circuitry is configured to enter the first power control mode when the core operates at the minimum speculative control level at or above the specified minimum frequency.

17. The machine-readable medium as claimed in any one of claims 10 to 16, wherein, In response to the program code, the power management circuitry is configured to perform dynamic voltage and frequency scaling (DVFS) in the first control mode to adjust the voltage and frequency of the core.

18. The machine-readable medium as claimed in any one of claims 13 to 17, wherein, In response to the program code, the power management circuit is used to gradually increase the speculative control level until the maximum speculative control level is reached, and the power management circuit is used to proportionally decrease the power virus protection threshold until the core frequency is equal to or greater than the specified minimum frequency.

19. A method comprising: The power management circuit controls the power consumption of multiple cores according to a first power control mode or a second power control mode, wherein when the frequency of one of the multiple cores has dropped below a specified minimum frequency, the second power control mode is entered. In the first power control mode, the voltage and frequency of the core are adjusted to control the power consumption of the core; and In the second power control mode, the dynamic capacitance (C) associated with the core is reduced. dyn To control power consumption.

20. The method of claim 19, wherein, When in the second power control mode, the power management circuit controls command processing parameters to reduce the C-value associated with the core. dyn .

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