Data storage control method for embedded acquisition and control devices for primary frequency modulation
Patent Information
- Application Number
- CN202611348251.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-02
- Publication Date
- 2026-09-29
AI Technical Summary
[0005]针对上述现有技术的缺陷，本发明提供了一种面向一次调频的嵌入式采集控制装置的数据存储控制方法，解决一次调频动作期间高优先级数据写入延迟不可控、丢失风险高，高优先级数据的存储写入依赖CPU搬运，存储任务对CPU资源占用率较高的问题
[0032]通过基于频率偏差变化率RoCoF的SRAM缓存区分配策略，根据电网扰动严重程度提前为高优先级实时数据预留足够的缓存空间，实现存储资源的预测性调配；通过DMA直接传输实现AD采样数据至SRAM的零CPU占用快速传输，降低写入延迟和CPU存储开销；多状态刷写策略与一次调频过程耦合，触发态暂停Flash刷写避免存储I/O与高优先级数据写入的争用，恢复期加急刷写快速释放缓存空间；对低优先级非实时数据的动态分区进行缩减，在一次调频期间将SRAM资源优先分配给高优先级数据，进一步保障高优先级数据的存储完整性和写入实时性。
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Figure CN122837756A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a data storage control method for an embedded system, and more particularly to a data storage control method for an embedded acquisition and control device for primary frequency modulation. Background Technology
[0002] In primary frequency regulation scenarios within power systems, embedded data acquisition and control devices need to simultaneously process high-frequency AD sampling data and low-priority non-real-time data used for plant maintenance. These two types of data differ in their real-time requirements and storage capacity needs.
[0003] In existing technologies, embedded systems typically use a unified cache queue with timed batch writes for data storage, without distinguishing data sources or priorities. AD sampling data and communication data share the same cache, with data sources queuing in order of arrival and being written to Flash or SD cards in a unified manner triggered by a timer. This approach is simple to implement and requires little code, but when the volume of low-priority communication data is large, high-priority AD sampling data must queue, introducing write latency in the range of milliseconds to tens of milliseconds.
[0004] Some embedded devices' real-time operating systems (RTOS) provide task-level preemptive scheduling capabilities, ensuring that high-priority control tasks receive priority CPU execution time. However, CPU task priority scheduling primarily operates at the CPU computing resource allocation level; data writing to the storage medium still requires waiting for I / O bus occupancy and Flash page programming time. While RTOS priority scheduling is effective at the computing resource level, it doesn't extend to the storage I / O resource allocation level; storage I / O is still executed serially on a first-come, first-served basis. When low-priority non-real-time data continuously occupies the Flash write queue, high-priority real-time AD sampling data still faces millisecond-level or even longer write latency, potentially leading to data loss within a single frequency modulation window. Furthermore, the storage write of high-priority data is typically handled by the CPU, resulting in high CPU resource utilization for storage tasks and impacting the execution efficiency of other control tasks. Summary of the Invention
[0005] To address the shortcomings of the prior art, this invention provides a data storage control method for an embedded acquisition and control device for primary frequency modulation, which solves the problems of uncontrollable writing delay and high risk of loss of high-priority data during primary frequency modulation, and the high CPU resource utilization of storage tasks due to CPU handling for high-priority data storage and writing.
[0006] The technical solution of the present invention is as follows:
[0007] A data storage control method for an embedded acquisition and control device for primary frequency modulation includes the following steps:
[0008] S1. The real-time sampling data collected by the AD sampling module is labeled as high-priority real-time data, and the non-real-time data obtained through the communication module is labeled as low-priority non-real-time data.
[0009] S2. Perform frequency domain analysis on the grid voltage waveform and calculate the frequency deviation rate of change RoCoF;
[0010] S3. Based on the preset buffer allocation strategy, calculate the SRAM buffer capacity required for high-priority real-time data according to the RoCoF, and dynamically divide the high-priority circular buffer in the SRAM accordingly.
[0011] S4. Write the high-priority real-time data into the high-priority circular buffer via direct DMA transfer.
[0012] S5. Based on the frequency modulation operation status, and using a preset multi-state writing strategy, asynchronously batch write the data in the high-priority circular buffer to the Flash. The multi-state writing strategy includes at least: pausing the initiation of new Flash writing requests when the frequency modulation is triggered, and performing writing in an expedited mode at a higher than normal rate when the frequency modulation is resumed.
[0013] S6. When a frequency modulation is triggered, the dynamic partition of low-priority non-real-time data in SRAM is reduced to the preset minimum reserved capacity, and the SRAM space is released for high-priority real-time data to use; when a frequency modulation is not triggered and the CPU utilization rate is lower than the preset threshold, the low-priority data is written in batches to the external storage target unit.
[0014] Furthermore, step S2 involves performing frequency domain analysis on the voltage waveform using Discrete Fourier Transform (DFT) to obtain the instantaneous frequency of the power grid. RoCoF is calculated based on the frequency difference between adjacent calculation windows:
[0015] ,
[0016] in, The instantaneous frequency of the power grid in this calculation window. The instantaneous frequency of the power grid in the previous calculation window. This is the time interval for calculating the window.
[0017] DFT frequency domain analysis can accurately obtain the instantaneous frequency of the power grid, and has stronger anti-harmonic interference capability compared with the time-domain zero-crossing detection method. Proper settings can ensure timely disturbance detection, enabling SRAM dynamic pre-allocation to start early in a frequency modulation event, thus providing a time window for advance reservation of cache space.
[0018] Furthermore, in step S2, the calculation method for the SRAM cache capacity required for high-priority real-time data is as follows:
[0019] ,
[0020] in, The scaling factor, determined by RoCoF, is based on a preset cache allocation strategy. The AD sampling frequency, This refers to the amount of data collected in a single sampling. This represents the maximum design duration of primary frequency regulation in the power grid. The set safety factor.
[0021] Furthermore, in the preset buffer allocation strategy, multiple tiers are defined based on RoCoF, with higher RoCoF values corresponding to higher tiers. The larger the value, the more severe the perturbation, until the preset expansion limit is reached. A higher RoCoF value indicates a more severe perturbation. The capacity of the SRAM cache used for high-priority real-time data caching is increased accordingly to enable dynamic configuration of storage resources on demand, avoiding resource waste or insufficiency caused by static allocation strategies.
[0022] Furthermore, the high-priority circular buffer consists of two equal-length sub-buffers and employs a ping-pong buffering mechanism.
[0023] Furthermore, the multi-state flashing strategy also includes: dividing multiple flashing strategies with different flashing rates based on the SRAM fill rate, wherein the higher the SRAM fill rate, the higher the flashing rate; and setting a fill rate threshold, wherein when the SRAM fill rate is greater than the fill rate threshold, the flashing strategy ignores pausing the initiation of new Flash flashing requests, and prioritizes performing selective precision degradation on non-critical monitoring point data before flashing at the highest flashing rate, while critical measurement point data maintains its original precision.
[0024] When storage resources are extremely scarce, the storage resources are protected in a tiered manner under extreme conditions by sacrificing the accuracy of key monitoring point data in exchange for the complete preservation of key monitoring point data; after selective degradation, the data generation rate is reduced, further alleviating the pressure on SRAM filling.
[0025] Furthermore, in the multi-state write strategy, when the SRAM fill rate is less than 50%, it is written at the normal write rate; when the SRAM fill rate is (50%, 75%), it is written at twice the normal write rate; when the SRAM fill rate is (75%, 90%), it is written at four times the normal write rate; and the fill rate threshold is 90%.
[0026] Furthermore, in step S3, when dynamically dividing the high-priority ring buffer, at the moment of a frequency modulation trigger, the high-priority ring buffer is first expanded to the corresponding preset multiple according to the RoCoF at the trigger time, and then its boundary is locked. During the duration of a frequency modulation, it is not adjusted according to the fluctuation of RoCoF; after the frequency modulation is restored, the lock is released and the dynamic adjustment capability is restored.
[0027] To avoid issues such as corrupted indexes, out-of-bounds write pointers, or data overwriting caused by repeated adjustments to the buffer boundary due to continuous fluctuations in RoCoF during a single frequency modulation operation.
[0028] Furthermore, the minimum reserved capacity is 5% to 10% of the total SRAM capacity.
[0029] Furthermore, the method includes step S7: establishing a fast index based on timestamp and grid connection point number for high-priority real-time data, establishing a regular index based on timestamp, data type and device number for low-priority non-real-time data, and realizing encrypted and secure transmission of high-priority real-time data and low-priority non-real-time data through a secure communication interface.
[0030] The fast index based on timestamps and grid connection point numbers supports millisecond-level data location during grid accident tracing, meeting the real-time requirements of the grid dispatching system for frequency regulation performance evaluation and compliance auditing; the secure communication interface ensures the confidentiality and integrity of data during transmission to the dispatching system, meeting the security protection requirements of the power monitoring system.
[0031] Compared with the prior art, the present invention has the following advantages:
[0032] By employing an SRAM cache allocation strategy based on the frequency deviation rate of change (RoCoF), sufficient cache space is reserved in advance for high-priority real-time data according to the severity of power grid disturbances, enabling predictive allocation of storage resources. Direct DMA transfer enables zero-CPU-occupancy, fast transfer of AD sampling data to SRAM, reducing write latency and CPU storage overhead. A multi-state flushing strategy is coupled with the primary frequency regulation process; in the triggered state, Flash flushing is paused to avoid contention between storage I / O and high-priority data writing, while in the recovery period, expedited flushing quickly releases cache space. Dynamic partitions for low-priority non-real-time data are reduced, and SRAM resources are preferentially allocated to high-priority data during the primary frequency regulation period, further ensuring the storage integrity and real-time write performance of high-priority data. Attached Figure Description
[0033] Figure 1 This is a flowchart illustrating the data storage control method of an embedded acquisition and control device for primary frequency modulation, as shown in the embodiment. Detailed Implementation
[0034] The present invention will be further described below with reference to embodiments, but these are not intended to limit the scope of the invention.
[0035] This embodiment uses a 10kV distributed photovoltaic power station acquisition and control device as an example to illustrate the data storage control method of the embedded acquisition and control device for primary frequency regulation according to the present invention. It needs to acquire current and voltage data from three grid-connected points and communicate with the photovoltaic power station's backend system. The specific system configuration is as follows: a 16-bit high-precision AD chip; three-phase current and line voltage data for the three grid-connected points; 32MB onboard SRAM + 64MB onboard Flash; an 8GB industrial-grade SD card; an ARM Cortex-M series MCU with a main frequency of 480MHz and a built-in DMA controller. At a sampling rate of 2kHz and 36 bytes per sample, the data volume is 72KB / s. After reserving 5% (1.6MB) of the 32MB SRAM for low-priority non-real-time data as the minimum reserved capacity, approximately 30.4MB is available for high-priority data, theoretically covering approximately 432 seconds of continuous sampling data (approximately 400 seconds after deducting protocol stack buffers, system stacks, and other miscellaneous overhead), which is sufficient to cover typical and most known primary frequency regulation scenarios.
[0036] Please combine Figure 1 As shown, the specific process of the data storage control method is as follows:
[0037] S1. Data Classification and Priority Calibration: Real-time current and voltage sampling data acquired through the AD analog-to-digital converter module are calibrated as high-priority real-time data, with a sampling frequency of 2kHz. Operating condition data and maintenance data acquired through the communication module are calibrated as low-priority non-real-time data, with a communication cycle of 10s / time.
[0038] S2. Frequency Monitoring: Perform frequency domain analysis on the grid voltage waveform and calculate the frequency deviation rate of change (RoCoF). The AD-sampled voltage waveform is subjected to Discrete Fourier Transform (DFT), with a 512-point sampling window determined based on a trade-off between MCU computing resource constraints and frequency detection accuracy requirements, corresponding to a sampling window of approximately 256ms. This ensures sufficient frequency resolution while completing the DFT calculation within a 500ms calculation period. The instantaneous grid frequency is obtained with a calculation period of 500ms. The frequency deviation change rate RoCoF is calculated based on the frequency difference between adjacent calculation windows.
[0039] ,
[0040] in, The instantaneous frequency of the power grid in this calculation window. The instantaneous frequency of the power grid in the previous calculation window. The time interval for the calculation window. In this embodiment, the 512-point DFT window is determined based on a trade-off between MCU computing resource constraints and frequency detection accuracy requirements, corresponding to a sampling window of approximately 256ms. This ensures that the DFT operation is completed within a 500ms calculation cycle while providing sufficient frequency resolution.
[0041] S3, SRAM Dynamic Pre-allocation Execution: Based on the preset cache allocation strategy, according to the RoCoF calculated in S2, the SRAM cache capacity required for high-priority real-time data is calculated, and a corresponding high-priority circular buffer is dynamically partitioned in the SRAM.
[0042] The buffer allocation strategy is configured based on the target power grid characteristics and loaded during system initialization. The buffer allocation strategy determines the power grid disturbance level based on the RoCoF (Route of Coefficients of Frequency) and accordingly determines the capacity of the high-priority data SRAM buffer. The disturbance level classification can be determined based on the Chinese power grid primary frequency regulation standard (GB / T 40595-2021) and the RoCoF tolerance capability of distributed generation (IEEE 1547-2018). In this embodiment, specifically:
[0043] When RoCoF (Hz / s) < 0.1, the disturbance level is Level I (normal), and the corresponding high-priority ring buffer is divided according to the design baseline value;
[0044] When RoCoF (Hz / s) is [0.1, 0.5], the disturbance level is Level II (note), and the corresponding high-priority ring buffer is expanded to k (1.5) times the design reference value;
[0045] When RoCoF (Hz / s) is (0.5, 1.0], the disturbance level is Level III (alert), and the corresponding high-priority ring buffer is expanded to k (2.0) times the design reference value;
[0046] When RoCoF (Hz / s) is (1.0, 2.0], the disturbance level is IV (severe), and the corresponding high-priority ring buffer is expanded to k (3.0) times the design reference value;
[0047] When RoCoF (Hz / s) > 2.0, the disturbance level is V (extreme), and the corresponding high-priority ring buffer is expanded to k (3.0) times the design baseline value.
[0048] In the above-mentioned preset cache allocation strategy, the higher the RoCoF value, the better. The larger the expansion, the higher the limit will be until it reaches the preset expansion limit (3.0 times in this embodiment); the above expansion is a one-time pre-allocation action at the moment of frequency modulation triggering. After the expansion is completed, the boundary of the high-priority ring buffer is locked and will no longer be adjusted with RoCoF fluctuations during the frequency modulation period.
[0049] Design baseline value The final adjusted size of the high-priority circular buffer is
[0050] ,
[0051] in, The AD sampling frequency, This refers to the amount of data collected in a single sampling. The maximum design duration for primary frequency regulation of the power grid (calibrated based on the frequency regulation control strategy and historical operating data of the target power grid). A safety factor is set (which can be 1.2 to 1.5). In this embodiment, 2000Hz It is 36B. For 30 seconds, It is 1.3.
[0052] When dynamically partitioning a high-priority circular buffer, the buffer is first expanded to the corresponding multiple based on the disturbance level detected at the trigger moment. Then, its boundaries are locked. During a single frequency modulation period, even if RoCoF fluctuates near the level boundary, the buffer boundaries are not adjusted again, preventing repeated buffer reallocation from causing index corruption, write pointer out-of-bounds errors, or data overwriting of written data. After the frequency modulation resumes, the lock is released, restoring the ability to dynamically adjust according to RoCoF. During a single frequency modulation trigger, the dynamic partition of low-priority non-real-time data in SRAM is reduced to a preset minimum reserved capacity, freeing up SRAM space for high-priority real-time data. The minimum reserved capacity is 5% to 10% of the total SRAM capacity; in this embodiment, 5% is used, meaning 1.6 MB is reserved as the minimum reserved capacity. The remaining approximately 12 MB is reserved for basic memory and flexible reserves required for system operation (including protocol stack buffers, system stack and dynamic memory, and flexible expansion reserves for high-priority buffers).
[0053] S4. High-priority real-time data is written to a high-priority circular buffer via direct DMA transfer. The buffer uses a ping-pong buffering mechanism, setting up two equal-length sub-buffers for alternating writing. When the buffer is full, the buffer is switched, and the flash engine asynchronously writes the full buffer to Flash, ensuring that no data is lost during the switching process.
[0054] S5. The background flashing engine, based on the frequency modulation operation status and a preset multi-state flashing strategy, asynchronously batch-writes data from the high-priority circular buffer to Flash. The multi-state flashing strategy includes: pausing new Flash flashing requests when a frequency modulation is triggered to avoid I / O contention with high-priority data writing; performing flashing at a higher-than-normal rate when a frequency modulation resumes, prioritizing the release of SRAM buffer space; and performing batch flashing according to a preset standard cycle under normal conditions. Additionally, multiple flashing strategies with different write rates are implemented based on the SRAM fill rate, with higher fill rates resulting in higher write rates. A fill rate threshold is also set; when the SRAM fill rate exceeds this threshold, the strategy of pausing new Flash flashing requests is ignored, and non-critical monitoring point data is selectively downgraded before being flashed at the highest write rate, while critical monitoring point data retains its original accuracy. Specifically, this multi-state flashing strategy based on fill rate is as follows:
[0055]
[0056] 90% is the critical fill rate threshold. The multi-state write strategy and the SRAM fill rate-based write strategy described above are two parallel operations. Pausing Flash write during a single frequency-triggered state may cause the SRAM fill rate to continue to rise. When the fill rate reaches the critical threshold, selective precision degradation is executed first to reduce the data generation rate, and its priority is higher than the trigger-state write pause strategy.
[0057] In this embodiment, in normal mode, 7.2KB is read from SRAM and written to Flash (approximately 30 256-byte pages) every 100ms. During the page programming wait period, the CPU can perform other tasks. In the triggered mode (absolute frequency deviation > 0.2 Hz), writing is paused after the current page programming is completed. In the recovery period (absolute frequency deviation ≤ 0.15 Hz and lasting more than 3 seconds), writing is performed in expedited mode at 25ms / time, increasing the rate to 4 times that of normal mode; after one complete frequency adjustment recovery, the buffer lock is released, and dynamic adjustment is allowed again. In the emergency mode (SRAM fill rate > 90%), selective accuracy degradation is performed on non-critical monitoring channels, reducing the sampling rate from 2kHz to 1kHz, reducing the data volume by 50%, while maintaining the original accuracy of critical measurement points, and writing to Flash at the maximum rate.
[0058] S6. Low-priority non-real-time data is cached to a low-priority dynamic partition in SRAM. Under normal conditions, the dynamic partition maintains a default capacity of 12.8MB. During a frequency modulation trigger, the dynamic partition of low-priority non-real-time data in SRAM is reduced to a preset minimum retention capacity, i.e., reduced to 1.6MB. Any excess is discarded or communication flow control is triggered, freeing up SRAM space for high-priority real-time data. If no frequency modulation is triggered and the CPU utilization rate is below a preset threshold (30% in this embodiment), low-priority data is written in batches to the external storage target unit (SD card or Flash).
[0059] S7. Establish a fast index based on timestamps and grid connection point numbers for high-priority real-time data to meet rapid retrieval requirements. Establish a regular index based on timestamps, data types, and device numbers for low-priority non-real-time data, and achieve encrypted and secure transmission of high-priority real-time data and low-priority non-real-time data through a secure communication interface.
[0060] Furthermore, it should be noted that the data storage control method of the embedded acquisition and control device for primary frequency regulation embodied in the above embodiments can be applied to various primary regulation scenarios, such as wind farm converter control devices. High-priority real-time data includes converter IGBT temperature and DC bus voltage (sampling frequency 5 kHz), while low-priority non-real-time data includes wind speed and power generation statistics (communication cycle 30 s). When a grid voltage drop triggers a low-voltage ride-through (LVRT), the same storage strategy as primary frequency regulation is implemented: the duration of LVRT is estimated based on the voltage drop characteristics, and SRAM capacity is dynamically allocated accordingly. Flash writing is paused during the triggering period, and accelerated writing is performed during the recovery period. This platform needs to be equipped with ≥16 MB SRAM to support long-term disturbance caching at a sampling rate of 5 kHz. Low-voltage ride-through and primary frequency regulation have similar characteristics at the storage control level, both being short-term high-density data influx events. The duration can be estimated by early signals such as RoCoF or voltage drop depth, and the data storage control method can be directly transferred and applied.
Claims
1. A data storage control method for an embedded acquisition and control device for primary frequency modulation, characterized in that, Includes the following steps: S1. The real-time sampling data collected by the AD sampling module is labeled as high-priority real-time data, and the non-real-time data obtained through the communication module is labeled as low-priority non-real-time data. S2. Perform frequency domain analysis on the grid voltage waveform and calculate the frequency deviation rate of change RoCoF; S3. Based on the preset buffer allocation strategy, calculate the SRAM buffer capacity required for high-priority real-time data according to the RoCoF, and dynamically divide the high-priority circular buffer in the SRAM accordingly. S4. Write the high-priority real-time data into the high-priority circular buffer via direct DMA transfer. S5. Based on the frequency modulation operation status and the preset multi-state write strategy, asynchronously write the data in the high-priority ring buffer to Flash in batches. The multi-state flashing strategy includes at least the following: when a frequency modulation is triggered, the initiation of a new Flash flashing request is paused, and when a frequency modulation is resumed, the flashing is performed in an expedited mode at a higher than normal rate. S6. When a frequency modulation is triggered, the dynamic partition of low-priority non-real-time data in SRAM is reduced to the preset minimum reserved capacity, and the SRAM space is released for high-priority real-time data to use; when a frequency modulation is not triggered and the CPU utilization rate is lower than the preset threshold, the low-priority data is written in batches to the external storage target unit.
2. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, Step S2 involves performing frequency domain analysis on the voltage waveform using Discrete Fourier Transform (DFT) to obtain the instantaneous frequency of the power grid. RoCoF is calculated based on the frequency difference between adjacent calculation windows: ， in, The instantaneous frequency of the power grid in this calculation window. The instantaneous frequency of the power grid in the previous calculation window. This is the time interval for calculating the window.
3. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, In step S2, the SRAM cache capacity required for high-priority real-time data is calculated as follows: ， in, The scaling factor, determined by RoCoF, is based on a preset cache allocation strategy. The AD sampling frequency, This refers to the amount of data collected in a single sampling. This represents the maximum design duration of primary frequency regulation in the power grid. The set safety factor.
4. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 3, characterized in that, In the preset buffer allocation strategy, multiple tiers are divided based on RoCoF, with higher RoCoF values corresponding to higher tiers. The larger it gets, the more it will expand until it reaches the preset expansion limit.
5. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, The high-priority circular buffer consists of two equal-length sub-buffers and employs a ping-pong buffering mechanism.
6. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, The multi-state flashing strategy also includes: dividing the flashing strategy into multiple different flashing rates based on the SRAM fill rate, with the higher the SRAM fill rate, the higher the flashing rate; and setting a fill rate threshold, whereby when the SRAM fill rate is greater than the fill rate threshold, the flashing strategy ignores pausing the initiation of new Flash flashing requests, prioritizes selective accuracy degradation for non-critical monitoring point data, and then flashes at the highest flashing rate, while critical measurement point data maintains its original accuracy.
7. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 6, characterized in that, In the multi-state write strategy, when the SRAM fill rate is less than 50%, it is written at the normal write rate; when the SRAM fill rate is (50%, 75%), it is written at twice the normal write rate; when the SRAM fill rate is (75%, 90%), it is written at four times the normal write rate; the fill rate threshold is 90%.
8. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, In step S3, when dynamically dividing the high-priority ring buffer, at the time of a frequency modulation trigger, the high-priority ring buffer is expanded to a preset multiple corresponding to the RoCoF at the trigger time, and its boundary is locked. During the duration of a frequency modulation, it is not adjusted according to the fluctuation of RoCoF. After the frequency modulation is restored, the lock is released and the dynamic adjustment capability is restored.
9. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, The minimum reserved capacity is 5% to 10% of the total SRAM capacity.
10. The data storage control method for an embedded acquisition and control device for primary frequency modulation according to claim 1, characterized in that, The method further includes: step S7, establishing a fast index based on timestamp and grid connection point number for high-priority real-time data, establishing a regular index based on timestamp, data type and device number for low-priority non-real-time data, and realizing encrypted and secure transmission of high-priority real-time data and low-priority non-real-time data through a secure communication interface.