Scheduling method and related apparatus
Patent Information
- Application Number
- CN202510370488.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2026-09-29
Smart Images
Figure CN122837997A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of terminals, and more particularly to a scheduling method and related apparatus. Background Technology
[0002] With the development of terminal technology, users are using electronic devices (such as smartphones, smartwatches, and smart bracelets) more and more frequently to handle daily tasks. At the same time, to meet users' growing demands, the performance of electronic devices is becoming increasingly powerful. Among these, the performance of the central processing unit (CPU) is one of the important indicators for measuring the performance of electronic devices. Therefore, how to rationally schedule the CPU in electronic devices to improve task processing efficiency and reduce CPU power consumption has become an urgent problem to be solved. Summary of the Invention
[0003] This application provides a scheduling method and related apparatus that enables electronic devices to process tasks in a timely manner, improves response speed, and saves power consumption and CPU resource consumption of electronic devices.
[0004] In a first aspect, this application provides a scheduling method, comprising: an electronic device creating a first thread and a second thread; the electronic device scheduling a first core in a central processing unit (CPU) to run the first thread; the electronic device recording a first resource transfer relationship of the first thread, wherein the first resource transfer relationship is used to instruct the first thread to send its resources to one or more threads; the electronic device determining a first system idle percentage based on the idle time of multiple CPU cores, wherein the multiple CPU cores include the first core; when the second thread is awakened by the first thread, and a synchronization relationship is determined between the second thread and the first thread based on the first resource transfer relationship, and the first system idle percentage is greater than or equal to a first preset value, the electronic device scheduling the first core to run the second thread.
[0005] In one possible implementation, the electronic device determines a first system idle percentage based on the idle time of multiple CPU cores, including: the electronic device calculating a second system idle percentage for the current period based on the idle time of the multiple CPU cores every first specified time interval. The electronic device determines the first system idle percentage based on the current frame rate and the second system idle percentage.
[0006] In one possible implementation, the electronic device calculates a second system idle percentage value for the current period based on the idle time of the plurality of CPU cores every first specified time interval, including: the electronic device determines the second system idle percentage value based on the idle time of the plurality of CPU cores and the product of the number of the plurality of CPU cores and the first specified time interval.
[0007] In one possible implementation, the electronic device determines the first system idle ratio based on the current frame rate and the second system idle ratio, including: the electronic device determining the average of the system idle ratios over the most recent i periods. Here, the value of i is related to the current frame rate, and the system idle ratios over the most recent i periods include the second system idle ratio. The electronic device determines the average of the system idle ratios over the most recent i periods as the first system idle ratio.
[0008] In one possible implementation, when the second thread is awakened by the first thread, and a synchronization relationship is determined between the second thread and the first thread based on the first resource transfer relationship, and the idle percentage of the first system is greater than or equal to a first preset value, the electronic device schedules the first core to run the second thread. This includes: when the second thread is awakened by the first thread, the electronic device determines, based on the first resource transfer relationship, that the first thread is currently only sending its resources to the second thread, and the electronic device determines that the first thread enters a sleep state after waking up the second thread; in this case, the electronic device determines that a synchronization relationship exists between the first thread and the second thread. When the first thread and the second thread are synchronized, and the idle percentage of the first system is greater than or equal to the first preset value, the electronic device schedules the first core to run the second thread.
[0009] In one possible implementation, the plurality of CPU cores further includes the second core. The method further includes: when the second thread is awakened, if the electronic device determines, based on the first resource transfer relationship, that the second thread and the first thread do not have a synchronization relationship, or if the first system idle percentage is less than a first preset value, the electronic device schedules the second core to run the second thread, wherein the second core and the first core are not the same.
[0010] In one possible implementation, the second core is either an idle core, or a core whose running task has a lower priority than the second thread, or a core that has previously run the second thread.
[0011] In a second aspect, this application provides an electronic device comprising: one or more processors and a memory. The memory is coupled to the one or more processors and is used to store computer program code, the computer program code including computer instructions, which the one or more processors invoke to cause the electronic device to perform a method as described in any of the possible implementations of the first aspect above.
[0012] Thirdly, this application provides a chip system applied to an electronic device, the chip system including one or more processors, the processors being configured to invoke computer instructions to cause the electronic device to perform a method as described in any of the possible implementations of the first aspect above.
[0013] Fourthly, this application provides a computer-readable storage medium including instructions that, when executed on an electronic device, cause the electronic device to perform a method as described in any of the possible implementations of the first aspect above.
[0014] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, causes the electronic device to perform the method as described in any of the possible implementations of the first aspect above. Attached Figure Description
[0015] Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application;
[0016] Figure 2A A timing diagram illustrating an image frame rendering task provided in an embodiment of this application;
[0017] Figures 2B-2C A schematic diagram of the state of multiple CPUs executing tasks provided in an embodiment of this application;
[0018] Figure 3 This is a schematic flowchart illustrating a scheduling method provided in an embodiment of this application.
[0019] Figure 4A This diagram illustrates a specific example of an inter-thread wake-up relationship provided in an embodiment of this application.
[0020] Figures 4B-4C A schematic diagram illustrating another specific example of an inter-thread wake-up relationship provided in this application embodiment;
[0021] Figure 4D A schematic diagram illustrating how an electronic device 100 acquires and records wake-up relationships, as provided in an embodiment of this application;
[0022] Figure 5A A flowchart illustrating a method for determining the system idle percentage as provided in an embodiment of this application;
[0023] Figure 5B A schematic diagram illustrating system idle percentage statistics provided in an embodiment of this application;
[0024] Figure 6 A schematic diagram of the software architecture modules of an electronic device 100 provided in an embodiment of this application;
[0025] Figure 7 This is a schematic diagram illustrating the effect of a scheduling method provided in an embodiment of this application. Detailed Implementation
[0026] The technical solutions in the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the word "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.
[0027] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.
[0028] Figure 1 This is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of this application.
[0029] like Figure 1 As shown, the electronic device 100 can be a mobile phone, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, cellular phone, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, wearable device, in-vehicle device, smart home device and / or smart city device. The embodiments of this application do not impose any special restrictions on the specific type of the electronic device 100.
[0030] like Figure 1 As shown, the electronic device 100 may include a processor 101, a memory 102, a wireless communication module 103, a display screen 104, a sensor module 105, an audio module 106 (optional), a speaker 107 (optional), and a microphone 108 (optional). These modules can be connected via a bus.
[0031] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0032] Processor 101 may include one or more processor units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.
[0033] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.
[0034] The processor 101 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 101 is a cache memory. This memory can store instructions or data that the processor 101 has just used or that are used repeatedly. If the processor 101 needs to use the instruction or data again, it can directly retrieve it from the memory. This avoids repeated accesses, reduces the waiting time of the processor 101, and thus improves the efficiency of the system.
[0035] In some embodiments, the processor 101 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.
[0036] In this embodiment, processor 101 can be a multi-core processor, meaning it can have multiple cores, such as core 1, core 2, core 3, etc. Typically, processor 101 can have 4 cores, hence a quad-core processor; or processor 101 can have 6 cores, hence a hexa-core processor; or processor 101 can have 8 cores, hence an octa-core processor. This application does not limit the specific number of cores in processor 101.
[0037] When processor 101 has multiple cores, the cores can be categorized into large cores, medium cores, and small cores based on their performance and computing power. Large cores typically have higher clock speeds and stronger computing power, suitable for handling high-performance tasks such as running large applications and games with high graphics requirements. Small cores are designed for low power consumption and high efficiency, capable of handling low-load tasks such as browsing the web and answering phone calls. Medium cores have performance and computing power between large and small cores. In subsequent embodiments, CPU1 refers to core 1 of the CPU, CPU2 refers to core 2 of the CPU, CPU3 refers to core 3 of the CPU, and so on.
[0038] The memory 102 is coupled to the processor 101 and is used to store various software programs and / or multiple sets of instructions. In specific implementations, the memory 102 may include volatile memory, such as random access memory (RAM); it may also include non-volatile memory, such as ROM, flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 102 may also include combinations of the above types of memory. The memory 102 may also store some program code so that the processor 101 can call the program code stored in the memory 102 to implement the implementation method of the present application embodiment in the electronic device 100. The memory 102 may store an operating system, such as uCOS, VxWorks, RTLinux, or other embedded operating systems.
[0039] The wireless communication module 103 can provide solutions for wireless communication applications on electronic devices 100, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, etc.
[0040] The wireless communication module 103 can be one or more devices integrating at least one communication processing module. The wireless communication module 103 receives electromagnetic waves via an antenna, modulates and filters the electromagnetic wave signal, and sends the processed signal to the processor 101. The wireless communication module 103 can also receive signals to be transmitted from the processor 101, modulate and amplify them, and then convert them into electromagnetic waves for radiation via the antenna. The electronic device 100 can communicate via the Bluetooth communication module in the wireless communication module 103. Figure 1(Not shown) The device transmits signals to detect or scan devices near electronic device 100 and establishes a wireless communication connection with those devices to transmit data. The Bluetooth communication module can provide solutions for one or more Bluetooth communication methods, including basic rate / enhanced data rate (BR / EDR) or Bluetooth Low Energy (BLE).
[0041] The display screen 104 can be used to display images, videos, etc. The display screen 104 may include a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini LED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include one or N display screens 104, where N is a positive integer greater than 1.
[0042] Sensor module 105 may include a gravity sensor ( Figure 1 (not shown in the image) and touch sensor ( Figure 1 (Not shown in the image). A gravity sensor can be used to detect the magnitude of acceleration in various directions (generally the x, y, and z axes), the magnitude and direction of gravity, and displacement along the direction of gravity in the electronic device 100. A touch sensor, also known as a "touch device," can be placed on the display screen 104. The touch sensor and the display screen 104 together form a touchscreen, also called a "touch screen." The touch sensor can be used to detect touch operations applied to or near it.
[0043] The audio module 106 can be used to convert digital audio information into analog audio signal output, and can also be used to convert analog audio input into digital audio signal. The audio module 106 can also be used to encode and decode audio signals. In some embodiments, the audio module 106 can also be disposed in the processor 101, or some functional modules of the audio module 106 can be disposed in the processor 101.
[0044] The speaker 107, also known as a "loudspeaker," is used to convert audio electrical signals into sound signals. The electronic device 100 can listen to music or make hands-free calls through the speaker 107.
[0045] Microphone 108, also known as a "microphone" or "voice transducer," is used to collect sound signals from the environment surrounding the electronic device. It then converts these sound signals into electrical signals, processes them (e.g., analog-to-digital conversion), and obtains a digital audio signal that can be processed by the processor 101 of the electronic device. When making a phone call or sending a voice message, the user can speak by bringing their mouth close to the microphone 108, inputting the sound signal into the microphone 108. The electronic device 100 may have at least one microphone 108. In some embodiments, the electronic device 100 may have two microphones 108, which, in addition to collecting sound signals, can also perform noise reduction. In other embodiments, the electronic device 100 may have three or more microphones 108, enabling sound signal collection, noise reduction, sound source identification, and directional recording, among other functions.
[0046] It should be noted that, Figure 1 The electronic device 100 shown is merely an illustrative explanation of the hardware structure of the electronic device provided in this application and does not constitute a specific limitation on this application.
[0047] During the operation of electronic device 100, the CPU always processes various tasks, and electronic device 100 also allocates CPU cores reasonably to each task according to the task priority and resource requirements. In some application scenarios, graphics processing tasks, audio processing tasks, and image frame rendering tasks can be defaulted to high-priority tasks (e.g., real-time tasks).
[0048] Figure 2A This is a timing diagram of an image frame rendering task provided in an embodiment of this application.
[0049] like Figure 2A As shown, the image frame rendering task is controlled by the vertical synchronization (Vsync) signal. That is to say, when each Vsync signal arrives, a core in the CPU can be used to render an image frame or the display screen can display the processed image frame.
[0050] For example, when Vsync signal 1 arrives at time t1, electronic device 100 can display image frame A on the screen, and draw, render and synthesize image frame B through the core in the CPU, and store image frame B in the buffer before Vsync signal 2 arrives.
[0051] When Vsync signal 2 arrives at time t2, electronic device 100 can display image frame B on the screen based on the data of image frame B in the buffer, and draw, render and synthesize image frame C through the core in the CPU, and store image frame C in the buffer before Vsync signal 3 arrives.
[0052] When Vsync signal 3 arrives at time t3, electronic device 100 can display image frame C on the screen based on the data of image frame C in the buffer, and draw, render and synthesize image frame D through the core in the CPU, and store image frame D in the buffer before Vsync signal 3 arrives.
[0053] When Vsync signal 4 arrives at time t4, electronic device 100 can display image frame D on the screen based on the data of image frame D in the buffer, and draw, render and composite image frame D through the CPU core, and store image frame D in the buffer before Vsync signal 5 arrives. Generally, the interval between each Vsync signal is 16.6ms.
[0054] Generally, when the electronic device 100 needs to process high-priority tasks with high latency requirements, such as image rendering tasks, and the CPU in the electronic device 100 includes multiple cores (e.g., 4 cores, 8 cores, etc.), in order to balance the load of each CPU core, the electronic device 100 will first wake up the CPU core in the idle state (i.e., the idle state) to execute the task.
[0055] For example, when CPU cores 0 through 6 are all processing tasks, while CPU core 7 is not processing tasks and is in an idle state, electronic device 100 will prioritize waking up CPU core 7 to execute a high-priority task.
[0056] However, under this scheduling method, if multiple small and medium cores have a lot of idle time and sufficient performance, but the electronic device 100 still prioritizes waking up the idle large cores to process tasks, this will cause the large cores to only process a short high-priority task after being woken up and then enter the idle state again, which will increase the power consumption of the electronic device 100 and the various cores in the CPU cannot be used reasonably.
[0057] Figures 2B-2C This is a schematic diagram illustrating the state of multiple cores in a CPU executing tasks, provided in an embodiment of this application.
[0058] like Figure 2B and Figure 2CAs shown, this CPU has 8 cores. CPU0 is core 0, CPU1 is core 1, CPU2 is core 2, CPU3 is core 3, CPU4 is core 4, CPU5 is core 5, CPU6 is core 6, and CPU7 is core 7. When a video application starts, CPUs 1 through 6 have ample idle time and sufficient performance to handle the threads related to the video application startup. However, in the above scheduling method, the electronic device 100 still wakes up the large core CPU7, which is in an idle state, to handle the threads related to the video application startup. After being woken up, the large core CPU7 only handles the very short video application startup threads before returning to an idle state. This not only increases the power consumption of the electronic device 100, but also prevents the efficient use of the sufficiently powerful small and medium-sized CPU cores on the electronic device 100.
[0059] Therefore, this application provides a scheduling method in which the electronic device 100 can record the resource transfer relationship between tasks and identify the wake-up relationship between tasks. Based on the above-mentioned resource transfer relationship and wake-up relationship, the electronic device 100 determines the synchronization relationship between tasks. The electronic device 100 can calculate the idle percentage of the system based on the idle time of multiple CPU cores every specified period T1. If the idle percentage of the system is greater than or equal to a preset first value, the electronic device 100 can schedule the same CPU for two tasks with a synchronization relationship. In this way, not only can the electronic device 100 process tasks in a timely manner and improve the response speed, but it can also save the power consumption and CPU resource overhead of the electronic device 100.
[0060] In this context, a wake-up relationship refers to a relationship between task A and task B if task A can trigger task B to run (i.e., task B is woken up by task A). A resource transfer relationship refers to a relationship between task A and task B if task B can receive resources from task A for processing. A synchronization relationship refers to a relationship between task A and task B if task A has a wake-up relationship, task A currently only has a resource transfer relationship with task B (i.e., only task B receives resources from task A), and task A will enter a sleep state after waking up task B. The "task" described in this embodiment may include threads, processes, etc., as described later.
[0061] Figure 3 This is a schematic diagram illustrating the specific process of a scheduling method provided in an embodiment of this application.
[0062] like Figure 3 As shown, the specific process of this scheduling method may include:
[0063] S301. Electronic device 100 creates a first thread and a second thread.
[0064] Specifically, when receiving and responding to an operation to launch a first application, the electronic device 100 can launch the first application and create a first thread and a second thread related to the first application. The first thread and the second thread can be used to run the relevant functions of the first application.
[0065] S302. Electronic device 100 schedules CPU1 to run the first thread.
[0066] CPU1 refers to core 1 on the CPU.
[0067] The type of core 1 can be small core, medium core or large core, and this application does not impose any restrictions.
[0068] S303. Electronic device 100 records the first resource transfer relationship of the first thread. The first resource transfer relationship is used to instruct the first thread to send its resources to one or more threads.
[0069] Specifically, when electronic device 100 runs the first thread, electronic device 100 can insert a stub function (which can be simply referred to as a stub) for the first thread. This stub can be used to obtain the first resource transfer relationship of the first thread.
[0070] Here, a stub refers to specific code inserted for the first thread to obtain relevant information (in this embodiment, this refers to the first resource transfer relationship, etc.) or monitor program execution during program runtime. The specific implementation will be described in detail in subsequent embodiments and will not be repeated here.
[0071] S304. Electronic device 100 determines the system idle percentage based on the idle time of multiple CPU cores.
[0072] Specifically, the electronic device 100 can calculate the system idle percentage based on the idle time of multiple CPU cores every specified time interval T1. This system idle percentage can be used to indicate the overall load status of the multiple CPU cores. The specific implementation will be described in detail in subsequent embodiments and will not be repeated here.
[0073] S305. When the first thread wakes up the second thread to run, the electronic device 100 determines whether the system idle percentage value is greater than or equal to the first preset value, and determines whether the first thread and the second thread have a synchronization relationship based on the first resource transfer relationship.
[0074] Preferredly, the first preset value can be 50%, that is, when the system idle percentage is greater than or equal to 50%, it indicates that multiple CPU cores are generally in a light or medium load state (i.e., the system is in a light or medium load state); when the system idle percentage is less than 50%, it indicates that multiple CPU cores are generally in a heavy load state (i.e., the system is in a heavy load state). However, this is not a limitation; the first preset value can also be other values, and this application does not impose any restrictions.
[0075] S306. When the system idle percentage is greater than or equal to the first preset value, and the first thread and the second thread have a synchronous relationship, the electronic device 100 schedules the CPU1 to run the second thread.
[0076] Specifically, when the system idle percentage is greater than or equal to the first preset value, the system is in a light or medium load state.
[0077] When the first thread wakes up the second thread, the electronic device 100 can determine that the first and second threads have a wake-up relationship. Furthermore, based on the first resource transfer relationship, the electronic device 100 determines that the first thread will only transfer its resources to the second thread, and based on the stub corresponding to the first thread, it detects that the first thread wakes up the second thread and then enters a sleep state. Therefore, the electronic device 100 can determine that the first and second threads have a synchronization relationship. Thus, the electronic device 100 can schedule the CPU1 used to run the first thread to run the second thread.
[0078] In this way, since the system is under light or medium load, CPU1 will likely have sufficient resources and capacity to run the second thread. Furthermore, because the first and second threads are synchronized, the resources on CPU1 used for the first thread can also be used for the second thread, eliminating the need to schedule other idle CPUs. This not only ensures smooth operation of the second thread but also saves 100% of the power consumption of the electronic device.
[0079] S307. When the system idle percentage is less than a first preset value, or when it is determined that the first thread and the second thread are not synchronized, the electronic device 100 schedules CPU2 to run the second thread. CPU2 and CPU1 are not the same.
[0080] Specifically, when the first thread wakes up the second thread, the electronic device 100 can determine that the first thread and the second thread have a wake-up relationship. However, if the electronic device 100 determines, based on the first resource transfer relationship, that the first thread is not simply transferring (i.e., sending) its resources to the second thread, or that the first thread is not transferring its resources to the second thread, or if, based on the stub corresponding to the first thread, it detects that the first thread does not enter a sleep state after waking up the second thread (i.e., the first thread and the second thread are running synchronously in time), the electronic device 100 can determine that the first thread and the second thread do not have a synchronous relationship. Therefore, the electronic device 100 can schedule CPU2 to run the second thread.
[0081] Specifically, when the system idle percentage is less than a first preset value, the system is in a heavily loaded state, and CPU1 is unlikely to have sufficient resources and capabilities to run the second thread. Therefore, electronic device 100 can schedule CPU2 to run the second thread.
[0082] CPU2 is different from CPU1. Electronic device 100 can schedule an idle CPU (which can be CPU2, i.e., core 2 in the CPU) to run the second thread, or schedule a CPU (which can be CPU2) whose task has a lower priority than the second thread to run the second thread, or schedule a CPU (which can be CPU2) that previously ran the second thread to run the current second thread. In other words, this application does not restrict how the CPU core used to run the second thread is scheduled.
[0083] In one possible implementation, when the system idle percentage is less than a first preset value, the system is in a heavily loaded state, and multiple tasks compete fiercely for CPU scheduling. Electronic device 100 can determine whether the priority of the second thread is higher than that of other threads currently competing for CPU1. If the priority of the second thread is higher than that of other threads currently competing for CPU1, electronic device 100 can schedule CPU1 to run the second thread; if the priority of the second thread is lower than that of other threads currently competing for CPU1, electronic device 100 can schedule CPU2 to run the second thread. The selection of CPU2 can be referred to the above explanation and will not be repeated here.
[0084] In one possible implementation, when the system idle percentage is greater than or equal to a first preset value and the first thread and the second thread are synchronized, the electronic device 100 can determine the load state of CPU1. When CPU1 is under light load, the electronic device 100 can schedule CPU1 to run the second thread. When CPU1 is under heavy load, the electronic device 100 can schedule an idle CPU core to run the second thread, or query the load state of other non-idle CPUs. If CPU3 is found to be under light load and the priority of the second thread is higher than that of the thread on CPU3, the electronic device 100 can schedule CPU3 to run the second thread.
[0085] Furthermore, the implementation method by which the electronic device 100 determines the synchronization relationship between the first thread and the second thread is described in detail:
[0086] Specifically, when electronic device 100 runs thread A, it can insert a stub for thread A. This stub can obtain the resource transfer relationship of thread A (e.g., sending resources from thread A to thread B). Then, when thread A wakes up thread B, electronic device 100 determines, based on the resource transfer relationship of thread A, that thread A only sends its own resources to thread B, and through the stub corresponding to thread A, that thread A enters a sleep state after waking up thread B. Electronic device 100 can determine that thread A and thread B have a synchronization relationship. Electronic device 100 can record the synchronization relationship between thread A and thread B in the kernel's first record table (i.e., the kernel's reserved space).
[0087] In this embodiment of the application, thread A may refer to the first thread and thread B may refer to the second thread.
[0088] Figure 4A This diagram illustrates a specific example of an inter-thread synchronization relationship provided in an embodiment of this application.
[0089] like Figure 4A As shown, the first application is For example, the main thread aweme22386 can wake up the child thread Thread-222426 to run, and the main thread aweme22386 enters a sleep state; after the child thread Thread-22426 runs for a period of time, the child thread Thread-22426 can wake up the main thread aweme22386 to run, and the child thread Thread-22426 enters a sleep state; after the main thread aweme22386 runs for a period of time, it can wake up the child thread Thread-32427 to run, and the main thread aweme22386 enters a sleep state; after the child thread Thread-322427 runs for a period of time, the child thread Thread-322427 can wake up the main thread aweme22386 to run, and the child thread Thread-322427 enters a sleep state.
[0090] It can be seen that there is a wake-up relationship between the main thread aweme22386, the child thread Thread-2 22426, and the child thread Thread-3 22427. In terms of time logic, there is a sequential execution order, that is, one thread wakes up the next thread to run before entering the sleep state. The time difference between the thread used to wake up entering the sleep state and the thread being woken up being scheduled to run on the CPU is usually small.
[0091] Taking the main thread aweme22386 and the child thread Thread-2 22426 as an example. When the main thread aweme22386 runs, the electronic device 100 can insert a stub for the main thread aweme22386. This stub can obtain the resource transfer relationship of the main thread aweme22386. Then, when the main thread aweme22386 wakes up the child thread Thread-2 22426, the electronic device 100 determines based on the resource transfer relationship of the main thread aweme22386 that the main thread aweme22386 only sends its own resources to the child thread Thread-2 22426, and through the stub corresponding to the main thread aweme22386, it determines that after waking up the child thread Thread-2 22426, the main thread aweme22386 enters a sleep state. The electronic device 100 can determine that the main thread aweme22386 and the child thread Thread-2 22426 have a synchronization relationship. Electronic device 100 can record the synchronization relationship between the main thread aweme22386 and the child thread Thread-2 22426 in the first record table of the kernel (i.e., the kernel's reserved space).
[0092] Figures 4B-4C This is a schematic diagram illustrating another specific example of an inter-thread wake-up relationship provided in an embodiment of this application.
[0093] like Figure 4B As shown, the first application is Taking the application's Timer Dispatch 2084 threads, app 2088 threads, aweme 9291 threads, and Render Thread 9486 threads as examples, when the electronic device 100 is in... During video playback or live streaming, if the timer clock signal arrives, the Timer Dispatch 2084 thread can execute a callback function, waking up the app 2088 thread. Then, the app 2088 thread can wake up the aweme 9291 thread (the main thread). The aweme9291 thread can wake up the Render Thread 9486 thread to generate the data needed for drawing the image frame. Then, the Render Thread 9486 thread can wake up the surfaceflinger process to render the image frame, which can be used for subsequent compositing and display. It can be seen that the above threads run sequentially in a chronological order.
[0094] Taking the Timer Dispatch 2084 thread and the app 2088 thread as examples. When the Timer Dispatch 2084 thread is running, the electronic device 100 can insert a stub for this thread. This stub can obtain the resource transfer relationship of the Timer Dispatch 2084 thread. Then, when the Timer Dispatch 2084 thread wakes up the app 2088 thread, the electronic device 100 determines, based on the resource transfer relationship of the Timer Dispatch 2084 thread, that the Timer Dispatch 2084 thread only sends its own resources to the app 2088 thread. Furthermore, through the stub corresponding to the Timer Dispatch 2084 thread, it determines that after waking up the app 2088 thread, the Timer Dispatch 2084 thread enters a sleep state. The electronic device 100 can thus determine that the Timer Dispatch 2084 thread and the app 2088 thread have a synchronization relationship. Electronic device 100 can record the synchronization relationship between Timer Dispatch 2084 thread and app 2088 thread in the kernel's first record table.
[0095] like Figure 4CAs shown, not only image frame rendering tasks, but also audio synthesis tasks can have synchronization relationships. For example, the AudioOut_1D 3235 thread wakes up the DTS AudioV2 3232 thread to run, and the AudioOut_1D 3235 thread and the DTS AudioV2 3232 thread have a logical sequential running relationship. Therefore, when the electronic device 100 runs the AudioOut_1D 3235 thread, stubs can be inserted for the AudioOut_1D 3235 thread to obtain the synchronization relationship between the AudioOut_1D 3235 thread and the DTS AudioV2 3232 thread, and the electronic device 100 can record this synchronization relationship in the kernel's first record table.
[0096] Figure 4D This is a schematic diagram illustrating how an electronic device 100 acquires and records synchronization relationships, as provided in an embodiment of this application.
[0097] like Figure 4D As shown, if the electronic device 100 is running threads in the application framework layer, the surfaceflinger module, and the system service module systemserver, the electronic device 100 can insert stubs for the running threads in these layers. The electronic device 100 can then obtain the synchronization relationships between the threads based on these stubs. The kernel layer can then receive the synchronization relationships obtained based on these stubs through the native layer and record these relationships in the first record table.
[0098] It is understandable that, depending on the thread's runtime environment and stage, the electronic device 100 can insert stubs for threads through the application framework layer, the surfaceflinger module, or the kernel TTWU wake-up chain to determine the synchronization relationship between threads. In other words, this application does not restrict how the electronic device 100 inserts stubs for threads.
[0099] Understandable Figures 4A-4D This is used only as an example to explain this application and does not constitute any limitation.
[0100] Furthermore, the specific implementation method for determining the system idle percentage in S304 is explained in detail:
[0101] Figure 5A This is a flowchart illustrating a method for determining the system idle percentage as provided in an embodiment of this application.
[0102] like Figure 5A As shown, the specific process for determining the idle percentage of this system may include:
[0103] A) Every specified time interval T1, calculate the system idle percentage for the current period based on the idle time of multiple CPU cores.
[0104] Specifically, electronic device 100 can set tick timer events through the kernel, and these tick timer events are associated with a specified duration T1. Every time the clock elapses for a duration T1, electronic device 100 can trigger the generation of a tick timer event; that is, the duration of one cycle is T1. In other words, when the clock has elapsed for the Nth duration T1 and triggers the Nth tick timer event, the current cycle is the Nth cycle. Electronic device 100 can determine a specific CPU core among multiple CPU cores to record the generation of tick timer events through the global variable `jiffies`. Whenever a tick timer event is generated, the specified CPU core can increment the value of `jiffies` by 1.
[0105] Then, when the value of jiffies increases by 1 for the Nth time, electronic device 100 can calculate the idle time of the M CPU cores on electronic device 100 within the Nth cycle. Therefore, the system idle percentage within the Nth cycle can be:
[0106] V N =delta÷total
[0107] Among them, V N Let delta be the system idle percentage within the Nth cycle, delta be the total idle time of the M CPU cores, and total be T1×M. It's understandable that because electronic device 100 calculates the system idle percentage reflecting the overall load of the M CPU cores, rather than the idle percentage of a single specified CPU core, delta is the total idle time of the M CPU cores. Correspondingly, total should be the product of the cycle duration and the number of CPU cores, not just the cycle duration, to reflect the overall system load status.
[0108] Preferredly, T1 can be set to 4ms, and M is generally taken as 8 (i.e., there are generally 8 CPU cores on the electronic device 100). However, T1 and M can also take other values, and this application does not impose any restrictions.
[0109] B). Based on the current frame rate (fps) and the current system idle percentage, determine the final system idle percentage.
[0110] Specifically, after the electronic device 100 determines the system idle percentage for the current period, it can calculate the average of the system idle percentages for the most recent i periods. This average can be used as the final system idle percentage to indicate the system load on the electronic device 100. The value of i is related to the current frame rate (fps). The current frame rate refers to the number of image frames rendered per second.
[0111] Generally, the value of i can be:
[0112] i = 1000 / (fps * T1)
[0113] The final system idle percentage can be:
[0114] V = avg(V) N +…+V N-i-1 )
[0115] Where V is the final system idle percentage, avg(V) N +…+V N-i-1 ) is the average of the system idle percentage over the most recent i periods, including the current period.
[0116] Figure 5B This is a schematic diagram illustrating the statistics of system idle percentage provided in an embodiment of this application.
[0117] like Figure 5B As shown, the first line, allidle0, indicates the system idle percentage coefficient, which is positively correlated with the aforementioned system idle percentage value (both can be set to be the same). The larger the system idle percentage coefficient, the lower the current system load and the more idle the CPU on electronic device 100 is; the smaller the system idle percentage coefficient, the higher the current system load and the busier the CPU on electronic device 100 is.
[0118] In this way, the system idle percentage reflects the system load on the electronic device 100. Based on the system load, CPU scheduling is performed on threads with synchronous relationships. This not only reduces the probability of CPU being preempted by higher priority tasks in light and medium load scenarios, but also avoids interference with low priority lock-holding tasks and core-binding tasks. It also makes task execution more stable, improves the efficiency of the electronic device 100, and reduces the power consumption of the electronic device 100.
[0119] Figure 6 This is a schematic diagram of the software architecture modules of an electronic device 100 provided in an embodiment of this application.
[0120] like Figure 6As shown, the software system of electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses the layered architecture Android system as an example to exemplify the software structure of electronic device 100.
[0121] A layered architecture divides software into several layers. Each layer has a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.
[0122] The application layer can include a series of application packages.
[0123] like Figure 6 As shown, the application package may include gallery, calendar, notes, browser, camera, and first application, etc.
[0124] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.
[0125] like Figure 6 As shown, the application framework layer may include a window manager, content provider, resource manager, notification manager, and synchronization relationship acquisition module, etc.
[0126] The window manager is used to manage windowed applications. It can retrieve screen size, determine the presence of a status bar, lock the screen, and capture screenshots, among other things.
[0127] Content providers store and retrieve data, making that data accessible to applications. This data may include videos, images, audio, made and received phone calls, browsing history and bookmarks, phone books, etc.
[0128] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.
[0129] The notification manager allows applications to display notifications in the status bar. These notifications can be used to deliver informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify users of completed downloads or message alerts. The notification manager can also display notifications as icons or scrolling text in the top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights.
[0130] In this embodiment of the application, the synchronization relationship acquisition module can be used to insert corresponding stubs for running threads and obtain the synchronization relationship between threads based on the stubs.
[0131] In this embodiment, when the first application is launched, the electronic device 100 can create a first thread and a second thread related to the first application. When the first thread runs, the synchronization relationship acquisition module can insert stubs for the first thread, which can obtain the resource transfer relationship of the first thread. Then, when the first thread wakes up the second thread, the electronic device 100 determines, based on the resource transfer relationship of the first thread, that the current first thread only sends its resources to the second thread, and determines, through the stubs corresponding to the first thread, that the first thread enters a sleep state after waking up the second thread. The synchronization relationship acquisition module can then determine that the first thread and the second thread have a synchronization relationship.
[0132] In this embodiment, the synchronization relationship acquisition module can be located at the application framework layer, and / or the system library layer, and / or the kernel layer. That is to say, this application does not limit which layer of the software architecture the synchronization relationship acquisition module is located at.
[0133] Android Runtime (i.e.) Figure 6 The Android runtime (as shown) includes the core libraries and the virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.
[0134] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.
[0135] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.
[0136] The system library can include multiple functional modules. For example: surface manager, 3D graphics processing library (e.g., OpenGL ES), 2D graphics engine (e.g., SGL), etc.
[0137] The Surface Manager manages the display subsystem and provides fusion of 2D and 3D layers for multiple applications. The 3D graphics processing library implements 3D graphics drawing, image rendering, compositing, and layer processing. The 2D graphics engine is the drawing engine for 2D graphics.
[0138] The kernel layer is the layer between hardware and software. At a minimum, the kernel layer includes a system idle percentage calculation module, a CPU scheduling module, a synchronization relationship recording module, a display driver, and a camera driver.
[0139] The display driver can be used to control the display screen on the electronic device 100 to display the content of the first application.
[0140] The camera driver can be used to control the camera on the electronic device 100 to take pictures of the target object.
[0141] In this embodiment, the system idle percentage calculation module can be used to calculate the system idle percentage of the electronic device 100 and determine whether the system idle percentage is greater than or equal to a first preset value; the synchronization relationship recording module can record the synchronization relationship between threads obtained based on stubs; the CPU scheduling module can be used to schedule appropriate CPU running threads according to whether the system idle percentage is greater than or equal to the first preset value and the synchronization relationship between threads.
[0142] Specifically, when the kernel layer obtains the synchronization relationship between the first thread and the second thread based on the stub of the first thread, the synchronization relationship recording module can record the synchronization relationship between the first thread and the second thread in the first record table.
[0143] When the second thread is awakened by the first thread, the CPU scheduling module can query the first record table to see if the awakened second thread has a synchronization relationship with the first thread. If the CPU scheduling module finds from the first record table that the second thread and the first thread have a synchronization relationship, the CPU scheduling module sends a load status judgment instruction to the system idle percentage calculation module. In response to this load status judgment instruction, the system idle percentage calculation module determines whether the system idle percentage is greater than or equal to a first preset value.
[0144] If the system idle percentage is greater than or equal to a first preset value, the system idle percentage calculation module sends a first indication to the CPU scheduling module, indicating that the current system is in a light or medium load state. In response to this first indication, the CPU scheduling module can schedule CPU1, which is running the first thread, to run the second thread. If the system idle percentage is less than the first preset value, the system idle percentage calculation module sends a second indication to the CPU scheduling module, indicating that the current system is in a heavy load state. In response to this second indication, the CPU scheduling module can schedule CPU2, which is different from CPU1, to run the second thread.
[0145] In one possible implementation, when the second thread is awakened by the first thread, the CPU scheduling module can send a load status judgment instruction to the system idle percentage calculation module. In response to this load status judgment instruction, the system idle percentage calculation module determines whether the system idle percentage is greater than or equal to a first preset value.
[0146] If the system idle percentage is greater than or equal to a first preset value, the system idle percentage calculation module sends a first indication to the CPU scheduling module, indicating that the current system is in a light or medium load state. In response to this first indication, the CPU scheduling module can query the first record table to see if the awakened second thread has a synchronization relationship with the first thread. If the CPU scheduling module finds from the first record table that the second thread and the first thread have a synchronization relationship, the CPU scheduling module can schedule CPU1, which is running the first thread, to run the second thread.
[0147] If the system idle percentage is less than a first preset value, the system idle percentage calculation module sends a second indication to the CPU scheduling module, indicating that the current system is in a heavy-load state. In response to this second indication, the CPU scheduling module can schedule CPU2 to run a second thread; CPU2 is different from CPU1.
[0148] Understandable Figure 6 The software architecture shown is for illustrative purposes only and does not constitute any limitation.
[0149] By implementing the scheduling method provided in this application, the electronic device 100 can process tasks in a timely manner, improve response speed, and save power consumption and CPU resource consumption of the electronic device 100.
[0150] Figure 7 This is a schematic diagram illustrating the effect of a scheduling method provided in an embodiment of this application.
[0151] like Figure 7As shown, implementing the scheduling method provided in this application, when the electronic device 100 schedules the CPU 6 (middle core) to run the Timer Dispatch 2084 thread, if the Timer Dispatch 2084 thread wakes up the app 2088 thread to run, and the Timer Dispatch 2084 thread and the app 2088 thread have a synchronization relationship, if the system idle percentage is greater than or equal to the first preset value, that is, when the system is in a light or medium load state, the electronic device 100 can directly schedule the CPU 6 to run the app 2088 thread.
[0152] When the app 2088 thread wakes up the aweme 9291 thread to run, and the app 2088 thread and the aweme 9291 thread are synchronized, if the system idle percentage is greater than or equal to a first preset value, that is, when the system is in a light or medium load state, the electronic device 100 can directly schedule CPU 6 to run the aweme 9291 thread. In other words, when the system is in a light or medium load state, the electronic device 100 can schedule the CPU core of thread 1 to run the woken-up thread 2, and thread 2 and thread 1 are synchronized. In this way, the electronic device 100 can not only execute tasks efficiently and smoothly, but also avoids having to wake up other idle CPU cores to run threads, saving the power consumption and resources of the electronic device 100.
[0153] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.
[0154] This application also provides a computer program product, including a computer program that, when run on a processor, can implement the steps executed by the electronic device in the above-described method embodiments.
[0155] This application also provides a chip system, which includes a processing circuit interface circuit. The interface circuit receives instructions and transmits them to the processing circuit, which executes the instructions to cause the chip system to perform the steps executed by the electronic device in any of the method embodiments of this application. The chip system can be a single chip or a chip module composed of multiple chips.
[0156] The term "user interface (UI)" used in the specification and accompanying drawings of this application refers to the medium through which an application or operating system interacts and exchanges information with the user. It converts the internal form of information into a form acceptable to the user. The user interface of an application is source code written in a specific computer language such as Java or Extensible Markup Language (XML). This source code is parsed and rendered on the terminal device, ultimately presenting user-recognizable content, such as images, text, buttons, and other controls. Controls, also known as widgets, are the basic elements of the user interface. Typical controls include toolbars, menu bars, text boxes, buttons, scroll bars, images, and text. The attributes and content of controls in the interface are defined through tags or nodes, such as XML. <textview> 、 <imgview> 、 <videoview>Nodes define the controls contained in the interface. A node corresponds to a control or property in the interface, and after parsing and rendering, the node is presented as the content visible to the user. In addition, many applications, such as hybrid applications, often contain web pages within their interfaces. A web page, also known as a webpage, can be understood as a special control embedded in the application interface. Web pages are source code written in a specific computer language, such as Hypertext Markup Language (HTML), Cascading Style Sheets (CSS), JavaScript (JS), etc. Web page source code can be loaded and displayed as user-readable content by a browser or a web page display component with browser-like functionality. The specific content contained in a webpage is also defined through tags or nodes in the webpage source code; for example, HTML uses tags or nodes to define the content. 、 、 <video> 、 <canvas>Used to define the elements and attributes of a webpage.
[0157] The most common form of user interface is the graphical user interface (GUI), which refers to a user interface related to computer operation displayed graphically. It can be an icon, window, control, or other interface element displayed on the screen of an electronic device. Controls can include visual interface elements such as icons, buttons, menus, tabs, text boxes, dialog boxes, status bars, navigation bars, and widgets.
[0158] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.
[0159] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.
[0160] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.< / canvas> < / video> < / videoview> < / imgview> < / textview>
Claims
1. A scheduling method, characterized in that, include: The electronic device creates a first thread and a second thread; The electronic device schedules the first core in the central processing unit (CPU) to run the first thread; The electronic device records a first resource transfer relationship of a first thread; wherein the first resource transfer relationship is used to instruct the first thread to send its resources to one or more threads; The electronic device determines a first system idle percentage value based on the idle time of multiple CPU cores; wherein, the multiple CPU cores include the first core; When the second thread is awakened by the first thread, and it is determined based on the first resource transfer relationship that there is a synchronization relationship between the second thread and the first thread, and the first system idle percentage is greater than or equal to the first preset value, the electronic device schedules the first core to run the second thread.
2. The method according to claim 1, characterized in that, The electronic device determines a first system idle percentage based on the idle time of multiple CPU cores, including: Every first specified time interval, the electronic device calculates the second system idle percentage value for the current period based on the idle time of the plurality of CPU cores; The electronic device determines the first system idle percentage based on the current frame rate and the second system idle percentage.
3. The method according to claim 2, characterized in that, Every first specified time interval, the electronic device calculates a second system idle percentage value for the current period based on the idle time of the plurality of CPU cores, including: The electronic device determines the second system idle percentage based on the idle time of the plurality of CPU cores and the product of the number of the plurality of CPU cores and the first specified time.
4. The method according to claim 2 or 3, characterized in that, The electronic device determines the first system idle percentage value based on the current frame rate and the second system idle percentage value, including: The electronic device determines the average value of the system idle percentage over the most recent i periods; wherein the value of i is related to the current frame rate, and the system idle percentage over the most recent i periods includes the second system idle percentage. The electronic device determines the first system idle percentage value as the average of the system idle percentage values of the most recent i periods.
5. The method according to claim 1, characterized in that, When the second thread is awakened by the first thread, and a synchronization relationship is determined between the second thread and the first thread based on the first resource transfer relationship, and the first system idle percentage is greater than or equal to a first preset value, the electronic device schedules the first core to run the second thread, including: When the second thread is awakened by the first thread, the electronic device determines, based on the first resource transfer relationship, that the first thread is only sending its own resources to the second thread, and the electronic device determines that the first thread enters a sleep state after the first thread wakes up the second thread, the electronic device determines that there is a synchronization relationship between the first thread and the second thread. When the first thread and the second thread are synchronized, and the idle percentage of the first system is greater than or equal to a first preset value, the electronic device schedules the first core to run the second thread.
6. The method according to claim 1, characterized in that, The plurality of CPU cores also includes the second core; The method further includes: When the second thread is awakened by the first thread, the electronic device determines, based on the first resource transfer relationship, that the second thread and the first thread do not have a synchronization relationship, or when the first system idle percentage is less than a first preset value, the electronic device schedules the second core to run the second thread, wherein the second core and the first core are different.
7. The method according to claim 6, characterized in that, The second core is either an idle core, or a core whose running task has a lower priority than the second thread, or a core that has previously run the second thread.
8. An electronic device, characterized in that, The electronic device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors call the computer instructions to cause the electronic device to perform the method as described in any one of claims 1-7.
9. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the processors being used to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1-7.
10. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-7.
11. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, causes the electronic device to perform the method as described in any one of claims 1-7.