An industrial control mainboard edge AI computing power autonomous method based on system layer scheduling

Abstract

The present application relates to the field of industrial control and edge computing technology, and more particularly to an industrial control mainboard edge AI computing power autonomous method based on system layer scheduling. A resource matrix is constructed by collecting intra-chip multi-dimensional resource states, a scheduling queue is generated in combination with a task descriptor and a comprehensive evaluation function, and distribution is performed; the highest priority task is bound to a dedicated CPU and bandwidth, and each task is allocated an NPU time window; when the temperature exceeds the threshold, frequency reduction or lightweight model switching is performed, and after falling back, recovery is performed step by step; when local computing power is insufficient, an elastic node pool is started to supplement; after execution, execution parameters are recorded, the evaluation function weight is updated, and playback verification is performed, realizing comprehensive perception and collaborative control of multi-dimensional heterogeneous computing power of the industrial control mainboard, effectively solving the problem of unpredictable interference of memory bandwidth contention and heat accumulation on real-time control tasks caused by AI reasoning load, ensuring the deterministic response of key real-time control tasks, and improving the operation stability and reliability of edge AI computing power in a wide temperature environment.

Description

Technical Field

[0001] This invention relates to the fields of industrial control and edge computing technology, and in particular to an autonomous method for edge AI computing power of industrial control motherboards based on system-level scheduling. Background Technology

[0002] With the deepening of industrial intelligence, industrial control motherboards have evolved from traditional single logic control devices into heterogeneous computing platforms integrating real-time control, data acquisition, and AI inference. Their computing power scheduling efficiency directly affects the response speed and control accuracy of industrial field equipment. However, the operating environment of industrial control motherboards is not statically controllable but constantly changing. Load characteristics fluctuate dynamically with changing operating conditions, heat dissipation conditions evolve continuously with changes in ambient temperature and passive cooling design, and the resource competition among heterogeneous computing units changes in real time depending on the task combination. However, existing scheduling methods mostly employ static priority configuration or independent scheduling strategies for individual computing units, failing to achieve unified perception and collaborative management of CPU, NPU, GPU, and memory bandwidth across units at the operating system kernel level. They also struggle to proactively adjust allocation strategies before temperature limits are exceeded to avoid a precipitous drop in inference performance. Therefore, there is an urgent need for unified perception of heterogeneous resource status and dynamic adaptation to changes in operating conditions to achieve on-demand allocation and stable operation of computing resources. How to integrate multi-dimensional resource status perception and temperature-driven autonomous management to establish a dynamic scheduling system for industrial control scenarios without relying on external networks or increasing additional hardware costs is a current challenge for edge AI computing power scheduling technology on industrial control motherboards.

[0003] Chinese Patent Publication No. CN121300982A discloses a heterogeneous computing scheduling method, device, terminal, and storage medium for industrial control vision inspection. This method decomposes the vision inspection process into several computing tasks and establishes a computing feature model. It sets up processing queues for both CPU and GPU and monitors dynamic load parameters. By comparing the utility function values ​​of tasks on different computing units using a preset utility function, it dynamically allocates computing tasks to the corresponding processing queues and predicts the estimated completion time of each task. If the estimated completion time exceeds the maximum allowable processing delay, a congestion control strategy is initiated. This achieves a certain degree of reasonable allocation of computing tasks between CPU and GPU, improving computing resource utilization, reducing processing latency, and providing some ability to cope with computing congestion. However, this method is mainly limited to CPU and GPU computing resources, failing to include edge AI inference cores such as NPUs in the unified perception and allocation scope. Furthermore, it lacks priority guarantees based on task criticality and temperature-driven computing power degradation and recovery mechanisms, making it difficult to effectively address the unpredictable interference to real-time control tasks caused by memory bandwidth contention and heat accumulation due to AI inference load on industrial control motherboards in multi-dimensional heterogeneous computing environments.

[0004] Existing technologies still have the following problems: The dynamic scheduling system for edge AI computing power on industrial control motherboards lacks the ability to perceive real-time changes in the status of heterogeneous resources and the dynamic evolution of operating conditions in the time dimension. The scheduling strategies mostly adopt fixed priority or general threshold configurations, instead of dynamically constructing scheduling decisions based on the real-time operating status of the system. Instead, they use static allocation rules and compare them with collected data, lacking an adaptive calibration mechanism that changes with load characteristics, temperature status, and resource contention. This results in scheduling decisions being insensitive to the specificity of operating conditions. In addition, the input of the scheduling module directly depends on the fixed priority configuration, which means that safety-critical tasks cannot obtain deterministic guarantees when resources are limited or temperatures rise. Consequently, the effect of ensuring the stable operation of edge AI computing power in a wide-temperature environment is not ideal, making it difficult to meet the needs of industrial sites for deterministic timing of real-time control tasks and flexible scheduling of AI inference tasks. Summary of the Invention

[0005] To address this, the present invention provides an autonomous method for edge AI computing power of industrial control motherboards based on system-level scheduling, which enables comprehensive perception and collaborative management of multi-dimensional heterogeneous computing power of industrial control motherboards. This effectively solves the problem of unpredictable interference to real-time control tasks caused by memory bandwidth contention and heat accumulation due to AI inference load, ensures deterministic response of critical real-time control tasks, and improves the operational stability and reliability of edge AI computing power under wide temperature environments.

[0006] To achieve the above objectives, this invention provides an autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling, comprising: Based on the predetermined period, multi-dimensional resource status data of the target industrial control motherboard is collected to construct a heterogeneous computing power resource status matrix and calculate the available resource quantity of each computing unit. Extract task feature data for each inference task, create task descriptors for each inference task based on the feature data, divide the tasks into priority levels, input them into the task feature database, and continuously update historical parameters with each execution. Based on the heterogeneous computing power resource state matrix and task descriptor, weight factors are configured for each evaluation dimension, a comprehensive evaluation function is constructed, and the priority score of each task is calculated and arranged in descending order to generate a scheduling queue. Based on the scheduling queue, a resource allocation scheme is generated in combination with the available resources, and the feasibility of the scheme is verified to ensure that the on-chip resources do not exceed the safety threshold and meet the requirements of the highest priority level tasks. If the verification fails, adjust the task quota and re-verify until it passes. If any resource status indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is triggered, and a new allocation scheme is generated again. Based on whether the temperature status index in the computing power resource status matrix reaches a preset threshold, determine whether to switch the current computing power allocation strategy to the next level temperature response strategy. Based on the allocation scheme, kernel-level resource allocation is performed. The first priority level tasks are bound to dedicated CPU cores and bandwidth is guaranteed. Each task is allocated a dedicated NPU time window. Poll and check the feature information of a single regular task module, and based on the feature information, determine whether to switch the corresponding single regular task module to a lightweight task module; After the temperature drops, observe the temperature period and then gradually restore it in the reverse order. If the degradation measures have been completed and the local computing power is still insufficient to meet the minimum inference requirements of the first priority task, then determine whether to enable the elastic node pool based on network latency, data transmission volume and available computing power of the edge server. Record execution parameters to form historical samples, periodically calculate deviations and update evaluation function weights, and determine the parameters to be used after replay verification. If both resource utilization and on-time completion rate improve, the update takes effect; otherwise, it reverts to the parameters of the previous version.

[0007] Furthermore, the predetermined collection period is determined based on task real-time constraints, chip performance and hardware specifications, system overhead, and heat dissipation conditions. Furthermore, the process of collecting multi-dimensional resource status data within the target industrial control motherboard based on a predetermined period, constructing a heterogeneous computing power resource status matrix, and calculating the available resource quantity of each computing unit includes: Deploy a computing power awareness protection module in the kernel space of the industrial control motherboard operating system and bind it to an isolated CPU core for operation; By monitoring the functional units, the utilization and interrupt response latency of each CPU core, the depth of the NPU inference queue and engine utilization, the GPU rendering load and video memory usage, the DDR read / write bandwidth utilization and cache hit rate, and the junction temperature and PCB temperature of each functional module are collected respectively.

[0008] The data from different sources and with different physical meanings are aligned with a unified timestamp and combined into a heterogeneous computing power resource status matrix containing five dimensions: CPU, NPU, GPU, memory bandwidth, and temperature. The available resources of each computing unit are calculated based on the current occupancy value and the corresponding total amount of each dimension.

[0009] The resource status matrix and available resource quantity are continuously updated at a set sampling period to provide input of the current system status for upper-level scheduling decisions.

[0010] The monitoring function unit includes a kernel performance counter, an NPU driver register interface, a GPU driver interface, a memory controller performance monitoring unit, and an onboard temperature sensor. Furthermore, the available resource quantity is calculated based on the current occupancy value of each dimension in the resource status matrix and the total hardware specifications; CPU availability is equal to the ratio of the total number of cores minus the current weighted average utilization of each core to the total number of cores; NPU available computing power is equal to the total NPU computing power minus the used computing power calculated based on the current utilization of each inference engine; GPU available resources are equal to the total GPU resources minus the used resources calculated based on the current video memory utilization and rendering load; memory available bandwidth is equal to the theoretical peak bandwidth of the bus minus the current measured bandwidth value. The available resources in each of the above dimensions represent the upper limits of CPU computing power, NPU computing power, GPU resources, and memory bandwidth that can be used by newly assigned tasks at the current moment, providing resource capacity constraints for the generation of subsequent computing power allocation schemes.

[0011] Furthermore, the process of extracting task feature data for each inference task, creating task descriptors for each inference task based on the feature data, assigning priority levels to the tasks, inputting the data into the task feature database, and continuously updating historical parameters with each execution includes: Extract task feature data for each inference task when it is created and after each round of scheduling execution. Based on the task feature data, a corresponding task descriptor is created for each inference task, and priority levels are assigned to each task according to the degree of impact of the inference results on equipment safety, product quality, or data statistics. The task descriptor and priority level are input into the task feature database for storage, and the corresponding historical parameters are continuously updated after each round of scheduling is completed. The task feature data includes the model identifier, input data size, expected inference cycle, and maximum tolerable inference latency for each inference task. The task descriptor is a data structure record for each inference task, including task identifier, task type, model identifier, expected inference cycle, maximum tolerable inference latency, input data size, historical average inference time, historical average NPU utilization, historical average memory bandwidth consumption, and task criticality level fields. The priority hierarchy includes three levels: safety-critical, process-critical, and analysis-supporting. Safety-critical tasks are the first priority, process-critical tasks are the second priority, and analysis-supporting tasks are the third priority. The task feature database is deployed in the kernel space and stores the task descriptors and corresponding historical execution parameters of each task in a linked list structure.

[0012] Furthermore, the process of configuring weight factors for each evaluation dimension based on the heterogeneous computing power resource state matrix and task descriptors, constructing a comprehensive evaluation function, and calculating the priority score of each task and arranging them in descending order to generate a scheduling queue includes: A computing power autonomous decision engine is deployed at the kernel layer of the industrial control motherboard operating system. The computing power autonomous decision engine receives the resource status matrix and the task descriptor at the current moment, sets corresponding weight factors for each evaluation dimension, and combines the above weight factors into a comprehensive evaluation function. Based on the comprehensive evaluation function, the decision engine performs a quantitative evaluation of each task to be scheduled and calculates the computing power allocation priority score for that task. Based on the computing power allocation priority score, the decision engine arranges all tasks to be scheduled in descending order of priority score from high to low to form a task scheduling queue. During execution, the autonomous decision-making engine continuously monitors the current occupancy value of each dimension in the resource status matrix. If any resource status indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is triggered, the current resource status matrix and task descriptor are reread, the priority score of each task is recalculated, and the scheduling queue is regenerated.

[0013] Furthermore, the evaluation dimensions include: task priority weight, resource matching weight, heat risk weight, and time urgency weight, which respectively reflect the criticality of the task, the matching status of resource supply and demand, the temperature risk level, and the time urgency. Furthermore, the weight factor of the task priority is assigned according to the criticality level in the task descriptor. The weight factor of safety-critical tasks is the highest and the weight factor of auxiliary analysis tasks is the lowest. Moreover, the weight factor does not change with the working conditions. The weight factor of the resource matching degree is calculated based on the comparison between the historical resource consumption of the task and the current available resource quantity in the resource status matrix. The higher the current available resource quantity and the higher the matching degree with the historical requirements of the task, the higher the value of the weight factor. The weighting factor for the heat risk is calculated based on the current temperature state vector in the resource state matrix and the average temperature change during the historical execution of the task. The higher the current temperature and the greater the historical heat generation of the task, the lower the weighting factor value. The weighting factor for the timeliness urgency is calculated based on the maximum tolerable delay in the task descriptor and the remaining margin of the current waiting time. The shorter the remaining time, the higher the weighting factor value. Furthermore, based on the scheduling queue, a resource allocation scheme is generated in conjunction with the available resource quantity, and the feasibility of the scheme is verified to ensure that the on-chip resources do not exceed the safety threshold and meet the requirements of the highest priority task level. This process includes: The autonomous computing decision engine allocates corresponding computing resources to each task in turn according to the order of tasks in the scheduling queue and the available resources of each computing unit in the current resource status matrix, thereby generating a resource allocation scheme. Feasibility verification is performed based on the aforementioned allocation scheme; If any verification item fails, the task quota of the lower priority level in the current failed allocation scheme will be reduced in order of priority from low to high. The allocation scheme will be regenerated and the feasibility will be verified again until all verification items pass. If any resource status indicator, such as CPU utilization, NPU engine utilization, memory bandwidth utilization, or temperature, exceeds the preset adjustment threshold, dynamic rescheduling is triggered. The decision engine rereads the current resource status matrix and task descriptor, regenerates the scheduling queue, and re-executes the generation and verification of the resource allocation scheme. Furthermore, the resource allocation scheme includes the CPU core number and time slice quota bound to each task, the NPU inference engine number and computing time window occupied, the GPU computing resource quota, and the memory bandwidth reservation ratio. During the execution of the resource allocation scheme, the computing power awareness and protection module continuously updates the resource status matrix at a sampling period; Furthermore, the verification content includes that the total time slices allocated to each CPU core do not exceed the available time of the corresponding core, the NPU computing time windows of each task do not overlap, the total memory bandwidth reserved for all tasks does not exceed the set safety threshold of the total bandwidth, and the resource requirements of the highest priority core control task must be fully met. Furthermore, the process of determining whether to switch the current computing power allocation strategy to the next-level temperature response strategy based on whether the temperature status index in the computing power resource status matrix reaches a preset threshold includes: Obtain the current junction temperature value and monitor the chip junction temperature in real time; The current junction temperature value is compared with the threshold values ​​at each level in the preset temperature threshold set to determine the current temperature state range of the system. The temperature state range is divided into normal state, warning state and restricted state, and each state range corresponds to a different computing power allocation strategy. When the system is determined to be in a normal state, the current full computing power scheduling strategy remains unchanged; when the junction temperature is detected to rise to the level of entering the warning state, the current computing power allocation strategy is switched to the preventive degradation strategy; when the junction temperature is detected to continue to rise to the level of entering the restricted state, the current computing power allocation strategy is switched to the restrictive degradation strategy. When the temperature drops back to the range where it exits the current state, the temperature response strategy is restored to the previous level in the reverse order of the downgrade. After each level is restored, an observation period is waited to confirm that the temperature is stable before continuing the restoration. The temperature state is determined based on the junction temperature of the CPU and NPU, and the state switching is triggered when the temperature reaches or exceeds the corresponding temperature threshold. Furthermore, the preventive degradation strategy is as follows: reduce the inference frequency of the third priority task, switch the second priority task to the lightweight model, and keep the resources of the first priority task unchanged; the restrictive degradation strategy is as follows: suspend the third priority task, switch the second priority task to the ultra-lightweight model and further reduce its frequency, and switch the first priority task to the minimized inference model. The temperature recovery after the initial drop is carried out in the reverse order of the downgrade, with each level of recovery followed by an observation period to confirm that the temperature is stable before continuing the recovery process. The observation period consists of several consecutive sampling cycles, and the temperature is considered stable only if it remains below the exit threshold in each cycle.

[0014] Furthermore, the process of performing kernel-level resource allocation based on the allocation scheme, binding first-priority tasks to dedicated CPU cores and ensuring bandwidth, and allocating dedicated NPU time windows to each task includes: According to the resource allocation scheme, the autonomous computing power decision engine sends CPU core binding instructions and time slice quota configuration instructions to the operating system kernel CPU scheduler, binds the first priority level of safety-critical tasks to the designated CPU core and runs them in exclusive mode, and allocates the second priority level and third priority level tasks to the remaining CPU cores and schedules them in time according to priority. Send inference time window allocation instructions to the NPU driver to assign corresponding NPU inference engine numbers and computation time windows to each task, so that the NPU executes only one task's inference computation within the same time window; Send a bandwidth reservation configuration command to the memory controller, reserve guaranteed bandwidth for the data access path of the first priority level tasks through the service quality configuration interface of the memory controller, allocate proportional bandwidth for the second priority level tasks, and use the remaining available bandwidth for the third priority level tasks.

[0015] The exclusive mode means that the time slice resources of the CPU core are completely occupied by the bound task, and other tasks are not allowed to be scheduled and run on the core. The time-sharing scheduling refers to multiple tasks using the time slice resources of the same CPU core in order of priority from high to low. The inference time window is a continuous time interval in which the NPU engine is dedicated to performing inference calculations for a specified task. The inference time windows of different tasks do not overlap. The guaranteed bandwidth is a memory access channel with the highest priority in the memory arbitration layer, which is set for a specified task through the QoS register of the memory controller, and its bandwidth quota is always satisfied at any time.

[0016] Furthermore, the process of polling and detecting the feature information of a single regular task module, and determining whether to switch the corresponding single regular task module to a lightweight task module based on the feature information, includes: The current running status information and current temperature status index of each task module are polled and checked. Based on the current running status information and current temperature status index, it is determined whether each task module meets the conditions for switching to the corresponding lightweight model. When any task module meets the switching condition, the inference model of the task module is switched from the current model to the target lightweight model.

[0017] The switching conditions include temperature triggering conditions and task status triggering conditions; Furthermore, the temperature triggering condition is that the current temperature status indicator reaches the temperature threshold corresponding to the warning state or the restriction state; the task status triggering condition is that the current inference frequency of the task module is lower than the preset lower limit, or the current model inference time exceeds the preset maximum tolerable delay, or the task module is currently in an idle waiting state and is about to enter a new round of inference cycle. Furthermore, the target lightweight model is a deployed backup model, including a lightweight model suitable for the early warning state, an ultra-lightweight model suitable for the restricted state, and a minimized inference model that retains only the core functions.

[0018] Furthermore, the process of determining whether to enable the elastic node pool includes: After all local computing power degradation measures have been executed, the computing power autonomous decision engine reads the current network status parameters and edge server resource status parameters to obtain network latency, available bandwidth, round-trip latency and available computing power of the edge server. If the network latency is lower than the predetermined threshold, the amount of data transmitted is less than the product of the current available bandwidth and the round-trip latency, and the available computing power of the edge server is greater than the computing power requirement of the task to be unloaded, then the unloading conditions are met, the elastic node pool is activated, and some inference tasks are unloaded to the elastic node pool for execution. If any condition is not met, the unloading condition is determined to be unmet, and the local minimal inference mode continues to run, while continuously monitoring the network status and edge server resource status until the condition is met or the local computing power is restored.

[0019] The degradation methods include reducing inference frequency, switching to a lightweight model, switching to an ultra-lightweight model, and switching to a minimized inference model. The statement that the local computing power is still insufficient to meet the minimum inference requirements of the first priority task means that, under the minimized inference model operation, the actual inference frame rate of the first priority task is still lower than the minimum frame rate threshold required for safe operation. Furthermore, the elastic node pool refers to a collection of one or more pre-deployed external computing nodes, including edge servers located on the same local area network as the industrial control motherboard, and cloud computing nodes; After all local degradation measures have been executed, if the minimum inference requirements of the first priority task still cannot be met, and the current network latency, the amount of data to be transmitted, and the available computing power of the node meet the offloading conditions, the decision engine will offload at least some inference tasks to the elastic node pool for execution, as a supplementary source of computing power when local computing power is insufficient.

[0020] Furthermore, the process of recording execution parameters to form historical samples, periodically calculating deviations and updating evaluation function weights, and determining the parameters to be used after replay verification includes: After each round of scheduling is completed, the computing power awareness guardian module records the actual inference time, actual NPU utilization, actual memory bandwidth consumption and temperature change during execution of each task, forming a historical sample of task scheduling, which is then stored in the historical database in association with the corresponding resource status matrix and allocation scheme. When the set update cycle arrives, the samples in the historical database are used as training data to calculate the deviation between the expected resource consumption and the actual resource consumption of each task. The weight adjustment gradient is constructed according to the direction and magnitude of the deviation, and the weight factors in the evaluation function are incrementally updated under the set stability boundary constraints. The updated evaluation function is applied to the historical sample set for replay verification. The scheduling scheme corresponding to each sample is recalculated. If the regenerated scheduling scheme improves both resource utilization and on-time task completion rate compared to the historical actual execution scheme, the update is confirmed to be effective and the new weights are saved. If any indicator does not improve or decreases, then abandon this update and revert to the previous version's weighting factor; Furthermore, the historical database is deployed in the non-volatile storage medium of the industrial control motherboard; The update cycle is determined based on the pre-set round scheduling cycle; The replay verification uses the same resource state matrix as the historical actual execution as the input condition to eliminate the impact of changes in operating conditions on the verification results. Compared with existing technologies, the beneficial effects of this invention are as follows: This invention overcomes the unpredictable interference of AI inference load on real-time control tasks through unified perception and collaborative scheduling at the operating system kernel layer, ensuring deterministic response of critical tasks. At the same time, it establishes a temperature-driven proactive autonomous mechanism, which proactively intervenes before the temperature reaches a critical point, avoiding a precipitous drop in inference performance. Furthermore, through a self-closed-loop system of smooth degradation and autonomous recovery, it ensures that core functions are not interrupted when resources are limited. On this basis, combined with online optimization driven by historical data, the scheduling strategy continuously evolves with the operating conditions, significantly improving the operational stability and reliability of edge AI computing power in a wide temperature environment.

[0021] In particular, this invention achieves hardware-level memory access bandwidth isolation by real-time monitoring of five-dimensional resource status, including CPU, NPU, GPU, memory bandwidth, and temperature, combined with the QoS configuration mechanism of the DDR controller. This solves the problem in existing technologies where independent management by each computing unit leads to interference with the timing determinism of real-time control tasks due to AI inference load. The system continuously monitors memory bandwidth utilization in the kernel space. When bandwidth usage exceeds a threshold, the scheduler reduces the bandwidth demand of high-load tasks in advance, mitigating the risk of contention at the source. During the allocation scheme execution phase, the DDR controller's QoS register configures fixed high-priority guaranteed bandwidth for safety-critical tasks, allowing their memory access requests to bypass the ordinary request queue at the memory arbitrator hardware level. Their read / write responses are not affected by the number of concurrent requests from other computing units, ensuring that even when the NPU is fully loaded, the memory access latency of real-time control tasks is always constrained within a controllable range. Through this method, this invention eliminates unpredictable interference caused by AI inference load at the hardware level, rather than merely mitigating conflicts at the software scheduling level, effectively guaranteeing the timing determinism of real-time control tasks.

[0022] In particular, this invention establishes a predictive temperature management and degradation mechanism. Temperature management introduces a heat risk weight factor into the comprehensive evaluation function built at the kernel layer. This factor is dynamically adjusted based on the temperature change range of the task during its historical execution: the higher the historical heat generation of a task, the lower its comprehensive score when scheduled under high temperature conditions. This enables the scheduler to predict heat accumulation trends and reduce the computing power allocation priority of high-heat tasks in advance before the temperature reaches the critical point. The degradation mechanism establishes three temperature state intervals: normal state, warning state, and restricted state. When the temperature enters the warning state, preventive degradation is triggered by actively reducing heat sources through lightweight model switching or frequency reduction to prevent the temperature from continuing to rise to the critical point that triggers hardware forced frequency reduction. Furthermore, when the temperature falls below the exit threshold, the system recovers step by step in the reverse order of degradation. After each level of recovery, an observation period is waited to confirm temperature stability, ensuring that the temperature does not rebound after the previous level of recovery. This allows the AI ​​inference performance to smoothly transition and avoid oscillations during temperature fluctuations, effectively improving the stability of the industrial control motherboard in a wide temperature environment. Attached Figure Description

[0023] Figure 1 This is a block diagram of the autonomous edge AI computing power system based on system-level scheduling of the industrial control motherboard according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the generation process of the computing power allocation scheme in an embodiment of the present invention. Figure 3 This is a flowchart illustrating the temperature response strategy and autonomous computing power degradation process in an embodiment of the present invention. Figure 4 This is a flowchart illustrating the steps of the autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling, as described in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0025] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0026] Please see Figure 1 This is a block diagram of the autonomous AI computing power edge system of the industrial control motherboard based on system-level scheduling according to an embodiment of the present invention. The system described in the embodiment includes: The computing power awareness and protection module constructs a heterogeneous computing power resource status matrix based on real-time collected multi-dimensional resource status data, calculates the available resources of each computing unit, records task execution parameters, and inputs them into the historical sample database. The task feature management module, which is connected to the computing power awareness and protection module, extracts task feature data, establishes and maintains task descriptors, and divides task priority levels. The task feature database, which is connected to the task feature management module, is used to store the task descriptors and execution parameters of each task. The autonomous decision-making engine for computing power is connected to the task feature database and the historical sample database respectively. Based on the resource status matrix and task descriptors, it calculates the task priority score through a comprehensive evaluation function and generates a scheduling queue. It performs feasibility verification on the resource allocation scheme. If the verification fails, it adjusts the resource quota according to the priority and re-verifies, and finally generates a resource allocation decision. The kernel resource allocation executor, which is connected to the autonomous decision engine for computing power, is used to perform CPU core binding, NPU inference time window allocation, memory bandwidth quality of service configuration, and model switching operations. The historical sample database, connected to the computing power awareness and protection module, is used to store the execution parameters, resource status matrix, and resource allocation scheme for each round of scheduling, providing training samples for the online optimization of the decision engine.

[0027] Please see Figure 2 This is a flowchart illustrating the generation process of the computing power allocation scheme in an embodiment of the present invention. The process described in the embodiment includes: When each scheduling cycle arrives or is triggered by dynamic rescheduling, the computing power autonomous decision engine receives the current resource status matrix and task descriptor, and determines the weighting factors for the four evaluation dimensions of task priority, resource matching degree, heat risk and time urgency. After the four-dimensional weights are normalized, they are combined into a comprehensive evaluation function. The decision engine substitutes the characteristics of each task into the function, calculates the weighted sum to obtain the computing power allocation priority score, and generates a scheduling queue by arranging the scores in descending order from high to low. Based on the queue order and the available resources of each computing unit, a complete allocation scheme is formed by allocating CPU cores and time slice quotas, NPU inference time windows and memory bandwidth reservation ratios to each task. When entering the feasibility verification, check each item to see if the total time slice of each CPU core exceeds the limit, whether the time windows of each NPU engine overlap, whether the total memory bandwidth reservation exceeds the safety threshold, and whether the requirements of the highest priority task are fully met. If any verification item fails, the quota is reduced from the lowest priority level according to the preset step size and the scheme is regenerated. The cycle continues until the verification is passed and the scheme is issued. During the execution of the scheme, the status indicators of each resource are continuously monitored. If any indicator exceeds the preset adjustment threshold, dynamic rescheduling is triggered. The resource status and task descriptor are read again and the above calculation, allocation and verification process is repeated to generate a new allocation scheme.

[0028] Specifically, during the quota reduction and dynamic rescheduling process after a feasibility check fails, the engine immediately performs a check on the allocation plan after it is generated. The check process extracts the time slice quota allocated to each CPU core from the plan item by item and sums them up. This summation is then compared with the available time of the corresponding core within the scheduling cycle to determine if the limit has been exceeded. At the same time, the computation time window of each task on each NPU inference engine is extracted, and it is checked whether there is any overlap in time windows on the same engine. The sum of the memory bandwidth reservation ratios of all tasks is then calculated to determine whether it exceeds the set safety threshold of the total bus bandwidth. In addition, it is also checked whether the CPU cores, NPU time windows, and memory bandwidth required by the highest priority tasks have all been met. If any of the above verification items fails, the engine will reduce the CPU time slice quota, NPU computing time window length or memory bandwidth reservation ratio of the third priority task in the scheme according to the priority level from low to high. The reduction step size is preset to a fixed percentage of the original quota. Then, the allocation scheme is regenerated and all verifications are performed again. If it still fails, the quota of the second priority task will continue to be reduced, but the resources of the first priority task will never be reduced. The cycle continues until all verification items pass. After the allocation plan is issued and executed, the computing power awareness and protection module continuously updates the resource status matrix at the sampling period. The decision engine synchronously monitors CPU utilization, NPU engine utilization, memory bandwidth utilization, and temperature status indicators. Once any indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is triggered. The engine rereads the current resource status matrix and task descriptor, recalculates the priority score, regenerates the scheduling queue, reallocates resources, and performs feasibility verification according to the same process to form a new allocation plan for issuance and execution, so that the scheduling results remain effective in real time after the system status changes.

[0029] Please see Figure 3 This is a flowchart illustrating the temperature response strategy and autonomous computing power degradation process according to an embodiment of the present invention. The process described in the embodiment includes: The system continuously monitors the CPU junction temperature and NPU junction temperature, compares the junction temperature with preset thresholds step by step, and determines the current temperature status. When the CPU junction temperature is below a predetermined threshold and the NPU junction temperature is below a second threshold, it is in a normal state and executes the full computing power scheduling strategy. When the CPU junction temperature reaches a predetermined threshold or the NPU junction temperature reaches a second threshold, the system enters an early warning state and switches to a preventive degradation strategy: the third priority task reduces the inference frequency, the second priority task enables a lightweight alternative model, and the first priority task keeps its resources unchanged. When the CPU junction temperature reaches the third threshold or the NPU junction temperature reaches the fourth threshold, the system enters a restricted state and switches to a restricted degradation strategy: the third priority task is suspended and its NPU time window and memory bandwidth are released; the second priority task is further downclocked and an ultra-lightweight alternative model is enabled; the first priority task is switched to a minimal inference model, retaining only the inference output required for core security decisions. When the temperature drops, the system recovers step by step in the reverse order of degradation. When exiting from the restricted state to the warning state, the first priority task is restored to the original model and resource guarantee. After waiting for the observation period consisting of continuous sampling periods to confirm that the temperature is stable, the second priority task is restored to the corresponding configuration in the warning state. After confirming stability again, the third priority task is restored to the reduced frequency execution state. When exiting from the warning state to the normal state, the third priority task is restored to the normal frequency, the second priority task to the original model, and the first priority task to the original resource allocation in sequence. After each level of recovery, the temperature must remain below the exit threshold during the observation period before proceeding to the next level. If any period exceeds the limit, the system waits again until it returns to the normal state full scheduling strategy.

[0030] Specifically, the core of the degradation mechanism is to implement graded and progressive computing power reduction for tasks of different priority levels based on the temperature range of the CPU and NPU junctions. The preventative degradation corresponding to the early warning state mainly targets auxiliary analysis tasks and process-critical tasks. It reduces overall computing power consumption by lowering the inference frequency and replacing the lightweight model, while safety-critical tasks are unaffected. The restrictive degradation corresponding to the restricted state further reduces computing power supply, suspends all auxiliary analysis tasks, enables ultra-lightweight models with lower computational load for process-critical tasks and continues to reduce the inference frequency, and switches safety-critical tasks to a minimized inference model, retaining only the inference output directly related to safety interlock or emergency shutdown decisions, maintaining safety functions with the lowest possible computing power cost. The three priority levels of degradation actions are progressively advanced, so that the system first sacrifices auxiliary analysis tasks that can be delayed or discarded in a high-temperature environment, then reduces the calculation accuracy and frequency of process-critical tasks, and finally retains only the minimum reasoning ability of safety-critical tasks, thus forming an orderly balance between thermal risk control and the continuity of critical tasks.

[0031] Please see Figure 4 This is a flowchart illustrating the steps of the autonomous AI computing power method for industrial control motherboards based on system-level scheduling in an embodiment of the present invention. The method described in the embodiment includes: Step S1: Collect multi-dimensional resource status data within the target industrial control motherboard based on a predetermined period, construct a heterogeneous computing power resource status matrix, and calculate the available resource quantity of each computing unit; Step S2: Extract task feature data for each inference task, create task descriptors for each inference task based on the feature data, divide the tasks into priority levels, input them into the task feature database, and continuously update historical parameters with each execution. Step S3: Based on the heterogeneous computing power resource state matrix and task descriptor, configure weight factors for each evaluation dimension, construct a comprehensive evaluation function, and calculate the priority score of each task through the comprehensive evaluation function and arrange them in descending order to generate a scheduling queue. Step S4: Based on the scheduling queue, generate a resource allocation scheme in combination with the available resource quantity, and perform a feasibility verification on the scheme to ensure that the on-chip resources do not exceed the safety threshold and meet the requirements of the highest priority level task. Step S5: Based on whether the temperature status index in the computing power resource status matrix has reached the preset threshold, determine whether to switch the current computing power allocation strategy to the next level temperature response strategy; if it is not necessary to switch the temperature response strategy, then perform kernel-level resource allocation based on the allocation scheme, bind the first priority level tasks to dedicated CPU cores and ensure bandwidth, and allocate NPU dedicated time windows for each task. Step S6: If it is necessary to switch the temperature response strategy, poll and check the feature information of a single regular task module. Based on the feature information, determine whether to switch the corresponding single regular task module to a lightweight task module. After the temperature drops, observe the period and then restore it step by step in the reverse order. Step S7: If the downgrade measures have been completed and the local computing power still cannot meet the minimum inference requirements of the first priority task, then determine whether to enable the elastic node pool based on network latency, data transmission volume and available computing power of the edge server. Step S8: Record execution parameters to form historical samples, periodically calculate deviations and update evaluation function weights, and determine the parameters to be used after replay verification. If both resource utilization and on-time completion rate are improved, the update will take effect; otherwise, it will revert to the previous version of parameters. Specifically, the predetermined collection period is determined based on task real-time constraints, chip performance and hardware specifications, system overhead and heat dissipation conditions; Specifically, the process of collecting multi-dimensional resource status data within the target industrial control motherboard at a predetermined period, constructing a heterogeneous computing power resource status matrix, and calculating the available resource quantity of each computing unit includes: Deploy a computing power awareness protection module in the kernel space of the industrial control motherboard operating system and bind it to an isolated CPU core for operation; By monitoring the functional units, the utilization and interrupt response latency of each CPU core, the depth of the NPU inference queue and engine utilization, the GPU rendering load and video memory usage, the DDR read / write bandwidth utilization and cache hit rate, and the junction temperature and PCB temperature of each functional module are collected respectively.

[0032] The data from different sources and with different physical meanings are aligned with a unified timestamp and combined into a heterogeneous computing power resource status matrix containing five dimensions: CPU, NPU, GPU, memory bandwidth, and temperature. The available resources of each computing unit are calculated based on the current occupancy value and the corresponding total amount of each dimension.

[0033] The resource status matrix and available resource quantity are continuously updated at a set sampling period to provide input of the current system status for upper-level scheduling decisions.

[0034] The monitoring function unit includes a kernel performance counter, an NPU driver register interface, a GPU driver interface, a memory controller performance monitoring unit, and an onboard temperature sensor. Specifically, the available resource quantity is calculated based on the current occupancy value of each dimension in the resource status matrix and the total hardware specifications; CPU availability is equal to the ratio of the total number of cores minus the current weighted average utilization of each core to the total number of cores; NPU available computing power is equal to the total NPU computing power minus the used computing power calculated based on the current utilization of each inference engine; GPU available resources are equal to the total GPU resources minus the used resources calculated based on the current video memory utilization and rendering load; memory available bandwidth is equal to the theoretical peak bandwidth of the bus minus the current measured bandwidth value. The available resources in each of the above dimensions represent the upper limits of CPU computing power, NPU computing power, GPU resources, and memory bandwidth that can be used by newly assigned tasks at the current moment, providing resource capacity constraints for the generation of subsequent computing power allocation schemes.

[0035] In this embodiment, the computing power awareness and protection module is deployed in the kernel space of the industrial control motherboard operating system and bound to the isolated CPU core for operation; the predetermined collection period is determined comprehensively based on the task's real-time constraints, chip performance and hardware specifications, system overhead and heat dissipation conditions: for tasks with a maximum tolerable inference latency in the millisecond range, the collection period is set to high-frequency collection; if the chip performance counter reading overhead is low and the temperature changes slowly, it can be appropriately relaxed, but it must not exceed the task's shortest tolerable latency. The computing power awareness protection module reads the utilization rate, context switching frequency, and interrupt response latency of each CPU core through the kernel performance counter, reads the NPU inference queue depth, inference engine utilization, and model cache hit rate through the NPU driver register interface, reads the GPU rendering load, video encoding / decoding queue utilization, and video memory utilization through the GPU driver interface, reads the DDR read / write bandwidth utilization, cache hit rate, and memory access latency through the memory controller performance monitoring unit, and obtains the junction temperature of each functional module and the PCB temperature through the onboard temperature sensor and the chip internal junction temperature sensor. The multi-dimensional resource status data is aligned with a unified timestamp and combined into a heterogeneous computing power resource status matrix containing five dimensions: CPU, NPU, GPU, memory bandwidth, and temperature. Based on the current occupancy values ​​of each dimension in the matrix and the total hardware specifications, the available resources of each computing unit are calculated as follows: CPU availability is equal to the ratio of the difference between the total number of cores and the current weighted average utilization of each core to the total number of cores; NPU available computing power is equal to the total NPU computing power minus the used computing power calculated based on the utilization of each inference engine; GPU available resources are equal to the total GPU resources minus the used resources calculated based on the current video memory utilization and rendering load; memory available bandwidth is equal to the theoretical peak bandwidth of the bus minus the current measured bandwidth value. The available resources mentioned above represent the upper limits of CPU, NPU, GPU, and memory bandwidth that can be used by newly assigned tasks at the current moment, providing resource capacity constraints for the generation of subsequent computing power allocation schemes.

[0036] In this embodiment, the sensing processes for five heterogeneous resources—CPU, NPU, GPU, memory bandwidth, and temperature—are uniformly deployed within the operating system kernel space. This avoids the additional latency and data inconsistency issues caused by frequent switching between user mode and kernel mode. Simultaneously, by aligning multi-source data using a unified timestamp, state indicators with different physical meanings are combined into a resource state matrix under the same time reference. This eliminates resource state estimation biases caused by asynchronous sampling times. The available resource quantity calculated based on this matrix accurately reflects the true remaining capacity of each computing unit at the current moment, providing high-precision resource capacity constraints for upper-layer computing power scheduling. This ensures that subsequent task priority calculations, computing power allocation scheme generation, and dynamic adjustments are all based on accurate resource data, guaranteeing the rationality of scheduling decisions. Furthermore, continuous periodic updates significantly improve the real-time performance and accuracy of resource sensing, reducing the risk of computing power allocation conflicts caused by resource state lag or distortion.

[0037] Specifically, the process of extracting task feature data for each inference task, creating task descriptors for each inference task based on the feature data, assigning priority levels to the tasks, inputting the data into the task feature database, and continuously updating historical parameters with each execution includes: Extract task feature data for each inference task when it is created and after each round of scheduling execution. Based on the task feature data, a corresponding task descriptor is created for each inference task, and priority levels are assigned to each task according to the degree of impact of the inference results on equipment safety, product quality, or data statistics. The task descriptor and priority level are input into the task feature database for storage, and the corresponding historical parameters are continuously updated after each round of scheduling is completed. The task feature data includes the model identifier, input data size, expected inference cycle, and maximum tolerable inference latency for each inference task. The task descriptor is a data structure record for each inference task, including task identifier, task type, model identifier, expected inference cycle, maximum tolerable inference latency, input data size, historical average inference time, historical average NPU utilization, historical average memory bandwidth consumption, and task criticality level fields. The priority hierarchy includes three levels: safety-critical, process-critical, and analysis-supporting. Safety-critical tasks are the first priority, process-critical tasks are the second priority, and analysis-supporting tasks are the third priority. The task feature database is deployed in the kernel space and stores the task descriptors and corresponding historical execution parameters of each task in a linked list structure.

[0038] In this embodiment, static feature data of the inference task is extracted during the task creation phase, including model identifier, input data size, expected inference cycle, and maximum tolerable inference latency. A task identifier and task type are assigned. Based on the impact of the inference result on equipment safety, product quality, or data statistics, the task is classified as one of safety-critical, process-critical, or auxiliary analysis-critical, corresponding to first, second, and third priorities, respectively. In the kernel space, the system creates a task descriptor for the task, which includes a task identifier, task type, model identifier, expected inference cycle, maximum tolerable inference latency, input data size, historical average inference time, historical average NPU utilization, historical average memory bandwidth consumption, and task criticality level. This, along with the priority level, is written to a task feature database organized in a linked list structure and stored as a linked list node. After each round of scheduling execution, the system reads the actual inference time, actual NPU utilization, and actual memory bandwidth consumption of the task in this round from the execution log and the computing power awareness protection module. A weighted average is calculated with the existing historical average values, updating the historical average field in the task descriptor and the historical execution parameters in the linked list node, thereby continuously revising the task profile as it runs.

[0039] In this embodiment, static task configuration information and dynamic execution feedback are uniformly encapsulated into a fixed-structure task descriptor and centrally managed through a linked list database deployed in the kernel space. This avoids data inconsistency and cross-state query overhead caused by task information being scattered across different modules or user-space storage. At the same time, after each round of scheduling execution, the historical average fields are weighted and updated using actual inference time, NPU utilization, and memory bandwidth consumption. This ensures that the task profile continuously approximates the actual running state, providing the task-side input to the autonomous decision-making engine with consistently high accuracy and timeliness. Based on this continuously corrected task feature data, priority levels and resource requirement descriptions can accurately reflect the actual running characteristics of the task, thereby reducing the risk of scheduling misjudgment and resource mismatch caused by distorted task descriptions and improving the real-time performance, consistency, and overall scheduling stability and efficiency of the task feature management process.

[0040] Specifically, the process of configuring weight factors for each evaluation dimension based on the heterogeneous computing power resource state matrix and task descriptors, constructing a comprehensive evaluation function, and calculating the priority score of each task and arranging them in descending order to generate a scheduling queue includes: A computing power autonomous decision engine is deployed at the kernel layer of the industrial control motherboard operating system. The computing power autonomous decision engine receives the resource status matrix and the task descriptor at the current moment, sets corresponding weight factors for each evaluation dimension, and combines the above weight factors into a comprehensive evaluation function. Based on the comprehensive evaluation function, the decision engine performs a quantitative evaluation of each task to be scheduled and calculates the computing power allocation priority score for that task. Based on the computing power allocation priority score, the decision engine arranges all tasks to be scheduled in descending order of priority score from high to low to form a task scheduling queue. During execution, the autonomous decision-making engine continuously monitors the current occupancy value of each dimension in the resource status matrix. If any resource status indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is triggered, the current resource status matrix and task descriptor are reread, the priority score of each task is recalculated, and the scheduling queue is regenerated.

[0041] Specifically, the evaluation dimensions include: task priority weight, resource matching weight, heat risk weight, and time urgency weight, which respectively reflect the criticality of the task, the matching status of resource supply and demand, the temperature risk level, and the time urgency. Specifically, the weight factor of the task priority is assigned according to the criticality level in the task descriptor. The weight factor of safety-critical tasks is the highest and the weight factor of auxiliary analysis tasks is the lowest. The weight factor does not change with the working conditions. The weight factor of the resource matching degree is calculated based on the comparison between the historical resource consumption of the task and the current available resource quantity in the resource status matrix. The higher the current available resource quantity and the higher the matching degree with the historical requirements of the task, the higher the value of the weight factor. The weighting factor for the heat risk is calculated based on the current temperature state vector in the resource state matrix and the average temperature change during the historical execution of the task. The higher the current temperature and the greater the historical heat generation of the task, the lower the weighting factor value. The weighting factor for the timeliness urgency is calculated based on the maximum tolerable delay in the task descriptor and the remaining margin of the current waiting time. The shorter the remaining time, the higher the weighting factor value. In this embodiment, the autonomous computing power decision engine is deployed in the kernel layer of the industrial control motherboard operating system. It reads the heterogeneous computing power resource status matrix at the current moment from the computing power awareness and protection module, and reads the task descriptors of all tasks to be scheduled from the task feature database. It sets weight factors for four evaluation dimensions: task priority, resource matching degree, heat risk and time urgency. The task priority weight factor is directly assigned according to the criticality level in the task descriptor, with the highest value for safety-critical tasks and the lowest value for auxiliary analysis tasks. The resource matching degree weighting factor is calculated by comparing the historical average NPU utilization rate and historical average memory bandwidth consumption of the task with the current available NPU computing power and available memory bandwidth in the resource status matrix. The higher the current available resources are and the higher the degree of matching with the historical needs of the task, the higher the value will be. The heat risk weight factor is calculated based on the temperature state vector in the resource state matrix and the average temperature change during the historical execution of the task. The higher the current temperature and the greater the historical heat generation of the task, the lower the value. The timeliness urgency weighting factor is calculated based on the remaining time margin obtained from the difference between the maximum tolerable inference delay in the task descriptor and the current waiting time. The smaller the remaining margin, the higher the value. The above four weighting factors are combined into a comprehensive evaluation function. The decision engine sequentially inputs the task descriptor and resource status matrix of each task to be scheduled into this function, quantifies and scores it in each of the four dimensions, multiplies it by the corresponding weighting factor, and then sums the results to obtain the computing power allocation priority score of the task. After all tasks to be scheduled have completed the score calculation, they are arranged in descending order of score to generate a task scheduling queue. During the scheduling cycle, the decision engine continuously monitors the current occupancy value of each dimension in the resource status matrix. Once any resource status indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is immediately triggered. The current resource status matrix and task descriptor are reread, and the priority scores of each task are recalculated according to the same process, and the scheduling queue is regenerated to ensure that the scheduling order is always consistent with the real-time status of the system.

[0042] In this embodiment, four interrelated scheduling factors—task criticality, resource supply and demand matching, temperature risk, and timeliness—are unified into a single comprehensive evaluation function for quantitative ranking. The calculation is based on historical execution data in the task descriptor and real-time availability in the resource status matrix, ensuring that the priority score simultaneously reflects the static importance of the task, dynamic resource requirements, and current system remaining capacity. This avoids scheduling biases caused by single-dimensional decision-making. Furthermore, the dynamic rescheduling mechanism, triggered by a threshold of resource status indicators, allows the scheduling queue to update rapidly when the system status changes significantly. This reduces task timeouts and resource contention caused by scheduling results lagging behind resource changes, thereby lowering the probability of high-priority tasks exceeding inference delay limits due to resource contention or temperature risk, and improving the overall stability and operational efficiency of the system.

[0043] Specifically, the process of generating a resource allocation scheme based on the scheduling queue and the available resource quantity, and verifying the feasibility of the scheme to ensure that the on-chip resources do not exceed the safety threshold and meet the requirements of the highest priority task includes: The autonomous computing decision engine allocates corresponding computing resources to each task in turn according to the order of tasks in the scheduling queue and the available resources of each computing unit in the current resource status matrix, thereby generating a resource allocation scheme. Feasibility verification is performed based on the aforementioned allocation scheme; If any verification item fails, the task quota of the lower priority level in the current failed allocation scheme will be reduced in order of priority from low to high. The allocation scheme will be regenerated and the feasibility will be verified again until all verification items pass. If any resource status indicator, such as CPU utilization, NPU engine utilization, memory bandwidth utilization, or temperature, exceeds the preset adjustment threshold, dynamic rescheduling is triggered. The decision engine rereads the current resource status matrix and task descriptor, regenerates the scheduling queue, and re-executes the generation and verification of the resource allocation scheme. Specifically, the resource allocation scheme includes the CPU core number and time slice quota bound to each task, the NPU inference engine number and computing time window occupied, the GPU computing resource quota, and the memory bandwidth reservation ratio. During the execution of the resource allocation scheme, the computing power awareness and protection module continuously updates the resource status matrix at a sampling period; Specifically, the verification content includes that the total time slices allocated to each CPU core do not exceed the available time of the corresponding core, the NPU computing time windows of each task do not overlap, the total memory bandwidth reserved for all tasks does not exceed the set safety threshold of the total bandwidth, and the resource requirements of the highest priority core control task must be fully met. In this embodiment, the autonomous decision engine for computing power reads the available resources of each computing unit from the current resource status matrix according to the order of each task in the scheduling queue, and allocates CPU core number and time slice quota, NPU inference engine number and computing time window, GPU computing resource quota and memory bandwidth reservation ratio to each task in turn to generate a resource allocation scheme. The feasibility of the scheme is verified. The verification process includes extracting the current utilization rate of each CPU core from the resource status matrix, comparing the sum of all task time slices allocated to the core with the available time of the core in the scheduling cycle to ensure that it does not exceed the upper limit of available time, checking whether the NPU computing time windows of each task overlap on the time axis, and calculating the total memory bandwidth reservation ratio of all tasks to determine whether it exceeds the set safety threshold of the total bus bandwidth. It also verifies whether the CPU, NPU and memory bandwidth resources required by the highest priority tasks are fully met. If any verification fails, the resource quota of low priority tasks such as auxiliary analysis tasks in the current allocation scheme is reduced in order of priority from low to high, the allocation scheme is regenerated and the above verification is performed again, and the process is repeated until all verification items pass. During the execution of the solution, the computing power awareness and protection module continuously updates the resource status matrix at the sampling period. The decision engine synchronously monitors the CPU utilization, NPU engine utilization, memory bandwidth utilization and temperature status indicators. Once any indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is immediately triggered. The current resource status matrix and task descriptor are reread, the scheduling queue is regenerated, and the resource allocation scheme generation and verification process is repeated to ensure that the allocation result always meets the real-time resource constraints.

[0044] In this embodiment, the scheduling queue is directly combined with the current real-time available resources. CPU time slices, NPU computing time windows, GPU resource quotas, and memory bandwidth reservation ratios are allocated sequentially according to the priority of each task. This ensures that the resource allocation scheme is always based on the actual remaining resources. Simultaneously, multiple feasibility checks are performed, including ensuring that the total CPU core time slices do not exceed the available time, that NPU computing time windows do not overlap, that the total memory bandwidth reservation does not exceed a safety threshold, and that the resource requirements of the highest priority tasks are fully met. This ensures that the resource allocation scheme will not lead to on-chip resource overload or the squeezing out of high-priority task resources. Furthermore, if any check fails... The system reduces the quota of low-priority tasks in ascending order of priority and re-verifies them, ensuring that the execution of safety-critical tasks is prioritized when resources are scarce. The dynamic rescheduling mechanism is triggered when resource status indicators such as CPU utilization, NPU engine utilization, memory bandwidth utilization, or temperature exceed preset adjustment thresholds. When abnormal changes occur in the system status, the scheduling queue and resource allocation scheme are immediately regenerated, ensuring that resource allocation is always synchronized with the real-time resource status. This reduces the risk of task timeouts, equipment overheating, or scheduling failures caused by resource allocation exceeding safety thresholds, and improves the system's security, stability, and operational efficiency at the resource allocation level.

[0045] Specifically, the process of determining whether to switch the current computing power allocation strategy to the next level temperature response strategy based on whether the temperature status index in the computing power resource status matrix reaches a preset threshold includes: Obtain the current junction temperature value and monitor the chip junction temperature in real time; The current junction temperature value is compared with the threshold values ​​at each level in the preset temperature threshold set to determine the current temperature state range of the system. The temperature state range is divided into normal state, warning state and restricted state, and each state range corresponds to a different computing power allocation strategy. When the system is determined to be in a normal state, the current full computing power scheduling strategy remains unchanged; when the junction temperature is detected to rise to the level of entering the warning state, the current computing power allocation strategy is switched to the preventive degradation strategy; when the junction temperature is detected to continue to rise to the level of entering the restricted state, the current computing power allocation strategy is switched to the restrictive degradation strategy. When the temperature drops back to the range where it exits the current state, the temperature response strategy is restored to the previous level in the reverse order of the downgrade. After each level is restored, an observation period is waited to confirm that the temperature is stable before continuing the restoration. The temperature state is determined based on the junction temperature of the CPU and NPU, and the state switching is triggered when the temperature reaches or exceeds the corresponding temperature threshold. Specifically, the preventive degradation strategy is to reduce the inference frequency of the third priority task, switch the second priority task to the lightweight model, and keep the resources of the first priority task unchanged; the restrictive degradation strategy is to suspend the third priority task, switch the second priority task to the ultra-lightweight model and further reduce its frequency, and switch the first priority task to the minimized inference model. The temperature recovery after the initial drop is carried out in the reverse order of the downgrade, with each level of recovery followed by an observation period to confirm that the temperature is stable before continuing the recovery process. The observation period consists of several consecutive sampling cycles, and the temperature is considered stable only if it remains below the exit threshold in each cycle.

[0046] In this embodiment, the computing power awareness and protection module reads the CPU junction temperature and NPU junction temperature from the onboard temperature sensor and the chip's internal junction temperature sensor at a set sampling period, and writes the values ​​into the temperature state vector of the resource state matrix. The computing power autonomous decision engine extracts the current CPU junction temperature and NPU junction temperature from the matrix and compares them step by step with the preset first, second, third and fourth temperature thresholds. If the CPU junction temperature is below the first temperature threshold and the NPU junction temperature is below the second temperature threshold, the system is determined to be in normal state and the current full computing power scheduling strategy is maintained. If the CPU junction temperature reaches the first temperature threshold or the NPU junction temperature reaches the second temperature threshold, the system is determined to enter the warning state, and the current computing power allocation strategy is switched to the preventive degradation strategy, that is, the inference frequency of the third priority tasks is reduced and the inference cycle is extended to a set multiple of the original cycle, the lightweight alternative model is enabled for the second priority tasks, and the resource allocation of the first priority tasks remains unchanged. If the CPU junction temperature continues to rise to the third temperature threshold or the NPU junction temperature reaches the fourth temperature threshold, the system is determined to enter the restricted state, and the current computing power allocation strategy is switched to the restrictive degradation strategy, that is, all third priority tasks are suspended, the inference frequency of the second priority tasks is further reduced and the ultra-lightweight alternative model is enabled, and the first priority tasks are switched to the minimized inference model. When the temperature drops to the point where the CPU junction temperature is below the exit threshold corresponding to the current state interval and the NPU junction temperature is below the corresponding exit threshold, the system recovers step by step in the reverse order of degradation. Task resources at each level are recovered in descending order of priority. After each priority level is recovered, an observation period consisting of several consecutive sampling cycles is entered. During the observation period, the CPU junction temperature and NPU junction temperature are continuously read. Temperature stability is determined only when the temperature is below the exit threshold in each sampling cycle, and the next priority level is recovered until the system returns to the previous level temperature response strategy or the normal full scheduling strategy. If the temperature exceeds the exit threshold in any cycle during the observation period, the system waits again to avoid repeated strategy switching caused by temperature fluctuations.

[0047] In this embodiment, the junction temperatures of both the CPU and NPU are used as the core basis for temperature status determination. By comparing the junction temperature with multi-level thresholds, the system temperature status is divided into normal, warning, and restricted states. This allows the computing power degradation response to directly follow the actual thermal state changes of the chip, avoiding misjudgments and response delays caused by relying solely on a single temperature point or non-core area temperature. At the same time, different graded degradation measures are implemented for different priority tasks, such as reducing inference frequency, switching lightweight models, and pausing execution. Under high temperature conditions, computing power contraction is prioritized for auxiliary analysis tasks while maintaining the core inference capability of safety-critical tasks. Furthermore, the recovery process is carried out in the reverse order of degradation, with each level having an observation period consisting of continuous sampling periods. This effectively prevents temporary fluctuations during temperature drop from causing repeated strategy switching, improving the stability and accuracy of the temperature-driven autonomous degradation and recovery mechanism. It also reduces the risk of device overheating and the probability of high-priority task inference interruption caused by sudden temperature changes or delayed status determination.

[0048] Specifically, the process of performing kernel-level resource allocation based on the allocation scheme, binding first-priority tasks to dedicated CPU cores and ensuring bandwidth, and allocating dedicated NPU time windows to each task includes: According to the resource allocation scheme, the autonomous computing power decision engine sends CPU core binding instructions and time slice quota configuration instructions to the operating system kernel CPU scheduler, binds the first priority level of safety-critical tasks to the designated CPU core and runs them in exclusive mode, and allocates the second priority level and third priority level tasks to the remaining CPU cores and schedules them in time according to priority. Send inference time window allocation instructions to the NPU driver to assign corresponding NPU inference engine numbers and computation time windows to each task, so that the NPU executes only one task's inference computation within the same time window; Send a bandwidth reservation configuration command to the memory controller, reserve guaranteed bandwidth for the data access path of the first priority level tasks through the service quality configuration interface of the memory controller, allocate proportional bandwidth for the second priority level tasks, and use the remaining available bandwidth for the third priority level tasks.

[0049] The exclusive mode means that the time slice resources of the CPU core are completely occupied by the bound task, and other tasks are not allowed to be scheduled and run on the core. The time-sharing scheduling refers to multiple tasks using the time slice resources of the same CPU core in order of priority from high to low. The inference time window is a continuous time interval in which the NPU engine is dedicated to performing inference calculations for a specified task. The inference time windows of different tasks do not overlap. The guaranteed bandwidth is a memory access channel with the highest priority in the memory arbitration layer, which is set for a specified task through the QoS register of the memory controller, and its bandwidth quota is always satisfied at any time.

[0050] In this embodiment, the autonomous decision-making engine extracts the CPU core number and time slice quota, NPU inference engine number and computing time window, and memory bandwidth reservation ratio corresponding to each task from the current resource allocation scheme. Based on the above parameters, it sends CPU core binding instructions and time slice quota configuration instructions to the operating system kernel CPU scheduler. Through the kernel CPU affinity interface, it binds the first priority level safety-critical tasks to the specified CPU core and configures the scheduling queue of the core to allow only the bound tasks to run, and prohibits other tasks from migrating to the core to achieve exclusive access. Second-priority and third-priority tasks are allocated to the remaining CPU cores and use the time slice resources of the same core in order of priority. Higher-priority tasks get the time slice quota first, and the remaining time slices are used by lower-priority tasks. The scheduler maintains the ready queue of each core based on the priority field in the task descriptor. Send inference time window allocation instructions to the NPU driver, establish a time window allocation table for each inference engine in the NPU driver layer, and label each time window with the corresponding task identifier, inference engine number and start and end time. The time windows of the same inference engine do not overlap on the time axis. The NPU scheduler executes only the inference calculation of the corresponding task in the specified interval according to the time window table, avoiding the uncertainty of latency caused by multi-task concurrency. Send a memory bandwidth reservation configuration command to the memory controller, write the bandwidth quota of each priority to the QoS register through the memory controller QoS configuration interface, set the guaranteed bandwidth for the data access path of the first priority level task, assign the highest priority at the memory arbitration layer, and its bandwidth quota will be given priority at any time, set the proportional bandwidth for the second priority level task, and do not set reservation for the third priority level task, only use the remaining available bandwidth. The time slice quota in each instruction is calculated by dividing the time slice length of the task in the resource allocation scheme by the scheduling cycle. The memory bandwidth reservation value is written to the register after multiplying the reservation ratio by the theoretical peak bandwidth of the bus. During execution, the computing power awareness guardian module continuously updates the resource status matrix at the sampling period. The decision engine monitors each resource status indicator. If any indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is triggered and the allocation scheme is regenerated and the allocation is executed.

[0051] In this embodiment, by binding CPU cores at the kernel level, the first-priority safety-critical tasks are run exclusively on designated cores, ensuring that their time slice resources are not preempted by other tasks. Simultaneously, NPU inference time window allocation guarantees that the same inference engine executes only a single task within the same time window, greatly reducing latency uncertainties caused by concurrent inference of multiple tasks. Furthermore, the memory controller's quality of service configuration interface sets a guaranteed bandwidth with the highest arbitration priority for the data access path of the first-priority tasks, ensuring deterministic resource guarantees for high-priority tasks in CPU computation, NPU inference, and memory access. Second-priority tasks receive bandwidth proportionally, while third-priority tasks use only the remaining bandwidth, achieving orderly isolation of heterogeneous computing resources among multiple tasks. The computing power awareness and protection module continuously updates the resource status matrix during allocation and execution, enabling the decision engine to trigger dynamic rescheduling and timely adjust allocation when any resource indicator exceeds its limit. This effectively reduces the risk of high-priority task inference timeouts caused by resource contention, overlapping time windows, or bandwidth preemption.

[0052] Specifically, the process of polling and detecting the feature information of a single regular task module, and determining whether to switch the corresponding single regular task module to a lightweight task module based on the feature information, includes: The current running status information and current temperature status index of each task module are polled and checked. Based on the current running status information and current temperature status index, it is determined whether each task module meets the conditions for switching to the corresponding lightweight model. When any task module meets the switching condition, the inference model of the task module is switched from the current model to the target lightweight model.

[0053] The switching conditions include temperature triggering conditions and task status triggering conditions; Specifically, the temperature trigger condition is when the current temperature status indicator reaches the temperature threshold corresponding to the warning state or the restriction state; the task status trigger condition is when the current inference frequency of the task module is lower than the preset lower limit, or the current model inference time exceeds the preset maximum tolerable delay, or the task module is currently in an idle waiting state and is about to enter a new round of inference cycle. Specifically, the target lightweight model is a deployed backup model, including a lightweight model suitable for the early warning state, an ultra-lightweight model suitable for the restricted state, and a minimized inference model that retains only the core functions.

[0054] In this embodiment, the computing power awareness and protection module polls and checks the current running status information and current temperature status index of each task module at a set sampling period. The running status information is read from the dynamic fields of each task descriptor in the task feature database, including the current inference frequency, the time spent on the most recent model inference, and the current status of the task module. The temperature status index is read from the temperature status vector in the resource status matrix. The system compares the current temperature status index with the temperature thresholds corresponding to the warning and restriction states to determine whether the temperature triggering conditions are met. At the same time, it determines whether the task status triggering conditions are met. The task status triggering conditions include the current inference frequency being lower than the preset lower limit, the current model inference time exceeding the preset maximum tolerable delay, or the task module being in an idle waiting state and about to enter a new round of inference cycle. When any task module meets the temperature trigger condition or task state trigger condition, the autonomous decision engine selects a target lightweight model corresponding to the current temperature state range from the deployed set of backup models. The warning state corresponds to the lightweight model, the restricted state corresponds to the ultra-lightweight model, and the minimum inference model corresponds to the model when only core functions are retained. The engine then notifies the task module to perform a model switching operation, updates the model identifier field in the task descriptor, and re-registers the model handle in the NPU driver so that subsequent inference calculations use the target lightweight model. After the switch is completed, the engine continues to monitor the running status and temperature indicators of the task module. If the condition is lifted, the engine switches back to the original model according to the recovery strategy.

[0055] In this embodiment, temperature status indicators and the real-time operating status of task modules are used simultaneously as triggering conditions for lightweight model switching. This ensures that model degradation is not only driven by the system's thermal state but also comprehensively judged based on the task's inference frequency, inference time, and idle status. This avoids degradation lag or over-degradation caused by triggering solely based on temperature thresholds. Furthermore, tiered backup models are pre-deployed, and the corresponding lightweight model is selected based on the temperature range and task status, achieving a step-by-step adaptation from mild to extreme degradation. This minimizes computing power and heat consumption while ensuring the core inference capabilities of safety-critical tasks. During model switching, task descriptors and NPU driver registration are updated synchronously to ensure consistency of scheduling resource information after switching. This improves the targeting and real-time performance of the temperature-driven degradation strategy, reduces the risk of task inference interruption due to improper switching timing or model mismatch, and enhances the system's stability and operating efficiency under high-temperature conditions.

[0056] Specifically, the process of determining whether to enable the elastic node pool includes: After all local computing power degradation measures have been executed, the computing power autonomous decision engine reads the current network status parameters and edge server resource status parameters to obtain network latency, available bandwidth, round-trip latency and available computing power of the edge server. If the network latency is lower than the predetermined threshold, the amount of data transmitted is less than the product of the current available bandwidth and the round-trip latency, and the available computing power of the edge server is greater than the computing power requirement of the task to be unloaded, then the unloading conditions are met, the elastic node pool is activated, and some inference tasks are unloaded to the elastic node pool for execution. If any condition is not met, the unloading condition is determined to be unmet, and the local minimal inference mode continues to run, while continuously monitoring the network status and edge server resource status until the condition is met or the local computing power is restored.

[0057] The degradation methods include reducing inference frequency, switching to a lightweight model, switching to an ultra-lightweight model, and switching to a minimized inference model. The statement that the local computing power is still insufficient to meet the minimum inference requirements of the first priority task means that, under the minimized inference model operation, the actual inference frame rate of the first priority task is still lower than the minimum frame rate threshold required for safe operation. Specifically, the elastic node pool refers to a collection of one or more pre-deployed external computing nodes, including edge servers located on the same local area network as the industrial control motherboard, and cloud computing nodes; After all local degradation measures have been executed, if the minimum inference requirements of the first priority task still cannot be met, and the current network latency, the amount of data to be transmitted, and the available computing power of the node meet the offloading conditions, the decision engine will offload at least some inference tasks to the elastic node pool for execution, as a supplementary source of computing power when local computing power is insufficient.

[0058] In this embodiment, after all local computing power degradation measures have been executed, the autonomous computing power decision engine reads the current network status parameters from the kernel network protocol stack, including the network latency measured by TCP connection round-trip time, the current available bandwidth and round-trip latency obtained by the network card statistics interface, and queries the edge server to obtain the available computing power of the edge server through the control channel between the edge server and the edge server. The available computing power of the edge server is obtained by summing the number of idle CPU cores, NPU idle computing power and GPU idle video memory reported by the resource manager on the edge server according to the conversion factor. The decision engine compares network latency with a predetermined threshold, which is set as the upper limit of acceptable one-way latency of the link from the local server to the edge server. It compares the estimated amount of data to be transmitted by the task to be unloaded with the product of the available bandwidth and round-trip latency at that moment. The amount of data to be transmitted is the sum of the input data size and intermediate results of a single inference of the task to be unloaded multiplied by the unloading frequency per unit time. At the same time, it compares the available computing power of the edge server with the computing power requirement of the task to be unloaded. The computing power requirement of the task to be unloaded is calculated by multiplying the historical average NPU utilization rate in the task descriptor with the total computing power of the local NPU. If the network latency is lower than the predetermined threshold, the amount of data transmitted is less than the product of the current available bandwidth and the round-trip latency, and the available computing power of the edge server is greater than the computing power requirement of the task to be unloaded, then the unloading conditions are met. The decision engine starts the elastic node pool, which is a pre-deployed set of external computing nodes including edge servers and cloud computing nodes in the same local area network. It selects some inference tasks from the scheduling queue to unload to the elastic node pool for execution. During the unloading process, the task descriptor and the current input data are packaged and sent to the target node through a secure channel. The target node performs inference and returns the result. If any condition is not met, the unloading condition is determined to be unmet. The decision engine continues to operate in local minimal inference mode and continuously monitors the network status and edge server resource status at a set period until the condition is met or the local computing power is restored to meet the minimum inference requirements of the first priority task.

[0059] In this embodiment, the feasibility of offloading is determined by a triple condition of network latency, data transmission volume, and available computing power of the edge server. This ensures that the elastic node pool is only activated when both network conditions and remote computing power are met, avoiding offloading failures and additional delays due to insufficient network or remote resources. Meanwhile, the elastic node pool includes local area network edge servers and cloud nodes, providing a hierarchical supplementary computing power source for the industrial control motherboard. The packaged transmission of task descriptors and input data during the offloading process ensures that remote nodes can accurately execute inference tasks, thereby guaranteeing the continuous operation of safety-critical tasks in extreme local degradation scenarios and reducing the risk of interruption of first-priority task inference due to insufficient local computing power.

[0060] Specifically, the process of recording execution parameters to form historical samples, periodically calculating deviations and updating evaluation function weights, and determining the parameters to be used after replay verification includes: After each round of scheduling is completed, the computing power awareness guardian module records the actual inference time, actual NPU utilization, actual memory bandwidth consumption and temperature change during execution of each task, forming a historical sample of task scheduling, which is then stored in the historical database in association with the corresponding resource status matrix and allocation scheme. When the set update cycle arrives, the samples in the historical database are used as training data to calculate the deviation between the expected resource consumption and the actual resource consumption of each task. The weight adjustment gradient is constructed according to the direction and magnitude of the deviation, and the weight factors in the evaluation function are incrementally updated under the set stability boundary constraints. The updated evaluation function is applied to the historical sample set for replay verification. The scheduling scheme corresponding to each sample is recalculated. If the regenerated scheduling scheme improves both resource utilization and on-time task completion rate compared to the historical actual execution scheme, the update is confirmed to be effective and the new weights are saved. If any indicator does not improve or decreases, then abandon this update and revert to the previous version's weighting factor; Specifically, the historical database is deployed in the non-volatile storage medium of the industrial control motherboard; The update cycle is determined based on the pre-set round scheduling cycle; The replay verification uses the same resource state matrix as the historical actual execution as the input condition to eliminate the impact of changes in operating conditions on the verification results. In this embodiment, after each round of scheduling is completed, the actual inference time, actual NPU utilization, actual memory bandwidth consumption, and temperature change during execution of each task are read from the task execution log, kernel performance counter, and temperature sensor. The above data are associated with the resource status matrix and resource allocation scheme at the beginning of the scheduling round and written as a task scheduling history sample into the historical database deployed in the non-volatile storage medium of the industrial control motherboard. The update cycle is determined according to the preset number of scheduling rounds. After the update cycle is reached, the system uses samples in the historical database as training data to read the expected resource consumption and actual resource consumption of each task in the corresponding round. The expected resource consumption is calculated by combining the NPU computing time window and memory bandwidth reservation ratio allocated in the resource allocation scheme with the historical average utilization rate in the task descriptor. The actual resource consumption is taken from the sample field. The deviation between the two is calculated and the deviation direction is recorded. The deviation direction includes whether the actual consumption is higher or lower than expected. The adjustment gradient of each weight factor is constructed according to the deviation direction and deviation magnitude. For example, when the resource matching degree weight is too low, the actual consumption is generally higher than expected. The adjustment is made in the direction of increasing the weight. The gradient magnitude is proportional to the deviation magnitude. At the same time, within the preset stability boundary constraints, the four weight factors of task priority, resource matching degree, heat risk and time urgency are incrementally updated. The amount of a single update does not exceed the boundary limit. The updated evaluation function is applied to the historical sample set for playback verification. For each sample, the same resource state matrix and task descriptor as the sample record are used as input conditions. The priority score of each task is recalculated and a scheduling plan is generated. The changes in resource utilization and on-time task completion rate are compared between the newly generated scheduling plan and the historical actual execution plan. If both indicators improve, the update is confirmed to be effective and the new weights are saved to the historical database. If either indicator does not improve or decreases, the update is abandoned and the previous version of the weight factor is rolled back to ensure the correctness of the evaluation function update direction.

[0061] In this embodiment, the continuous optimization process of the scheduling strategy is fully integrated into the system's autonomous closed loop. After each round of scheduling execution, the computing power awareness and protection module automatically records the actual inference time, NPU utilization, memory bandwidth consumption, and temperature variation of each task, and associates this data with the resource status and allocation scheme of the current round to form historical samples. This allows for the accumulation of training data reflecting real-world operating conditions without manual annotation or external intervention. Upon reaching a preset update cycle, the system automatically calculates the deviation between expected and actual resource consumption based on these historical samples. It then autonomously constructs a weight adjustment gradient based on the direction and magnitude of the deviation, incrementally updating each weight factor in the evaluation function under stability boundary constraints. This enables the evaluation function to automatically correct itself as operating conditions change. The new evaluation function regenerates the scheduling scheme under the same resource state input conditions through replay verification, and automatically compares it with the historical actual execution scheme in terms of resource utilization and task on-time completion rate. The update is confirmed to be effective and the new weights are saved only when both indicators are improved; otherwise, it automatically reverts to the previous version. The entire process constitutes a complete autonomous optimization loop from execution to recording, from recording to evaluation, from evaluation to update, from update to verification, and from verification to effectiveness or reversion. This allows the system to gradually approach a better scheduling strategy without manual parameter tuning, enhancing the adaptive ability of the edge AI computing power autonomous system to changes in task load, fluctuations in resource state, and temperature disturbances, and improving the accuracy, stability, and autonomy of scheduling decisions under long-term operation.

[0062] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A method for autonomous edge AI computing power of industrial control motherboards based on system-level scheduling, characterized in that, include: Based on the predetermined period, multi-dimensional resource status data of the target industrial control motherboard is collected to construct a heterogeneous computing power resource status matrix and calculate the available resource quantity of each computing unit. Based on the heterogeneous computing power resource status matrix, calculate the priority score of each task and arrange them in descending order to generate a scheduling queue; Based on the scheduling queue, a resource allocation scheme is generated in combination with the available resource quantity, and the feasibility of the scheme is verified. Based on the feasibility verification, determine whether to switch the current computing power allocation strategy to the next level temperature response strategy. Poll and check the feature information of a single regular task module, and based on the feature information, determine whether to switch the corresponding single regular task module to a lightweight task module; Based on network latency, data transmission volume, and available computing power of edge servers, determine whether to enable the elastic node pool.

2. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, The process of calculating the available resources for each computing unit includes: A computing power awareness and protection module is deployed in the kernel space of the industrial control motherboard operating system. The computing power awareness and protection module collects multi-dimensional resource status data at a set sampling period. A heterogeneous computing power resource status matrix is ​​formed based on the combination of the multidimensional resource status data, and the available resource quantity of each computing unit is calculated according to the current occupancy value and the corresponding total amount of each dimension. The resource status matrix and available resource quantity are continuously updated at a set sampling period; The multidimensional resource status data is collected through the kernel performance counter, NPU driver register interface, GPU driver interface, memory controller performance monitoring unit and onboard temperature sensor respectively. The multidimensional resource status data includes the utilization rate and interrupt response latency of each CPU core, the NPU inference queue depth and engine utilization, the GPU rendering load and video memory usage, the DDR read / write bandwidth utilization and cache hit rate, and the junction temperature and PCB temperature of each functional module.

3. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, The process of calculating the priority score for each task includes: Extract task feature data for each inference task; Based on the task feature data, a corresponding task descriptor is created for each inference task, and priority levels are assigned to each task according to the degree of impact of the inference results on equipment safety, product quality, or data statistics. The task descriptor and priority level are input into the task feature database for storage, and the corresponding historical parameters are continuously updated. The task feature data includes the model identifier, input data size, expected inference cycle, and maximum tolerable inference latency for each inference task.

4. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, The process of generating a scheduling queue by arranging data in descending order includes: Deploy a computing power autonomous decision-making engine at the kernel layer of the industrial control motherboard operating system, and combine and construct a comprehensive evaluation function; The priority score is calculated for each task to be scheduled using the comprehensive evaluation function. All tasks to be scheduled are then arranged in descending order of their scores to generate a scheduling queue. The autonomous decision-making engine continuously monitors the current occupancy value of each dimension in the resource status matrix; If any resource status indicator is detected to exceed the preset adjustment threshold, dynamic rescheduling is triggered, the priority scores of each task are recalculated, and the scheduling queue is regenerated.

5. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 2, characterized in that, The process of generating a resource allocation plan based on available resources and verifying the feasibility of the plan includes: The autonomous computing decision engine allocates corresponding computing resources to each task in turn according to the order of tasks in the scheduling queue and the available resources of each computing unit in the current resource status matrix, thereby generating a resource allocation scheme. Feasibility verification is performed based on the aforementioned allocation scheme; If any verification item fails, the task quota of the lower priority level in the current failed allocation scheme is reduced according to the priority level, the allocation scheme is regenerated and the feasibility is verified again until all verification items pass. The resource allocation scheme includes the CPU core number and time slice quota bound to each task, the NPU inference engine number and computing time window occupied, the GPU computing resource quota, and the memory bandwidth reservation ratio. During the execution of the resource allocation scheme, the computing power awareness and protection module continuously updates the resource status matrix at sampling intervals.

6. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, The process of determining whether to switch the current computing power allocation strategy to the next level of temperature response strategy includes: The chip junction temperature is monitored in real time, and the current junction temperature is compared with a preset temperature threshold to determine the temperature range in which the system is located. The temperature state range is divided into normal state, warning state and restricted state, and each state range corresponds to a different computing power allocation strategy. When the temperature drops back to the range where it exits the current state, the temperature response strategy is restored to the previous level in the reverse order of the downgrade. After each level is restored, an observation period is waited to confirm that the temperature is stable before continuing the restoration. The temperature state is determined based on the junction temperature of the CPU and NPU, and the state switch is triggered when the temperature reaches or exceeds the corresponding temperature threshold.

7. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, Based on the aforementioned allocation scheme, kernel-level resource allocation is performed, with first-priority tasks bound to dedicated CPU cores and bandwidth guaranteed. The process of allocating dedicated NPU time windows to each task includes: The autonomous computing decision engine sends CPU core binding instructions and time slice quota configuration instructions according to the resource allocation scheme. Send an inference time window allocation command to assign a corresponding NPU inference engine number and computation time window to each task, so that the NPU executes only one task's inference computation within the same time window; Send a bandwidth reservation configuration command to reserve guaranteed bandwidth for the data access path of the first priority level tasks through the service quality configuration interface of the memory controller, allocate proportional bandwidth for the second priority level tasks, and use the remaining available bandwidth for the third priority level tasks. Among them, the exclusive mode means that the time slice resources of the CPU core are completely occupied by the bound task, and other tasks are not allowed to be scheduled and run on the core. Time-sharing scheduling refers to multiple tasks using the time slice resources of the same CPU core in order of priority from highest to lowest. The inference time window is a continuous time interval in which the NPU engine is dedicated to performing inference calculations for a specified task. The inference time windows of different tasks do not overlap. The guaranteed bandwidth is a memory access channel with the highest priority in the memory arbitration layer, which is set for a specified task through the QoS register of the memory controller, and its bandwidth quota is always satisfied at any time.

8. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, The process of polling and detecting feature information of a single regular task module includes: Poll and check the current running status information and current temperature status indicators of each task module; Based on the current operating status information and the current temperature status index, determine whether each task module meets the conditions for switching to the corresponding lightweight model; When any task module meets the switching condition, the inference model of the task module is switched from the current model to the target lightweight model; The switching conditions include temperature triggering conditions and task status triggering conditions.

9. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 1, characterized in that, The process of determining whether to enable the elastic node pool includes: After all local computing power degradation measures have been executed, the minimum inference requirements of the first priority task still cannot be met. The computing power autonomous decision engine reads the current network status parameters and edge server resource status parameters, and determines whether to execute the unload decision based on the network status parameters and edge server resource status parameters. If the network latency is lower than the predetermined threshold and the amount of data transmitted is less than the product of the current available bandwidth and the round-trip latency, and the available computing power of the edge server is greater than the computing power requirement of the task to be unloaded, then it is determined to enable the elastic node pool and unload some inference tasks to the elastic node pool for execution.

10. The autonomous edge AI computing power method for industrial control motherboards based on system-level scheduling according to claim 5, characterized in that, Also includes: The computing power awareness and protection module records the actual inference time, actual NPU utilization, actual memory bandwidth consumption, and temperature change during execution for each task, forming a historical sample of task scheduling. Using samples from the historical database as training data, the deviation between the expected resource consumption and the actual resource consumption of each task is calculated. The weight adjustment gradient is constructed according to the direction and magnitude of the deviation. Under the constraint of setting stability boundary, the weight factors in the evaluation function are incrementally updated. The updated evaluation function was applied to the historical sample set for replay verification.

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