Debugging system, method, electronic device, storage medium, and program product
Patent Information
- Application Number
- CN202510360230.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-09-29
AI Technical Summary
[0004]但是，现有技术的调试方法，难以满足不同应用场景下的调试需求，从而延长了系统级芯片的开发周期，并增大了维护难度和开发成本
[0061]本申请实施例提供的调试系统、方法、电子设备、存储介质及程序产品，通过调试主机根据用户输入的调试指令生成调试信息，将调试信息写入调试模块，并控制调试模块向调试处理器发送调试触发信号，以使调试处理器在接收到调试触发信号后，轮询调试模块中的调试信息是否写入完成，并在确定写入完成时，根据获得的调试信息进行对应的调试操作，以完成调试指令指示的调试任务。满足了用户在不同场景下的调试需求，降低了调试过程的复杂性和对调试功能的升级难度，进一步提升了调试效率，降低系统级芯片的开发周期和开发成本。
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Abstract
Description
Technical Field
[0001] This application relates to the field of computers, and more particularly to a debugging system, method, electronic device, storage medium, and program product. Background Technology
[0002] The RISC-V debug subsystem is an invasive chip hardware debug system for system-level chip hardware debugging of the RISC-V architecture, which includes a debug host, debug transport hardware, and a debug module.
[0003] Existing technologies are based on hardware debugging modules to debug RISC-V architecture system-on-a-chip. When the debugging module receives a debugging command, it performs a series of hardware debugging functions according to the instructions of the debugging command, such as monitoring the processor status, viewing general-purpose registers, single-step execution, memory breakpoints, conditional breakpoints, memory read / write, and other debugging functions.
[0004] However, existing debugging methods are insufficient to meet the debugging needs of different application scenarios, thus extending the development cycle of system-on-a-chip and increasing maintenance difficulty and development costs. Summary of the Invention
[0005] This application provides debugging systems, methods, electronic devices, storage media, and program products to reduce the development cycle and cost of system-on-a-chip (SoC) and to reduce the difficulty of upgrades and maintenance.
[0006] In a first aspect, embodiments of this application provide a debugging system, including:
[0007] The debugging host is used to receive debugging commands input by the user, generate debugging information based on the debugging commands, and write the debugging information into the debugging module;
[0008] The debug processor receives debug trigger signals and determines whether debug information has been written completely based on the debug trigger signals. The debug information includes debug data and debug strategies. The debug trigger signals are sent by the debug host controlling the debug module. When it is determined that the debug information has been written completely, the debug data is processed based on the debug strategy to complete the debug task indicated by the debug command.
[0009] Optionally, the debug module includes multiple trigger registers;
[0010] The debugging host is also used for:
[0011] The debugging instructions are parsed, and the corresponding debugging functions are determined. The debugging functions are used to determine the trigger registers corresponding to the debugging instructions in the debugging module and control the trigger registers to send debugging trigger signals to the debugging processor. The debugging trigger signals include reset trigger signals, software trigger signals, and hardware trigger signals.
[0012] Optionally, the debug module includes static random access memory;
[0013] Static random access memory is used to store debugging information in the target debugging format written by the debugging host, which writes the debugging information by calling debugging functions.
[0014] Optionally, the debug processor includes a debug kernel and debug service software;
[0015] The debug processor, when determining whether debug information has been written completely, specifically uses the following:
[0016] Receive debug trigger signals by debugging the kernel;
[0017] Based on the debug trigger signal, the debug kernel controls the debug service software to poll the static random access memory in the debug module to determine whether the debug information has been written.
[0018] Optionally, after performing the debugging task, the debug processor is also used for:
[0019] A confirmation signal is generated and written to the static random access memory of the debug module, so that when the static random access memory receives a query command from the debug host, it sends a confirmation signal to the debug host.
[0020] The query command is sent by the debugging host after writing the debugging information corresponding to the debugging command into the static random access memory.
[0021] Secondly, embodiments of this application provide a debugging method applied to a debugging host, comprising:
[0022] Receive debugging commands from the user;
[0023] Debugging information is generated according to the debugging instructions, written to the debugging module, and the debugging module is controlled to send a debugging trigger signal to the debugging processor according to the debugging instructions. The debugging information includes debugging data and debugging strategy. The debugging processor receives the debugging trigger signal, determines whether the debugging information has been written, and processes the debugging data according to the debugging strategy when the debugging information has been written, so as to complete the debugging task indicated by the debugging instructions.
[0024] Optionally, the debug module includes multiple trigger registers; the method also includes:
[0025] The debugging instructions are parsed, and the corresponding debugging functions are determined. The debugging functions are used to determine the trigger registers corresponding to the debugging instructions in the debugging module and control the trigger registers to send debugging trigger signals to the debugging processor. The debugging trigger signals include reset trigger signals, software trigger signals, and hardware trigger signals.
[0026] Optionally, the debugging module includes static random access memory; the method further includes:
[0027] The debug information in the target debug format is written to the static random access memory by calling the debug function.
[0028] Thirdly, embodiments of this application provide a debugging method applied to a debugging processor, comprising:
[0029] The system receives a debug trigger signal and determines whether the debug information has been written completely based on the debug trigger signal. The debug information includes debug data and debug strategy, which are generated by the debug host according to the debug instructions received from the user and written into the debug module. The debug trigger signal is sent by the debug host controlling the debug module according to the debug instructions.
[0030] Once the debugging information writing is complete, the debugging data is processed based on the debugging strategy to complete the debugging task indicated by the debugging command.
[0031] Optionally, the debug module includes multiple trigger registers; the method also includes:
[0032] The debug trigger signal is received. The debug trigger signal is sent by the debug host after the debug host determines the trigger register corresponding to the debug instruction in the debug module based on the debug function. The debug function is determined by the debug host after parsing the debug instruction. The debug trigger signal includes reset trigger signal, software trigger signal and hardware trigger signal.
[0033] Optionally, the debug processor includes a debug kernel and debug service software; specifically, determining whether the debug information has been written completely includes:
[0034] Receive debug trigger signals by debugging the kernel;
[0035] Based on the debug trigger signal, the debug kernel controls the debug service software to poll the static random access memory in the debug module to determine whether the debug information has been written.
[0036] Optionally, after performing the debugging task, the following may also be included:
[0037] A confirmation signal is generated and written to the static random access memory of the debug module, so that when the static random access memory receives a query command from the debug host, it sends a confirmation signal to the debug host.
[0038] The query command is sent by the debugging host after writing the debugging information corresponding to the debugging command into the static random access memory.
[0039] Fourthly, embodiments of this application provide a debugging apparatus applied to a debugging host, comprising:
[0040] The first receiving module is used to receive debugging commands input by the user;
[0041] The first processing module is used to generate debugging information according to the debugging instructions, write the debugging information into the debugging module, and control the debugging module to send a debugging trigger signal to the debugging processor according to the debugging instructions. The debugging information includes debugging data and debugging strategy. The debugging processor receives the debugging trigger signal and determines whether the debugging information has been written based on the debugging trigger signal. When it is determined that the debugging information has been written, the debugging data is processed based on the debugging strategy to complete the debugging task indicated by the debugging instructions.
[0042] Optionally, the debug module includes multiple trigger registers;
[0043] The first processing module is also used to parse debugging instructions and determine the debugging function corresponding to the debugging instructions; wherein, the debugging function is used to determine the trigger register corresponding to the debugging instructions in the debugging module and control the trigger register to send a debugging trigger signal to the debugging processor; the debugging trigger signal includes a reset trigger signal, a software trigger signal and a hardware trigger signal.
[0044] Optionally, the debug module includes static random access memory;
[0045] The first processing module is also used to write debugging information in the target debugging format into the static random access memory by calling the debugging function.
[0046] Fifthly, embodiments of this application provide a debugging apparatus for debugging a processor, comprising:
[0047] The second receiving module is used to receive the debug trigger signal and determine whether the debug information has been written based on the debug trigger signal. The debug information includes debug data and debug strategy, which are generated by the debug host according to the debug instructions input by the user and written into the debug module. The debug trigger signal is sent by the debug host controlling the debug module according to the debug instructions.
[0048] The second processing module is used to process the debugging data based on the debugging strategy when it is determined that the debugging information has been written, so as to complete the debugging task indicated by the debugging command.
[0049] Optionally, the debug module includes multiple trigger registers;
[0050] The second receiving module is also used to receive debug trigger signals. The debug trigger signals are sent by the debug host after the debug host determines the trigger register corresponding to the debug instruction in the debug module based on the debug function. The debug function is determined by the debug host after parsing the debug instruction. The debug trigger signals include reset trigger signals, software trigger signals and hardware trigger signals.
[0051] Optionally, the debug processor includes a debug kernel and debug service software;
[0052] The second receiving module is also used to receive debug trigger signals through the debug kernel;
[0053] Based on the debug trigger signal, the debug kernel controls the debug service software to poll the static random access memory in the debug module to determine whether the debug information has been written.
[0054] Optionally, the second processing module is further configured to generate an acknowledgment signal and write it into the static random access memory of the debugging module after the debugging task is executed, so that the static random access memory sends the acknowledgment signal to the debugging host when it receives a query instruction from the debugging host.
[0055] The query command is sent by the debugging host after writing the debugging information corresponding to the debugging command into the static random access memory.
[0056] Sixthly, embodiments of this application provide an electronic device, including: a memory and a processor;
[0057] The memory stores the instructions that the computer executes;
[0058] The processor executes computer execution instructions stored in memory, causing the processor to perform various possible implementations of the second and / or third aspects described above.
[0059] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement various possible implementations of the second and / or third aspects described above.
[0060] Eighthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements various possible implementations of the second and / or third aspects described above.
[0061] The debugging system, method, electronic device, storage medium, and program product provided in this application's embodiments generate debugging information based on user-input debugging instructions through a debugging host. This debugging information is then written into a debugging module, which in turn sends a debugging trigger signal to a debugging processor. Upon receiving the trigger signal, the debugging processor polls the debugging module to check if the debugging information has been written completely. If completion is confirmed, the processor performs corresponding debugging operations based on the obtained information to complete the debugging task indicated by the debugging instructions. This meets user debugging needs in different scenarios, reduces the complexity of the debugging process and the difficulty of upgrading debugging functions, further improves debugging efficiency, and reduces the development cycle and cost of system-on-a-chip (SoC). Attached Figure Description
[0062] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0063] Figure 1 A schematic diagram illustrating the application scenario of the debugging system provided in this application;
[0064] Figure 2 A schematic diagram of the debugging system provided in this application;
[0065] Figure 3 A schematic diagram of the structure of the debugging host provided in this application;
[0066] Figure 4 A flowchart illustrating the debugging method provided in this application;
[0067] Figure 5 Schematic diagram of the debugging device provided in this application Figure 1 ;
[0068] Figure 6 Schematic diagram of the debugging device provided in this application Figure 2 ;
[0069] Figure 7 A schematic diagram of the structure of the electronic device provided in this application.
[0070] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0071] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0072] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of the relevant data all comply with the relevant laws, regulations, and standards of the relevant regions, have taken necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation portals for users to choose to authorize or refuse.
[0073] First, let me explain the terms used in this application:
[0074] RISC-V: refers to an open-source instruction set architecture (ISA) based on the Reduced Instruction Set Computing (RISC) principle.
[0075] GDB (GNU symbolic debugger): refers to a debugging terminal used for testing and debugging programs;
[0076] JTAG (Joint Test Action Group) is an international standard testing protocol used for testing and debugging within system-on-a-chip (SoC).
[0077] OpenOCD (Open On-Chip Debugger) is an open-source chip debugger used for the development and debugging of embedded systems.
[0078] The RISC-V debug subsystem is an invasive chip hardware debugging system for system-level chip hardware debugging of the RISC-V architecture. For example... Figure 1 As shown, the RISC-V debug subsystem includes a debug host, debug transport hardware, and a debug module. The debug host provides the user interface and debug logic, the debug transport hardware is responsible for communication, and the debug module implements the specific debug functions.
[0079] Existing technologies employ a purely hardware-based approach to design RISC-V debug subsystems for debugging RISC-V architecture system-on-a-chip (SoC). The debug host translates GDB debug commands into SoC-recognizable commands and transmits these commands to the debug module via debug transmission hardware. The debug module then performs a series of debug operations on the RISC-V SoC based on the received commands, such as monitoring the debug processor's status, viewing its registers, single-stepping, setting memory breakpoints, conditional breakpoints, and memory read / write operations. Through the collaborative work of the components within the RISC-V debug subsystem, developers can effectively debug and monitor RISC-V SoCs. However, existing debug subsystems require long development cycles, are costly, and struggle to meet the debugging needs of different application scenarios. They also lack the ability to quickly upgrade and iterate debug functionality, further reducing the development efficiency of RISC-V SoCs.
[0080] The debugging method provided in this application involves a debugging host controlling a debugging module to send a debugging trigger signal to a debugging processor. Upon receiving the trigger signal, the debugging kernel of the debugging processor controls the debugging service software to continuously poll the static random access memory (SRAM) of the debugging module. When debugging information corresponding to the debugging instructions is obtained from the SRAM, the debugging data is processed according to the debugging strategy within the SRAM to complete the debugging task indicated by the debugging instructions. After completing the debugging task, an acknowledgment signal is generated and written to the SRAM of the debugging module. When the debugging host sends a query instruction to the debugging module, this acknowledgment signal is fed back to the debugging host, ending the current debugging session. This application enables the debugging host to generate debugging information based on debugging instructions and write the debugging information to the SRAM. The debugging service software then retrieves the written debugging information and executes the corresponding debugging operations, meeting debugging needs in multiple scenarios, further reducing system development cycle and upgrade / maintenance difficulty, thereby improving the development efficiency of RISC-V architecture system-on-a-chip.
[0081] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0082] The debugging system in this application can be integrated into the system-on-a-chip (SoC) to be debugged, or it can be integrated into a separate SoC. This application does not impose any restrictions on this.
[0083] Figure 2A schematic diagram of the debugging system provided in this application is shown below. Figure 2 As shown, the system includes a debugging host, debugging transmission hardware, and a debugging platform. The debugging platform includes a JTAG interface, a debugging module, and a debugging processor. The debugging host receives user-input debugging commands, generates debugging information based on the commands, and writes the debugging information into the debugging module. The debugging processor receives a debugging trigger signal and determines whether the debugging information has been written completely based on the trigger signal. The debugging information includes debugging data and a debugging strategy. The debugging trigger signal is sent by the debugging module controlled by the debugging host. When it is determined that the debugging information has been written completely, the debugging data is processed based on the debugging strategy to complete the debugging task indicated by the debugging command. This embodiment, by having the debugging host write the debugging information determined by the user-input debugging commands into the debugging module and triggering the debugging processor to determine whether the debugging information has been written completely via a debugging trigger signal, executes the corresponding debugging task upon confirmation of completion. This satisfies the debugging needs of users in different scenarios, reduces debugging complexity and the difficulty of upgrading and maintaining debugging functions, and further improves debugging efficiency.
[0084] Optionally, the debug module includes multiple trigger registers; the debug host is also used to: parse debug instructions and determine the debug function corresponding to the debug instructions; wherein, the debug function is used to determine the trigger register corresponding to the debug instructions in the debug module and control the trigger register to send a debug trigger signal to the debug processor; the debug trigger signal includes a reset trigger signal, a software trigger signal and a hardware trigger signal.
[0085] Optionally, the debugging module includes a static random access memory (SRAM); the SRAM is used to store debugging information in the target debugging format written by the debugging host, which is written by the debugging host by calling a debugging function.
[0086] In one possible embodiment, Figure 3 A schematic diagram of the structure of the debugging host provided in this application is shown below. Figure 3 As shown, the debugging host includes a debugging terminal and a chip debugger. The chip debugger includes a GDB Server, a debugging service layer, and a hardware transport layer. For example, the debugging host includes: a debugging terminal (GDB), a chip debugger (OpenOCD), Transport, and a GDB Server. The GDB Server can be a standalone executable file on the user's terminal device that supports command-line interaction, providing a debugging command input interface to relevant users who need to perform debugging. Alternatively, it can be embedded in an IDE (Integrated Development Environment) to provide users with a debugging command input interface in the development environment.
[0087] Optionally, the debug module includes static random access memory.
[0088] In one possible implementation, the user inputs debugging commands (e.g., load, breakpoint, step, watch) through a GDB debugging terminal or development environment IDE. When the debugging terminal receives a load debugging command, it generates a load debugging command in the GDB Remote Serial Protocol (RSP) standard remote communication protocol format based on the command and sends it to the open port of the chip debugger via TCP (Transmission Control Protocol). When the GDB Server in the debugging service layer receives the load debugging command, it parses the command to convert the string into a structured load debugging command and transmits the structured load debugging command to the debugging service layer. The debugging service layer, upon receiving a debugging instruction, identifies it as a load debugging instruction. Based on the characteristics and debugging logic of the system-on-a-chip to be debugged, it determines the corresponding debugging function as the write_memory() function. This function is then used to verify the validity of the memory address indicated by the load debugging instruction. If the address is valid, the layer further determines the memory type indicated by the load debugging instruction (e.g., I / O, cacheable, DMA). Based on the memory type, the layer determines the data access method to obtain the trigger register that issues the current debugging trigger signal (e.g., debug trigger). This allows the layer to control the trigger register in the debugging module to send the current debugging trigger signal to the debugging processor.
[0089] For example, when the debugging host determines through the debugging function that the trigger register of the debugging trigger signal corresponding to the load debugging instruction is a software trigger register, it controls the software trigger register to send the debugging trigger signal to the debugging kernel.
[0090] In one possible embodiment, debug data and debug strategy are determined by a debug function, and the debug data and debug strategy are converted into debug information in the target debug format based on debug transfer hardware, thereby being copied into the static random access memory (e.g., debug SRAM) of the debug module.
[0091] For example, data transmission between the debug host and the debug module is implemented through a hardware transport layer and debug transport hardware, such as... Figure 3 As shown, the hardware transport layer (e.g., a USB-to-JTAG adapter) serves as the hardware connector between the debug host and the debug module. Figure 2As shown, the USB driver is invoked through the hardware transport layer to send the information to be transmitted to the debug transport hardware. The debug transport hardware then transmits the information to the debug module via the JTAG interface in JTAG format. In this embodiment, the JTAG format is the target debug format.
[0092] This embodiment achieves efficient storage of large amounts of data by transmitting and copying debugging-related information into the memory of the debugging module, reducing the complexity of the debugging process and further improving the reliability of system debugging.
[0093] Optionally, the debug processor includes a debug kernel and debug service software; when determining whether the debug information has been written, the debug processor specifically performs the following: receiving a debug trigger signal through the debug kernel; and, based on the debug trigger signal, controlling the debug service software through the debug kernel to poll the static random access memory in the debug module to determine whether the debug information has been written.
[0094] Alternatively, the debug service software is a piece of debug firmware that runs on the debug kernel.
[0095] In one possible embodiment, when the debug processor's debug kernel (e.g., a RISC-V core) receives the debug trigger signal, it controls the debug service software (e.g., a debug service) to poll the static random access memory (SRAM) of the debug module to determine whether the debug information corresponding to the load debug instruction in the SRAM has been written completely. When the debug service software determines that the writing is complete and that the debug strategy indicates that the debug data should be moved to address a, the debug data in the debug information is transferred to address a. This embodiment uses the debug host to call the debug function corresponding to the debug instruction, which in turn controls the corresponding trigger register in the debug module to send a debug trigger signal to the debug processor. Simultaneously, it writes the corresponding debug information to the debug processor's SRAM. The debug trigger signal triggers the debug processor to poll the debug information writing process. Upon determining that the debug information writing is complete, the debug information is promptly obtained, and the corresponding debug operation is executed based on the instructions in the debug information. This achieves a complete response process for executing debug operations on the system-on-a-chip for various debug instructions in different scenarios, effectively enriching the achievable debug functions, improving debug efficiency, and reducing upgrade and maintenance difficulty and debug costs.
[0096] Optionally, after executing the debugging task, the debug processor is further configured to: generate an acknowledgment signal and write it into the static random access memory of the debug module, so that when the static random access memory receives a query instruction from the debug host, it sends an acknowledgment signal to the debug host; wherein the query instruction is sent by the debug host after writing the debug information corresponding to the debug instruction into the static random access memory.
[0097] For example, the acknowledgment signal is the ACK (Acknowledgment) command signal.
[0098] In this embodiment, after completing the debugging task, the debugging processor writes a confirmation signal of the task execution to the static random access memory, so as to respond to the debugging host's request in a timely manner when the debugging host needs to provide feedback on the debugging results, thereby enhancing the user's debugging experience.
[0099] Figure 4 A flowchart illustrating the debugging method provided in this application is shown below. Figure 4 As shown, in this embodiment... Figure 2 Based on the embodiments, the debugging method based on this debugging system is described in detail, and the method includes:
[0100] S401. The debugging host determines the target trigger register and debugging information corresponding to the debugging instruction, and generates the control instruction corresponding to the target trigger register.
[0101] More specifically, the debugging host acquires the debugging instructions input by the user, converts the debugging instructions into debugging instructions in the standard remote communication protocol format, determines the characteristics of the system-on-a-chip to be debugged and the corresponding debugging logic based on the debugging instructions, thereby generating debugging information. At the same time, it determines the target trigger register corresponding to the debugging instructions and generates control instructions for controlling the target trigger register.
[0102] S402, The debugging host sends control commands to the debugging module.
[0103] More specifically, after generating control commands, the debug host sends the control commands to the target trigger register of the debug module.
[0104] S403, The debug module sends a trigger instruction to the debug processor.
[0105] More specifically, the debug module sends a trigger instruction to the debug kernel in the debug processor via the target trigger register.
[0106] S404. The debugging host writes debugging information to the debugging module.
[0107] More specifically, after generating debugging information, the debugging host begins writing the debugging information into the static random access memory of the debugging module.
[0108] S405, the debug processor determines whether the debug information has been written completely.
[0109] More specifically, when the debug kernel of the debug processor receives a trigger instruction, it controls the debug service software to continuously poll the static random access memory in the debug module until it is determined that the debug information in the static random access memory has been written.
[0110] S406. When the debug processor determines that the write operation is complete, it acquires debug information and performs debug operations.
[0111] More specifically, the debug processor obtains the debug information when the debug information in the static random access memory is written, and then debugs the system-on-a-chip to be debugged based on the debug information, by determining through the debug service software.
[0112] S407. When debugging is complete, the debug processor sends an acknowledgment signal to the debug module.
[0113] More specifically, when the debug processor determines that debugging is complete through the debug service software, it generates an acknowledgment signal and writes it to the static random access memory of the debug module.
[0114] S408, The debugging host sends a query command to the debugging module.
[0115] S409. The debugging module sends an acknowledgment signal to the debugging host.
[0116] More specifically, when the static random access memory of the debugging module receives a query command sent by the debugging module, it sends an acknowledgment signal corresponding to the current debugging information back to the debugging host, so that the debugging host can record it and provide the debugging results to the user.
[0117] The debugging method provided in this application process the debugging command input by the user to obtain the debugging information and target trigger register corresponding to the debugging command. By controlling the target trigger register to send a debugging trigger signal to the debugging processor, the debugging processor is further triggered to start polling the memory of the debugging module until it is determined that the debugging host has completely written the debugging information into the debugging module. Then, the debugging operation is performed on the system-on-a-chip to be debugged according to the obtained debugging information. This achieves effective response to debugging commands in various scenarios, reduces the debugging difficulty and development cost of system-on-a-chip, improves debugging reliability and efficiency, and enhances user experience.
[0118] Figure 5 Schematic diagram of the debugging device provided in this application Figure 1 ,like Figure 5 As shown, the debugging device 50 provided in this embodiment includes:
[0119] The first receiving module 501 is used to receive debugging commands input by the user;
[0120] The first processing module 502 is used to generate debugging information according to the debugging instructions, write the debugging information into the debugging module, and control the debugging module to send a debugging trigger signal to the debugging processor according to the debugging instructions. The debugging information includes debugging data and debugging strategy. The debugging processor receives the debugging trigger signal and determines whether the debugging information has been written based on the debugging trigger signal. When it is determined that the debugging information has been written, the debugging data is processed based on the debugging strategy to complete the debugging task indicated by the debugging instructions.
[0121] Optionally, the debug module includes multiple trigger registers;
[0122] The first processing module 502 is also used to parse debugging instructions and determine the debugging function corresponding to the debugging instructions; wherein, the debugging function is used to determine the trigger register corresponding to the debugging instructions in the debugging module and control the trigger register to send a debugging trigger signal to the debugging processor; the debugging trigger signal includes a reset trigger signal, a software trigger signal and a hardware trigger signal.
[0123] Optionally, the debug module includes static random access memory;
[0124] The first processing module 502 is also used to write debugging information in the target debugging format into the static random access memory by calling the debugging function.
[0125] The debugging device provided in this embodiment is applied to the debugging host and can execute the debugging method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0126] Figure 6 Schematic diagram of the debugging device provided in this application Figure 2 ,like Figure 6 As shown, the debugging device 60 provided in this embodiment includes:
[0127] The acquisition module 601 is used by the second receiving module 601 to receive the debugging trigger signal and determine whether the debugging information has been written based on the debugging trigger signal. The debugging information includes debugging data and debugging strategy, which are generated by the debugging host according to the debugging instructions input by the user and written into the debugging module. The debugging trigger signal is sent by the debugging host controlling the debugging module according to the debugging instructions.
[0128] The second processing module 602 is used to process the debugging data based on the debugging strategy when it is determined that the debugging information has been written, so as to complete the debugging task indicated by the debugging command.
[0129] Optionally, the debug module includes multiple trigger registers;
[0130] The second receiving module 601 is also used to receive debug trigger signals. The debug trigger signals are sent by the debug host after the debug host determines the trigger register corresponding to the debug instruction in the debug module based on the debug function. The debug function is determined by the debug host after parsing the debug instruction. The debug trigger signals include reset trigger signals, software trigger signals and hardware trigger signals.
[0131] Optionally, the debug processor includes a debug kernel and debug service software;
[0132] The second receiving module 601 is also used to receive debug trigger signals through the debug kernel;
[0133] Based on the debug trigger signal, the debug kernel controls the debug service software to poll the static random access memory in the debug module to determine whether the debug information has been written.
[0134] Optionally, the second processing module 602 is further configured to generate an acknowledgment signal and write it into the static random access memory of the debugging module after executing the debugging task, so that the static random access memory sends the acknowledgment signal to the debugging host when it receives a query instruction from the debugging host.
[0135] The query command is sent by the debugging host after writing the debugging information corresponding to the debugging command into the static random access memory.
[0136] The debugging device provided in this embodiment is applied to the debugging host and can execute the debugging method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0137] Figure 7 A schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device 70 provided in this embodiment includes at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. The processor 701, memory 702, and communication component 703 are connected via a bus 704.
[0138] In a specific implementation, at least one processor 701 executes computer execution instructions stored in memory 702, causing at least one processor 701 to perform the above-described method.
[0139] The specific implementation process of processor 701 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0140] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0141] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0142] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0143] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0144] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.
[0145] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0146] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0147] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0148] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0149] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0150] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0151] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0152] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A debugging system, characterized in that, include: The debugging host is used to receive debugging commands input by the user, generate debugging information according to the debugging commands, and write the debugging information into the debugging module; A debug processor is used to receive a debug trigger signal and determine whether the debug information has been written completely based on the debug trigger signal. The debug information includes debug data and debug strategy. The debug trigger signal is sent by the debug module controlled by the debug host. When it is determined that the debugging information has been written, the debugging data is processed based on the debugging strategy to complete the debugging task indicated by the debugging instruction.
2. The system according to claim 1, characterized in that, The debugging module includes multiple trigger registers; The debugging host is also used for: The debugging instruction is parsed, and the corresponding debugging function is determined. The debugging function is used to determine the trigger register corresponding to the debugging instruction in the debugging module, and to control the trigger register to send a debugging trigger signal to the debugging processor. The debugging trigger signal includes a reset trigger signal, a software trigger signal, and a hardware trigger signal.
3. The system according to claim 2, characterized in that, The debugging module includes a static random access memory; The static random access memory is used to store debugging information in a target debugging format written by the debugging host, which is written by the debugging host by calling a debugging function.
4. The system according to claim 3, characterized in that, The debug processor includes the debug kernel and debug service software; When determining whether the debugging information has been written completely, the debug processor is specifically used for: The debug trigger signal is received through the debug kernel; Based on the debug trigger signal, the debug kernel controls the debug service software to poll the static random access memory in the debug module to determine whether the debug information has been written.
5. The system according to claim 4, characterized in that, After executing the debugging task, the debug processor is further configured to: A confirmation signal is generated and written to the static random access memory of the debugging module, so that when the static random access memory receives a query instruction of the debugging instruction sent by the debugging host, it sends the confirmation signal to the debugging host. The query command is sent by the debugging host after writing the debugging information corresponding to the debugging command into the static random access memory.
6. A debugging method, characterized in that, Applied to debugging hosts, including: Receive debugging commands from the user; Debugging information is generated according to the debugging instructions, the debugging information is written into the debugging module, and the debugging module is controlled to send a debugging trigger signal to the debugging processor according to the debugging instructions. The debugging information includes debugging data and debugging strategy. The debugging processor receives the debugging trigger signal, determines whether the debugging information has been written completely based on the debugging trigger signal, and processes the debugging data according to the debugging strategy when the debugging information has been written completely, so as to complete the debugging task indicated by the debugging instructions.
7. A debugging method, characterized in that, Applied to debug processors, including: The system receives a debug trigger signal and determines whether the debug information has been written completely based on the debug trigger signal. The debug information includes debug data and debug strategy, which are generated by the debug host according to the debug instructions input by the user and written into the debug module. The debug trigger signal is sent by the debug host controlling the debug module according to the debug instructions. When it is determined that the debugging information has been written, the debugging data is processed based on the debugging strategy to complete the debugging task indicated by the debugging instruction.
8. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in claim 6 or 7.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in claim 6 or 7.
10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of claim 6 or 7.