Data transmission method and system

Abstract

The application provides a data transmission method and system. The method comprises the following steps: sending a first read command to a storage device, the first read command being used to control the storage device to send data to the controller; receiving the data from the storage device and performing a check calculation on the data in the process of receiving the data to generate and store a first check value; after completing the reception of the data, sending a second read command to the storage device, the second read command being used to read a second check value generated by the storage device in the process of sending the data to the controller; receiving the second check value returned by the storage device in response to the second read command; comparing the first check value and the second check value, if the comparison result is consistent, confirming that the data transmission is correct, and if the comparison result is inconsistent, performing an abnormal processing operation.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data transmission method and system. Background Technology

[0002] In high-speed read operations of NAND Flash, during the data transfer from the storage device to the controller, the data strobe signal (DQS) may experience signal integrity degradation such as jitter and duty cycle distortion after passing through physical media such as circuit board traces and connectors, leading to errors in the data sampled by the controller. However, existing NAND Flash interface protocols lack integrity verification methods for the read-direction transmission link. Data read from the storage device usually goes directly to the error correction module for error correction code decoding. If the data error is caused by signal integrity degradation of the transmission link rather than physical degradation of the storage cell itself, the error correction module will still perform repeated decoding operations on this invalid data. This not only increases power consumption and occupies internal bus bandwidth, but may also cause the controller to misjudge a momentary link error as severe degradation of the storage medium, thereby triggering unnecessary reread adjustments, data migration, or even bad block marking.

[0003] Furthermore, when existing technologies detect data read errors, they cannot determine whether the error originates from signal integrity degradation in the transmission link or from physical degradation of the storage unit, making error localization difficult and recovery methods difficult to select precisely. Summary of the Invention

[0004] This application provides a data transmission method and system that can solve the signal integrity degradation problem on the data transmission link without changing the existing data transmission protocol or increasing the transmission bandwidth overhead.

[0005] In a first aspect, embodiments of this application provide a data transmission method applied to a controller, the method comprising the following steps: Send a first read command to the storage device, the first read command being used to control the storage device to send data to the controller; The data is received from the storage device, and during the process of receiving the data, the data is verified and a first verification value is generated and stored. After receiving the data, a second read command is sent to the storage device. The second read command is used to read the second check value generated by the storage device during the process of sending the data to the controller. Receive the second verification value returned by the storage device in response to the second read command; Compare the first check value and the second check value. If the comparison results are consistent, the data transmission is confirmed to be correct. If the comparison results are inconsistent, an exception handling operation is performed.

[0006] Secondly, embodiments of this application provide a data transmission method applied to a storage device, the method comprising the following steps: In response to a first read command from the controller, data is sent to the controller; During the process of sending the data to the controller, the data is verified and a second verification value is generated and stored. In response to a second read command from the controller, the second verification value is returned to the controller.

[0007] Thirdly, embodiments of this application provide a controller, including the following: Read data buffer; The first physical layer interface is used to communicate with storage devices; The first calculation module is used to perform verification calculations on the data during the process of receiving data from the storage device and generate a first verification value. A first register is used to store the first verification value; A command generator is used to generate a first read command and a second read command. The first read command is used to control the storage device to send data to the controller, and the second read command is used to read a second checksum generated by the storage device during the process of sending the data to the controller. A comparator is used to compare the first check value and the second check value. If the comparison results are consistent, the data transmission is confirmed to be correct. If the comparison results are inconsistent, an exception handling operation is performed.

[0008] Fourthly, embodiments of this application provide a storage device, including the following: The second physical layer interface is used for communication with the controller; The second calculation module is used to perform verification calculations on the data during the process of sending data to the controller, and generate a second verification value. A second register is used to store the second verification value; and A command parser is used to parse a first read command and a second read command from the controller, wherein, in response to the first read command, data is sent to the controller, and in response to the second read command, the second check value is returned to the controller.

[0009] Fifthly, embodiments of this application provide a data transmission system, including the following: The controller as described in the third aspect; and The storage device as described in the fourth aspect.

[0010] This application embodiment implements real-time integrity verification of the transmission link during read operations. The controller and storage device independently calculate checksums during data transmission and reception. After data transmission is complete, a dedicated command retrieves the checksum from the storage device side for comparison. This accurately detects data errors introduced by signal quality degradation in the read-direction transmission link. When read-direction checks are inconsistent, it indicates that an error occurred during data transmission from the storage device to the controller, but the data in the storage device's page cache is correct and can be recovered by rereading. This avoids misjudging recoverable transmission errors as physical damage to storage units and triggering bad block marking. The checksum is not transmitted with the data, does not affect the data format and timing of standard read commands, and has good compatibility with existing storage devices. The checksum is calculated in real-time during data reception or transmission, without adding additional time overhead. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a data transmission method applied to a controller, provided in an embodiment of this application. Figure 2 This is a schematic flowchart of a data transmission method applied to a storage device according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a controller provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a data transmission system provided in an embodiment of this application; Figure 6 This is a schematic diagram of the controller chip and NAND Flash chip provided in the embodiments of this application; Figure 7 This is a schematic diagram of the read-direction CRC check process provided in an embodiment of this application; Figure 8 This is a timing diagram of the command to read the verification value provided in the embodiments of this application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0014] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0015] Currently, there are still some issues in the read direction during high-speed data transmission of NAND Flash. For example, without changing the existing data transmission protocol or increasing transmission bandwidth overhead, how can we detect data errors introduced by signal integrity (SI) degradation on the data transmission link, and perform efficient link recovery operations (such as data retransmission and DQS retraining) when errors are detected? Furthermore, how can we prevent the additional power consumption, bandwidth waste, and erroneous error correction processes caused by the propagation of read-direction link errors to downstream error correction modules?

[0016] The first issue is distinguishing between read link errors and storage unit errors. During a read operation, if the controller detects a data error, existing methods cannot determine whether the error is caused by a SI problem in the transmission link or by physical degradation of the storage unit.

[0017] Secondly, there is the issue of read link errors propagating to the error correction module. In the existing architecture, data read from NAND Flash goes directly into the error correction module (e.g., LDPC, BCH decoder). If an error occurs in the read transmission link, the error correction module will be forced to process this noise data not caused by the storage medium, resulting in a significant increase in the power consumption of the error correction module, such as a surge in the number of LDPC soft decoding iterations. The internal data bus bandwidth is occupied by invalid error correction operations, and the controller may misjudge the link error as NAND medium degradation, triggering unnecessary read retry adjustments or data migration.

[0018] Furthermore, data misalignment caused by DQS signal SI degradation cannot be detected. In NAND IO synchronization interfaces, the DQS signal serves as the data sampling clock. When DQS SI degradation occurs (e.g., edge degradation, increased jitter, duty cycle distortion, etc.), it may cause sampling timing offset, resulting in complete data misalignment. Existing technologies lack link-level verification mechanisms in the read direction.

[0019] Furthermore, link recovery methods are limited and lack tiered recovery strategies. When Cyclic Redundancy Check (CRC) / Error Correction Code (ECC) checks fail multiple times consecutively, it indicates that the DQS timing margin has severely deteriorated. Current technologies lack a mechanism to automatically link CRC / ECC check failures with retraining.

[0020] Existing methods include a write-back check approach. After writing a page of data, the controller reads the same page back using a page read command and compares it byte-by-byte with the original written data. If they match, the write is confirmed as correct; otherwise, a rewrite is initiated. However, this method has drawbacks: the readback check requires an additional full page read operation, effectively halving the actual throughput. This method cannot distinguish the source of the error; when the comparison is inconsistent, it could be a write link error or a read link error. If the data obtained from the readback already contains read link errors, passing it back to the error correction module will waste power and increase the risk of incorrect error correction.

[0021] Existing methods include embedding CRC checksums into the data stream, appending a CRC checksum to the end of the data packet, and then extracting the checksum for verification upon receiving the data from the NAND Flash. For example, in interface protocols such as UFS, CRC checksums are used at the link layer to protect data transmission integrity. However, embedding CRC checksums into the data stream alters the data format and timing of standard NAND Flash protocols. Forced implementation requires design modifications to the NAND Flash chips, resulting in extremely poor compatibility and increasing the actual data transfer volume per page.

[0022] Existing methods include one that utilizes the built-in ECC error correction in NAND Flash. NAND Flash typically integrates ECC error correction circuitry. However, the built-in ECC in NAND Flash is mainly designed for scenarios such as data retention errors in storage cells and programming interference. Its error correction capability is limited (usually 1-4 bits / 512 bytes), and it mainly operates on the path from the page cache to the storage cell, failing to cover the complete transmission link from the controller to the page cache.

[0023] Existing methods include an end-to-end CRC signature verification approach, where the controller calculates the CRC signature when decoding data and compares it with the original CRC signature generated during data writing. However, the CRC signature of this method is stored internally within the device during writing, rather than being calculated and compared in real time during transmission. This makes it impossible to detect read link errors in real time during each transmission, and also poses the risk of confusing link errors with storage medium errors.

[0024] In summary, these methods lack an independent CRC link protection mechanism in the read direction. The CRC signature is generated and stored during writing, and link errors are not detected in real time. They do not support the distinction between read-direction link errors and storage unit errors, do not support blocking link errors before data enters the error correction module, and do not support retraining linkage mechanisms.

[0025] The technical problems that this application aims to solve include the following: 1. The read direction cannot distinguish between link errors and storage unit errors. During a read operation, if the controller detects a data error, current technology cannot determine the source of the error. If it is caused by a link SI problem, recovery can be achieved by rereading, and complex error correction procedures should not be initiated. If it is caused by physical degradation of the storage unit, recovery requires complex error correction procedures such as threshold voltage (VTH) adjustment, soft decoding, and redundant array of independent disks (RAID). The lack of distinguishing ability leads to incorrectly entering the error correction process, resulting in increased read latency, increased power consumption, and even introducing confusion into the error correction process, ultimately preventing data from being read correctly.

[0026] II. Read-direction link errors propagate to the error correction module. The negative impacts of read-direction link errors propagating to the error correction module include: a significant increase in the power consumption of the error correction module, for example, the number of iterations of LDPC soft decoding surges due to a large number of link errors; the internal data bus bandwidth is occupied by invalid error correction operations, affecting other parallel read and write tasks; the controller may misjudge link errors as NAND media degradation, triggering unnecessary read retry adjustments or data migrations.

[0027] Third, the existing link recovery methods are limited to retransmission or retries after an error is detected, lacking a tiered recovery mechanism that extends from link-layer retransmission to physical-layer DQS retraining. When link parameters drift, simple retransmission cannot fundamentally solve the problem.

[0028] Therefore, this application proposes a data transmission method for use in controllers and storage devices. This method protects the transmission link in the read direction by completely decoupling CRC check from the data protocol. The CRC value is not transmitted as part of the data stream but is obtained and compared through post-event active querying. This achieves integrity protection of the transmission link in the read direction without modifying the standard protocol or increasing transmission bandwidth overhead, and fundamentally cuts off the path for errors in the read direction link to propagate to the error correction module.

[0029] First, a brief explanation of the technical terms used in the embodiments of this application will be given.

[0030] Cyclic Redundancy Check (CRC) is a data integrity verification algorithm based on polynomial division, which generates a fixed-length check value by calculating the data sequence. In this embodiment, CRC is used to detect bit errors caused by signal integrity (SI) problems in the NAND Flash read-direction data transmission link.

[0031] The Data Strobe (DQS) signal is the source synchronization clock signal in the NAND Flash high-speed interface, used to latch data on the data bus. During read operation, the NAND Flash emits the DQS signal, and the controller samples the data on the data bus based on the edge of the DQS signal. Duty cycle distortion, jitter, and edge degradation of the DQS signal can all lead to data sampling errors at the receiving end.

[0032] Signal integrity (SI) refers to the quality characteristics of a signal on its transmission path, including parameters such as rise / fall time, eye diagram opening, timing margin (setup / hold margin), crosstalk, and reflections.

[0033] The Read CRC command is a novel extended command proposed in this application. After the data transmission is completed, the controller can use this command to read the CRC value calculated in real time by the NAND Flash side during data transmission, and compare it with the calculation result on the controller side to determine whether there is an error in the link transmission.

[0034] The following is in conjunction with the appendix Figures 1 to 8 The present application provides a detailed description of a data transmission method, system, electronic device, and computer program product through specific embodiments and application scenarios.

[0035] Figure 1 This application illustrates a data transmission method provided by an embodiment of the present application, applied to a controller. The method includes the following steps: Step 110: Send a first read command to the storage device. The first read command is used to control the storage device to send data to the controller.

[0036] The controller is typically the master device in a storage system, used to send commands, addresses, and data to the storage devices and receive responses from them. In this embodiment, the controller can specifically be a NAND Flash controller.

[0037] The storage device in this system is typically a slave device used for persistent data storage. In this embodiment, the storage device can specifically be a NAND Flash chip or NAND Flash particle, conforming to the ONFI or Toggle standard interface protocol.

[0038] In this step, the controller, acting as the master device, can send a sequence of read commands to the storage device via a command latch enable signal to initiate the data transmission process from the storage device to the controller. The first read command is the starting command in the read operation flow, used to inform the storage device that a data read operation is about to begin and to put the storage device into a data output preparation state. The controller can send the first read command to the storage device through the first physical layer interface. This command is transmitted to the command parser of the storage device via the command latch enable signal line, and the command parser decodes and recognizes the received command. After recognizing the first read command, the storage device reads the data from its internal storage unit into the page cache and prepares to send the data to the controller via the data bus.

[0039] For a standard NAND Flash interface, the first read command can include a sequence of commands. After sending the first read command, the controller can also send a target address to the storage device to specify the storage location of the data to be read. Based on the received commands and address, the storage device reads the target data from the memory cell into the page cache and waits for subsequent operations from the controller.

[0040] Step 120: Receive the data from the storage device, and in the process of receiving the data, perform a verification calculation on the data to generate and store a first verification value.

[0041] The verification calculation is a computational process for verifying the integrity of data. The verification calculation can employ a Cyclic Redundancy Check (CRC) algorithm, which generates a fixed-length check value by calculating the data sequence. The first check value is the result obtained by the controller after performing the verification calculation during data reception. This value is then compared with the second check value returned by the storage device to determine if there are errors in the data transmission link in the read direction. For example, the CRC algorithm can be a standard polynomial such as CRC-32 or CRC-16.

[0042] In this step, the controller performs byte-by-byte verification calculations on the data output from the storage device while receiving data from the storage device. After the storage device reads the target data from the storage unit into the page cache, it sends the data to the controller byte by byte through the data bus driven by the synchronization clock signal. The controller receives the data through its first physical layer interface. The received data is temporarily stored in the read data buffer and simultaneously sent to the first calculation module for real-time verification calculations.

[0043] In some implementations, the checksum calculation is performed synchronously with the transmission of the synchronization clock signal. The storage device sends a synchronization clock signal, which may be a data strobe (DQS), to the controller simultaneously with data transmission. The controller samples the data on the data bus based on the edges of the synchronization clock signal. For each received data byte, the first calculation module performs a partial calculation on that byte and updates the intermediate checksum. When all data has been received, the first checksum is also calculated synchronously, without introducing any additional calculation delay. The controller stores the calculated first checksum in a first register.

[0044] Step 130: After receiving the data, a second read command is sent to the storage device. The second read command is used to read the second check value generated by the storage device during the process of sending the data to the controller.

[0045] The second checksum is the verification result obtained by the storage device during data transmission to the controller. While sending data from the page cache to the controller, the storage device performs a checksum calculation on the transmitted data, generates a second checksum, and temporarily stores it in its internal second register. The verification algorithm used to calculate the second checksum is the same as the algorithm used to calculate the first checksum on the controller side, ensuring that the first checksum calculated by the controller side is consistent with the second checksum calculated by the storage device side, assuming error-free data transmission.

[0046] In this step, after receiving the data, the controller sends a second read command to the storage device via the command latch enable signal line. This second read command has a different command code than the first read command to distinguish their functions. This second read command is used to read the second checksum calculated on the storage device side, rather than reading the data in the storage device. The second read command is sent after the data output phase of the standard read operation timing and before the data is sent to the error correction module, enabling integrity verification of the transmission link to be completed before the data undergoes error correction processing.

[0047] Step 140: Receive the second verification value returned by the storage device in response to the second read command.

[0048] In this step, after receiving the second read command, the storage device returns the second checksum stored in its second register to the controller via the data bus. This return operation does not involve reading data from the storage unit; it only outputs the checksum temporarily stored in the internal register to the controller. The controller receives the second checksum through its first physical layer interface and temporarily stores it in the comparator's input buffer for subsequent comparison. This return operation has a small time overhead, requiring only a few bus cycles to complete.

[0049] Step 150: Compare the first check value and the second check value. If the comparison results are consistent, the data transmission is confirmed to be correct. If the comparison results are inconsistent, an exception handling operation is performed.

[0050] In this step, the controller reads the first check value from the first register and the second check value from the input buffer of the comparator, and the comparator performs the comparison operation.

[0051] If the comparison results are consistent, it indicates that no errors occurred in the read-direction data transmission link, and the data sent by the storage device is consistent with the data received by the controller. The controller confirms that the data transmission is correct. In some implementations, the controller allows error correction processing on the received data, that is, the data is sent to the error correction module to perform error correction code decoding to complete the normal read operation process.

[0052] If the comparison results are inconsistent, it indicates that there may be an error in the data transmission link in the read direction. In some implementations, the controller prohibits error correction processing on the received data and instead performs exception handling operations. Since data errors may originate from signal integrity degradation of the transmission link rather than the storage unit itself, if erroneous data is sent to the error correction module, the error correction module will perform ineffective decoding operations on data containing link noise, wasting power consumption and bandwidth. Therefore, when a link error is detected, the controller first performs a link layer recovery operation.

[0053] Anomaly handling operations include resending the first read command to the storage device, i.e., restarting the entire read operation process, and restoring correct data by rereading the data in the storage device. Anomaly handling operations also include timing retraining of the synchronization clock signal. When multiple consecutive checksum inconsistencies occur, it indicates that the timing parameters of the synchronization clock signal may have deviated from the normal operating range. The controller initiates timing retraining of the synchronization clock signal to adjust the delay parameters or edge positions of the synchronization clock signal and improve signal integrity. Anomaly handling operations also include reducing the clock frequency of the synchronization clock signal and resending the first read command to the storage device. This involves increasing the period width of each data bit by reducing the transmission rate, providing the receiving end with more setup and hold time margins. These three anomaly handling methods can be executed sequentially.

[0054] In this embodiment, by implementing real-time integrity verification of the transmission link during read operations, the controller and storage device independently calculate the checksum during data transmission and reception. After data transmission is completed, a dedicated command is used to obtain the checksum from the storage device side for comparison. This accurately detects data errors introduced by signal quality degradation in the read-direction transmission link. When the read-direction checks are inconsistent, it indicates that an error occurred during data transmission from the storage device to the controller, but the data in the storage device's page cache is correct and can be recovered by rereading. This avoids misjudging recoverable transmission errors as physical damage to the storage unit and triggering bad block marking. The checksum is not transmitted with the data, does not affect the data format and timing of the standard read command, and has good compatibility with existing storage devices. The checksum is calculated in real time during data reception or transmission, without adding additional time overhead.

[0055] In yet another exemplary embodiment, based on step 120 of the above embodiment, data is received from the storage device, and during the process of receiving the data, a verification calculation is performed on the data to generate and store a first verification value. The method of this embodiment may further include the following specific steps: A synchronization clock signal is received from the storage device, and the verification calculation is performed synchronously with the transmission of the synchronization clock signal.

[0056] The synchronization clock signal is used to coordinate the data transmission timing between the data transmitter and receiver. In high-speed data transmission, the transmitter drives data output based on the edge of the synchronization clock signal, and the receiver samples the data based on the edge of the synchronization clock signal, thereby ensuring correct latching and recovery of data during transmission. For example, the synchronization clock signal can specifically be a data strobe signal. The data strobe signal is the source synchronization clock signal used in the NAND Flash high-speed interface; it is issued by the controller during write operations and by the storage device during read operations. The data strobe signal is transmitted synchronously with the data signal and supports double data rate mode, meaning that data transmission and sampling occur on both the rising and falling edges of the data strobe signal.

[0057] In this step, while receiving data from the storage device, the controller also receives a synchronization clock signal from the storage device. The storage device sends the synchronization clock signal to the controller simultaneously with the data signal; this synchronization clock signal is transmitted synchronously with the data signal and serves as the timing reference for the controller's data sampling. The controller samples the data on the data bus based on the edges of this synchronization clock signal, with each edge corresponding to one data byte.

[0058] The verification calculation is performed synchronously with the transmission of the synchronization clock signal. The first calculation module inside the controller uses the edge of the synchronization clock signal as the trigger reference. Each time a data byte is received, it is simultaneously sent to the first calculation module for partial calculation. The first calculation module then performs a partial calculation on that byte and updates the intermediate verification value. Because the verification calculation is synchronized with the data reception driven by the synchronization clock signal, the first verification value is also calculated synchronously when all data has been received, requiring no additional time overhead. Furthermore, this synchronous design allows the verification calculation to match the high-speed data transmission rate, meeting the real-time verification requirements of the NAND Flash interface in high-frequency mode.

[0059] In this embodiment, the verification calculation and the transmission of the synchronization clock signal are performed synchronously, so that the verification calculation process does not introduce additional delay relative to the data transmission process. The synchronization clock signal can include various specific implementation forms such as data strobe signals, and can be applied to various storage interface standards including NAND Flash and DDR memory, with good versatility and scalability.

[0060] In yet another exemplary embodiment, based on step 150 of the above embodiment, the first check value and the second check value are compared. If the comparison result is consistent, the data transmission is confirmed to be correct; if the comparison result is inconsistent, an exception handling operation is performed. The method of this embodiment may further include the following specific steps: If the comparison results are consistent, error correction is allowed; if the comparison results are inconsistent, error correction is prohibited.

[0061] Error correction processing refers to the process of decoding received data using error correction codes to detect and correct bit errors that may occur during storage or transmission. In storage systems, error correction is typically performed by an error correction module, which uses error correction code (ECC) algorithms to decode the data and automatically detect and correct errors. Common error correction codes include BCH codes and low-density parity-check codes. However, error correction consumes power and bus bandwidth and requires certain data validity. If the data is corrupted due to transmission link errors before entering the error correction module, the module will be forced to perform invalid decoding operations on data containing link noise, wasting power and bandwidth and potentially misinterpreting link errors as storage medium degradation, triggering unnecessary read rereads or data migrations.

[0062] In this step, after comparing the first and second checksums, the controller determines whether error correction processing is allowed based on the comparison result. If the comparison results match, it indicates that no errors occurred in the data transmission link in the read direction, and the data sent by the storage device is consistent with the data received by the controller. The controller confirms that the data remained intact during transmission. At this point, the controller allows error correction processing on the received data, that is, the data is sent to the error correction module for error correction code decoding. Through error correction processing, the controller can further detect and correct any bit errors that may exist in the storage unit itself, completing the normal read operation process.

[0063] If the comparison results are inconsistent, it indicates that there may be an error in the read-direction data transmission link, and the data may have been corrupted during transmission from the storage device to the controller. In this case, the controller prohibits error correction processing on the received data, and the data is not sent to the error correction module. Since data errors may originate from signal integrity degradation of the transmission link rather than physical degradation of the storage unit itself, sending erroneous data already contaminated by link noise to the error correction module would consume power and bandwidth to decode invalid data, and the decoding result itself would be of no reference value. More importantly, if a link error is misjudged as storage medium degradation, the controller may trigger unnecessary reread adjustments or bad block marking, affecting the reliability and lifespan of the storage system.

[0064] In this embodiment, by linking the enabling or disabling of error correction processing to the transmission link verification result, transmission link errors and storage unit errors can be distinguished in the read direction. Data is only allowed to undergo error correction processing after the transmission link verification passes. If the verification fails, error correction processing is directly disabled and a link layer recovery operation is triggered. This approach can cut off the path for read-direction link errors to propagate to the error correction module, avoiding ineffective error correction calculations and wasted power, while preventing the controller from misjudging momentary link errors as severe degradation of the storage medium. Furthermore, the error correction module can focus on processing bit errors within the storage unit itself, improving decoding efficiency and accuracy, and extending the lifespan of the storage system.

[0065] In yet another exemplary embodiment, the exception handling operation includes at least one of the following: The first read command is resent to the storage device; the timing of the synchronization clock signal is retrained; the clock frequency of the synchronization clock signal is reduced, and the first read command is resent to the storage device.

[0066] When the controller compares the first checksum with the second checksum, if the comparison results are inconsistent, it indicates that there may be an error in the data transmission link in the read direction. In this case, the controller does not send the data to the error correction module, but instead performs an exception handling operation. The exception handling method provided in this embodiment can be selected to be executed one or more of the following based on the error type, error frequency, and system configuration.

[0067] The first method: resend the first read command to the storage device.

[0068] When the CRC comparison for the read direction is inconsistent, it indicates that an error occurred during the data transmission link from the storage device's page buffer to the controller's reception, but the data may be correct in the storage device's page buffer. In this case, the controller resends the first read command to the storage device, restarting the entire read operation. The storage device reads the target data from the storage unit into the page buffer again and resends the data to the controller. The controller receives the data again, recalculates the checksum, and recomputes the comparison. Since link errors are usually transient signal integrity issues, rereading has a high probability of recovering the correct data. After the read operation is re-executed, the controller performs another checksum comparison; if they match, the data transmission is confirmed to be correct.

[0069] The second method is to retrain the synchronization clock signal according to its timing.

[0070] When multiple consecutive checksum inconsistencies occur, it may indicate that the timing parameters of the synchronization clock signal need adjustment. The controller can initiate a timing retraining process for the synchronization clock signal to adjust its delay parameters, duty cycle, or edge position, improving signal integrity. After timing retraining is complete, the controller resends the first read command to the storage device, re-executes the read operation, and performs checksum comparison again. Triggering timing retraining after multiple consecutive failures automatically links checksum failures with link parameter adjustments, preventing situations where simple retransmission cannot fundamentally solve the problem.

[0071] The third method is to reduce the clock frequency of the synchronization clock signal and resend the first read command to the storage device.

[0072] When multiple consecutive checksum inconsistencies occur, and re-performing read operations and timing retraining of the synchronization clock signal fails to restore link transmission quality, it indicates that the signal integrity margin at the current operating frequency may be insufficient to support reliable transmission. In this case, the controller can reduce the clock frequency of the synchronization clock signal and resend the first read command to the storage device. Reducing the clock frequency of the synchronization clock signal increases the period width of each data bit, increasing the opening of the data eye diagram on the time axis, providing the receiver with more sufficient setup and hold time margins to improve data sampling errors caused by insufficient timing margins. After reducing the frequency, the controller re-receives data, recalculates and compares the checksum. If the comparison is consistent, it indicates that the link quality after reducing the frequency meets the data transmission requirements. The controller confirms the data transmission is correct and can record the current link status information for subsequent frequency decisions. If the comparison is still inconsistent, the clock frequency can be further reduced for retry.

[0073] In this embodiment, the above-mentioned exception handling methods can be used individually or in combination. For example, the controller can first try to resend the first read command to the storage device one or more times. If it still fails, it performs timing retraining of the synchronization clock signal. If the problem still exists, it reduces the clock frequency of the synchronization clock signal and tries again. Through a hierarchical progressive recovery strategy from link layer retransmission to physical layer timing retraining and then to frequency reduction, the controller can quickly recover when a link error occurs, ensuring the reliability of data reading and the availability of the system.

[0074] In yet another exemplary embodiment, the timing retraining of the synchronization clock signal includes the following steps: If the number of consecutive times the comparison results are inconsistent reaches a preset threshold, then timing retraining of the synchronization clock signal is triggered.

[0075] Timing retraining of the synchronous clock signal refers to the process of recalibrating the timing parameters of the synchronous clock signal. In high-speed data transmission, the phase relationship between the synchronous clock signal and the data signal directly affects the accuracy of data sampling. When the signal integrity of the transmission link changes due to factors such as temperature variations, voltage drift, or aging, the edge position of the synchronous clock signal may deviate from the optimal sampling point, leading to data sampling errors. Timing retraining adjusts the delay parameters, duty cycle, or edge position of the synchronous clock signal to restore the phase relationship between the synchronous clock signal and the data signal to its optimal state, thereby improving signal integrity.

[0076] The timing retraining is triggered by the checksum comparison results. A retry counter is installed in the controller to count the number of consecutive checksum comparisons that are inconsistent. After each checksum comparison, if the results are inconsistent, the controller increments the retry counter. If the results are consistent, the controller resets the retry counter. When the retry counter reaches a preset threshold, it indicates that the transmission link has experienced multiple consecutive errors, and simply re-performing the read operation is no longer sufficient to effectively restore link quality. At this point, the controller triggers timing retraining of the synchronization clock signal.

[0077] The specific process of timing retraining includes: the controller sending a timing retraining command to the storage device, which then enters timing retraining mode in response. During training, the controller sends a specific training sequence, gradually adjusts the delay parameter of the synchronization clock signal, and receives the training response returned by the storage device at each delay value. The optimal delay parameter is determined by evaluating the quality of the training response. After training is complete, the controller locks the synchronization clock signal to the optimal delay value and exits the training mode. After timing retraining is complete, the controller resends the first read command to the storage device, re-executes the read operation, and performs the checksum comparison again.

[0078] The preset threshold can be configured according to the reliability requirements of the application scenario. For example, in scenarios with sufficient signal integrity margin, the preset threshold can be set to a larger value to reduce unnecessary timing retraining. In scenarios with limited signal integrity margin, the preset threshold can be set to a smaller value to quickly respond to link quality degradation and restore link transmission quality in a timely manner.

[0079] In this embodiment, by associating the triggering of timing retraining with the number of consecutive verification failures, automatic linkage between link layer errors and physical layer timing adjustments can be achieved. This enables proactive recovery of link quality when link parameters drift due to changes in the working environment, preventing the system from passively reducing the transmission rate or reporting errors after signal integrity deteriorates.

[0080] In yet another exemplary embodiment, the verification calculation is a cyclic redundancy check calculation.

[0081] Cyclic Redundancy Check (CRC) is a data integrity verification algorithm based on polynomial division. It generates a fixed-length check value by calculating the data sequence. Its basic principle is to treat the data sequence to be checked as a binary polynomial, perform a modulo-2 division operation with a pre-determined generator polynomial, and the remainder is the CRC value.

[0082] During data transmission, the sending end performs a cyclic redundancy check (CRC) calculation on the original data to generate a check value, and the receiving end performs the same CRC calculation on the received data to generate a check value. By comparing whether the two check values ​​are consistent, it is determined whether an error occurred during data transmission.

[0083] In this embodiment, both the controller and storage device sides employ Cyclic Redundancy Check (CRC) as the specific implementation method for verification calculation. During the process of receiving data from the storage device, the controller performs CRC calculation byte-by-byte on the received data to generate a first check value. During the process of sending data to the controller, the storage device performs the same CRC calculation on the sent data to generate a second check value. Both sides use the same generator polynomial to ensure that the first and second check values ​​are consistent in the event of error-free data transmission.

[0084] Cyclic Redundancy Check (CRC) has strong error detection capabilities. Taking CRC-32 as an example, it can detect all single-bit errors, all double-bit errors, all odd-numbered bit errors, and all consecutive burst errors with a length not exceeding 32 bits. In this embodiment, by applying CRC to the read-direction data transmission link, it can detect data errors introduced by signal integrity issues such as synchronous clock signal degradation, jitter, and crosstalk.

[0085] In yet another exemplary embodiment, Figure 2 This application illustrates a data transmission method provided by an embodiment of the present application, applied to a storage device. The method includes the following steps: Step 210 responds to the first read command from the controller by sending data to the controller.

[0086] The storage devices within the storage system are slave devices used for persistent data storage. Internally, each storage device contains modules such as a storage cell array, page cache, physical layer interface, and command parser. The storage cell array consists of multiple storage cells, with data stored in units of pages. The page cache temporarily stores data read from the storage cells; data is first read from the storage cells and temporarily stored in the page cache before being sent to the controller.

[0087] In this step, the storage device receives a first read command from the controller via its second physical layer interface. The command parser decodes and identifies the received command. After recognizing the first read command, the storage device reads the target data from the memory cell into the page cache and sends the data to the controller via the second physical layer interface and the data bus. Simultaneously, the storage device can also send a synchronization clock signal to the controller, which provides a timing reference for data sampling. For a standard NAND Flash interface, the first read command can be a command sequence; the storage device executes the read operation after receiving the complete read command sequence and the target address.

[0088] Step 220: During the process of sending the data to the controller, the data is verified and a second verification value is generated and stored.

[0089] The second checksum can be the checksum result obtained by the storage device performing a checksum calculation on the transmitted data during the data transmission process. The storage device temporarily stores the second checksum in its internal second register, waiting for the controller to read it. The checksum calculation algorithm used for the second checksum is the same as the checksum calculation algorithm used on the controller side to ensure that the checksums calculated on both sides are consistent when there are no errors in the data transmission. In some embodiments, the checksum calculation can be a cyclic redundancy check calculation, that is, both the storage device side and the controller side use the same cyclic redundancy check generator polynomial.

[0090] The storage device internally houses a second calculation module, which is piped into the data transmission path between the second physical layer interface and the page cache. During the process of the storage device reading data from the page cache and sending it to the controller via the second physical layer interface, the data is simultaneously fed into the second calculation module for real-time verification calculation. In some embodiments, the verification calculation is performed synchronously with the transmission of the synchronization clock signal. The storage device sends a synchronization clock signal to the controller while transmitting data; each edge of the synchronization clock signal corresponds to one data byte. The second calculation module performs a partial calculation on each data byte at each edge and updates the intermediate verification value. When all data has been transmitted, the second verification value is also synchronously calculated and stored in the second register. Because the verification calculation is performed synchronously with data transmission, no additional computational delay is introduced.

[0091] Step 230: In response to the second read command from the controller, the second verification value is returned to the controller.

[0092] The second read command is sent by the controller after data reception is complete, and is used to read the second checksum calculated by the storage device. This second read command has a different command code than the first read command to distinguish their functions. This second read command does not involve reading data from the storage unit, nor does it involve outputting data from the page cache; it only outputs the checksum temporarily stored in the internal register to the controller via the data bus.

[0093] In this step, the storage device receives a second read command from the controller via the second physical layer interface. The command parser decodes and identifies the second read command. After recognizing the second read command, the storage device returns the second checksum stored in its second register to the controller via the data bus. This return operation only requires a few bus cycles to complete, with minimal time overhead. After the return is complete, the storage device continues to operate normally, waiting for subsequent read operations or other commands from the controller.

[0094] In this embodiment, the storage device performs a verification calculation during the read operation and returns the verification value to the controller, enabling the controller to perform integrity verification on the transmission link after data reception, providing a basis for subsequent error correction control.

[0095] In yet another exemplary embodiment, based on step 220 of the above embodiment, during the process of sending the data to the controller, the data is subjected to verification calculation to generate and store a second verification value. The method of this embodiment may further include the following specific steps: A synchronization clock signal is sent to the controller, and the verification calculation is performed synchronously with the transmission of the synchronization clock signal.

[0096] The synchronization clock signal is used to coordinate the timing of data transmission between the data transmitter and receiver. In high-speed data transmission, the transmitter drives data output based on the edge of the synchronization clock signal, and the receiver samples the data based on the edge of the same synchronization clock signal, thereby ensuring correct latching and recovery of data during transmission. In some implementations, the synchronization clock signal may specifically be a data strobe signal.

[0097] In this step, the storage device sends a synchronization clock signal to the controller while sending data. This synchronization clock signal is transmitted synchronously with the data signal and serves as the timing reference for the controller's data sampling. The storage device drives the data output on the data bus according to the edges of the synchronization clock signal, with each edge corresponding to one data byte.

[0098] In some implementations, the verification calculation is performed synchronously with the transmission of the synchronization clock signal. A second calculation module within the storage device uses the edge of the synchronization clock signal as a trigger reference. Each time a data byte is transmitted, it is simultaneously fed into the second calculation module for partial calculation. The second calculation module performs a partial calculation on that byte and updates the intermediate verification value. Because the verification calculation is performed synchronously with the data transmission driven by the synchronization clock signal, the second verification value is also calculated synchronously when all data has been transmitted, eliminating the need for additional time overhead. Furthermore, this synchronous design allows the verification calculation to match high-speed data transmission rates, meeting the real-time verification requirements of the NAND Flash interface in high-frequency mode.

[0099] In this embodiment, the storage device sends a synchronization clock signal to the controller simultaneously with the data transmission. Verification calculation is performed synchronously with the transmission of this synchronization clock signal. By synchronizing the verification calculation on the storage device side with the data transmission process, the verification result is generated upon completion of data transmission. The controller can immediately obtain the second verification value after sending the second read command, without waiting for additional calculation time. The synchronization clock signal can include various specific implementations such as a data strobe signal, and is applicable to various storage interface standards, including NAND Flash and DDR memory, exhibiting good versatility and scalability.

[0100] In yet another exemplary embodiment, the verification calculation is a cyclic redundancy check calculation, as detailed in the relevant descriptions of the foregoing embodiments.

[0101] Corresponding to the data transmission method provided in the above embodiments, based on the same technical concept, this application also provides a controller. See Figure 3 The controller 300 includes a read data buffer 310, a first physical layer interface 320, a first calculation module 330, a first register 340, a command generator 350, and a comparator 360.

[0102] The system includes: a read data buffer 310; a first physical layer interface 320 for communicating with the storage device; a first calculation module 330 for performing verification calculations on the data received from the storage device to generate a first verification value; a first register 340 for storing the first verification value; a command generator 350 for generating a first read command and a second read command, wherein the first read command controls the storage device to send data to the controller, and the second read command reads the second verification value generated by the storage device during the data transmission to the controller; and a comparator 360 for comparing the first verification value and the second verification value, wherein if the comparison results are consistent, the data transmission is confirmed to be correct, and if the comparison results are inconsistent, an exception handling operation is performed.

[0103] In yet another exemplary embodiment, the verification calculation is a cyclic redundancy check calculation.

[0104] It should be noted that the controller and components provided in this application embodiment are based on the same application concept as the data transmission method applied to the controller provided in this application embodiment. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned data transmission method, and repeated parts will not be described again.

[0105] Corresponding to the data transmission method provided in the above embodiments, based on the same technical concept, this application also provides a storage device. See Figure 4 The storage device 400 includes a second physical layer interface 410, a second computing module 420, a second register 430, and a command parser 440.

[0106] The second physical layer interface 410 is used to communicate with the controller; the second calculation module 420 is used to perform verification calculation on the data during the process of sending data to the controller and generate a second verification value; the second register 430 is used to store the second verification value; and the command parser 440 is used to parse the first read command and the second read command from the controller, wherein, in response to the first read command, data is sent to the controller, and in response to the second read command, the second verification value is returned to the controller.

[0107] In yet another exemplary embodiment, the verification calculation is a cyclic redundancy check calculation.

[0108] It should be noted that the storage device and components provided in this application embodiment are based on the same application concept as the data transmission method applied to the storage device provided in this application embodiment. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned data transmission method, and repeated parts will not be described again.

[0109] Corresponding to the data transmission method provided in the above embodiments, based on the same technical concept, this application also provides a data transmission system. See [link to previous document]. Figure 5 The data transmission system 500 includes a controller 510 and a storage device 520. The controller 510 is the controller described in the previous embodiments; the storage device 520 is the storage device described in the previous embodiments.

[0110] It should be noted that the specific implementation of the controller and storage device in the embodiments of this application can be found in the description of the controller and storage device provided in the foregoing embodiments, and the repeated parts will not be described again.

[0111] In yet another exemplary embodiment, a method for protecting the NAND Flash read-direction data transmission link is proposed. Figure 6The module division and connection relationship between the controller chip and the NAND Flash chip are shown. The controller chip and the NAND Flash chip are connected as two equal computing entities through a standard ONFI or Toggle physical interface. It includes an 8-bit DQ data bus, DQS differential data strobe signal, REn read enable signal, WEN write enable signal, CEN chip select signal, and ALE / CLE address / command latch signal. The controller chip side and the NAND Flash chip side use the same CRC algorithm.

[0112] The main modules on the controller chip side include write data channel, read data channel, TX CRC calculation, RX CRC calculation, task control and scheduling, CRC comparison and control, protocol processor, etc.

[0113] The write data channel is used for write direction and data ECC encoding, such as BCH / LDPC.

[0114] The read data channel is used to receive read data and perform ECC decoding and error correction.

[0115] The CRC calculation at the transmitting end (Transmit, TX) and the CRC calculation at the receiving end (Receive, RX) are used to perform real-time CRC calculations while data is being transmitted.

[0116] Task control and scheduling are used to schedule tasks sent from the host and tasks sent from the chip's internal firmware. CRC comparison and control is used to compare the CRC data obtained by the read CRC command. When the CRC comparison fails, an interrupt can be reported to the error correction module to avoid invalid error correction calculations and wasted power, and the data buffer can be cleared. Optional triggering logic includes the retransmission counting / threshold module and DQS retraining.

[0117] The protocol processor is used to convert the main control chip's NAND operations into NAND interface protocols. It supports the Read CRC command (as a second read command). For example, the command code can be 79h-LUN, selected from the ONFI reserved command code space, or obtained using the get feature command.

[0118] The modules on the NAND Flash chip side mainly include CRC calculation circuit, CRC result register, command parser, etc.

[0119] The CRC calculation circuit is used for read-write multiplexing, performing real-time CRC calculations while data is being transmitted.

[0120] The CRC result register is used to uniformly store the CRC calculation result of the current operation, and the write direction and read direction are distinguished by the address parameter.

[0121] The command parser is used to support the Read CRC command.

[0122] See Figure 7 During a complete read operation, the controller can decide whether to enable link checking based on preset conditions. For example, the CRC check process in the read direction can be performed after data transmission is complete and before the data is sent to the error correction module, to prevent link errors from propagating downstream at the source. Specific steps include the following: Step 601: The controller sends the 00h command, the target address, and the 30h confirmation command.

[0123] Taking the ONFI standard as an example, when the controller performs a page read operation, it first sends a 00h command to the storage device through a command latch cycle. This command notifies the storage device that a data read operation is about to begin. Subsequently, the controller sends the target address through an address latch cycle, specifying the storage location of the data to be read. Finally, the controller sends a 30h command, which confirms that the address has been sent and triggers the storage device to perform an internal read operation. After receiving the 30h command, the storage device reads the target data from the memory cell array into the page cache. This process requires a certain internal read time tR. After the tR delay, the data is ready, and the controller can read the data from the page cache through a data output command.

[0124] Step 602: After the NAND flash memory has been read by the tR read delay, data is read from the storage array into the page cache.

[0125] Step 603: The controller sends a random data out command to the NAND, then toggle REn, and the NAND starts driving DQS and DQ output data.

[0126] Step 604: During data transmission, the NAND flash memory calculates the TX CRC while outputting data, and the controller calculates the RX CRC while receiving data. Received data enters the read data buffer and the error correction module.

[0127] Step 605: Wait for the data transfer to complete. It should be noted that the data can be of any length and does not necessarily have to be a page.

[0128] Step 606: The controller sends a Read CRC command to obtain the CRC value of the NAND terminal.

[0129] Step 607: The controller compares the RX CRC with the CRC value at the NAND terminal. If the comparison matches, wait for the error correction module to complete before ending the task.

[0130] If the comparison is inconsistent, the hierarchical recovery process is initiated: triggering the read retry process, rereading data from step 601, and incrementing the read retry counter by 1; triggering read data transmission and retraining when the number of retries reaches the threshold, and rereading after completion; or triggering a reduction in data transmission frequency and then rereading.

[0131] By performing CRC checks in the read direction as described above, link errors and memory cell errors can be distinguished. When the CRC does not match, it indicates that an error occurred during the data transmission link from the NAND page register output to the controller reception, such as DQS degradation or signal interference, but the data in the NAND page register is correct. In this case, there is a high probability that the correct data can be recovered by retrying the read (i.e., rereading from the memory array to the page register and then outputting it again). If the CRC matches after multiple retries but the data content is incorrect, for example, as detected by ECC, it indicates that the error originates from the memory cell itself, and a bad block management strategy should be adopted.

[0132] In yet another exemplary embodiment, a read command, Read CRC, is proposed as a second read command for reading the CRC result in the read direction. In some implementations, the command code can use the VendorSpecific reserved command code space in the ONFI / Toggle specification, for example, 79h + LUN address + CRC data, to avoid conflicts with existing commands. The NAND returns the CRC result via the DQ bus after a t_READ_CRC delay. This command does not affect page cache data or programming status. In some implementations, the get feature command can be used directly to read CRC information from the corresponding LUN particle's internal register.

[0133] See Figure 8 The complete timing sequence of the Read CRC command consists of four phases: the command phase (CMD, command code 79h), the address phase (ADDR, 1 LUN address cycle), the wait phase (WAIT t_READ_CRC), and the data return phase (DATA, CRC[31:0]). CE# is active low throughout, DQS remains inactive during the wait phase, and toggle is restored during the CRC data return phase.

[0134] The timing parameters include the following: t_CRC_CALC: CRC calculation time, calculated on the side of transmission, with approximately zero additional latency; t_READ_CRC: Read CRC command read latency, typically 80ns.

[0135] The data transmission method and system provided in this application embodiment perform CRC calculations independently by the controller and NAND Flash during NAND Flash write data transmission. However, the CRC value is not transmitted as part of the data stream, avoiding changes to the existing NAND Flash protocol. Read-direction CRC verification blocks the propagation of link errors to the error correction module. Read data is verified for the correctness of the read transmission link through CRC verification. If the CRC fails, link layer error information is sent to the error correction decoding module, avoiding invalid error correction calculations and triggering error correction processes. Read-direction CRC verification distinguishes between read-direction link errors and memory cell errors. When the CRC does not match, it is determined to be a link error and retry recovery is performed to avoid mislabeling bad blocks. When the CRC matches but the data is erroneous, it is determined to be a memory cell error, and error correction processes such as VTH hard decode and soft decode are performed. A hierarchical recovery strategy can be implemented in the read direction, for example, from link layer retransmission to physical layer DQS retraining. When read-direction CRC comparison fails, link layer retransmission is attempted first. After multiple failures, DQS retraining is triggered, and the transmission frequency is reduced.

[0136] This application provides a NAND Flash controller, including a TX CRC calculation module, an RX CRC calculation module, a read / write data buffer, a command generator, a CRC comparison and control module, and a data error correction encoding / decoding module.

[0137] This application provides a NAND Flash chip, including an RX CRC calculation module, a TX CRC calculation module, a CRC result register, and a command parser, for responding to a unified CRC read command.

[0138] This application provides a Read CRC command for NAND Flash, used to read the CRC check result calculated by the NAND Flash for read / write data transfer. Commands designed by the NAND vendor can be used, such as 79h+LUN+CRC data or the get feature command.

[0139] This application provides a read link error recovery operation. When reading data, the correctness of the read transmission link is verified by CRC check. If the CRC fails, the link layer error information is sent to the error correction decoding module to avoid invalid error correction calculation and triggering the error correction process. The data buffer is cleared, and the controller is triggered to restart the read operation to re-transmit data and perform error correction.

[0140] This application provides a method for retransmitting NAND Flash data. When the CRC check link layer transmission fails, the controller restarts the read data transmission, including full retransmission, incremental retransmission, and adaptive retransmission strategies. If multiple retransmissions fail, the NAND IO interface is retrained.

[0141] This application provides a configurable NAND Flash data verification strategy. The controller dynamically decides whether to perform a Read CRC check based on factors such as transmission frequency, PCB signal integrity margin assessment results, historical bit error rate statistics, and application reliability requirements.

[0142] The controller in this application embodiment can flexibly decide whether to enable link checks based on the actual SI risk level of the application scenario. In low-speed, short-distance, and stable environments, checks can be skipped to achieve maximum throughput. In high-speed, long-distance, multi-connector, or unknown SI conditions, checks can be enabled to ensure data integrity. This adaptive strategy provides flexibility for system designers.

[0143] The data transmission method and system of this application can block the propagation of read link errors to ECC. Through a data gating mechanism, data is only sent to the error correction module after CRC confirms that the link is error-free. The error correction module avoids invalid iterative decoding of data containing a large amount of link noise, which can reduce dynamic power consumption and solve the problem of the number of iterations of LDPC soft decoding surging due to a large number of link errors. There is no need to consume internal bus bandwidth for additional reading or soft decoding data transfer for link errors, affecting other parallel read and write tasks. It prevents the controller from misjudging instantaneous link errors as severe degradation of NAND media, avoiding triggering unnecessary Read Retry offset adjustment, LDPC soft decoding rollback, off-site data reconstruction, or bad block marking, thus extending the lifespan of NAND.

[0144] The data transmission method and system of this application can distinguish between link errors and memory cell errors through read-direction CRC check. When the CRC does not match, it is determined that the transmission error is caused by a link SI problem, and a retry recovery is performed to avoid mislabeling bad blocks. When the CRC matches but the data is erroneous, it is determined that the memory cell is physically degraded, and bad block management is performed. This ability to distinguish can reduce unnecessary bad block marking and extend the lifespan of NAND Flash. When the CRC check fails continuously, retraining is automatically initiated, which can recalibrate the DQS timing, restore the transmission quality of the link, and avoid the system being able to passively slow down or report errors after SI deterioration. It can adapt to changes in SI conditions caused by changes in the working environment (such as temperature drift, aging, etc.).

[0145] The data transmission method and system of this application embodiment do not change the existing protocol and have zero additional bandwidth consumption. The CRC value is calculated independently on the controller side and the NAND Flash side, and is not transmitted with the data stream. It does not change the existing NAND Flash standard command protocol data transmission format at all, and does not require significant modification to the core protocol state machine of the NAND Flash chip. Only a CRC calculation circuit and Read CRC command recognition logic need to be added, making the complexity controllable and not affecting forward compatibility with existing NAND Flash controllers. The CRC calculation circuit has extremely small area and power consumption overhead, and the data gating logic only requires simple switching control, without complex data processing. The training control module reuses the existing training hardware, requiring only the addition of a state machine and triggering logic.

[0146] Corresponding to the data transmission method provided in the above embodiments, based on the same technical concept, this application also provides an electronic device for executing the above method, including a controller; and a storage device communicatively connected to the controller; wherein the controller is configured to execute the data transmission method applied to the controller as described above, and the storage device is configured to execute the data transmission method applied to the storage device as described above.

[0147] This application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer, implement the steps of the data transmission method described above.

[0148] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, apparatus, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0149] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems, devices), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0150] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0151] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0152] In a typical configuration, an electronic device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0153] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0154] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0155] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0156] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0157] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A data transmission method applied to a controller, characterized in that, The method includes the following steps: Send a first read command to the storage device, the first read command being used to control the storage device to send data to the controller; The data is received from the storage device, and during the process of receiving the data, the data is verified and a first verification value is generated and stored. After receiving the data, a second read command is sent to the storage device. The second read command is used to read the second check value generated by the storage device during the process of sending the data to the controller. Receive the second verification value returned by the storage device in response to the second read command; Compare the first check value and the second check value. If the comparison results are consistent, the data transmission is confirmed to be correct. If the comparison results are inconsistent, an exception handling operation is performed.

2. The method according to claim 1, characterized in that, The step of receiving data from the storage device, and performing verification calculations on the data during the data reception process to generate and store a first verification value, further includes the following steps: A synchronization clock signal is received from the storage device, and the verification calculation is performed synchronously with the transmission of the synchronization clock signal.

3. The method according to claim 1, characterized in that, The step of comparing the first check value and the second check value, and confirming that the data transmission is correct if the comparison results are consistent, and performing an exception handling operation if the comparison results are inconsistent, further includes the following steps: If the comparison results are consistent, error correction processing of the data is permitted; If the comparison results are inconsistent, error correction processing of the data is prohibited.

4. The method according to claim 1, characterized in that, The exception handling operation includes at least one of the following: Resend the first read command to the storage device; Perform timing retraining on the synchronous clock signal; Reduce the clock frequency of the synchronization clock signal and resend the first read command to the storage device.

5. The method according to claim 4, characterized in that, The timing retraining of the synchronous clock signal includes the following steps: If the number of consecutive times the comparison results are inconsistent reaches a preset threshold, then timing retraining of the synchronization clock signal is triggered.

6. The method according to claim 1, characterized in that, The verification calculation is a cyclic redundancy check calculation.

7. A data transmission method applied to a storage device, characterized in that, The method includes the following steps: In response to a first read command from the controller, data is sent to the controller; During the process of sending the data to the controller, the data is verified and a second verification value is generated and stored. In response to a second read command from the controller, the second verification value is returned to the controller.

8. The method according to claim 7, characterized in that, The step of performing verification calculations on the data during the process of sending the data to the controller, generating and storing a second verification value, further includes the following steps: A synchronization clock signal is sent to the controller, and the verification calculation is performed synchronously with the transmission of the synchronization clock signal.

9. The method according to claim 7, characterized in that, The verification calculation is a cyclic redundancy check calculation.

10. A controller, characterized in that, include: Read data buffer; The first physical layer interface is used to communicate with storage devices; The first calculation module is used to perform verification calculations on the data during the process of receiving data from the storage device and generate a first verification value. A first register is used to store the first verification value; A command generator is used to generate a first read command and a second read command. The first read command is used to control the storage device to send data to the controller, and the second read command is used to read a second check value generated by the storage device during the process of sending the data to the controller. as well as A comparator is used to compare the first check value and the second check value. If the comparison results are consistent, the data transmission is confirmed to be correct. If the comparison results are inconsistent, an exception handling operation is performed.

11. The controller according to claim 10, characterized in that, The verification calculation is a cyclic redundancy check calculation.

12. A storage device, characterized in that, include: The second physical layer interface is used for communication with the controller; The second calculation module is used to perform verification calculations on the data during the process of sending data to the controller, and generate a second verification value. The second register is used to store the second verification value; as well as A command parser is used to parse a first read command and a second read command from the controller, wherein, in response to the first read command, data is sent to the controller, and in response to the second read command, the second check value is returned to the controller.

13. The storage device according to claim 12, characterized in that, The verification calculation is a cyclic redundancy check calculation.

14. A data transmission system, characterized in that, include: The controller as described in any one of claims 10 to 11; as well as The storage device as described in any one of claims 12 to 13.

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