Transmit driver impedance calibration technique for bidirectional serializer / deserializer

Abstract

This disclosure relates to a transmit driver impedance calibration technique for a bidirectional serializer / deserializer. A method for calibrating the impedance of a first TX driver of a first bidirectional SerDes, wherein the first bidirectional SerDes is connected to a second bidirectional SerDes via a data transmission line and the second bidirectional SerDes includes a second TX driver, wherein, for each of a plurality of driver impedance code values ​​applied to the first TX driver, transmission of a data pattern corresponding to the impedance code value is received at the second SerDes; and eye diagram height of the data sequence transmitted by the second SerDes is measured at the second SerDes. The method further includes determining an eye diagram height that includes a maximum eye diagram height among the measured eye diagram heights, and transmitting driver impedance code values ​​from the second SerDes to the first SerDes, the driver impedance code values ​​corresponding to one of the eye diagram heights including the maximum eye diagram height for the first TX driver.

Description

Priority application

[0001] This patent application claims priority and / or benefit to U.S. Provisional Application No. 63 / 779,261, filed March 27, 2025, entitled “New Transmit (Tx) Driver Impedance Calibration Method for Bidirectional SerDes,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to transmit driver impedance calibration techniques, and more specifically to transmit driver impedance calibration techniques for bidirectional serializers / deserializers. Background Technology

[0003] The impedance of a bidirectional serializer / deserializer (SerDes) emitter (TX) driver can be calibrated so that the output impedance of the driver is the same as the characteristic impedance of the transmission line to which the SerDes is connected. The purpose of TX driver impedance calibration is to minimize reflections of the TX driver output signal, thereby maximizing the achievable signal eye diagram height on the transmission line.

[0004] Impedance calibration associated with bidirectional serializer / deserializer (SerDes) transmit (TX) drivers is typically achieved by using a scaled-down replica driver, constant current, and constant bandgap voltage to target the master driver's impedance. This technique has several drawbacks, including but not limited to low accuracy. Furthermore, it must be integrated into each TX lane in the SerDes, which increases circuit area and unnecessarily increases power consumption. Therefore, a more efficient technique for performing TX driver impedance calibration is needed. Summary of the Invention

[0005] One aspect of this disclosure provides a method for calibrating the impedance of a first transmit TX driver of a first bidirectional serializer / deserializer SerDes, wherein the first bidirectional SerDes is connected to a second bidirectional SerDes via a data transmission line, the second bidirectional SerDes including a second TX driver, the method comprising: measuring, at the second SerDes, an eye diagram height of an eye diagram of a data sequence transmitted by the second SerDes for each of a plurality of driver impedance code values ​​applied to the first TX driver; determining an eye diagram height among the measured eye diagram heights that includes a maximum eye diagram height; and transmitting a driver impedance code value from the second SerDes to the first SerDes, the driver impedance code value corresponding to one of the eye diagram heights including the maximum eye diagram height for the first TX driver.

[0006] A calibration system includes: a first serializer / deserializer (SerDes) including a first transmit driver; a second SerDes including a second transmit driver and connected to the first SerDes via a data transmission line; wherein the first SerDes further includes circuitry for controlling the impedance of the first transmit driver based on an impedance code received from the second SerDes; and wherein the second SerDes further includes: circuitry for performing the following steps for each of a plurality of impedance code values: transmitting the impedance code value to the first SerDes, the first SerDes using the impedance code value to control the impedance of the first transmit driver; measuring the eye height of an eye diagram of a predetermined data sequence transmitted by the second SerDes; circuitry for determining an eye height among the measured eye heights that includes the maximum eye height of the first transmit driver; and circuitry for communicating the impedance code value to the first SerDes, the impedance code value being associated with the eye height including the maximum eye height of the first transmit driver.

[0007] A calibration system includes: a first serializer / deserializer (SerDes) including a first transmit driver, wherein the impedance of the first transmit driver is controlled by an impedance code; a second SerDes including a second transmit driver and connected to the first SerDes via a data transmission line, the second SerDes further including circuitry for measuring the eye diagram of the second transmit driver, the circuitry including: a sampler for sampling data at the output of the second transmit driver; an error counter for comparing data output from the sampler with local data and outputting an error signal indicating whether the data output from the sampler is the same as the local data; and a delay tuning block for tuning the delayed clock of the sampler. Attached Figure Description

[0008] The embodiments will be readily understood from the following detailed description in conjunction with the accompanying drawings. For ease of description, the same reference numerals designate the same structural elements. The embodiments are shown in the drawings by way of example rather than limitation.

[0009] Figure 1A A block diagram of a processor module including an AI server processor according to some embodiments of the present disclosure is shown.

[0010] Figure 1B Some embodiments according to this disclosure are shown. Figure 1A Block diagram of the die-to-die clock and serializer-deserializer (SerDes) circuit of the processor module.

[0011] Figure 2 Example eye diagrams are shown according to some embodiments of this disclosure.

[0012] Figures 3A-3B A block diagram of an example system for performing TX driver impedance calibration in a bidirectional SerDes is shown, according to some embodiments of the present disclosure.

[0013] Figure 4 The following are illustrations of some embodiments of the present disclosure. Figures 3A-3B The flowchart shows an example operation related to the system used to perform TX driver impedance calibration in bidirectional SerDes. Detailed Implementation

[0014] Overview

[0015] Based on the features of the embodiments described herein, an innovative technique for performing TX driver impedance calibration in a bidirectional SerDes system is described. In a particular embodiment, TX drivers at both ends of a set of transmission lines transmit data simultaneously, each driver being treated as a resistor termination relative to an opposite driver. The eye diagram height of each TX driver is maximized when the impedance of the opposite TX driver equals the characteristic impedance of the transmission line. According to the features of the embodiments described herein, the TX driver impedance calibration technique directly monitors the eye diagram height of the TX drivers and adjusts the impedance of the opposite TX driver accordingly using sideband communication, thereby eliminating the need for duplicate drivers, constant current, and bandgap voltage required by previous calibration techniques.

[0016] Exemplary AI Server Processor

[0017] AI server processors are high-performance integrated circuits designed to perform computationally intensive workloads such as AI inference, training, and large-scale server operations. Such AI server processors typically include several common components, including a scalable core complex, die-to-die interconnects (I / O subsystem), phase-locked loops (PLLs), memory hierarchies, and power and thermal management.

[0018] A scalable core complex may include multiple processing cores arranged in a scalable architecture to support different performance and power requirements. Each core may include vector or matrix acceleration units optimized for AI workloads, as well as a general-purpose execution pipeline for server tasks. The cores may be interconnected via a high-bandwidth on-chip interconnect structure to enable low-latency communication and dynamic workload allocation.

[0019] Die-to-die interconnects or I / O subsystems may include high-speed die-to-die interfaces for connecting multiple processor dies within a package or across chiplets. These interfaces can utilize advanced signaling technologies to achieve low-latency and high-throughput memory access and inter-processor communication. The I / O subsystems typically support coherence protocols to maintain data consistency across dies.

[0020] PLL circuits can be used to generate and synchronize clock signals for the processor core and I / O interfaces. Multiple PLLs can be distributed on the die to provide local clock domains, ensuring timing integrity for high-speed links and scalable core clusters. PLLs can also enable dynamic frequency scaling to optimize performance and energy efficiency.

[0021] The memory hierarchy can include integrated cache structures (e.g., L1, L2, and shared L3) to reduce memory access latency. An external memory controller can be provided to support Double Data Rate (DDR), HBM, or other high-bandwidth memory technologies for large-scale data processing.

[0022] Power and thermal management may include an on-chip power delivery network and voltage regulators for fine-grained control of core and I / O power states. Temperature sensors and dynamic throttling mechanisms may be provided to maintain operational reliability under heavy loads.

[0023] Figure 1AA processor module 10 is shown, comprising an AI server processor 100 configured for scalable computational throughput and multi-die expansion. The processor 100 includes a scalable core array 110 coupled to an interconnect structure 130. The scalable core array 110 includes multiple processor cores 112 arranged as one or more core clusters, core tiles, or core complexes, and private or semi-private cache resources, such as L1 / L2 caches 114. The interconnect structure 130 provides communication between the scalable core array 110, shared cache 120, AI accelerator 140, memory subsystem 150, and die-to-die I / O subsystem 170. The shared cache 120 provides a shared final cache (LLC), system-level cache (SLC), or other shared cache architecture to support reduced off-chip bandwidth requirements and reduced average memory access latency for workloads including AI inference, AI training, and server processing.

[0024] AI accelerator 140 includes one or more fixed-function or programmable engines that perform matrix, vector, or tensor operations, with data paths supporting parallel multiply-accumulate (MAC) operations and optional sparsity, quantization, or mixed-precision processing. DMA / copy engine 160 supports data movement between shared cache 120, memory subsystem 150, AI accelerator 140, and peripheral interfaces, with its queuing structure and command processor supporting asynchronous transfers, scatter-aggregate operations, and memory-to-memory copy operations.

[0025] The memory subsystem 150 includes one or more memory controllers 152 and one or more memory physical interfaces (PHYs) 154 that couple the processor 100 to external memory 60. External memory 60 includes high-bandwidth memory (HBM), double data rate memory (DDR), or other memory technologies. The memory controllers 152 support scheduling, refresh, sorting rules, and quality of service (QoS) arbitration, while the memory PHYs 154 support high-speed signaling, training, and calibration of memory channels.

[0026] The die-to-die I / O subsystem 170 provides high-speed communication between the processor 100 and at least one additional die or chiplet within the module 10. The die-to-die I / O subsystem 170 includes a protocol layer 171, a serializer / deserializer circuit (SerDes) 172, and a link training / equalization circuit 173. Protocol layer 171 supports grouping, ordering, flow control, and optional consistency semantics for transactions traversing the die-to-die path 175. Link training / equalization circuit 173 supports path initialization, deskipation, equalization setting selection, margin testing, and retry behavior. Die-to-die path 175 supports high-throughput point-to-point signaling implemented as a parallel single-ended path, a differential path, or a combination thereof, with optional forward error correction (FEC) and cyclic redundancy check (CRC) protection. In some embodiments, the die-to-die I / O subsystem 170 supports coherent communication that maintains cache consistency between shared cache 120 instances distributed across multiple dies, wherein the protocol layer 171 exchanges consistency messages and associated data payloads via die-to-die path 175.

[0027] Clock system 180 supports the generation and distribution of timing for scalable core array 110, interconnect structure 130, memory subsystem 150, and die-to-die I / O subsystem 170. Clock system 180 includes a reference clock source 182, one or more PLLs 184, and clock distribution / division circuitry 186. Reference clock source 182 provides a reference frequency derived from an oscillator, onboard clock, or package-distributed clock. PLLs 184 generate one or more synthesized clocks whose frequency and phase are adapted to the core clock domain, structure clock domain, memory clock domain, and I / O clock domain. PLLs 184 provide frequency multiplication and optional fractional synthesis, jitter filtering, and phase alignment to support timing convergence for high-speed interfaces. Clock distribution / division circuitry 186 distributes the synthesized clock to the clock domains and may include dividers, multiplexers, glitch-free clock switching logic, clock gating units, and cross-clock domain (CDC) support circuitry. In some embodiments, the clock system 180 includes independent PLL instances 184 assigned to different domains, including core PLL instances supporting scalable core array 110 and I / O PLL instances supporting die-to-die I / O subsystem 170, each domain having independent voltage and frequency scaling.

[0028] The power and thermal management subsystem 190 supports power delivery and reliability of the processor 100. Subsystem 190 includes voltage regulation circuitry 192 and sensor circuitry 194. Voltage regulation circuitry 192 includes an integrated voltage regulator, a low-dropout regulator, a switched-capacitor regulator, or a digitally controlled external regulator interface. Sensor circuitry 194 includes a temperature sensor, a voltage monitor, a current monitor, and a performance counter for performing power and thermal limiting. In some embodiments, subsystem 190 controls dynamic voltage and frequency scaling (DVFS) by controlling PLL 184 and domain voltage rails, a strategy that maintains performance targets while satisfying thermal and power constraints.

[0029] The security / manageability subsystem 195 supports platform security and operational management. Subsystem 195 includes a root of trust circuit 196 and a management controller or firmware processor 198. The root of trust circuit 196 supports secure boot, key storage, authentication, and cryptographic primitives. The management controller 198 supports telemetry, debug access control, and lifecycle management functions, including configuring the die-to-die I / O subsystem 170, configuring the clock system 180, and configuring the power / thermal management subsystem 190.

[0030] Figure 1B A die-to-die path clock arrangement is illustrated, implemented by die 20A coupled to die 20B via die-to-die path 175. Die 20A includes a reference clock input 182A coupled to PLL 184A. PLL 184A generates a transmit (TX) clock 185A, which drives a serializer / TX SerDes 172A. The serializer / TX SerDes 172A transmits serial data via die-to-die path 175 through link conditioning via equalization circuitry 173A. Die 20B includes a reference clock input 182B coupled to PLL 184B. In one embodiment, PLL 184B generates one or more receive (RX) clocks 185B to support sampling and recovery of the deserializer / RX SerDes 172B. In another embodiment, the deserializer / RXSerDes 172B includes Clock Data Recovery (CDR) within circuitry 173B, which recovers the sampled phase from transitions embedded in the path signaling. PLL 184B provides a low-jitter local reference for CDR loop stability or retiming. Protocol / link layers 171A and 171B perform link initialization, path alignment, deskipation, and integrity checks before presenting transactions to consistency / structure ports 130A and 130B. This arrangement supports scalable multi-die constructions by replicating dies to die instances and expanding path counts, where PLL instances support clock domain isolation and jitter management for incremental link speeds.

[0031] Example eye diagram height in a data transmission system

[0032] The quality or integrity of a digital signal transmitted from a transmitter to a receiver through a transmission channel can be affected by many factors, including the transmitter itself, the transmission channel, and factors such as cables or PCB traces and connectors. Signal quality is also known as signal integrity. An eye diagram is a graphical tool used to evaluate the quality of a digital signal. It can be described as an infinite, continuous superposition of all the bits captured by an oscilloscope to show when the bits are valid, providing a composite picture of the overall quality of the system's physical layer characteristics. The eye diagram covers all possible combinations of variations that affect the signal, including amplitude, timing uncertainties, and uncommon signal anomalies.

[0033] Eye height refers to the peak-to-peak vertical measurement of an eye diagram (usually measured at the center of the eye diagram), corresponding to the signal-to-noise ratio (SNR) of the transmitted signal represented by the eye diagram. Therefore, eye height indicates the amount of noise present in the transmitted signal. A larger eye height / more open eye diagram indicates less noise in the transmitted signal, while a smaller eye height / closer eye diagram indicates severe signal degradation. Eye height is used to determine the signal quality in a system and is therefore a key indicator for evaluating digital communication signals.

[0034] Figure 2 A schematic diagram of eye diagram 200 is shown, with eye diagram height 202 measured at the horizontal center of eye diagram 200. (See diagram for details.) Figure 2 As shown, the eye diagram height 202 is at low voltage V L and high voltage V H Extending between. The eye width 204 of eye diagram 200 is measured at the vertical center of eye diagram 200, corresponding to the reference voltage V in the schematic diagram shown. REF .

[0035] Example system for impedance calibration of TX driver in bidirectional SerDes systems

[0036] Figures 3A-3B A block diagram of an example 300 system for performing TX driver impedance calibration in a bidirectional SerDes is shown, according to some embodiments of the present disclosure. Figures 3A-3B As shown, system 300 includes a first die 302A and a second die 302B, each die including TX circuit devices 304A and 304B connected via bidirectional die-to-die paths 306. In a particular embodiment, there are 64 die-to-die paths, each with a corresponding TX circuit; however, for simplicity and ease of explanation, Figures 3A-3B Only a single representative path (with the corresponding TX circuit) is shown and described in the figure.

[0037] Each TX circuit device 304A, 304B includes TX drivers 308A, 308B, whose impedance must (and may) be calibrated before use (and / or periodically and / or continuously throughout use). Sidebands 310A, 310B are provided for use during the calibration process, as will be described in more detail below.

[0038] Each TX circuit device 304A, 304B also includes samplers 312A, 312B, which are controlled by impedance code settings of digital-to-analog converters (DACs) 313A, 313B to sample data outputs from drivers 308A, 308B. The outputs of each sampler 312A, 312B are input to error counting modules 314A, 314B, another input of which is connected to receive local data outputs from 16:2 MUX 316A, 316B. In a particular embodiment, the error counting module may be implemented as a comparator to compare the input data streams and output a flag bit (e.g., DQ_DR_TX_EYE_CAL_UP_O) indicating whether the input data match (e.g., 0) or does not match (e.g., 1). Delay tuning modules 318A, 318B control the clock delay tuning of samplers 312A, 312B. Digital blocks 320A and 320B provide processing and storage functions for TX circuit devices 304A and 304B.

[0039] Continue to refer to Figures 3A-3B The selection signals shown are defined in Table 1 below. Table I

[0040] Example operation for impedance calibration of TX driver in a bidirectional SerDes system

[0041] Figure 4 A flowchart 400 is shown according to some embodiments of the present disclosure, illustrating a system (e.g., system 300) for performing TX driver impedance calibration in a bidirectional SerDes. Figures 3A-3B Related example operations. In some embodiments, Figure 4 One or more operations shown can be performed by, for example Figure 1A , Figure 1B And perform with one or more of the elements shown in Figure 3.

[0042] In operation 402, the preselected digital signal mode is selected from the first die (e.g., die 302A). Figures 3A-3B Transmitted to the second die (e.g., die 302B). Figures 3A-3BIn a particular embodiment, the preselected digital signal mode includes a series of 1s, but other modes are also expected to be used. In a particular embodiment, operation 402 can be performed by setting the initial impedance code DQ_DR_TX_IMP_BINARY_P / N<4:0> to MAX / 2, and setting the first die (e.g., die 302A) to MAX / 2. Figures 3A-3B Set DQ_TX_DIN_RT to 1111...111 and set the first die (e.g., die 302A) ... Figures 3A-3B This can be accomplished by setting DQ_TX_DIN_VALID_RT to 1.

[0043] In operation 404, in the second die (e.g., die 302B) Figures 3A-3B The horizontal sampling position of the eye diagram is determined at (e.g., die 302A). In a particular embodiment, operation 404 can be performed by directing the sampling to the first die (e.g., die 302A). Figures 3A-3B The pseudo-random binary sequence (PRBS), such as PRBS7, is transmitted while scanning all values ​​of DQ_SR_TX_IMP_CAL_SAMP_CLK_DLY<5:0>. Simultaneously, DQ_DR_TX_EYE_CAL_UP_O is monitored, identifying the minimum (min_DLY) and maximum (max_DLY) values ​​of the DQ_SR_TX_IMP_CAL_SAMP_CLK_DLY<5:0> code when DQ_DR_TX_EYE_CAL_UP_O=0. This is then used to set DQ_SR_TX_IMP_CAL_SAMP_CLK_DLY<5:0> to (min_DLY + max_DLY) / 2. Once the horizontal sampling position of the eye diagram is determined, the impedance code value (i) is set to 0 and transmitted via the sideband (e.g., sideband 310A). Figures 3A-3B Sending the signal to the first die (e.g., die 302A). Figures 3A-3B )).

[0044] In operation 406, in the first die (e.g., die 302A ( Figures 3A-3B At this location, the transmitter driver (e.g., TX driver 308A) will be used. Figures 3A-3B The impedance code is set to the impedance value i transmitted via the sideband in operation 404, and the preselected digital mode is transmitted again to the second die (e.g., die 302B). Figures 3A-3B In a particular embodiment, this operation can be performed by inserting a second die (e.g., die 302B). Figures 3A-3BSet the impedance code DQ_DR_TX_IMP_BINARY_P / N<4:0> to MAX / 2, set DQ_TX_DIN_RT to 1111...111, and set DQ_TX_DIN_VALID_RT to 1 to complete the operation, as described in operation 402 above.

[0045] In operation 408, in the second die (e.g., die 302B ( Figures 3A-3B At point )), calculate the eye diagram height of the current i value at the horizontal sampling position determined in operation 404. In a particular embodiment, this operation can be performed by sending a signal to the first die (e.g., die 302A). Figures 3A-3B Transmit PRBS, such as PRBS7, while scanning all values ​​of DQS_DR_TX_IMP_CAL_VREF_DAC_CODE_RT<7:0>, and monitoring DQ_DR_TX_EYE_CAL_UP_O. Identify the minimum (minCAL) and maximum (maxCAL) values ​​of the DQS_DR_TX_IMP_CAL_VREF_DAC_CODE_RT<7:0> code when DQ_DR_TX_EYE_CAL_UP_O=0, and set TX_EYE_V_OPEN. This is accomplished by setting it to maxCAL-minCAL.

[0046] In operation 410, in the second die (e.g., die 302B ( Figures 3A-3B At point )), determine whether the current value of i is equal to i. max In a particular embodiment, i max It can be equal to 15. If a negative confirmation is made in operation 410, the execution proceeds to operation 412; otherwise, the execution proceeds to operation 414.

[0047] In operation 412, in the second die (e.g., die 302B ( Figures 3A-3B At point ), the impedance code value i is incremented by 1, and the current (i.e., the incremented) value of i is transmitted via the sideband (e.g., sideband 310A). Figures 3A-3B Transmitted to the first die (e.g., die 302A). Figures 3A-3B Then execution returns to operation 406 and continues in this manner until a positive determination is made in operation 410, at which point execution proceeds to operation 414.

[0048] In operation 414, in the second die (e.g., die 302B ( Figures 3A-3BAt point )), the maximum value of the eye diagram height calculated in operation 408 is determined, and the impedance code value i corresponding to the determined maximum value of the calculated eye diagram height is transmitted to the first die (e.g., die 302A). Figures 3A-3B )).

[0049] Furthermore, in the first die (e.g., die 302A ( Figures 3A-3B At the location, place the TX drive (e.g., TX drive 308A). Figures 3A-3B The impedance code is set to the value i transmitted via the sideband, at which point the TX driver is calibrated.

[0050] Although reference Figure 4 The operations shown and described are depicted as being performed once per operation and occurring in a specific order; however, it should be understood that the operations can be performed in any suitable order and repeated as needed. Furthermore, one or more operations can be performed in parallel. Figure 4 The operations shown may be combined or may include more or less detail than described.

[0051] Further attention should be paid to, Figure 4 The operations shown can be performed on each channel, in which case they can be performed simultaneously or substantially simultaneously (e.g., each operation on each channel is completed before proceeding to the next operation) or sequentially (e.g., all operations on the next channel are performed after all operations on one channel have been completed). It should also be noted that method 400 should be performed on each die (e.g., replacing the second die with the first die and the first die with the second die in the above operations).

[0052] Select Example

[0053] 1. A method for calibrating the impedance of a first transmit (TX) driver of a first bidirectional serializer / deserializer (SerDes), wherein the first bidirectional SerDes is connected to a second bidirectional SerDes via a data transmission line, the second bidirectional SerDes including a second TX driver, the method comprising: measuring, at the second SerDes, an eye diagram height of an eye diagram of a data sequence transmitted by the second SerDes for each of a plurality of driver impedance code values ​​applied to the first TX driver; determining an eye diagram height that includes a maximum eye diagram height among the measured eye diagram heights; and transmitting a driver impedance code value from the second SerDes to the first SerDes, the driver impedance code value corresponding to one of the eye diagram heights including the maximum eye diagram height for the first TX driver.

[0054] 2. The method according to Example 1 further includes identifying the horizontal sampling position of the eye diagram at the second SerDes, wherein for each of the plurality of driver impedance code values, measuring the eye diagram height at the second SerDes is performed at the horizontal sampling position.

[0055] 3. The method according to Example 1 or 2, further comprising: for each of a plurality of second driver impedance code values ​​applied to the second TX driver, measuring at the first SerDes a second eye height of a second eye diagram of a second data sequence transmitted by the first SerDes; determining a second eye height that includes a second maximum eye height among the second eye heights measured at the first SerDes; and transmitting a second driver impedance code value from the first SerDes to the second SerDes, the second driver impedance code value corresponding to one of the second eye heights that includes the second maximum eye height for the second TX driver.

[0056] 4. The method according to Example 3 further includes identifying a second horizontal sampling position of the second eye diagram at the first SerDes, wherein for each of the plurality of second driver impedance code values, measuring the height of the second eye diagram at the second SerDes is performed at the second horizontal sampling position.

[0057] 5. The method according to any one of Examples 1-4, wherein the data sequence includes a pseudo-random data sequence (PRDS).

[0058] 6. The method according to any one of Examples 1-5 further includes receiving a data pattern transmitted from the first SerDes at the second SerDes, wherein the transmission corresponds to an impedance code value applied to the first TX driver.

[0059] 7. The method according to Example 6, wherein the data pattern comprises a series of binary 1s.

[0060] 8. The method according to any one of Examples 1-7, wherein the driver impedance code value is transmitted to the first SerDes via a sideband.

[0061] 9. The method according to Example 3 or 4, wherein the second driver impedance code value is transmitted to the second SerDes via a sideband.

[0062] 10. The method according to any one of Examples 1-9, wherein the first SerDes and the second SerDes each include a plurality of channels, and wherein each measurement, determination, and communication operation is performed individually for each channel.

[0063] 11. A calibration system comprising: a first serializer / deserializer (SerDes) including a first transmit driver; a second SerDes including a second transmit driver and connected to the first SerDes via a data transmission line; wherein the first SerDes further includes circuitry for controlling the impedance of the first transmit driver based on an impedance code received from the second SerDes; and wherein the second SerDes further includes circuitry for performing the following steps for each of a plurality of impedance code values: transmitting the impedance code value to the first SerDes, the first SerDes using the impedance code value to control the impedance of the first transmit driver; measuring the eye height of an eye diagram of a predetermined data sequence transmitted by the second SerDes; circuitry for determining an eye height among the measured eye heights that includes a maximum eye height for the first transmit driver; and circuitry for transmitting an impedance code value to the first SerDes, the impedance code value being associated with one of the eye heights including the maximum eye height of the first TX driver.

[0064] 12. The calibration system according to Example 11, wherein the second SerDes further includes circuitry for identifying the horizontal sampling position of the eye diagram.

[0065] 13. The calibration system according to Example 12, wherein for each of the plurality of impedance code values, the eye height of the eye diagram is measured at the horizontal sampling position.

[0066] 14. The calibration system according to any one of Examples 11-13, wherein the second SerDes further includes circuitry for transmitting the predetermined data sequence.

[0067] 15. The calibration system according to Example 14, wherein the predetermined data sequence includes a pseudo-random data sequence (PRDS).

[0068] 16. The calibration system according to any one of Examples 11-15, wherein the first SerDes further includes circuitry for transmitting a data pattern comprising a series of binary 1s.

[0069] 17. The calibration system according to any one of Examples 11-16, wherein the circuitry for transmitting the impedance code value to the first SerDes includes a sideband communication channel.

[0070] 18. A calibration system comprising: a first serializer / deserializer (SerDes) including a first transmit driver, wherein the impedance of the first transmit driver is controlled by an impedance code; a second SerDes including a second transmit driver and connected to the first SerDes via a data transmission line, the second SerDes further comprising circuitry for measuring an eye diagram of the second transmit driver, the circuitry comprising: a sampler for sampling data at the output of the second transmit driver; an error counter for comparing data output from the sampler with local data and outputting an error signal indicating whether the data output from the sampler is the same as the local data; and a delay tuning block for tuning a delayed clock of the sampler.

[0071] 19. The calibration system according to Example 18 further includes a digital-to-analog converter (DAC) for providing the impedance code to the first transmit driver.

[0072] 20. The calibration system according to Example 18 or 19 further includes a sideband communication channel, wherein the value of the impedance code is provided from the second SerDes to the first SerDes via the sideband communication channel.

[0073] Variations and other instructions

[0074] Detailed descriptions, such as the “Selected Examples” section, provide various examples of the embodiments disclosed herein.

[0075] As used herein, the term "coupled to" or "coupled with" refers to a relationship between electronic components or circuit elements, wherein said components communicate electrically with each other and are capable of transmitting and / or receiving electrical signals between them. The term "coupled to" does not require a direct physical or electrical connection between the coupled components. Rather, "coupled to" can encompass an arrangement in which said components are connected via one or more intermediate elements, components, circuits, or transmission paths. For example, a first component may be "coupled to" a second component via an intermediate component such as a resistor, capacitor, inductor, transistor, logic gate, bus, transformer, or other electronic component, or via an intermediate transmission path, while still maintaining the ability for electrical communication between the first and second components.

[0076] The foregoing description of the disclosed illustrated embodiments, including the description in the abstract, is not intended to be exhaustive or to limit the disclosure to its precise form. While specific embodiments and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications may be made within the scope of the disclosure, as will be recognized by those skilled in the art. These modifications can be made to the disclosure based on the detailed description above.

[0077] For illustrative purposes, specific figures, materials, and configurations have been set forth to provide a thorough understanding of the illustrated embodiments. However, it will be apparent to those skilled in the art that this disclosure may be practiced without these specific details, and / or may be practiced using only some of the aspects described. In other instances, well-known features have been omitted or simplified to avoid obscuring the illustrated embodiments.

[0078] Furthermore, reference is made to the accompanying drawings, which form part of this document, which illustrate feasible embodiments. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of this disclosure.

[0079] Therefore, the following detailed description should not be considered restrictive.

[0080] Various operations can be described as multiple discrete actions or operations, the order of which best facilitates understanding the disclosed subject matter. However, the described order should not be construed as implying that these operations necessarily depend on a specific order. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. Various additional operations may be performed in additional embodiments, or the described operations may be omitted.

[0081] For the purposes of this disclosure, the phrase "A or B" or the phrase "A and / or B" refers to (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, or C" or the phrase "A, B, and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used with a measurement range includes the endpoints of the measurement range.

[0082] The description uses the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," etc., as used with respect to embodiments of this disclosure, are synonymous. This disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side," to interpret various features in the drawings, but these terms are for convenience of discussion only and do not imply a desired or necessary orientation. The drawings are not necessarily drawn to scale. Unless otherwise stated, the use of ordinal adjectives such as "first," "second," and "third," etc., to describe a common object merely refers to different instances of similar objects and is not intended to imply that the described objects must exist in a given order, whether temporally, spatially, hierarchically, or in any other way.

[0083] In the following detailed description, terms commonly used by those skilled in the art will be used to describe various aspects of the exemplary embodiments in order to convey their substance to others skilled in the art.

[0084] The terms “substantially,” “nearly,” “approximately,” and “about” generally refer to within + / - 20% of the target value described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements, generally refer to within + / - 5-20% of the target value described herein or known in the art.

[0085] Furthermore, the terms "comprising," "including," "having," or any other variations thereof are intended to cover non-exclusive inclusion. For example, a method, process, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such a method, process, or apparatus. Additionally, the term "or" refers to inclusive "or," not exclusive "or."

[0086] The systems, methods, and apparatuses disclosed herein each have several innovative aspects, none of which alone is responsible for all the desired properties disclosed herein. Details of one or more implementations of the subjects described in this specification are set forth in the description and accompanying drawings.

Claims

1. A method for calibrating the impedance of a first transmit TX driver for a first bidirectional serializer / deserializer SerDes, wherein the first bidirectional SerDes is connected to a second bidirectional SerDes via a data transmission line, the second bidirectional SerDes including a second TX driver, the method comprising: For each of the plurality of driver impedance code values ​​applied to the first TX driver, the eye height of the eye diagram of the data sequence transmitted by the second SerDes is measured at the second SerDes. Determine the eye height that includes the maximum eye height among the measured eye heights; and The driver impedance code value is transmitted from the second SerDes to the first SerDes, and the driver impedance code value corresponds to one of the eye diagram heights including the maximum eye diagram height for the first TX driver.

2. The method according to claim 1, further comprising: The horizontal sampling position of the eye diagram is identified at the second SerDes, wherein the eye diagram height is measured at the second SerDes at the horizontal sampling position for each of the plurality of driver impedance code values.

3. The method according to claim 1, further comprising: For each of the plurality of second driver impedance code values ​​applied to the second TX driver, the second eye height of the second eye diagram of the second data sequence transmitted by the first SerDes is measured at the first SerDes; The second eye height measured at the first SerDes is determined to include the second maximum eye height; and A second driver impedance code value is transmitted from the first SerDes to the second SerDes, the second driver impedance code value corresponding to one of the second eye diagram heights including the second maximum eye diagram height for the second TX driver.

4. The method of claim 3, further comprising identifying a second horizontal sampling position of the second eye diagram at the first SerDes, wherein for each of the plurality of second driver impedance code values, measuring the height of the second eye diagram at the second SerDes is performed at the second horizontal sampling position.

5. The method of claim 1, wherein the data sequence comprises a pseudo-random data sequence (PRDS).

6. The method of claim 1, further comprising receiving, at the second SerDes, a data pattern transmitted from the first SerDes, wherein the transmission corresponds to an impedance code value applied to the first TX driver.

7. The method of claim 6, wherein the data pattern comprises a series of binary 1s.

8. The method of claim 1, wherein the driver impedance code value is transmitted to the first SerDes via a sideband.

9. The method of claim 3, wherein the second driver impedance code value is transmitted to the second SerDes via a sideband.

10. The method of claim 1, wherein the first SerDes and the second SerDes each comprise a plurality of channels, and wherein each of the measurement, the determination, and the transmission operations is performed individually for each of the channels.

11. A calibration system, comprising: The first serializer / deserializer, SerDes, includes a first transmit driver; The second SerDes includes a second transmit driver and is connected to the first SerDes via a data transmission line; The first SerDes further includes circuitry for controlling the impedance of the first transmit driver based on an impedance code received from the second SerDes. as well as The second SerDes also includes: Circuit apparatus for performing the following steps for each of a plurality of impedance code values: The impedance code value is transmitted to the first SerDes, which is used to control the impedance of the first transmit driver using the impedance code value; Measure the eye height of the eye diagram of the predetermined data sequence transmitted by the second SerDes; Circuitry means for determining the eye diagram height that includes the maximum eye diagram height for the first transmit driver among the measured eye diagram heights; as well as Circuitry means for transmitting an impedance code value to the first SerDes, the impedance code value being associated with one of the eye diagram heights including the maximum eye diagram height of the first TX driver.

12. The calibration system of claim 11, wherein the second SerDes further includes circuitry for identifying the horizontal sampling position of the eye diagram.

13. The calibration system of claim 12, wherein for each of the plurality of impedance code values, the eye diagram height of the eye diagram is measured at the horizontal sampling position.

14. The calibration system of claim 11, wherein the second SerDes further comprises circuitry for transmitting the predetermined data sequence.

15. The calibration system of claim 14, wherein the predetermined data sequence comprises a pseudo-random data sequence PRDS.

16. The calibration system of claim 11, wherein the first SerDes further comprises circuitry for transmitting a data pattern comprising a series of binary 1s.

17. The calibration system of claim 11, wherein the circuitry for transmitting the impedance code value to the first SerDes includes a sideband communication channel.

18. A calibration system, comprising: The first serializer / deserializer, SerDes, includes a first transmit driver, wherein the impedance of the first transmit driver is controlled by an impedance code; A second SerDes includes a second transmit driver and is connected to the first SerDes via a data transmission line. The second SerDes also includes circuitry for measuring the eye diagram of the second transmit driver, the circuitry including: A sampler used to sample data at the output of the second transmit driver; An error counter is used to compare the data output from the sampler with local data and output an error signal indicating whether the data output from the sampler is the same as the local data; Delay tuning block used to tune the delay clock of the sampler.

19. The calibration system of claim 18, further comprising a digital-to-analog converter (DAC) for providing the impedance code to the first transmit driver.

20. The calibration system of claim 18, further comprising a sideband communication channel, wherein the value for the impedance code is provided from the second SerDes to the first SerDes via the sideband communication channel.

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