A high-speed interface transmission system and method, electronic device, storage medium and computer program product

Abstract

The present disclosure relates to the technical field of computer, and particularly relates to a high-speed interface transmission system and method, electronic equipment, storage medium and computer program product. The system comprises a sending end and a receiving end. The sending end comprises a Flit data generation module, a link training data generation module and a mode switching module. The mode switching module switches to a link training mode in a link initialization stage. The link training data generation module generates and sends a link training frame for link training between the sending end and the receiving end to the receiving end in the link training mode. The mode switching module switches to a data transmission mode after completing the link training between the sending end and the receiving end. The Flit data generation module generates and sends a Flit data frame to the receiving end in the data transmission mode. According to the embodiment of the present disclosure, the automatic switching of the link training mode and the data transmission mode can be effectively realized, the high packet performance is achieved, the link delay is reduced, and the transmission performance is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a high-speed interface transmission system and method, electronic device, storage medium and computer program product. Background Technology

[0002] Among high-speed interface controllers, the most well-known and widely used protocols are Peripheral Component Interconnect Express (PCIe) and Ethernet. However, PCIe's link control logic is relatively complex and requires a dedicated PCIe serial deserializer (serdes) for adaptation; Ethernet can only implement link training functions in serdes and cannot support link parameter negotiation. Summary of the Invention

[0003] In view of this, this disclosure presents a high-speed interface transmission system and method, electronic device, storage medium and computer program product.

[0004] According to one aspect of this disclosure, a high-speed interface transmission system is provided, comprising: a transmitting end and a receiving end; wherein the transmitting end includes: a Flit data generation module, a link training data generation module, and a mode switching module; the mode switching module is used to switch to a link training mode during the link initialization phase; the link training data generation module is used to generate and send link training frames to the receiving end in the link training mode, wherein the link training frames are used for link training between the transmitting end and the receiving end; the mode switching module is used to switch to a data transmission mode after link training is completed between the transmitting end and the receiving end; the Flit data generation module is used to generate and send Flit data frames to the receiving end in the data transmission mode.

[0005] In one possible implementation, the Flit data frame includes a data link layer packet (DLLP); wherein the DLLP includes flow control information indicating the number of available credits in the flow control buffer, and one credit is configured as the storage width of the flow control buffer.

[0006] In one possible implementation, the Flit data frame includes: a Byte Transaction Layer (TLP) data packet; the byte length of the DLLP and the byte length of the TLP are variable, and the byte length of the compressed DLLP is positively correlated with the byte length increase of the TLP.

[0007] In one possible implementation, the length of the Flit data frame is 256 bytes; the Flit data frame includes: 238 bytes of TLP, 2 bytes of control information, 2 bytes of DLLP, 8 bytes of Cyclic Redundancy Check (CRC), and 6 bytes of Forward Error Correction (FEC); the 2-byte DLLP includes: a 5-bit flow control message type field and an 11-bit flow control message field; wherein, the 5-bit flow control message type field supports the transmission of 32 flow control message types, and the 11-bit flow control message field supports the transmission of flow control messages indicating the number of available Credits in a flow control buffer with a depth of 1024.

[0008] In one possible implementation, the link training frame includes: a frame tag field, a control and status field, and a training sequence field; the frame tag field is used to transmit a frame tag that identifies the start boundary of the link training frame; the control and status field is used to transmit negotiation information for link layer negotiation, wherein the negotiation information is obtained by encoding user-defined data, and the user-defined data is used to define the type of the link training frame and the link layer parameters that need to be negotiated; the training sequence field is used to transmit a pseudo-random training sequence for physical layer training.

[0009] In one possible implementation, the negotiation information is obtained by encoding the user-defined data using the Differential Manchester Encoding (DME) method.

[0010] In one possible implementation, the link training frame type includes at least one of the following: First Training Sequence (TS1) type, Second Training Sequence (TS2) type, Start Data Stream (SDS) type, Skip SKP type, and Electrically Idle Sequence (EIOS) type; the TS1 and TS2 type link training frames are used to complete link layer parameter negotiation between the transmitter and the receiver; the SDS and SKP type link training frames are used to identify the start of the Flit data stream after link training is completed between the transmitter and the receiver; the EIOS type link training frame is used to indicate that the transmitter has entered an idle state and stops transmitting data.

[0011] In one possible implementation, the link layer parameters that need to be negotiated include at least one of the following: link width and physical channel rate.

[0012] In one possible implementation, the pseudo-random training sequence is a random code pattern generated based on a pseudo-random binary sequence (PRBS) generator, wherein the number of 0s and 1s in the pseudo-random training sequence is balanced.

[0013] In one possible implementation, when there are multiple physical channels at the physical layer, the PRBS polynomials and / or PRBS default seeds used by different physical channels are configured to be different.

[0014] In one possible implementation, the link training data generation module is configured to: generate and send an even number of the link training frames to the receiving end when the length of the frame marker is half the width of the parallel bus of the system and the length of the link training frame is an odd multiple of the length of the frame marker.

[0015] In one possible implementation, the link training data generation module is configured to: generate and send multiple TS1 and TS2 type link training frames to the receiving end before the link layer parameter negotiation is completed; generate and send an SDS type link training frame to the receiving end after the link layer parameter negotiation is completed; and after sending an SDS type link training frame to the receiving end, and if it is determined that the Flit data generation module has not yet generated the first Flit data frame, generate and send at least one SKP type link training frame to the receiving end.

[0016] In one possible implementation, the receiving end includes: an alignment state machine and a link training data parsing module; the alignment state machine is used to control the link training data parsing module to perform sliding detection on the received data stream in an unaligned state to determine whether there is a frame marker with a full code match; the alignment state machine is used to jump to a preliminary alignment state when the link training data parsing module detects the first frame marker with a full code match, and to control the link training data parsing module to record the offset position according to the first frame marker with a full code match.

[0017] In one possible implementation, the alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the detection state if the link training data parsing module detects that the next frame marker fuzzy matching fails.

[0018] In one possible implementation, the alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the detection state if the link training data parsing module detects the frame marker with full code matching again, but it is not aligned with the recorded offset position.

[0019] In one possible implementation, the alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the detection state, and to jump to the unaligned state if the link training data parsing module detects that the first number of frame markers have failed to match fuzzily.

[0020] In one possible implementation, the alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the detection state, and to jump to the preliminary alignment state when the link training data parsing module detects the frame marker and the fuzzy match is successful.

[0021] In one possible implementation, the alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the intra-frame state when the link training data parsing module detects that the second number of frame markers have been successfully fuzzily matched. The alignment state machine is used to control the link training data parsing module to parse the received link training frame according to the recorded offset position in the intra-frame state.

[0022] In one possible implementation, the alignment state machine is used to jump to the unaligned state if it is determined in the intra-frame state that a change in the physical channel rate is required.

[0023] In one possible implementation, the alignment state machine is configured to jump to the unaligned state if, in the intra-frame state, the link training data parsing module detects a third consecutive failure of fuzzy matching of the frame markers.

[0024] In one possible implementation, the receiving end includes: a Flit data extraction module; an alignment state machine, configured to, in the intra-frame state, if the link training data parsing module receives link training frames of SDS type and SKP type, and the Flit data frame is followed by the SKP type link training frame, jump to the data state; the alignment state machine is configured to, in the data state, control the Flit data extraction module to extract the Flit data frame from the received data stream.

[0025] In one possible implementation, the alignment state machine is used to jump to the unaligned state if it is determined in the data state that a change in the physical channel rate is required.

[0026] In one possible implementation, the alignment state machine is configured to jump to the unaligned state when the Flit data extraction module detects a frame marker with a full code match in the data state.

[0027] According to another aspect of this disclosure, a high-speed interface transmission method is provided, the method being applied to a high-speed interface transmission system; the high-speed interface transmission system includes: a transmitting end and a receiving end; wherein, the transmitting end includes: a Flit data generation module, a link training data generation module, and a mode switching module; during the link initialization phase, the mode switching module is controlled to switch to a link training mode; in the link training mode, the link training data generation module is controlled to generate and send link training frames to the receiving end, wherein the link training frames are used for link training between the transmitting end and the receiving end; after the link training is completed between the transmitting end and the receiving end, the mode switching module is controlled to switch to a data transmission mode; in the data transmission mode, the Flit data generation module is controlled to generate and send Flit data frames to the receiving end.

[0028] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned high-speed interface transmission system.

[0029] According to another aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0030] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0031] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0032] The high-speed interface transmission system of this disclosure includes a transmitter and a receiver. The transmitter includes a Flit data generation module, a link training data generation module, and a mode switching module. During the link initialization phase, the mode switching module switches to link training mode. Then, the link training data generation module generates and sends link training frames to the receiver for link training between the transmitter and receiver. After link training is completed between the transmitter and receiver, the mode switching module switches to data transmission mode.

[0033] The Flit data generation module generates and sends Flit data frames to the receiving end. The mode switching module can effectively realize the automatic switching between link training mode and data transmission mode; the link training data generation module can generate link training frames that meet the requirements using simple control logic in link training mode, so as to quickly and efficiently complete physical layer SERDE training and link layer parameter negotiation during link training; the Flit data generation module can generate Flit data frames according to the Flit packet format in data transmission mode, which has high packet performance, reduces link latency, and improves transmission efficiency.

[0034] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0035] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0036] Figure 1 A block diagram of a high-speed interface transmission system according to an embodiment of the present disclosure is shown.

[0037] Figure 2 This diagram illustrates a PCIe Flit data frame in the prior art.

[0038] Figure 3 This diagram illustrates a 6B TLP in a PCIe Flit data frame in the prior art.

[0039] Figure 4 A schematic diagram of a Flit data frame according to an embodiment of the present disclosure is shown.

[0040] Figure 5 A schematic diagram of a 4B TLP in a Flit data frame according to an embodiment of the present disclosure is shown.

[0041] Figure 6 A schematic diagram of a 2B DLLP in a Flit data frame according to an embodiment of the present disclosure is shown.

[0042] Figure 7 A schematic diagram of a PBRS13 generator according to an embodiment of the present disclosure is shown.

[0043] Figure 8 A schematic diagram illustrating the generation of pseudo-random training sequences according to an embodiment of the present disclosure is shown.

[0044] Figure 9 A schematic diagram of a link training frame according to an embodiment of the present disclosure is shown.

[0045] Figure 10The diagram illustrates the operation and transitions of the aligned state machine under different states according to embodiments of the present disclosure.

[0046] Figure 11 A flowchart illustrating a high-speed interface transmission method according to an embodiment of the present disclosure is shown.

[0047] Figure 12 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0048] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0049] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0050] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0051] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0052] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0053] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0054] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0055] Among high-speed interface controllers, the most well-known and widely used protocols are Peripheral Component Interconnect Express (PCIe) and Ethernet.

[0056] To address the increased error rate (BER) of Served Desserts (SRDs) at high speeds, the PCIe protocol introduced the concept of Flit in its sixth generation (Gen6). This involves encapsulating transaction layer data into several fixed-length data link layer (Flit) packets. In the Gen6 PCIe protocol, the Flit data frame size is fixed at 256 bytes (B), including: payload, data link layer (DLP) packets, cyclic redundancy check (CRC), and forward error correction (FEC). The Flit mechanism offers numerous advantages: it simplifies the design complexity of error-correcting codes (ECC), reduces link latency and processing complexity, and ensures high transmission performance regardless of the size of the data packets sent by the user.

[0057] The Ethernet protocol still uses a variable-length MAC packet format in its Media Access Control (MAC) layer. When the data sent by the user is in small packets, the variable-length MAC packet format has lower transmission performance. Furthermore, to address the increased bit error rate (BER) of SERDEs at high speeds, the Ethernet protocol also introduces FEC (Flexible Encoding). In this case, the MAC packet format requires complex transformations before FEC encoding, and once a retransmission is triggered, the MAC packet format introduces more latency compared to the Flit format.

[0058] In terms of physical layer serial deserializer training (serdes training), PCIe and Ethernet employ two completely different approaches.

[0059] PCIe controls serdes training and handshakes with link partners through the Link Training and Status State Machine (LTSSM). The LTSSM controls the generation and parsing of training patterns and negotiates link layer parameters with the link partner.

[0060] Although Ethernet high-speed interface controllers have optional SERDes training patterns, such as pseudo-random binary sequence (prbs) codes, these patterns do not carry valid control information. They cannot handshake with the link partner, thus failing to obtain the link partner's status and enabling automatic switching between user data and training patterns. Furthermore, because they lack patterns capable of carrying control information, they cannot negotiate link-layer parameters with the link partner. Link-layer parameters such as the data transmission rate and the number of working lanes can only be determined during initialization; channel rate switching and lane addition / reduction operations are not possible during controller operation. Meanwhile, Ethernet SERDes define link training patterns that can be used for SERDes training and negotiation, carrying parameters for SERDes training. However, since this function is currently only implemented in SERDS, the Ethernet controller still cannot use this pattern to transmit upper-layer (link layer) control information. The switching between userdata and SERDS link training pattern can only be accomplished by software obtaining the status of SERDS and then configuring the register to switch the data source.

[0061] Compared to traditional Ethernet MAC packets, PCIe introduces fixed-length 256-byte fragments, simplifying FEC design complexity, reducing link latency, and achieving efficient retransmission and stable transmission performance. In terms of interaction with SERDes, PCIe's LTSSM link control logic is very complex and requires a dedicated PCIe SERDes for adaptation. While Ethernet's link training pattern generation and control are relatively simple, link training functionality is only implemented in the SERDes; the controller itself does not support negotiation of link layer parameters such as link width and lane speed.

[0062] To address the aforementioned technical problems, and combining the advantages of PCIe Flit and Ethernet link training patterns, this disclosure provides a high-speed interface transmission system. This system utilizes simple control logic to generate required link training frames, enabling rapid and efficient completion of physical layer SERDES training and link layer parameter negotiation during link training. This allows for automatic switching between link training and data transmission modes, and generates Flit data frames according to the Flit packet format. This results in high packet performance, reduced link latency, and improved transmission performance. The high-speed interface transmission system of this disclosure is described in detail below.

[0063] Figure 1 A block diagram of a high-speed interface transmission system according to an embodiment of the present disclosure is shown. Figure 1 As shown, the high-speed interface transmission system includes a transmitter and a receiver. The transmitter includes a Flit data generation module, a link training data generation module, and a mode switching module. The mode switching module is used to switch to link training mode during the link initialization phase. The link training data generation module is used to generate and send link training frames to the receiver in link training mode, wherein the link training frames are used for link training between the transmitter and the receiver. The mode switching module is used to switch to data transmission mode after link training between the transmitter and the receiver is completed. The Flit data generation module is used to generate and send Flit data frames to the receiver in data transmission mode.

[0064] The mode switching module can effectively switch between link training mode and data transmission mode automatically; the link training data generation module can generate required link training frames using simple control logic in link training mode to quickly and efficiently complete physical layer SERDE training and link layer parameter negotiation during link training; the Flit data generation module can generate Flit data frames in the Flit packet format in data transmission mode, which has high packet performance, reduces link latency, and improves transmission efficiency.

[0065] Figure 2 This diagram illustrates a PCIe Flit data frame in the prior art. (Example) Figure 2 As shown, a PCIe Flit data frame is 256 bytes long, consisting of: a 236-byte Transaction Layer Packet (TLP), a 6-byte Data Link Layer Packet (DLP), an 8-byte CRC, and a 6-byte FEC. The 6-byte DLP contains 2 bytes of control information and a 4-byte Data Link Layer Packet (DLLP) payload, primarily used to transmit flow control messages.

[0066] Figure 3 This diagram illustrates a 6-byte TLP in a PCIe Flit data frame in the prior art. Figure 3 As shown, the 6B TLP includes 2B (16 bits) of control information ( Figure 3 32-47 bits) and 4B (32 bits) DLLP ( Figure 3 (0-31 bits).

[0067] To improve transmission efficiency, the PCIe Flit data frame is optimized to obtain the Flit data frame of this embodiment.

[0068] In one possible implementation, the Flit data frame includes: a data link layer packet DLLP; wherein the DLLP includes a flow control message indicating the number of available Credits in the flow control buffer, and one Credit is configured as the storage width of the flow control buffer.

[0069] By configuring one Credit as the storage width of the flow control buffer, the calculation of flow control messages can be effectively simplified, thereby reducing the width of the flow control messages.

[0070] In one possible implementation, the Flit data frame includes: a TLP; the byte length of the DLLP and the byte length of the TLP are variable, and the byte length of the compressed DLLP is positively correlated with the byte length increase of the TLP.

[0071] Since the calculation of flow control messages can be simplified to reduce the bit width of flow control messages, by adjusting the byte length of DLLP and TLP, the byte length of DLLP compression is positively correlated with the byte length increase of TLP, thereby increasing the amount of data in TLP and effectively improving the transmission efficiency of Flit data frames.

[0072] In one example, the length of the TLP is increased by compressing the DLLP and allocating the free bytes saved from the compression to the TLP.

[0073] By reducing the amount of DLLP data in the Flit data frame to compress the DLLP's byte length, the free byte length saved after compression can be allocated to the TLP, thereby increasing the TLP's byte length and adding more data to the TLP, effectively improving the transmission efficiency of the Flit data frame.

[0074] In one possible implementation, the length of the Flit data frame is 256 bytes; the Flit data frame includes: 238 bytes of TLP, 2 bytes of control information, 2 bytes of DLLP, 8 bytes of CRC, and 6 bytes of FEC; the 2-byte DLLP includes: a 5-bit flow control message type field and an 11-bit flow control message field; wherein, the 5-bit flow control message type field supports the transmission of 32 flow control message types, and the 11-bit flow control message field supports the transmission of flow control messages indicating the number of available Credits in the flow control buffer with a depth of 1024.

[0075] Compared to the existing PCIe Flit data frame data packet formats of 236B TLP, 6B DLP, 8B CRC and 6B FEC, the Flit data frame of this disclosure embodiment can optimize the original 6B DLP to 4B, specifically by compressing 4B DLP to 2B. The saved 2B space can be reserved for TLP, increasing the original 236B TLP to 238B to transmit more payload.

[0076] Figure 4 A schematic diagram of a Flit data frame according to an embodiment of the present disclosure is shown. Figure 3As shown, the length of the Flit data frame in this embodiment of the disclosure is 256B, including: 238B TLP, 4B DLP, 8B CRC, and 6B FEC. Among them, the 4B DLP includes 2B control information and 2B DLLP, which are mainly used to transmit flow control messages.

[0077] Figure 5 A schematic diagram of a 4B DLP in a Flit data frame according to an embodiment of the present disclosure is shown. Figure 5 As shown, the 4B TLP includes 2B (16 bits) of control information ( Figure 5 16-31 bits) and 2B (16-bit) DLLP ( Figure 5 (16-31 bits).

[0078] Figure 6 A schematic diagram of a 2B DLLP in a Flit data frame according to an embodiment of the present disclosure is shown. Figure 6 As shown, 2BDLLP includes: a 5-bit flow control message type field ( Figure 6 (0-4 bits of byte 0), 11-bit flow control message field ( Figure 6 (Bits 5-7 of byte 0 and 8 bits of byte 1).

[0079] The 5-bit flow control message type field supports the transmission of 32 flow control message types, and the 11-bit flow control message field supports the transmission of flow control messages indicating the number of available credits in a flow control buffer with a depth of 1024.

[0080] While existing Ethernet link training patterns are relatively simple to generate and control, they only implement link training functionality in the SERDEs layer, and the controller itself does not support negotiation of link layer parameters such as link width and lane speed. Therefore, this disclosure provides a link training pattern that can simultaneously complete physical layer SERDEs training and link layer parameter negotiation.

[0081] In one possible implementation, the link training frame includes: a frame tag field, a control and status field, and a training sequence field; the frame tag field is used to transmit a frame tag that identifies the start boundary of the link training frame; the control and status field is used to transmit negotiation information for link layer negotiation, wherein the negotiation information is obtained by encoding user-defined data, and the user-defined data is used to define the type of link training frame and the link layer parameters that need to be negotiated; the training sequence field is used to transmit the pseudo-random training sequence for physical layer training.

[0082] In this embodiment of the application, in order to enable the link training pattern to complete both physical layer serdestraining and link layer parameter negotiation, the data structure of the link training frame includes three parts: frame marker field, control and status field, and training pattern field.

[0083] The frame tag field is used to transmit frame tags that identify the start boundary of a link training frame, indicating the beginning of a link training frame.

[0084] In one possible implementation, frames are labeled as predefined sequences.

[0085] For example, a frame marker consists of 16 symbols 3 and 16 symbols 0, where each symbol is 2 bits. That is, symbol 3 is 11 and symbol 0 is 00. In this case, the frame marker is a predefined sequence of 64 bits in length.

[0086] In one possible implementation, the link training data generation module is used to generate and send an even number of link training frames to the receiving end when the length of the frame marker is half the width of the parallel bus of the high-speed interface transmission system and the length of the link training frame is an odd multiple of the length of the frame marker.

[0087] When the length of the frame marker is half the width of the parallel bus (data path) of the high-speed interface transmission system, and the length of the link training frame is an odd multiple of the length of the frame marker, when multiple link training frames are sent consecutively, the frame markers of adjacent link training frames will alternately appear in the high half bit and low half bit of the parallel bus (data path).

[0088] At this point, in order to smoothly switch from link training mode to data transmission mode, the link training data generation module generates and sends an even number of link training frames to the receiving end before sending the first Flit data frame to the receiving end.

[0089] A clean switch refers to the switching point from sending the last link training frame to sending the first Flit data frame occurring within a complete, aligned clock cycle boundary on the parallel bus. In other words, the last bit of the last link training frame exactly fills the parallel bus in the previous clock cycle; in the next clock cycle, the first bit of the Flit data frame starts filling from the beginning of the parallel bus, and the data stream of the Flit data frame has no residual "half-data" on the parallel bus.

[0090] The clean switch from link training mode to data transmission mode allows the transmitter to count only an even number of link training frames and then unconditionally switch modes in the next clock cycle at the end of the last link training frame, eliminating the need for complex phase calculations. After the receiver has fully detected the last link training frame, the next clock cycle will inevitably transmit the beginning of a complete Flit data frame, avoiding the risk of truncated, misaligned, or confused Flit data frames with the tail data of the link training frames.

[0091] For example, with a frame marker length of 64 bits, a link training frame length of 448 bits (7 times the frame marker length), and a high-speed interface transmission system using a 128-bit parallel bus (data path), the length of one link training frame corresponds to 3.5 clock cycles of transmission on the 128-bit parallel bus (data path). In this case, the frame marker for the first link training frame appears in the high 64 bits of the 128-bit parallel bus (data path) during the first clock cycle; the frame marker for the second link training frame appears in the low 64 bits of the 128-bit parallel bus (data path) during the fourth clock cycle; the frame marker for the third link training frame appears in the high 64 bits of the 128-bit parallel bus (data path) during the eighth clock cycle; the frame marker for the fourth link training frame appears in the low 64 bits of the 128-bit parallel bus (data path) during the eleventh clock cycle, and so on. The frame markers of adjacent link training frames will alternately appear in the high and low 64 bits of the 128-bit parallel bus (data path).

[0092] Assume that before sending the first Flit data frame to the receiving end, the link training data generation module generates and sends an odd number (3) of link training frames to the receiving end, and then sends the first Flit data frame. According to the above description, the switching point from the 3rd link training frame to the first Flit data frame occurs within the 11th clock cycle of the 128-bit parallel bus (data path). During the 11th clock cycle of the 128-bit parallel bus (data path), the high 64 bits represent the data stream of the 3rd link training frame, and the low 64 bits represent the data stream of the first Flit data frame. Therefore, a clean switch from link training mode to data transmission mode cannot be achieved.

[0093] Assume that before sending the first Flit data frame to the receiving end, the link training data generation module generates and sends an even number (4) of link training frames to the receiving end, and then sends the first Flit data frame. According to the above description, the switching point from the 4th link training frame to the first Flit data frame occurs at the boundary between the 14th and 15th clock cycles of the 128-bit parallel bus (data path). The 14th clock cycle's 128-bit parallel bus (data path) carries the data stream of the 4th link training frame, while the 15th clock cycle's 128-bit parallel bus (data path) carries the data stream of the first Flit data frame, effectively achieving a clean switch from link training mode to data transmission mode.

[0094] The length and number of link training frames mentioned above are merely examples and do not constitute any limitation on the actual length and number of link training frames in real applications.

[0095] The control and status fields in the link training frame are used to transmit negotiation information for the link layer. The sending end defines the type of the link training frame and the link layer parameters to be negotiated using user-defined data. This user-defined data is then encoded and encapsulated into the control and status fields of the link training frame. The receiving end parses the key information from the control and status fields of the link training frame and, combined with its local state and supported parameters, negotiates parameters that are supported by both the sending and receiving ends (both links).

[0096] In one possible implementation, the link training frame type includes at least one of the following: First Training Sequence (TS1) type, Second Training Sequence (TS2) type, Start Data Stream (SDS) type, Skip SKP type, Electrically Idle Sequence (EIOS) type; TS1 and TS2 type link training frames are used to complete link layer parameter negotiation between the sender and receiver; SDS and SKP type link training frames are used to identify the start of the Flit data stream after link training is completed between the sender and receiver; EIOS type link training frames are used to indicate that the sender has entered an idle state and stops transmitting data.

[0097] Based on the type of link training frames, the link training frames are divided into the first training sequence (TS) type TS1, the TS2 type, the start of data stream (SDS) type, the skip (siip, SKP) type, and the electrical Idle sequence (EIOS) type. This provides standardized frame types for different training stages and scenarios, making the link training process more standardized and orderly, and facilitating state recognition and switching at the receiving end.

[0098] TS1 and TS2 type link training frames are used for link initialization and to complete link layer parameter negotiation between the sender and receiver. SDS and SKP type link training frames are used to mark the start of the Flit data stream after link training is completed between the sender and receiver. EIOS type link training frames are used to mark that the sender has entered an idle state and stopped transmitting data; that is, the sender neither sends link training frames nor Flit data frames.

[0099] In one example, the sender defines the type of the link training frame and the link layer parameters that need to be negotiated through user-defined data. Then, the user-defined data is encoded to obtain the negotiation information, and the negotiation information is encapsulated into the control and status fields in the link training frame.

[0100] In one possible implementation, the negotiation information is obtained by encoding user-defined data using the Differential Manchester Encoding (DME) method.

[0101] By leveraging the inherent characteristics of Differential Manchester Encoded (DME) encoding—namely, the absence of DC components, built-in clock information, and strong anti-interference capabilities—user-defined data is encoded using DME to obtain negotiation information, thereby enhancing the reliability and stability of the negotiation information transmission over the link.

[0102] In DME mode, each bit of valid information requires one symbol (DME cell) to represent it. One DME cell is 8 Unit Intervals (UIs), or 16 bits long. UI is the physical layer time unit, representing the time required to transmit one symbol. The DME encoding rules are as follows: At the beginning of each cell, a transition occurs from level 0 to 3 or from level 3 to 0. At the midpoint of the cell (i.e., four unit intervals from the start of the transition), if a transition occurs from level 0 to 3 or from level 3 to 0, it corresponds to a logic "1". If no transition occurs at the midpoint of the cell, it corresponds to a logic "0". For example, encoding 6 bits of valid information 101101, the DME encoded code is as follows: 33330000---33333333---00003333---00003333---00000000---33330000.

[0103] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. The control and status field includes a type subfield (os_type), occupying the 3 bits of Byte0[2:0] in the control and status field, used to transmit the type of the user-defined link training frame. The format of the type subfield (os_type) is bit width + radix + value, specifically a bit width of 3, binary 'b', and a specific value. For example, when the Byte0[2:0] bit field is 3'b000, it indicates a TS1 type link training frame; when the Byte0[2:0] bit field is 3'b001, it indicates a TS2 type link training frame; when the Byte0[2:0] bit field is 3'b110, it indicates an SDS type link training frame; when the Byte0[2:0] bit field is 3'b011, it indicates an SKP type link training frame; and when the Byte0[2:0] bit field is 3'b100, it indicates an EIOS type link training frame.

[0104] TS1 and TS2 type link training frames are used to complete the negotiation of link layer parameters between the sender and receiver. Therefore, user-defined link layer parameters that need to be negotiated can be transmitted in the control and status fields of TS1 and TS2 type link training frames.

[0105] In one example, the control and status field can transmit 4 bytes (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a physical channel number subfield (lane_number), occupying the 4 bits of Byte0[6:3] in the control and status field, used to transmit the physical channel number. The format of the physical channel number subfield (lane_number) is bit width + hexadecimal + value, specifically bit width 4, hexadecimal h, and specific value. For example, when the bit field of Byte0[6:3] is 4'h0, it indicates physical channel 0 (lane0); when the bit field of Byte0[6:3] is 4'h1, it indicates physical channel 1 (lane1); when the bit field of Byte0[6:3] is 4'hf, it indicates that the physical channel is disabled (PAD); and so on.

[0106] In one possible implementation, the link layer parameters that need to be negotiated include at least one of the following: link width and physical channel rate.

[0107] The high-speed interface transmission system of this disclosure has lightweight link width and lane speed negotiation capabilities.

[0108] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a link width change subfield (link width_change) and a target link width subfield (target_link width). The link width change subfield occupies the 1-bit field of Byte1[0] in the control and status field and is used to indicate whether the local end requests or confirms the change of link width; the target link width subfield occupies the 4-bit field of Byte1[4:1] in the control and status field and is used to indicate the link width (i.e., the number of physical channels) that the local end wants to negotiate.

[0109] The format of the link width change subfield (link width_change) is bit width + radix + value, specifically bit width 1, binary b, and specific value. For example, when the Byte1[0] bit field is 1'b1, it indicates that the local end requests or confirms the change of the link width; when the Byte1[0] bit field is 1'b0, it indicates that the local end does not request or rejects the change of the link width.

[0110] The target link width subfield (target_link width) is formatted as bit width + radix + value, specifically bit width 4, decimal d, and the specific value. For example, when the Byte1[4:1] bit field is 4'd1, it indicates that the local end wants to negotiate the use of 1 physical channel (1 lane); when the Byte1[4:1] bit field is 4'd2, it indicates that the local end wants to negotiate the use of 2 physical channels (2 lanes); and so on.

[0111] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a physical channel rate change subfield (speed_change) and a target physical channel rate subfield (target_change). The physical channel rate change subfield (speed_change) occupies 1 bit field of Byte2[0] in the control and status field and is used to indicate whether the local end requests or confirms the change of physical channel rate; the target physical channel rate subfield (target_change) occupies 5 bits field of Byte2[5:1] in the control and status field and is used to indicate the physical channel rate that the local end wants to negotiate.

[0112] The format of the physical channel rate change subfield (speed_change) is bit width + radix + value, specifically bit width 1, binary b, and specific value. For example, when the Byte2[0] bit field is 1'b1, it indicates that the local end requests or confirms the change of physical channel rate; when the Byte2[0] bit field is 1'b0, it indicates that the local end does not request or rejects the change of physical channel rate.

[0113] The target physical channel rate subfield (target_change) is formatted as bit width + radix + value, specifically a bit width of 5, binary 'b', and a specific value. For example, when the Byte2[5:1] bit field is 5'b00, it indicates that the local end wants to negotiate the use of the base rate (gen0 rate, 26 / 28G); when the Byte2[5:1] bit field is 5'b01, it indicates that the local end wants to negotiate the use of double the rate (gen1 rate, 53 / 56G); when the Byte2[5:1] bit field is 5'b10, it indicates that the local end wants to negotiate the use of quadruple the rate (gen2 rate, 106 / 112G), and so on.

[0114] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a retraining subfield, which occupies the 1-bit field of Byte2[6] in the control and status field and is used to indicate whether the local end requests link retraining. The format of the retraining subfield is bit width + radix + value, specifically bit width 1, binary b, and specific value. For example, when the Byte2[6] bit field is 1'b1, it indicates that the local end requests link retraining; when the Byte2[6] bit field is 1'b0, it indicates that the local end does not request link retraining.

[0115] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a hot_reset subfield, which occupies the 1-bit bit field of Byte3[1] in the control and status field, and is used to indicate handshaking with the peer and synchronously resetting its own controller.

[0116] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a physical layer receiver ready subfield (rx_phy_ready), which occupies the 1-bit field of Byte3[2] in the control and status field and is used to indicate whether the local physical layer receiver is ready. For example, when the Byte3[2] bit field is 1, it indicates that the local physical layer training has been completed and the receiver is ready to receive data; when the Byte3[2] bit field is 0, it indicates that the local physical layer training has not been completed and requests to continue sending training sequences.

[0117] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a receiver frame lock status subfield (rx_frame_lock), which occupies the 1-bit field of Byte3[3] in the control and status subfield and is used to indicate the frame lock status of the local physical layer receiver. For example, when the Byte3[3] bit field is 1, it indicates that the local physical layer receiver has successfully identified the frame boundaries of the data stream; when the Byte3[3] bit field is 1, it indicates that the local physical layer receiver has not identified or has lost the frame boundaries of the data stream.

[0118] In one example, the control and status field can transmit 4 bytes (32 bits) of user-defined data. In TS1 and TS2 type link training frames, each byte in the control and status field is accompanied by its own parity_check subfield, occupying the highest bit field of each byte, for error detection to verify data transmission. For example, the parity check field (parity_check0) in the first byte Byte0 occupies the bit field of Byte0[7], and the bit field of Byte0[7] is ^byte0[6:0], that is, the value of the bit field of Byte0[7] is the result of the XOR operation of all the lower 7 bits of Byte0[6:0] in Byte0; the parity check field (parity_check1) in the second byte Byte1 occupies the bit field of Byte1[7], and the bit field of Byte1[7] is ^byte1[6:0], that is, the value of the bit field of Byte1[7] is the result of the XOR operation of all the lower 7 bits of Byte1[6:0] in Byte1; and so on.

[0119] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In TS1 and TS2 type link training frames, the control and status field includes a goto_recovery subfield, occupying the Byte3[0] bit field. Assuming that the goto_recovery subfield is not currently needed or enabled in the high-speed interface transmission system, the Byte3[0] bit field is sent as 0, and the receiving end ignores this bit. If it is necessary to add the function of forcing the link to jump to the recovery state later, there is no need to change the structure of the TS1 and TS2 type link training frames; it is only necessary to configure the Byte3[0] bit field to 1.

[0120] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. The control and status field includes several reserved subfields to ensure the length alignment of each byte in the control and status field.

[0121] SDS and SKP type link training frames are used to identify the start of the Flit data stream after link training is completed between the sender and receiver.

[0122] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In an SDS-type link training frame, the control and status field includes an SDS subfield (SDS_pattern), which occupies 16 bits of Byte2[7:0] and Byte3[7:0] in the control and status field. The value register in this bit field is configurable and defaults to 0x6c.

[0123] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In a link training frame of type SKP, the control and status field includes the skp subfield (sds_pattern), which occupies the 16-bit bit fields of Byte2[7:0] and Byte3[7:0] in the control and status field. The value register in this bit field is configurable and defaults to 0xf0.

[0124] EIOS type link training frames are used to indicate that the sender has entered an idle state and stopped transmitting data.

[0125] In one example, the control and status field can transmit 4B (32 bits) of user-defined data. In an EIOS type link training frame, the control and status field includes an eios subfield (eios_pattern), which occupies the 16-bit bit fields of Byte2[7:0] and Byte3[7:0] in the control and status field. The value register in this bit field is configurable and defaults to 0x0f.

[0126] In addition to the examples above, the specific forms of different types of EIOS control and status fields can be flexibly set according to actual application needs, and this disclosure does not impose specific limitations on them.

[0127] The training pattern field in the link training frame is used to transmit the pseudo-random training sequence for the physical layer training. After receiving consecutive training frames, the receiver uses the pseudo-random training sequence in the training pattern field to train its own equalizer and clock recovery circuit.

[0128] In one possible implementation, the pseudo-random training sequence is a random code pattern generated based on a pseudo-random binary sequence (PRBS) generator, wherein the number of 0s and 1s in the pseudo-random training sequence is balanced.

[0129] The pseudo-random training sequence of the training pattern field in the link training frame can be a random code generated by a PRBS generator, ensuring a balance between the number of 0s and 1s. This utilizes the randomness and DC balance characteristics of the PRBS sequence to provide an ideal training code for the physical layer.

[0130] In one example, based on the random code pattern generated by the PRBS generator, the pseudo-random training sequence supports three output modes according to the current physical layer modulation method: Non-Return-to-Zero (NRZ) output mode, Pulse Amplitude Modulation 4 (PAM4) output mode (graycoding) and PAM4 with precoding output mode (graycoding+precoding).

[0131] In one example, the PRBS generator can take the PBRS13 generator.

[0132] Figure 7 A schematic diagram of a PBRS13 generator according to an embodiment of this disclosure is shown. Figure 7As shown, the PBRS13 generator includes 13-bit shift registers: S0 to S12. The initial state of these shift registers is the PRBS default seed. The connection method of the XOR gates ⊕ between the shift registers in the PBRS13 generator depends on the selected PRBS polynomial. Figure 7 This is merely an example and does not constitute any limitation on PBRS13 generators.

[0133] The PBRS13 generator generates a set of random code patterns with a length of 8191 bits, including 4096 1s and 4095 0s. Given that the pseudo-random training sequence in the training pattern field of the link training frame has a length of 32764 bits, PBRS needs to generate 4 sets of random code patterns. To maintain a balance between the number of 0s and 1s, 4 0s are added to the end of the 4 sets of random code patterns to obtain the final pseudo-random training sequence.

[0134] In one possible implementation, when there are multiple physical channels at the physical layer, the PRBS polynomials and / or PRBS default seeds used by different physical channels are configured to be different.

[0135] In high-speed interface transmission systems, the physical layer SERDEs have multiple physical lanes. To reduce the mutual influence between the physical lanes, the PRBS polynomials and / or PRBS default seeds used by different physical lanes are configured to be different, so that the pseudo-random training sequences of different physical lanes are different.

[0136] In one example, when generating pseudo-random training sequences using the PBRS13 generator, at least four PRBS polynomials are required. The specific form of the PRBS polynomial for each physical lane can be implemented according to the software configuration.

[0137] In one example, the default seed for each physical lane (PRBS) can also be flexibly configured via registers.

[0138] For example, the PRBS polynomial configuration of physical channel 1 (lane1) is 1+x+x 2 +x 12 +x 13 The default PRBS seed is configured as 0030330330000; the PRBS polynomial for physical channel 2 (lane2) is configured as 1+x. 2 +x 4 +x 8 +x 13The default seed for PRBS is configured as 0303333033030.

[0139] Figure 8 A schematic diagram illustrating the generation of pseudo-random training sequences according to embodiments of the present disclosure is shown. Figure 8 As shown, after selecting the PRBS polynomial and the default PRBS seed for the PBRS generator, the PBRS generator generates the corresponding random code pattern. Then, based on the currently selected output mode, it can output any one of the three different output modes (00=PAM2 (NRZ), 10=PAM4, 11=PAM4 with precoding)) of the pseudo-random training sequence.

[0140] The link training data generation module generates link training frames and then sends them to the other end.

[0141] Figure 9 A schematic diagram of a link training frame according to an embodiment of the present disclosure is shown. (As shown) Figure 9 As shown, the link training frame includes a 64-bit frame marker field (16 symbols 3, then 16 symbols 0), a 512-bit control and status field (16 symbols (symbol 0 to symbol 15) 256-bit control bit field, 16 symbols (symbol 0 to symbol 15) 256-bit status bit field), and a 32768-bit training sequence field. Figure 9 The training frames shown are transmitted from left to right and from top to bottom. In PAM4 or PAM4 with precoding output mode, Figure 9 The link training frame shown requires 32 UI to output a 64-bit frame tag field, 128 UI to output a 256-bit control field, 128 UI to output a 256-bit state field, and 16384 UI to output a 32768-bit training sequence field.

[0142] In one possible implementation, the link training data generation module is configured to: generate and send multiple TS1 and TS2 type link training frames to the receiving end before the link layer parameter negotiation is completed; generate and send an SDS type link training frame to the receiving end after the link layer parameter negotiation is completed; and after sending an SDS type link training frame to the receiving end, and if it is determined that the Flit data generation module has not yet generated the first Flit data frame, generate and send at least one SKP type link training frame to the receiving end.

[0143] By sending multiple TS1 / TS2 type link training frames before the link layer parameter negotiation is completed, sending an SDS type link training frame after the negotiation is completed, and sending at least one SKP type link training frame after the SDS and before the first Flit data frame is generated, a complete set of link training is provided, thereby ensuring a smooth switch from training mode to data transmission mode and avoiding data loss or state errors during the mode switching process.

[0144] During link initialization, the mode switching module switches to link training mode, and link training frames gain transmission rights. At this time, the link training data generation module at the transmitting end generates and sends multiple TS type (including TS1 and TS2 types) link training frames to the receiving end. Simultaneously, it also receives multiple TS type (including TS1 and TS2 types) link training frames returned by the receiving end. The process of the receiving end generating and sending TS type (including TS1 and TS2 types) link training frames to the transmitting end can be referenced from the process of the transmitting end generating and sending TS type (including TS1 and TS2 types) link training frames to the receiving end, and will not be elaborated here.

[0145] After the sending and receiving ends exchange a certain number of TS type (including TS1 and TS2 types) link training frames, the link layer parameter negotiation is completed.

[0146] After the link layer parameter negotiation is completed, the link training data generation module at the sending end generates and sends an SDS-type link training frame to the receiving end to inform the receiving end that it is about to start sending Flit data frames.

[0147] However, if the link training data generation module sends an SDS-type link training frame to the receiving end, but the Flit data generation module has not yet generated the first Flit data frame, the link training data generation module can generate and send at least one SKP-type link training frame to the receiving end until the Flit data generation module generates the first Flit data frame to avoid link idleness.

[0148] After the Flit data generation module generates the first Flit data frame, the mode switching module switches to data transmission mode, and the Flit data frame gains transmission rights. At this time, the Flit data generation module sends the Flit data frame to the receiving end.

[0149] The parallel data stream (link training frame or Flit data frame) sent out by the transmitting end through the parallel bus of the link layer is converted from parallel to serial within the physical layer's SERDEs and then transmitted serially between SERDEs. At the receiving end, the SERDEs convert the serial data stream from serial to parallel to obtain a parallel data stream. However, this parallel data stream is not aligned. Therefore, it is necessary to find the block boundary based on the frame marker in the link training frame. After finding the block boundary, subsequent data is taken from this position, and parameters are matched and parsed according to the contents of each field in the control and status fields of the link training frame.

[0150] In one possible implementation, the receiver includes an alignment state machine.

[0151] The high-speed interface transmission system in this embodiment has five different states in the alignment state machine of the receiving end, according to the delimitation stage: unaligned state (UALIGNED_PHASE), preliminary alignment state (ALIGNED_PHASE), detection state (DETECT_PHASE), intra-frame state (IN_FRAME_PHASE), and data state (DATA_PHASE). The operations and transitions in different states are described in detail below.

[0152] In one possible implementation, the receiving end includes: a link training data parsing module; an alignment state machine, used to control the link training data parsing module to perform sliding detection on the received data stream in an unaligned state to determine whether there is a frame marker with full code matching; and an alignment state machine, used to jump to the preliminary alignment state when the link training data parsing module detects the first frame marker with full code matching, and to control the link training data parsing module to record the offset position according to the first frame marker with full code matching.

[0153] By using an alignment state machine to control the link training data parsing module to perform sliding detection on the received data stream in the unaligned state (UALIGNED_PHASE) to determine whether there is a frame marker with a full code match, the system jumps to the preliminary alignment state (ALIGNED_PHASE) and records the offset position when the first frame marker with a full code match is detected, thereby realizing automatic search and preliminary positioning of frame boundaries.

[0154] During the link initialization phase, the alignment state machine is in an unaligned state (UALIGNED_PHASE). At this time, the link training data parsing module performs sliding detection on the received data stream to determine whether there is a data stream that fully matches the frame marker. If so, it is determined that the first fully matched frame marker has been detected.

[0155] After the link training data parsing module detects the first fully matched frame marker, the alignment state machine jumps from the unaligned state (UALIGNED_PHASE) to the preliminary alignment state (ALIGNED_PHASE). Simultaneously, the link training data parsing module records the offset position based on the location of the first detected fully matched frame marker. For example... Figure 1 As shown, the receiving end includes a link training data parsing module.

[0156] Figure 10 The diagram illustrates the operation and transitions of the aligned state machine under different states according to embodiments of the present disclosure. Figure 10 As shown, in the unaligned state (UALIGNED_PHASE), it continuously detects whether there is a data stream that fully matches the frame marker; and after detecting the first fully matched frame marker, it jumps to the initial aligned state (ALIGNED_PHASE).

[0157] In one possible implementation, an alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the detection state if the link training data parsing module detects that the next frame marker fuzzy matching has failed.

[0158] By continuing to detect based on the recorded offset position in the initial alignment state (ALIGNED_PHASE), and jumping to the detection state (DETECT_PHASE) when the next frame flag fuzzy match fails, alignment deviations caused by temporary interference can be detected in a timely manner, avoiding the continuous misuse of incorrect alignment states and improving the fault tolerance of link alignment.

[0159] Since the length L of the training frame is fixed, the interval between adjacent frame markers is also fixed. Assuming the offset position recorded based on the position of the first full-code matching frame marker is p, then the predicted position of the next frame marker should be p+L, the predicted position of the next frame marker after that should be p+2L, and so on.

[0160] In the initial alignment state (ALIGNED_PHASE), the link training data parsing module continues to detect the received data stream based on the recorded offset position p. If a frame marker fuzzy match failure is detected at the next frame marker prediction position p+L, it can be determined that the current recorded offset position p may be incorrect. At this time, the alignment state machine jumps from the initial alignment state (ALIGNED_PHASE) to the detection state (DETECT_PHASE).

[0161] In this context, a successful fuzzy match means that the number of matching bits in the frame marker is greater than or equal to a preset number, without requiring a full code match. A failed fuzzy match means that the number of matching bits in the frame marker is less than a preset number. The preset number can be flexibly set according to the actual application scenario, and this disclosure does not impose a specific limitation on it.

[0162] like Figure 10 As shown, in the initial alignment state (ALIGNED_PHASE), after detecting that the next frame marker fails to match fuzzily based on the currently recorded offset position, it jumps to the detection state (DETECT_PHASE).

[0163] In one possible implementation, an alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the detection state if the link training data parsing module detects a frame marker with full code matching again, but it is not aligned with the recorded offset position.

[0164] By continuing to detect based on the recorded offset position in the initial alignment state (ALIGNED_PHASE), and jumping to the detection state (DETECT_PHASE) when a full code matching frame mark is detected again but is not aligned with the recorded offset position, the frame mark position drift caused by data misalignment can be detected, thereby triggering the realignment process in a timely manner to ensure the accuracy of alignment.

[0165] In the initial alignment state (ALIGNED_PHASE), the link training data parsing module continues to inspect the received data stream based on the recorded offset position p. If a frame marker with a complete code match is detected again, but it is not aligned with the recorded offset position p, that is, the position of the frame marker with a complete code match is not p+L, it can be determined that the currently recorded offset position p may be incorrect. At this time, the alignment state machine jumps from the initial alignment state (ALIGNED_PHASE) to the detection state (DETECT_PHASE).

[0166] In one possible implementation, an alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the detection state, and to jump to the unaligned state if the link training data parsing module detects that the first number of frame markers have failed to match fuzzily.

[0167] By continuing detection based on the recorded offset position in the detection state (DETECT_PHASE), and jumping to the unaligned state (UALIGNED_PHASE) when the first number of consecutive frame markers fail to match fuzzily, the error rate is determined to be high after multiple consecutive alignment failures, thereby triggering a complete realignment process starting from the beginning and avoiding continuous invalid detection.

[0168] In the detection state (DETECT_PHASE), the link training data parsing module continues to detect the received data stream based on the recorded offset position. If the first number of frame markers are detected as failing to match fuzzily, it can be determined that the current bit error rate is high, affecting the link parsing and detection, or that the recorded offset position is incorrect. At this time, the alignment state machine jumps from the detection state (DETECT_PHASE) to the unaligned state (UALIGNED_PHASE) and performs full code matching again. The size of the first number can be flexibly set according to the actual application scenario, and this disclosure does not impose a specific limitation on it.

[0169] like Figure 10 As shown, in the detection state (DETECT_PHASE), if the first number of framemarks are detected and all fail to match fuzzily, the system jumps to the unaligned state (UALIGNED_PHASE).

[0170] In one possible implementation, an alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the detection state, and to jump to the preliminary alignment state when the link training data parsing module detects the frame marker and the fuzzy match is successful.

[0171] By continuing detection based on the recorded offset position in the detection state (DETECT_PHASE) and jumping back to the initial alignment state (ALIGNED_PHASE) when a frame marker is detected and a fuzzy match is successful, the system can quickly recover to the initial alignment state after experiencing a brief alignment failure, thereby improving alignment robustness and recovery speed.

[0172] In the detection state (DETECT_PHASE), the link training data parsing module continues to detect the received data stream based on the recorded offset position. If a frame marker is detected again and the fuzzy match is successful, the alignment state machine jumps from the detection state (DETECT_PHASE) back to the initial alignment state (ALIGNED_PHASE).

[0173] like Figure 10 As shown, in the detection state (DETECT_PHASE), the detection continues based on the recorded offset position. If the frame marker is detected again and the fuzzy match is successful, the system jumps back to the initial alignment state (ALIGNED_PHASE).

[0174] In one possible implementation, an alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the intra-frame state when the link training data parsing module detects that the second number of frame markers have been successfully fuzzy matched. The alignment state machine is used to control the link training data parsing module to parse the received link training frame according to the recorded offset position in the intra-frame state.

[0175] By jumping to the intra-frame state (IN_FRAME_PHASE) when the second number of frame markers are successfully matched in the initial alignment state (ALIGNED_PHASE), the probability of misalignment is reduced by using multiple consecutive successful matches as the basis for entering the stable parsing state. This ensures the reliability and accuracy of parsing the link training frames based on the recorded offset position in the intra-frame state (IN_FRAME_PHASE).

[0176] In the initial alignment state (ALIGNED_PHASE), the link training data parsing module continues to detect the received data stream based on the recorded offset position. If a second number of frame markers are detected and all fuzzy matches are successful, the alignment is considered successful. At this point, the alignment state machine transitions from the initial alignment state (ALIGNED_PHASE) to the intra-frame state (IN_FRAME_PHASE). The size of the second number can be flexibly set according to the actual application scenario, and this disclosure does not impose specific limitations on it.

[0177] like Figure 10 As shown, in the initial alignment state (ALIGNED_PHASE), after the second number of frame markers are detected to be fuzzily matched successfully, the process jumps to the intra-frame state (IN_FRAME_PHASE).

[0178] In the intra-frame state (IN_FRAME_PHASE), the recorded offset position is locked. At this time, the frame boundary of the link training frame can be identified from the data stream based on the locked offset position, and then the link training frame can be extracted and parsed.

[0179] In one possible implementation, an alignment state machine is used to jump to an unaligned state if it is determined in the intra-frame state that a change in the physical channel rate is needed.

[0180] By jumping to the unaligned state (UALIGNED_PHASE) when it is determined that the physical channel rate needs to be changed in the intra-frame state (IN_FRAME_PHASE), the realignment process is actively triggered when the link parameters need to be renegotiated, ensuring that the link can be realigned after the physical channel rate is changed, and avoiding data errors caused by rate mismatch.

[0181] In the intra-frame state (IN_FRAME_PHASE), it may be determined that a change in the physical channel rate is needed. For example, the link training data parsing module, by parsing the TS-type link training frame, detects from the control and status fields of the TS-type link training frame that the physical channel rate change subfield (speed_change) indicates that the peer has requested a change in the physical channel rate; or, the local end has a need to change the physical channel rate. In this case, link training needs to be re-performed, therefore, the alignment state machine jumps from the intra-frame state (IN_FRAME_PHASE) to the unaligned state (UALIGNED_PHASE).

[0182] like Figure 10As shown, in the intra-frame state (IN_FRAME_PHASE), after detecting that the physical channel rate needs to be changed, it jumps to the unaligned state (UALIGNED_PHASE).

[0183] In one possible implementation, an alignment state machine is used to jump to an unaligned state when the link training data parsing module detects a third consecutive failure of fuzzy matching of frame markers in the intra-frame state.

[0184] By jumping to the unaligned state (UALIGNED_PHASE) when a third consecutive frame tag fails to match fuzzily in the intra-frame state (IN_FRAME_PHASE), the system can exit the intra-frame state (IN_FRAME_PHASE) in a timely manner if consecutive alignment failures occur during stable parsing, thus avoiding invalid data parsing when the link quality is poor.

[0185] In the intra-frame state (IN_FRAME_PHASE), if the link training data parsing module detects that the third number of frame markers have all failed to match fuzzily, it can be determined that the frame boundaries in the current data stream have been lost. At this point, re-alignment is required. Therefore, the alignment state machine jumps from the intra-frame state (IN_FRAME_PHASE) back to the unaligned state (UALIGNED_PHASE). The size of the third number can be flexibly set according to the actual application scenario, and this disclosure does not impose a specific limitation on it.

[0186] like Figure 10 As shown, in the intra-frame state (IN_FRAME_PHASE), after the third consecutive frame marker is detected as failing to match fuzzily, it jumps to the unaligned state (UALIGNED_PHASE).

[0187] In one possible implementation, the receiving end includes: a Flit data extraction module; an alignment state machine, used to switch to the data state when the link training data parsing module receives link training frames of SDS type and SKP type, and the SKP type link training frame is followed by a Flit data frame; and an alignment state machine, used to control the Flit data extraction module to extract Flit data frames from the received data stream when the receiving end is in the data state.

[0188] By receiving SDS and SKP type link training frames in the intra-frame state (IN_FRAME_PHASE) and then switching to the data state (Data_PHASE) when the SKP type frame is followed by a Flit data frame, and controlling the Flit data extraction module to extract Flit data frames from the data stream in the data state (Data_PHASE), the state transition and mode switching from link training mode to data transmission mode are effectively realized, ensuring that Flit data frames can be correctly identified and extracted.

[0189] In the intra-frame state (IN_FRAME_PHASE), when the link training data parsing module parses and determines that it has received SDS and SKP type link training frames, and that the SKP type link training frame is followed not by a new link training frame but by a Flit data frame, it can be determined that the current sender has switched to data transmission mode and is sending user data stream. At this time, the alignment state machine jumps from the intra-frame state (IN_FRAME_PHASE) to the data state (Data_PHASE).

[0190] like Figure 10 As shown, in the intra-frame state (IN_FRAME_PHASE), after receiving link training frames of SDS type and SKP type, it jumps to the data state (Data_PHASE).

[0191] In the Data PHASE state, the receiving end's Flit data extraction module extracts Flit data frames from the data stream. For example... Figure 1 As shown, the receiving end includes the Flit data extraction module.

[0192] In one possible implementation, an alignment state machine is used to jump to an unaligned state if it is determined in the data state that a change in the physical channel rate is needed.

[0193] By jumping to the unaligned state (UALIGNED_PHASE) when it is determined that the physical channel rate needs to be changed in the data state (Data_PHASE), the realignment process is actively triggered when the link parameters need to be renegotiated during data transmission, ensuring the safety of rate changes and avoiding data errors caused by sudden rate changes during data transmission.

[0194] In the data state (Data_PHASE), if there is a need to change the physical channel rate at the local end, the link needs to be retrained. Therefore, the alignment state machine jumps from the data state (Data_PHASE) to the unaligned state (UALIGNED_PHASE).

[0195] like Figure 10As shown, in the Data PHASE state, after detecting that the physical channel rate needs to be changed, it jumps to the unaligned state (UALIGNED_PHASE).

[0196] In one possible implementation, an alignment state machine is used to jump to an unaligned state when the Flit data extraction module detects a frame marker with a full code match in the data state.

[0197] By jumping to the unaligned state (UALIGNED_PHASE) when a frame marker with a full code match is detected in the data state (Data_PHASE), the system can exit the data state (Data_PHASE) in a timely manner when the frame marker reappears in the data stream, thus avoiding the misinterpretation of link training frames as Flit data frames and ensuring a fast response to link training frames.

[0198] In the data state (Data_PHASE), if a frame marker with a full code match is detected, it indicates that the peer may want to retrain the link. At this time, the alignment state machine jumps from the data state (Data_PHASE) to the unaligned state (UALIGNED_PHASE).

[0199] like Figure 10 As shown, in the Data PHASE state, the frame marker that matches the full code jumps to the unaligned state (UALIGNED_PHASE).

[0200] By aligning the various states of the state machine and the corresponding operations of the link training data parsing module or Flit data extraction module under different states, the receiving end can effectively and automatically complete link training and user data reception.

[0201] Figure 11 A flowchart illustrating a high-speed interface transmission method according to an embodiment of the present disclosure is shown. This method is applied to... Figure 1 The high-speed interface transmission system shown includes a transmitter and a receiver; the transmitter includes a Flit data generation module, a link training data generation module, and a mode switching module. Figure 11 As shown, the method may include:

[0202] In step S110, during the link initialization phase, the control mode switching module switches to the link training mode;

[0203] In step S111, in the link training mode, the link training data generation module is controlled to generate and send link training frames to the receiving end, wherein the link training frames are used for link training between the sending end and the receiving end.

[0204] In step S112, after link training is completed between the sending end and the receiving end, the control mode switching module switches to data transmission mode.

[0205] In step S113, in data transmission mode, the Flit data generation module is controlled to generate and send Flit data frames to the receiving end.

[0206] In one possible implementation, the Flit data frame includes: DLLP; wherein the DLLP includes flow control information indicating the number of available Credits in the flow control buffer, and one Credit is configured as the storage width of the flow control buffer.

[0207] In one possible implementation, the Flit data frame includes: a TLP; the byte length of the DLLP and the byte length of the TLP are variable, and the byte length of the compressed DLLP is positively correlated with the byte length increase of the TLP.

[0208] In one possible implementation, the length of the Flit data frame is 256 bytes; the Flit data frame includes: 238 bytes of TLP, 2 bytes of control information, 2 bytes of DLLP, 8 bytes of CRC, and 6 bytes of FEC; the 2-byte DLLP includes: a 5-bit flow control message type field and an 11-bit flow control message field; wherein, the 5-bit flow control message type field supports the transmission of 32 flow control message types, and the 11-bit flow control message field supports the transmission of flow control messages indicating the number of available Credits in the flow control buffer with a depth of 1024.

[0209] In one possible implementation, the link training frame includes: a frame tag field, a control and status field, and a training sequence field; the frame tag field is used to transmit a frame tag that identifies the start boundary of the link training frame; the control and status field is used to transmit negotiation information for link layer negotiation, wherein the negotiation information is obtained by encoding user-defined data, and the user-defined data is used to define the type of link training frame and the link layer parameters that need to be negotiated; the training sequence field is used to transmit the pseudo-random training sequence for physical layer training.

[0210] In one possible implementation, the negotiation information is obtained by encoding user-defined data based on the DME method.

[0211] In one possible implementation, the link training frame type includes at least one of the following: TS1 type, TS2 type, SDS type, SKP type, and EIOS type; TS1 and TS2 type link training frames are used to complete link layer parameter negotiation between the sender and receiver; SDS and SKP type link training frames are used to identify the start of the Flit data stream after link training is completed between the sender and receiver; and EIOS type link training frames are used to indicate that the sender has entered an idle state and stopped transmitting data.

[0212] In one possible implementation, the link layer parameters that need to be negotiated include at least one of the following: link width and physical channel rate.

[0213] In one possible implementation, the pseudo-random training sequence is a random code pattern generated by a PRBS generator, wherein the number of 0s and 1s in the pseudo-random training sequence is balanced.

[0214] In one possible implementation, when there are multiple physical channels at the physical layer, the PRBS polynomials and / or PRBS default seeds used by different physical channels are configured to be different.

[0215] In one possible implementation, in the link training mode, controlling the link training data generation module to generate and send link training frames to the receiving end includes: when the length of the frame marker is half the parallel bus bit width of the high-speed interface transmission system and the length of the link training frame is an odd multiple of the length of the frame marker, controlling the link training data generation module to generate and send an even number of link training frames to the receiving end.

[0216] In one possible implementation, in link training mode, controlling the link training data generation module to generate and send link training frames to the receiving end includes: before the link layer parameter negotiation is completed, controlling the link training data generation module to generate and send multiple TS1 and TS2 type link training frames to the receiving end; after the link layer parameter negotiation is completed, controlling the link training data generation module to generate and send an SDS type link training frame to the receiving end; after sending an SDS type link training frame to the receiving end, and if it is determined that the Flit data generation module has not yet generated the first Flit data frame, controlling the link training data generation module to generate and send at least one SKP type link training frame to the receiving end.

[0217] In one possible implementation, the receiving end includes: an alignment state machine and a link training data parsing module; the method further includes: when the alignment state machine is in an unaligned state, controlling the link training data parsing module to perform sliding detection on the received data stream to determine whether there is a frame marker with full code matching; when the link training data parsing module detects the first frame marker with full code matching, controlling the alignment state machine to jump to the preliminary alignment state, and controlling the link training data parsing module to record the offset position according to the first frame marker with full code matching.

[0218] In one possible implementation, the method further includes: when the alignment state machine is in the initial alignment state, controlling the link training data parsing module to continue detecting the received data stream according to the recorded offset position, and when the link training data parsing module detects that the next frame marker fuzzy matching has failed, controlling the alignment state machine to jump to the detection state.

[0219] In one possible implementation, the method further includes: when the alignment state machine is in the initial alignment state, controlling the link training data parsing module to continue to detect the received data stream according to the recorded offset position, and when the link training data parsing module detects a frame marker with full code matching again, but it is not aligned with the recorded offset position, controlling the alignment state machine to jump to the detection state.

[0220] In one possible implementation, the method further includes: when the alignment state machine is in the detection state, controlling the link training data parsing module to continue to detect the received data stream according to the recorded offset position, and when the link training data parsing module detects that the first number of frame markers have failed to match fuzzily, controlling the alignment state machine to jump to the unaligned state.

[0221] In one possible implementation, the method further includes: when the alignment state machine is in the detection state, controlling the link training data parsing module to continue to detect the received data stream according to the recorded offset position, and when the link training data parsing module detects the frame marker and the fuzzy match is successful, controlling the alignment state machine to jump to the initial alignment state.

[0222] In one possible implementation, the method further includes: when the alignment state machine is in the initial alignment state, controlling the link training data parsing module to continue detecting the received data stream according to the recorded offset position, and when the link training data parsing module detects that the second number of frame markers have been successfully fuzzily matched, controlling the alignment state machine to jump to the intra-frame state; when the alignment state machine is in the intra-frame state, controlling the link training data parsing module to parse the received link training frame according to the recorded offset position.

[0223] In one possible implementation, the method further includes: when the alignment state machine is in an intra-frame state and it is determined that the physical channel rate needs to be changed, controlling the alignment state machine to jump to an unaligned state.

[0224] In one possible implementation, the method further includes: when the alignment state machine is in the intra-frame state, if the link training data parsing module detects that the third number of frame tags have failed to match fuzzily, the alignment state machine is controlled to jump to the unaligned state.

[0225] In one possible implementation, the receiving end includes a Flit data extraction module; the method further includes: when the alignment state machine is in the intra-frame state, if it is detected that the link training data parsing module has received link training frames of SDS type and SKP type, and the link training frame of SKP type is followed by a Flit data frame, controlling the alignment state machine to jump to the data state; when the alignment state machine is in the data state, controlling the Flit data extraction module to extract Flit data frames from the received data stream.

[0226] In one possible implementation, the method further includes: when the alignment state machine is in the data state and it is determined that the physical channel rate needs to be changed, controlling the alignment state machine to jump to the unaligned state.

[0227] In one possible implementation, the method further includes: when the alignment state machine is in the data state and the Flit data extraction module detects a frame marker with a full code match, controlling the alignment state machine to jump to the unaligned state.

[0228] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0229] This disclosure also provides an electronic device including the high-speed interface transmission system described above.

[0230] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0231] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0232] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0233] Figure 12 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. (Refer to...) Figure 12 Device 1900 can be provided as a server or terminal device. (See reference...) Figure 12 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0234] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0235] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0236] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0237] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0238] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0239] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0240] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0241] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0242] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0243] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A high-speed interface transmission system, characterized in that, include: The transmitter and receiver; wherein the transmitter includes: a Flit data generation module, a link training data generation module, and a mode switching module; The mode switching module is used to switch to link training mode during the link initialization phase. The link training data generation module is used to generate and send link training frames to the receiving end in link training mode, wherein the link training frames are used for link training between the sending end and the receiving end. The mode switching module is used to switch to data transmission mode after link training is completed between the sending end and the receiving end. The Flit data generation module is used to generate and send Flit data frames to the receiving end in data transmission mode.

2. The system according to claim 1, characterized in that, The Flit data frame includes: a data link layer packet DLLP; wherein, the DLLP includes flow control information for indicating the number of available credits in the flow control buffer, and one credit is configured as the storage width of the flow control buffer.

3. The system according to claim 2, characterized in that, The Flit data frame includes: a byte transaction layer data packet (TLP); The byte length of the DLLP and the byte length of the TLP are variable, and the byte length of the DLLP compression is positively correlated with the byte length increase of the TLP.

4. The system according to claim 2 or 3, characterized in that, The length of the Flit data frame is 256 bytes; The Flit data frame includes: 238 bytes of TLP, 2 bytes of control information, 2 bytes of DLLP, 8 bytes of cyclic redundancy check (CRC) code, and 6 bytes of forward error correction (FEC) code; The 2-byte DLLP includes: a 5-bit flow control message type field and an 11-bit flow control message field; wherein, the 5-bit flow control message type field supports the transmission of 32 flow control message types, and the 11-bit flow control message field supports the transmission of flow control messages indicating the number of available Credits in a flow control buffer with a depth of 1024.

5. The system according to claim 1, characterized in that, The link training frame includes: a frame tag field, a control and state field, and a training sequence field; The frame tag field is used to transmit a frame tag that identifies the start boundary of the link training frame; The control and status fields are used to transmit negotiation information for link layer negotiation. The negotiation information is obtained by encoding user-defined data, which is used to define the type of the link training frame and the link layer parameters that need to be negotiated. The training sequence field is used to transmit pseudo-random training sequences for physical layer training.

6. The system according to claim 5, characterized in that, The negotiation information is obtained by encoding the user-defined data using the Differential Manchester Encoding (DME) method.

7. The system according to claim 5, characterized in that, The type of the link training frame includes at least one of the following: first training sequence TS1 type, second training sequence TS2 type, start data stream SDS type, skip SKP type, and electrical idle sequence EIOS type. The link training frames of TS1 and TS2 types are used to complete the link layer parameter negotiation between the sending end and the receiving end; The link training frames of SDS and SKP types are used to identify the start of the Flit data stream after link training is completed between the sending end and the receiving end; The link training frame of type EIOS is used to identify that the sending end has entered an idle state and stopped transmitting data.

8. The system according to claim 5, characterized in that, The link layer parameters that need to be negotiated include at least one of the following: link width and physical channel rate.

9. The system according to claim 5, characterized in that, The pseudo-random training sequence is a random code pattern generated based on a pseudo-random binary sequence (PRBS) generator, wherein the number of 0s and 1s in the pseudo-random training sequence is balanced.

10. The system according to claim 9, characterized in that, When there are multiple physical channels at the physical layer, the PRBS polynomials and / or PRBS default seeds used by different physical channels are configured differently.

11. The system according to claim 5, characterized in that, The link training data generation module is used for: When the length of the frame marker is half the width of the parallel bus of the system, and the length of the link training frame is an odd multiple of the length of the frame marker, an even number of the link training frames are generated and sent to the receiving end.

12. The system according to claim 7, characterized in that, The link training data generation module is used for: Before the link layer parameter negotiation is completed, multiple TS1 and TS2 type link training frames are generated and sent to the receiving end. After the link layer parameter negotiation is completed, an SDS type link training frame is generated and sent to the receiving end; After sending an SDS-type link training frame to the receiving end, and determining that the Flit data generation module has not yet generated the first Flit data frame, at least one SKP-type link training frame is generated and sent to the receiving end.

13. The system according to claim 7, characterized in that, The receiving end includes: an alignment state machine and a link training data parsing module; The alignment state machine is used to control the link training data parsing module to perform sliding detection on the received data stream in the unaligned state to determine whether there is a frame marker with full code matching. The alignment state machine is used to jump to the preliminary alignment state when the link training data parsing module detects the first full code matching frame marker, and to control the link training data parsing module to record the offset position according to the first full code matching frame marker.

14. The system according to claim 13, characterized in that, The alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the detection state when the link training data parsing module detects that the next frame marker fuzzy matching fails.

15. The system according to claim 13, characterized in that, The alignment state machine is used to control the link training data parsing module to continue detecting the received data stream according to the recorded offset position in the initial alignment state, and to jump to the detection state when the link training data parsing module detects the frame marker with full code matching again, but it is not aligned with the recorded offset position.

16. The system according to claim 14 or 15, characterized in that, The alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the detection state, and to jump to the unaligned state when the link training data parsing module detects that the first number of frame markers have failed to match fuzzily.

17. The system according to claim 14 or 15, characterized in that, The alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the detection state, and to jump to the preliminary alignment state when the link training data parsing module detects the frame marker and the fuzzy match is successful.

18. The system according to claim 14, characterized in that, The alignment state machine is used to control the link training data parsing module to continue to detect the received data stream according to the recorded offset position in the initial alignment state, and to jump to the intra-frame state when the link training data parsing module detects that the second number of frame markers are successfully fuzzy matched. The alignment state machine is used to control the link training data parsing module to parse the received link training frame according to the recorded offset position in the intra-frame state.

19. The system according to claim 18, characterized in that, The alignment state machine is used to jump to the unaligned state when it is determined in the intra-frame state that a change in the physical channel rate is required.

20. The system according to claim 18, characterized in that, The alignment state machine is used to jump to the unaligned state when the link training data parsing module detects a third consecutive failure of fuzzy matching of the frame markers in the intra-frame state.

21. The system according to claim 18, characterized in that, The receiving end includes: a Flit data extraction module; The alignment state machine is used to, in the intra-frame state, detect that the link training data parsing module has received the link training frames of SDS type and SKP type, and that the link training frame of SKP type is followed by the Flit data frame, and then jump to the data state. The alignment state machine is used to control the Flit data extraction module to extract the Flit data frame from the received data stream in the data state.

22. The system according to claim 21, characterized in that, The alignment state machine is used to jump to the unaligned state when it is determined in the data state that a change in the physical channel rate is required.

23. The system according to claim 21, characterized in that, The alignment state machine is used to jump to the unaligned state when the Flit data extraction module detects a frame marker with a full code match in the data state.

24. A high-speed interface transmission method, characterized in that, The method is applied to high-speed interface transmission systems; The high-speed interface transmission system includes a transmitter and a receiver; wherein the transmitter includes a Flit data generation module, a link training data generation module, and a mode switching module. During the link initialization phase, the mode switching module is controlled to switch to link training mode; In link training mode, the link training data generation module is controlled to generate and send link training frames to the receiving end, wherein the link training frames are used for link training between the sending end and the receiving end; After link training is completed between the sending end and the receiving end, the mode switching module is controlled to switch to data transmission mode. In data transmission mode, the Flit data generation module is controlled to generate and send Flit data frames to the receiving end.

25. An electronic device, characterized in that, Includes the system described in any one of claims 1 to 23.

26. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method of claim 24.

27. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 24.

28. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 24.

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