Control device, in-memory computing system, control method, and electronic device

Abstract

A control device, in-memory computing system, control method, and electronic device are disclosed, relating to the field of in-memory computing technology. The control device includes a first control circuit and a second control circuit. The first control circuit is configured to generate and send a first instruction, which instructs a storage circuit to perform a first operation. The first instruction includes first type information indicating the type of the first operation. The second control circuit is connected to the first control circuit and is configured to receive and parse the first instruction, convert it into a first command sequence based on the first type information, and send the first command sequence to the storage circuit. The second control circuit is also configured to send the execution result of the first command sequence to the first control circuit. This solution concentrates more control components in the control device implementation, reducing the complexity of the logic control section of the storage circuit, allowing the storage circuit to have more physical space for implementing functions such as storage or in-memory computing.

Description

[0001] This application claims priority to Chinese Patent Application No. 202510388321.1, filed on March 28, 2025, entitled "Control Device, In-Memory System, Control Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to a control device, a memory computing system, a control method, and an electronic device. Background Technology

[0003] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0004] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their computational performance still needs improvement. Summary of the Invention

[0005] This application provides a control device, a memory computing system, a control method, and an electronic device that can improve the computing performance of a memory computing architecture.

[0006] In a first aspect, a control device is provided, comprising a first control circuit and a second control circuit connected to the first control circuit. The first control circuit is configured to generate and transmit a first instruction, which instructs a storage circuit to perform a first operation, and the first instruction includes first type information indicating the type of the first operation. The second control circuit is configured to receive and parse the first instruction, convert the first instruction into a first command sequence based on the first type information, and transmit the first command sequence to the storage circuit.

[0007] Based on the above scheme, a first control circuit and a second control circuit are integrated into the control device. The second control circuit is further enhanced with settings for instruction parsing capabilities, such as in-memory computing instructions. This rich instruction parsing functionality enables the storage circuit to process data locally, reducing the time and resource consumption associated with data transmission. Furthermore, command sequences can be used to enhance the in-memory computing system's processing capabilities in fields such as big data analytics and artificial intelligence, providing efficient support for data storage and computation in these fields.

[0008] In some implementations of the first aspect, the second control circuit is further configured to send the execution result of the first command sequence to the first control circuit.

[0009] Based on the above scheme, the first control circuit can promptly understand the execution result of the instruction and control the sending of subsequent instructions according to the execution result, thereby improving the computing efficiency of the in-memory computing system.

[0010] In some implementations of the first aspect, the first command sequence includes an identification command and an address command, wherein the identification command is used to identify the type of the first operation and the address command is used to indicate the first storage area within the storage circuit where the first operation is performed.

[0011] Based on the above scheme, the second control circuit sends a command sequence including an identification command and an address command to the storage circuit, enabling the storage circuit to perform a first operation in the first storage area based on the command sequence.

[0012] In some implementations of the first aspect, the first instruction further includes first logical address information, which is used to indicate a first storage region, and the address command includes an initial address command and an address change command group; the second control circuit is further configured to generate an initial address command based on the first logical address information, which is used to indicate the starting address of a first operation unit in the first storage region; the second control circuit is further configured to generate an address change command group based on the first logical address information and first type information, whereby the address change command in the address change command group is used to indicate the address change of the first operation unit, and the address change command group is used to indicate the execution order of the first operation in the first storage region.

[0013] Based on the above scheme, the first control circuit sends a first instruction to the second control circuit to instruct the storage circuit to perform a first operation in the first storage area; after receiving the first instruction, the second control circuit can parse the first instruction to generate an initial address command and an address change command group, and send a first command sequence to the storage circuit to instruct the storage circuit to perform the first operation in the first storage area to start at the address and in the order of execution, so that the storage circuit can respond to the command execution operation faster and improve the response efficiency of the storage circuit.

[0014] In some implementations of the first aspect, the operation types of the storage circuit include in-memory computation, data reading, data writing, and erasure, wherein the first type information is used to indicate that the type of the first operation includes in-memory computation.

[0015] Based on the above scheme, the flexibility of the storage circuit is improved by increasing the types of operating states that the storage circuit can support.

[0016] In some implementations of the first aspect, the first instruction further includes input data; the first command sequence further includes an input data command group; the address change command group includes a first address change command group; and the second control circuit is further configured to convert the input data into an input data command group based on the first type information, and to use the combination of the input data command group and the first address change command group to indicate the execution order of in-memory computation in the first storage area.

[0017] In some implementations of the first aspect, in-memory computation is performed on a per-computation-unit basis within the first storage region, and the address change command in the first address change command group is used to indicate the address change of the computation unit.

[0018] The memory circuit can be divided into multiple computing units. Depending on the computational requirements, in-memory computation can be implemented in one or more computing units, which can increase the flexibility of in-memory computation and better adapt to the needs of different computational scales.

[0019] In some implementations of the first aspect, the computing unit includes multiple computing sub-units, and the first command sequence further includes an instruction command, which is used to instruct computing sub-units within the computing unit that do not participate in in-memory computation.

[0020] Based on the above scheme, the second control circuit can instruct the storage circuit to participate in the in-memory computation and / or not participate in the in-memory computation through the first command sequence, so that the resources of the storage circuit participating in the in-memory computation can be flexibly configured to further adapt to the needs of different computation scales. Moreover, the setting of this command sequence is conducive to the storage circuit responding to the command execution operation faster and improving the response efficiency of the storage circuit.

[0021] In some implementations of the first aspect, the computing unit includes multiple computing sub-units, and the second control circuit is further configured to generate a mask for processing input data on a per-computational-sub-unit basis.

[0022] Based on the above scheme, all "0" data can be input into the computational sub-units that do not participate in the calculation. This can reduce the impact of computational sub-units that do not participate in the calculation on other computational sub-units and improve the reliability of the calculation.

[0023] In some implementations of the first aspect, the first type of information is used to indicate data reading, and the address change command group includes a second address change command group, which is used to indicate the execution order of data reading in the first storage area.

[0024] Based on the above scheme, the second control circuit can simplify the original large amount of physical address information into a second address change command group, thereby enabling faster data reading and improving data reading efficiency.

[0025] In some implementations of the first aspect, the first control circuit is further configured to generate and send a second instruction, the second instruction being used to instruct the storage circuit to perform a second operation, and the second instruction including second type information, the second type information being used to indicate the type of the second operation; the second control circuit is further configured to receive and parse the second instruction, and convert the second instruction into a second command sequence based on the second type information, and send the second command sequence to the storage circuit.

[0026] In some implementations of the first aspect, the transmission of the second command sequence overlaps with the transmission of the first command sequence in time.

[0027] Based on the above scheme, the command transmission channel can be fully utilized to achieve efficient transmission of command sequences.

[0028] In some implementations of the first aspect, the second control circuit is further configured to generate an enable command and send the enable command to the storage circuit, wherein the enable command is generated based on the first instruction or the third instruction.

[0029] Secondly, a control method is provided for a control device, the control device including a first control circuit and a second control circuit, the second control circuit being connected to the first control circuit. The control method includes: the first control circuit generating and sending a first instruction, the first instruction instructing a storage circuit to perform a first operation, and the first instruction including first type information indicating the type of the first operation; the second control circuit receiving and parsing the first instruction, converting the first instruction into a first command sequence based on the first type information, and sending the first command sequence to the storage circuit.

[0030] In some implementations of the second aspect, the second control circuit sends the execution result of the first command sequence to the first control circuit.

[0031] For a description of the technical solution and beneficial effects of the second aspect, please refer to the description of the technical solution and beneficial effects of the first aspect, which will not be repeated here.

[0032] Thirdly, a storage computing system is provided, the storage computing system including the control device described in the first aspect above; and a storage circuit connected to the control device and configured to receive a first command sequence sent by the control device and perform a first operation based on the first command sequence.

[0033] In some implementations of the third aspect, the storage circuit is also configured to send the execution result of the first command sequence to the control device.

[0034] Fourthly, an electronic device is provided, including any of the storage and computing systems of the third aspect. Attached Figure Description

[0035] Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0036] Figure 2 A schematic diagram of another in-memory computing system according to an exemplary embodiment of this application is shown.

[0037] Figure 3 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0038] Figure 4 A schematic diagram of a three-dimensional memory cell array in a memory circuit according to an exemplary embodiment of this application is shown.

[0039] Figure 5 A flowchart illustrating a control method according to an exemplary embodiment of this application is shown.

[0040] Figure 6 A schematic diagram of the instruction processing flow of an in-memory computing flash controller according to an exemplary embodiment of this application is shown.

[0041] Figure 7 A schematic diagram of the instruction processing flow of another in-memory computing flash controller according to an exemplary embodiment of this application is shown.

[0042] Figure 8 A schematic diagram of a storage circuit is shown.

[0043] Figure 9 A schematic diagram of the enable logic signal transmission path in a storage circuit according to an exemplary embodiment of this application is shown.

[0044] Figure 10 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0045] Figure 11A schematic diagram of another control device according to an exemplary embodiment of this application is shown.

[0046] Figure 12 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0047] Figure 13 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0048] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0049] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0050] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0051] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other elements, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other elements. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other elements.

[0052] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0053] In this application, the terms "exemplarily," "for example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0054] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0055] For ease of understanding, Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. This in-memory computing system is described as an example of implementing in-memory computation using memory as a carrier.

[0056] like Figure 1As shown, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0057] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0058] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0059] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0060] As an example, Figure 2 A schematic diagram of another in-memory computing system according to an exemplary embodiment of this application is shown.

[0061] like Figure 2 As shown, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0062]

[0063] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0064] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense, amplify, or process the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in Figure 2 In the example, the in-memory computing system 200 may further include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0065] Figure 2 This is merely an example illustrating a connection method of storage cells in a storage cell array 210, except... Figure 2Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells are connected in columns with collinearity, and the output terminals of the memory cells are connected in rows with collinearity. Furthermore, the input terminals of the memory cells may include the gate of a transistor memory device, or the input terminals of the memory cells may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell may include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), floating-gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0066] This application provides a control device, a memory computing system, a control method, and an electronic device, which concentrate more control components in the control device, reduce the complexity of the logic control part of the memory circuit, and allow the memory circuit to have more physical space for implementing functions such as storage or in-memory computing, thereby improving the computing performance of the memory computing architecture.

[0067] This application provides a control device, which can be found in the embodiments described above. Figure 3 . Figure 3 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0068] like Figure 3As shown, the control device 300 includes a first control circuit 310 and a second control circuit 320, which are connected together. The first control circuit 310 is configured to generate and send a first instruction, which instructs a storage circuit to perform a first operation. The first instruction includes first type information indicating the type of the first operation. The second control circuit 320 is configured to receive and parse the first instruction, convert it into a first command sequence based on the first type information, and send the first command sequence to the storage circuit.

[0069] The first control circuit 310 may include a main control circuit, such as having the functions of the control circuit described in the above embodiments, for controlling the working state of the storage circuit. According to some embodiments, the first control circuit 310 may be used as the host or upper-layer circuit of the chip or in-memory computing system where the storage circuit is located. The second control circuit 320 may include the control circuit of the storage circuit, such as a flash controller, etc. The second control circuit 320 completes the conversion of upper-layer instructions into command sequences of the storage circuit, reducing the need for command parsing functions of the storage circuit, reducing the complexity of the logic control part of the storage circuit, and allowing the storage circuit to have more physical space for implementing storage or in-memory computing functions, that is, improving the computing performance of the in-memory computing architecture.

[0070] The control device integrates a first control circuit and a second control circuit, and adds settings for instruction parsing capabilities to the second control circuit, such as in-memory computing instructions. This rich instruction parsing functionality enables the storage circuit to process data locally, reducing the time and resource consumption caused by data transmission. Furthermore, through command sequences, the in-memory computing system's processing capabilities in fields such as big data analysis and artificial intelligence can be enhanced, providing efficient support for data storage and computation in these fields.

[0071] In one possible implementation, the second control circuit 320 is further configured to send the execution result of the first command sequence to the first control circuit 310. This allows the first control circuit 310 to promptly understand the execution result of the instructions and control the sending of subsequent instructions based on the result, thereby improving the computational efficiency of the in-memory computing system.

[0072] In one possible implementation, the first command sequence includes an identification command and an address command, wherein the identification command is used to identify the type of the first operation and the address command is used to indicate the first storage area within the storage circuit.

[0073] The second control circuit 320 sends a command sequence, including an identification command and an address command, to the storage circuit, enabling the storage circuit to perform a first operation based on the command sequence in the first storage area.

[0074] In one possible implementation, the first instruction further includes first logical address information, which indicates a first storage region. The address command includes an initial address command and an address change command group. The second control circuit 320 is further configured to generate an initial address command based on the first logical address information. The initial address command indicates the starting address of a first operation unit in the first storage region. The second control circuit 320 is also configured to generate an address change command group based on the first logical address information and first type information. The address change command group indicates the address change of the first operation unit, and the address change command group indicates the execution order of the first operation within the first storage region.

[0075] The first control circuit 310 sends a first instruction to the second control circuit 320 to instruct the storage circuit to perform a first operation in the first storage area. After receiving the first instruction, the second control circuit 320 can parse the first instruction to generate an initial address command and an address change command group, and send a first command sequence to the storage circuit to instruct the storage circuit to perform the first operation in the first storage area, thereby enabling the storage circuit to respond to the command execution operation faster and improving the response efficiency of the storage circuit.

[0076] Furthermore, when the second control circuit 320 converts the logical address to the physical address, it converts the logical address into a combination of the initial physical address and the address change command based on the operation type. This reduces the amount of information in the address command based on the operation type, thereby reducing the amount of transmission resources required when sending the address command and improving transmission efficiency.

[0077] In some embodiments of this application, the operation types of the storage circuit may include one or more operations such as in-memory computation, data reading, data writing, and erasing. In an in-memory computing system that supports in-memory computation, the operation types of the storage circuit may include operations such as in-memory computation, data reading, data writing, and erasing. In an in-memory computing system that supports near-memory computation, the operation types of the storage circuit may include operations such as data reading, data writing, and erasing; data reading may include a first type of reading and a second type of reading, wherein the data read by the first type can be used for near-memory computation, such as computation by a processing circuit integrated within a control device, which is integrated with the storage circuit to achieve more efficient data processing. The data read by the second type can be used for processing traditionally stored data, such as off-chip data processing of the chip where the storage circuit is located. The read rate of the first type is higher than the read rate of the second type. In some embodiments, the in-memory computing system may support both in-memory computation and near-memory computation.

[0078] In some possible embodiments, the first type of information is used to indicate in-memory computation, the first instruction further includes input data, the first command sequence further includes an input data command group, and the address change command group includes a first address change command group. The second control circuit 320 is also configured to convert the input data into an input data command group based on the first type of information, and to use the combination of the input data command group and the first address change command group to indicate the execution order of in-memory computation within the first storage region.

[0079] During in-memory computation, the control device 300 can send input data to the storage circuit and indicate the location of the weight data stored in the storage circuit that is being computed with the input data. This allows the storage circuit to perform computation with the input data based on the instructions of the control device 300, outputting the computation result. The second control circuit 320 simplifies the indication of the weight data location into an initial physical address and a first address change command group, and combines the input data command group and the first address change command group. Compared with the command sequence formed by combining specific physical address groups and input data command groups each time, this reduces the information content and length of the command sequence, thereby reducing the time required to send the command sequence during in-memory computation and improving the efficiency of in-memory computation.

[0080] In some possible embodiments, in-memory computation is performed on a per-computation-unit basis within the first storage region, and the address change commands in the first address change command group are used to indicate address changes of the computation units. The storage circuitry can be divided into multiple computation units, and depending on the computational requirements, in-memory computation can be implemented in one or more computation units, thus increasing the flexibility of in-memory computation and better adapting to the needs of different computational scales.

[0081] In some possible embodiments, the computing unit may include multiple computing sub-units to further increase the flexibility of in-memory computing. For example, in some possible embodiments, the first command sequence may also include an instruction command, which is used to instruct computing sub-units within the computing unit that do not participate in in-memory computing. That is, the second control circuit 320 can instruct the storage circuit to participate in and / or not participate in in-memory computing through the first command sequence, so that the resources of the storage circuit participating in in-memory computing can be flexibly configured to further adapt to the needs of different computing scales. Moreover, the setting of this command sequence helps the storage circuit to respond to command execution operations faster and improve the response efficiency of the storage circuit.

[0082] According to some embodiments, among the multiple computing subunits included in a computing unit, at least one computing subunit is used for backup; this backup computing subunit is called a backup unit. The backup unit can be statically or dynamically configured. Static configuration means that at least one fixed computing subunit among the multiple computing subunits is set as the backup unit; dynamic configuration means that the backup unit of the multiple computing subunits changes dynamically, for example, rotating as the backup unit. The backup unit can support data refresh of other computing subunits to improve the reliability of the weight data stored in the computing unit. For example, the weight data stored in the computing subunit currently to be refreshed can be refreshed into the backup unit, and the currently refreshed computing subunit can be used as the new backup unit. The storage state of the backup unit can be empty or can contain invalid data. Through the setting of the above instruction commands, computing subunits within the computing unit that do not participate in the calculation can be indicated. Thus, the backup unit can be instructed not to participate in in-memory calculation, preventing the backup unit from affecting the in-memory calculation.

[0083] Optionally, the first control circuit 310 can indicate to the second control circuit 320 the computational sub-units that do not participate in the calculation, and then the second control circuit 320 can indicate to the storage circuit the computational sub-units that do not participate in the calculation. Optionally, the second control circuit can determine the computational sub-units that do not participate in the calculation and indicate them to the storage circuit. For example, the first control circuit 310 can carry information indicating the backup unit in the first instruction. The second control circuit 320 can generate a first command sequence including the instruction command according to the first instruction. As another example, if the second control circuit 320 maintains or calls the information of the backup unit, it can generate a first command sequence of instruction commands based on the information of the backup unit.

[0084] According to some embodiments, the computing unit includes multiple computing sub-units that can correspond to different input data. To improve the reliability of in-memory computing, the input data is sparsely encoded. Therefore, among the multiple computing sub-units included in the computing unit, there may be at least one computing sub-unit whose input data consists of all "0"s. By instructing this at least one computing sub-unit not to participate in in-memory computing through the above method, the influence of the device noise of the computing sub-unit itself on the in-memory computing result can be reduced, that is, the amount of computation is reduced and the reliability of the calculation result is improved.

[0085] Optionally, the first control circuit 310 can indicate to the second control circuit 320 which computational sub-units do not participate in the calculation, and then the second control circuit 320 can indicate to the storage circuit which do not participate in the calculation. For example, the first control circuit 310 determines a computational sub-unit whose input data includes all "0"s and carries information indicating this computational sub-unit in a first instruction. The second control circuit 320 can generate a first command sequence including the indication command according to the first instruction. Optionally, the second control circuit 320 can determine the computational sub-units that do not participate in the calculation and indicate them to the storage circuit. For example, the second control circuit 320 can determine a computational sub-unit whose input data includes all "0"s according to the logical address information of the first instruction and the input data, and then generate an indication command.

[0086] According to some embodiments, the second control circuit 320 is also configured to generate a mask for processing input data on a per-computational-subunit basis. This allows for inputting all-zero data to computational subunits that are not involved in the computation, thereby reducing the impact of these subunits on other subunits and improving computational reliability.

[0087] In some possible embodiments, the first type of information is used to indicate data reading, and the address change command group includes a second address change command group, which is used to indicate the execution order of data reading within the first storage area. Optionally, the first control circuit 310 or the second control circuit 320 is also configured to control the operation of the output circuit 140. Optionally, the second control circuit 320 is also configured to control the reception or reading of data stored in the first storage area based on the second address change command group.

[0088] From the perspective of storage units, the number of storage units involved in data reading is much smaller than that involved in in-memory computation. Therefore, data reading requires sending a large amount of physical address information. Through the solution described in the above embodiments, the second control circuit 320 can simplify the originally large amount of physical address information into a second address change command group, thereby enabling faster data reading and improving data reading efficiency.

[0089] The above implementation is provided for ease of understanding and does not exclude other solutions. The above description uses the example of the first control circuit 310 being configured to generate and send a first instruction. This application does not limit the number of instructions that the first control circuit 310 can generate and send. That is, the first control circuit 310 can be configured to generate and send one or more instructions, and correspondingly, the second control circuit 320 can also be configured to receive and parse one or more instructions, thereby instructing the storage circuit to perform one or more operations. In other words, the first control circuit 310 can send various instructions to the second control circuit 320, each used to indicate different types of operations of the storage circuit.

[0090] For ease of description and understanding, this application uses the example of the first control circuit 310 being configured to generate and send the first and second instructions. Optionally, the first control circuit 310 may also generate and send the third or fourth instructions, etc., without limitation.

[0091] In one possible implementation, the first control circuit 310 is further configured to generate and send a second instruction, which instructs the storage circuit to perform a second operation. The second instruction includes second type information indicating the type of the second operation. The second control circuit 320 is further configured to receive and parse the second instruction, convert it into a second command sequence based on the second type information, and send the second command sequence to the storage circuit. Further, the second control circuit 320 is also configured to send the execution result of the second command sequence to the first control circuit.

[0092] According to some embodiments, the transmission of the second command sequence and the transmission of the first command sequence overlap in time. For example, the time domain resources occupied by transmitting the second command sequence partially or completely overlap with the time domain resources occupied by transmitting the first command sequence. For example, the second control circuit 320 can transmit the first command sequence in a first time period and transmit the second command sequence in a second time period, and the first time period includes the second time period. The start time of the second time period can be the same as or different from the start time of the first time period, and there is no limitation thereto.

[0093] In this way, the command transmission channel can be fully utilized to achieve efficient transmission of command sequences. For example, a portion of the first command sequence can be sent, and during the execution of the first operation corresponding to that portion of the command, a portion of the second command sequence can be sent using the command transmission channel. This can improve the utilization rate of channel resources, reduce the waiting time of subsequent first or second operations, and improve the efficiency of operation execution.

[0094] For example, a first command sequence may include multiple first command segments, which may be transmitted non-contiguously; for example, there may be a first gap between at least two first command segments. A second command sequence may include multiple second command segments, which may be transmitted non-contiguously; for example, there may be a second gap between at least two second command segments. At least one second command segment can be transmitted using the first gap; and / or at least one first command segment can be transmitted using the second gap. Thus, during the execution of the first operation corresponding to the first command segment, the second command segment can be transmitted using the command transmission channel, thereby improving the utilization of channel resources and reducing the waiting time for the second operation corresponding to subsequent second command segments, thus improving the efficiency of operation execution.

[0095] For a description of the second instruction and the second command sequence, please refer to the relevant descriptions of the first instruction and the first command sequence mentioned above. For the sake of brevity, they will not be described here.

[0096] Optionally, this application does not limit whether the types of the first operation and the second operation are the same. For example, the type of the first operation can be in-memory computation, and the type of the second operation can be data reading; or, the type of the first operation can be in-memory computation, and the type of the second operation can also be in-memory computation, etc., without limitation.

[0097] Optionally, this application does not limit the size (or length, or number of bits occupied) of the first command sequence and the second command sequence. For example, the sizes of the first command sequence and the second command sequence can be the same or different.

[0098] The following description uses a memory circuit that includes a three-dimensional array of memory cells.

[0099] Figure 4 A schematic diagram of a three-dimensional memory cell array in a memory circuit according to an exemplary embodiment of this application is shown. Figure 4 As shown, the three-dimensional spatial directions, including the X, Y, and Z directions, are used as examples. To facilitate storage resource management, the storage circuit 400 can be divided into multiple storage sets, for example, storage sets P1 to P2. s Where s represents the number of storage sets and is a positive integer greater than 1; for example, storage sets P1 to P2... s It can be arranged along the X direction. Storage set P u It can be further divided, for example, including multiple storage groups G u1 -G ug Where u∈[1,s], g represents the number of storage groups in a storage set, and is a positive integer greater than 1; for example, storage group G u1 -G ug Storage group G can be arranged along the Y direction.uv It can be further divided, for example, including multiple storage blocks B. uv1 -B uvt Where v∈[1,g], t represents the number of storage blocks in a storage group and is a positive integer greater than 1; for example, storage block B uv1 -B uvt Storage group G can be arranged along the Y direction. uv Including a multi-layer memory cell array A stacked along the Z direction uv1 -A uvw Where w represents the number of layers in the storage cell array and is a positive integer greater than 1. Storage cell array A uvr For example, consider a two-dimensional storage cell array, where r∈[1,w], and this storage cell array A... uvr It can include memory cells arranged in an array along the X and Y directions. Memory cell array A uvr It may include multiple storage pages arranged along the Y direction, and each storage page includes storage cells arranged along the X direction. The unit for reading data may include a storage page.

[0100] In the above embodiments, the X, Y, and Z directions are merely examples. In other embodiments, other coordinate systems may be used to identify the three-dimensional storage circuit. In some embodiments of this application, the stacking direction may be referred to as the first direction, which is, for example, a direction perpendicular to the chip substrate on which the storage circuit is located. For example, the first direction may be the Z direction in the above embodiments. The second and third directions are used, for example, to identify a two-dimensional plane perpendicular to the stacking direction, such as a plane parallel to the chip substrate on which the storage circuit is located. For example, the second direction may be the Y direction in the above embodiments, and the third direction may be the X direction in the above embodiments; or, the second direction may be the X direction in the above embodiments, and the third direction may be the Y direction in the above embodiments.

[0101] In some possible embodiments, the storage circuitry includes, but is not limited to, NAND flash memory; storage sets are referred to as Planes, storage groups as Banks, storage blocks as Blocks, and storage pages as Pages. This application is not limited thereto; storage circuitry with different three-dimensional structures may have different naming conventions, diversity schemes, or grouping methods, etc.

[0102] In some possible embodiments, memory cells at the same horizontal position within different layers of memory cell arrays can share input lines or input terminals, thus simplifying the routing of the memory circuitry. These memory cells are stacked in the Z direction, which can be referred to as a string of memory cells. For example, this string of memory cells can be connected in series, and any memory cell can be coupled to an input signal via a transistor at the top or bottom, which can be referred to as a switch. Optionally, the gate of the switch can be coupled to the input signal. In some possible embodiments, a single layer of memory cell array includes multiple groups of memory cells, and groups of memory cells at the same position in a second or third direction within different layers of memory cell arrays can share output lines or output terminals. The selection of memory cells can be implemented in the stacking direction via control lines (e.g., word lines).

[0103] According to some embodiments, the storage region may include one or more storage sets, or may include one or more storage groups. The first storage region described above is the storage region where the current instruction instructs the storage circuitry to perform an operation.

[0104] For example, a computing unit may include a storage set or storage group; a computing subunit may include a storage block. Address change commands can be used to indicate the manner or order of address changes of the storage cell arrays participating in the computation within the computing unit. For example, the storage cell arrays within the computing unit may participate in the computation sequentially in a first direction, or the storage cell arrays at positions indicated by the address change command in the first direction may participate in the computation. For example, the address change command in the first address change command group can be used to indicate that the address of the storage cell array within the computing unit changes by 1 unit in the Z direction. The storage cell array within the computing unit performs the computation in the Z direction according to the address change command.

[0105] During data writing, data writing can be performed in a one-dimensional array (e.g., page) within the storage area. The second address change command group can include second to fourth address change commands. The second address change command instructs the address of a storage page to change in the Y direction within the storage cell array Auvw, for example, by one unit. The third address change command instructs the address of a storage page to change to the address of a storage page within another storage block. For example, changing to the address of a storage page within a storage block adjacent in the Y direction. For example, changing to the initial address of the storage block or the initial address of the storage cell array within another storage block. The initial address of the storage block indicates, for example, the address of the storage page within the storage block closest to the origin of the coordinate system in the diagram. The initial address of the storage cell array indicates, for example, the address of the storage page within the storage cell array closest to the origin of the coordinate system in the diagram. The fourth address change command instructs the address of a storage page to change in the Z direction, for example, by one unit. The third address change command group, through the combination of the second to fourth address change commands, allows data reading to be performed sequentially within the first storage area.

[0106] During data retrieval, data can be read in a one-dimensional array (e.g., page) within the storage area. This application does not limit the order of data retrieval within the storage area of ​​the storage circuit. For example, assuming the storage area includes storage groups, the second address change command group can instruct the storage circuit to output data layer by layer in the first direction or block by block in the second direction, etc.

[0107] For example, a second address change command group can indicate a first read order, which includes outputting data layer by layer in a first direction (e.g., the Z direction), and storing page output data within a layer in a second direction (e.g., the Y direction); layer-by-layer or page-by-page output can include sequential output or output at indicated positions. As another example, a second address change command group can indicate a second read order, which includes outputting data block by memory in a second direction (e.g., the Y direction), outputting data layer by layer within a memory block in the first direction (e.g., the Z direction), and storing page output data within a layer in the second direction (e.g., the Y direction). Layer-by-layer or page-by-page output can include sequential output or output at indicated positions.

[0108] For example, the second address change command group includes a first command for indicating a change in the address of a one-dimensional array (e.g., a memory page) arranged along a third direction (e.g., the X direction), in a first direction, such as a change of 1 unit (layer) in the Z direction; the second address change command group also includes a second command for indicating a change in the memory block to which the one-dimensional array belongs, such as a change of 1 unit (one memory block) in the second direction. Optionally, the second address change command group may also include a third command for indicating a change in the address of the one-dimensional array in the second direction within a two-dimensional memory cell array (a layer of memory cell array within a memory group or a layer of memory cell array within a memory block), such as a change of 1 unit (one memory page). The second address change command group can perform data reading in the memory area in a first read order or a second read order by a combination of the first and second commands or a combination of the first and third commands. According to some embodiments, the second control circuit 320 is also configured to generate an enable command and send the enable command to the memory circuit, wherein the enable command is generated based on a first instruction or a third instruction. The first instruction is used to instruct the memory circuit to perform any of the above operations; the third instruction may also be referred to as an enable instruction. The first control circuit 310 is further configured to generate and send a third instruction, which instructs the storage circuit to open a target storage area; the second control circuit 320 is further configured to receive and parse the third instruction, convert the third instruction into an open command, and send the open command to the storage circuit.

[0109] For a memory region performing any of the above operations for the first time, preparatory work is required before the operation, such as activating word lines and establishing voltage. By preparing the memory region to be operated on in advance using the enable command, the memory region in the enabled or activated state can be prepared in advance, and when invoked, it is in a state of completed preparation, thus enabling a rapid response to subsequent different types of operations on the memory region.

[0110] According to some embodiments, the open command may include an identification command and an address command. The identification command can be used to identify that the command is used to open a target storage region, and the address command can be used to indicate the one or more target storage regions. The storage region may include a storage set, a storage group, or a storage block, etc., and this application is not limited thereto. Optionally, the open command may simultaneously indicate that the command is used to open a target storage region and the type of the target storage region. For example, the open command includes command 1 and command 2, where command 1 indicates to open a storage block, and command 2 indicates to open a storage group or storage set; or, for example, the open command includes command 1, command 2, and command 3, where command 1 indicates to open a storage block, command 2 indicates to open a storage group, and command 3 indicates to open a storage set. Optionally, the open command can be used to indicate that the command is used to open a target storage region; and the address command can be used to indicate the type of storage region. For example, the open command indicates to open a target storage region, and the address command indicates the address of the target storage region. If the address command points to the address of a storage block, the target storage region is a storage block; if the address command points to the address of a storage group or storage set, the target storage region is a storage group or storage set. Address commands may include addresses of various types of storage units, such as the address of a storage set, the address of a storage group, and the address of a storage block. The type of the target storage region can be specified using the smallest unit of storage. For example, an address command might include the address of storage set P3 and storage group G. 32 If the address is specified, the target storage region can include storage group G. 32 The target storage area is a storage group.

[0111] Before controlling the storage circuit to perform an operation, the first control circuit 310 or the second control circuit 320 can send an enable command or enable instruction to the storage circuit. For example, the storage group to be computed in memory can be enabled by the enable command or enable instruction before in-memory computation. Similarly, the storage block or storage group containing the storage page of the data to be read can be enabled by the enable command or enable instruction before data reading. This can improve operational efficiency. For example, when the data to be read is distributed across different storage blocks in a storage group, the enable command can be used to control the storage group to be in an enabled state, thereby reducing the latency when switching between different storage blocks within the storage group for data reading and improving data reading efficiency.

[0112] According to some embodiments, the target storage area includes a storage block, and the address command of the enable command includes the address of the storage block. Optionally, the address command of the enable command may also include an intra-block address, which is used to indicate a reference position within the storage block. This reference position may, for example, include a reference position in a first direction (e.g., the Z direction) or a second direction (e.g., the Y direction). For example, the intra-block address may include the address of a storage page or the address of a word line. For example, the intra-block address may indicate a storage page by its position, order, or number within the storage block. The intra-block address may indicate a layer within the block by the position, order, or number of a word line in the first direction. The intra-block address may be used to determine a reference storage page or a reference layer, which may be used as a reference for subsequent operations. For example, if the subsequent operation is a read, the read operation may start from the reference storage page.

[0113] According to some embodiments, when the address command of the enable command indicates multiple memory blocks, the intra-block addresses of the multiple blocks can be the same or reused. This reduces the execution complexity of the memory circuitry.

[0114] According to some embodiments, the target storage area may include a storage group, and the address command of the enable command may include the address of the storage group. Optionally, the storage group may include multiple storage blocks, and the enable command may enable some of the storage blocks, for example, by indicating which storage blocks are enabled or disabled through status indication information. For example, the storage group may include backup storage blocks, redundant storage blocks, or bad blocks, etc., and when enabling the storage group, the aforementioned backup storage blocks, redundant storage blocks, or bad blocks may not be enabled. Optionally, the address command of the enable command may also include an intra-group address, which is used to indicate a reference position within the storage group. This reference position may, for example, include a reference position in a first direction (e.g., the Z direction). For example, the intra-group address may include the address of a word line or the address of a storage page. For example, the intra-group address may indicate the layer within the group by the position, order, or number of the word line in the first direction. The intra-group address may indicate the layer where the storage page is located by the position, order, or number of the storage page within the storage group; the form of the intra-block address can reuse the form of the intra-block address in the command sequence for other purposes, reducing the use of address types, for example, reducing the use of layer addresses.

[0115] The address within a group can be used to determine the base level, which can then serve as the reference for subsequent operations. For example, if the subsequent operation is an in-memory computation, the in-memory computation operation can begin from the base level. Furthermore, by setting the base level, latency in switching word lines can be reduced in subsequent operations, or it can be used as the base word line in subsequent command sequences to indicate operations on memory pages or memory cell arrays corresponding to other word lines, thus simplifying the subsequent command sequences.

[0116] According to some embodiments, the operation types of the storage circuitry include data reading. When the opened storage area includes a storage group, the data reading methods can include intra-layer read, adjacent-layer read, and selected-layer read.

[0117] According to some embodiments, the identification command of the command sequence (e.g., the second command sequence) can identify the type of the current operation as data reading, and the data reading method as intra-layer read. Intra-layer read is used to select a storage page for reading within a layer in the first direction. The command sequence may also include a switch command to control the operating state of the switch transistors in the storage area during the data reading operation. The switch command can activate a set of switch transistors in the X direction within the storage group. Under the control of the activation command, the storage group is in an activated state, and the reference word line is activated. Thus, the set of switch transistors activated in the X direction and the reference word line can determine the storage page to be read. The switch command can work in conjunction with the reference word line to select a storage page for data reading. Therefore, by using the switch command to select a storage page, the latency of switching word lines can be eliminated when reading data from the storage page corresponding to the reference word line within the storage group, improving the efficiency of data reading.

[0118] According to some embodiments, the switching command may include a block selection command and a transistor selection command. The block selection command is used to indicate a memory block within a memory group, and the transistor selection command is used to indicate a switching transistor within a memory block. This two-level structure of block selection and transistor selection commands can optimize the indication method for selecting the transistor. According to some embodiments, at least one of the block selection and transistor selection commands may adopt a one-hot code form to improve the response speed of the memory circuit to the block selection and transistor selection commands.

[0119] According to some embodiments, multiple storage groups can be enabled, and each storage group can correspond to one power on / off command. Multiple power on / off commands can have a preset correspondence with multiple storage groups, thus implicitly indicating data reading from multiple storage groups through the order of the power on / off commands in the command sequence, improving command transmission efficiency. In other embodiments, data reading from multiple storage groups can also be explicitly indicated.

[0120] According to some embodiments, the identification command of the command sequence (e.g., the second command sequence) can identify that the current operation type is data read, and the data read method is adjacent layer read. Adjacent layer read is used to read memory pages in the adjacent layer of the base layer or the adjacent layer of the previous operation layer. The identification command can also be used to indicate that the active word line changes from the base word line or the previously active word line to an adjacent word line in the Z direction, for example, an adjacent word line in the +Z direction or an adjacent word line in the -Z direction. Thus, the identification command can indicate the word line corresponding to the operation, instead of using word line or layer address commands to implement adjacent layer read, simplifying the command sequence and improving control efficiency. The command sequence can also include a switch command, which, in conjunction with the identification command, selects a memory page for data reading. This command sequence can then be used to change the operation word line and read data, improving command efficiency and thus control efficiency.

[0121] According to some embodiments, the identification command of the command sequence (e.g., the second command sequence) can identify that the current operation is a data read and the data read method is a layer-selective read. The layer-selective read is used to select a layer in a first direction to read a storage page. For example, the command sequence may include an identification command, an address command, and a switch command. The address command may include a layer address or a block address, used to change the operation word line. The switch command is used in conjunction with the changed operation word line to select a storage page to read data. The identification command indicates that the layer-selective read command sequence can control the reading of data from any location of a storage page from the enabled storage group, thereby improving the flexibility of data reading.

[0122] In the control device 300 described above, a second control circuit 320 is integrated, serving as a bridge between the first control circuit 310 and the storage circuit. This reduces the complexity of the logic control section of the storage circuit, allowing more control components to be implemented within the control device 300. This provides the storage circuit with more physical space for functions such as storage or in-memory computation. Furthermore, it expands the types of operating states that the storage circuit can support, improving its operational flexibility. In addition, the second control circuit 320 converts the first instruction into a first command sequence corresponding to the first operation type, simplifying the complexity of the command sequence transmitted between the control device 300 and the storage circuit, thereby improving the reliability and compatibility of the in-memory computing system.

[0123] This application also provides a control method, which can be found in the embodiments described above. Figure 5 . Figure 5 A flowchart illustrating a control method according to an exemplary embodiment of this application is shown. Figure 5 As shown, the method may include the following steps.

[0124] S510, the first control circuit generates and sends a first instruction, which instructs the storage circuit to perform a first operation, and the first instruction includes first type information, which instructs the type of the first operation.

[0125] S520, the second control circuit receives and parses the first instruction, converts the first instruction into a first command sequence based on the first type information, and sends the first command sequence to the storage circuit.

[0126] In one implementation, after receiving the first command sequence, the storage circuit performs a first operation in a first storage area and obtains the execution result. Then, the storage circuit sends the execution result of the first command sequence to the second control circuit.

[0127] That is, in some embodiments of this application, the above control method may further include step S530, in which the second control circuit sends the execution result of the first command sequence to the first control circuit.

[0128] In one implementation, the storage circuit performs a first operation and obtains an execution result. The first control circuit receives the execution result of the first command sequence from the storage circuit. For example, the first control circuit directly receives the execution result of the first command sequence from the storage circuit.

[0129] For details regarding the first instruction, the first command sequence, and the different parsing and processing methods of the second control circuit for the first operation, please refer to the relevant descriptions above. For the sake of brevity, these will not be explained here.

[0130] In the above embodiments of this application, Figure 5 The method shown may also include other functions performed by the control device, as described above, and will not be repeated here.

[0131] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0132] Below, in conjunction with Figure 6 and Figure 7 The instruction processing flow of the in-memory computing integrated control device of some embodiments of this application is illustrated by example.

[0133] As an example, Figure 6 An in-memory computing flash controller (e.g., according to an exemplary embodiment of this application) is shown. Figure 3 The diagram shows the instruction processing flow of the second control circuit 320.

[0134] like Figure 6As shown, the second control circuit receives instructions from the upper layer (the first control circuit), performs error checking and correction on the instructions, parses the operation type and logical address from the instructions, converts the logical address into a physical address, and sends commands to the storage circuit (e.g., NAND flash) according to the operation type, such as store-read command, store-read command, store-write command, or store-erase command. After the operation is completed, the operation result is fed back to the upper layer.

[0135] In this instruction processing flow, the second control circuit has the function of parsing stored-in computation instructions. When the second control circuit recognizes a stored-in computation instruction, it parses the instruction and allocates the computation task to the storage-side computing unit, realizing the function of on-site computation and processing of data at the storage end. This reduces the time and resource consumption caused by data transmission between the control device and the storage circuit, improves the processing efficiency of the storage circuit, and further optimizes the instruction pipeline, enhancing the system's processing capabilities in scenarios such as big data analysis and artificial intelligence training. This provides efficient support for data storage and computation in various fields and is more suitable for the needs of the big data era.

[0136] The above-described store-and-read commands include, for example, the first command sequence described in the above embodiments. This first command sequence can control the storage circuit to perform in-memory calculations and output the calculation results. In this case, the data received by the control device can include the calculation results; therefore, the first command sequence can be called a store-and-read command. The store-read command can, for example, include the second command sequence described in the above embodiments. This second command sequence can control the data reading of the storage circuit; therefore, it can be called a store-read command. The store-write command is used for writing data, and the store-erase command is used for erasing data. For example, the unit of writing can include a storage page, and the unit of erasing can include a storage block.

[0137] As an example, Figure 7 An in-memory computing flash controller (e.g., according to an exemplary embodiment of this application) is shown. Figure 3 The schematic diagram of the instruction processing flow of the second control circuit 320 shown may include the following steps.

[0138] Step 1: The flash controller receives an instruction (e.g., the first instruction mentioned above), which may include a raw command. The raw command may include type information indicating the type of operation, such as in-memory computation, data read, data write, or data erase. The raw command may include, for example, an in-memory computation command, a read command, a write command, or an erase command. The instruction may also include a logical address (e.g., first logical address information) indicating the memory region (e.g., a first memory region) corresponding to the operation. Optionally, the flash controller may also receive data, which may include weight data and / or input data. For example, if the switching transistor is located at the top of a string of memory cells, the input data may include top select gate (TSG) data. The weight data is written to the memory region for in-memory computation.

[0139] Step 2: The flash controller checks the correctness of the received command. If the check passes, it proceeds to the next step; otherwise, if the check fails, the command processing flow is terminated.

[0140] Step 3: If the command check passes, the flash controller breaks down the command to convert the original command into a command sequence (e.g., first command sequence, second command sequence, etc.).

[0141] Step 4: The flash controller sends an address translation request to the logical-to-physical address translation (LDAP) module and determines whether the address translation is complete based on the response received from the module. If complete, proceed to the next step; otherwise, if incomplete, resend the address translation request to the LAP module until the address translation is complete. The LAP module can store a LAP translation table, which provides the flash controller with the mapping between logical addresses and physical addresses, allowing the flash controller to retrieve the physical address corresponding to the received logical address from the LAP translation table.

[0142] Step 5: The flash controller executes the corresponding process based on the different command types.

[0143] For example, command types include store-to-store read commands (also known as in-store compute commands), store-to-store read commands, store-to-store program commands, or store-to-store erase commands.

[0144] For example, for a read-write command, the flash controller sends the physical address of the sub-in-memory unit and input data (e.g., TSG-data). After each operation, it checks whether it is complete. If complete, it proceeds to the next step; otherwise, if incomplete, it checks again until the operation is complete, and then begins receiving data, including the result of the in-memory computation. Optionally, the flash controller can generate and send a mask, taking a block mask as an example, to process the input data, so that all "0"s are input to memory blocks that are not involved in the computation.

[0145] For example, for a read command, the flash controller can send the page physical address to determine the completion status of the operation. If the operation is complete, it proceeds to the next step; otherwise, if the operation is not complete, it re-determines the status until the operation is completed, and then starts receiving data.

[0146] For example, when storing a program command, the flash controller sends the page physical address and program-data (i.e., weight data). After each operation, it checks whether it is complete. If it is complete, it proceeds to the next step; otherwise, if it is not complete, it checks again until the operation is complete.

[0147] For example, for the storage erase command, the flash controller sends the block physical address to determine the completion status of the operation. If the operation is completed, it proceeds to the next step; otherwise, if the operation is not completed, it re-determines the status until the operation is completed.

[0148] Step 6: Check the completion status of command disassembly. If completed, proceed to the next step; otherwise, return to step 3 above.

[0149] Step 7: The flash controller generates and sends a response packet, at which point the instruction processing flow ends.

[0150] Based on the above solutions, the flash controller in this embodiment has instruction parsing capabilities with different original commands, enhancing the system's processing capabilities in different scenarios. This enables on-site computation at the storage end, reducing data transmission between storage and computing units and improving data processing efficiency. Furthermore, in key stages such as address translation and operation completion judgment, this embodiment can also set up retransmission or re-judgment mechanisms, improving the reliability of instruction processing, avoiding process interruptions due to occasional errors, and overall improving the performance and stability of the flash controller.

[0151] Regarding the in-memory computing scenarios mentioned above, as the number of stacking layers increases, the word lines shared between memory cells may exacerbate global leakage current issues. The following section provides relevant explanations on power management of block word lines for in-memory computing applications using 3D NAND.

[0152] As an example, Figure 8 A schematic diagram of a storage circuit is shown. For ease of understanding, in... Figure 8 The description of the storage bank has been omitted.

[0153] like Figure 8 As shown in the above embodiments, during in-memory computation, some blocks may not need to be activated, meaning one or more blocks in a plane can be inactive. For example, the second control circuit sends a first command sequence to the storage circuit, instructing the storage circuit to perform in-memory computation (i.e., the first operation) in plane 0 (i.e., the first storage region, including N computational sub-units), and the instruction carried in the first command sequence is used to instruct block 1 (i.e., the computational sub-unit) not to participate in in-memory computation. Therefore, block 1 can be inactive and not participate in in-memory computation. In this scenario, the wordline of the inactive block 1 can be managed, reducing additional power consumption and increasing the lifespan of the NAND flash memory. To address this, this application provides a storage circuit that integrates a dynamic power gating switch for the storage block. Through storage block wordline activation instructions, wordlines connecting multiple storage blocks can be locally activated and deactivated, thereby enabling deactivation of individual computational sub-units within the computational unit during in-memory computation, achieving fine-grained power management, and balancing power consumption and performance.

[0154] Reference Figure 9 This illustration shows a schematic diagram of the enable logic signal transmission path in a memory circuit according to an exemplary embodiment of this application. The enable logic signal is used to turn a word line on or off, thereby activating or deactivating the corresponding memory block. A command sequence may include the enable logic signal. Alternatively, the memory circuit may generate the enable logic signal based on an instruction command of the command sequence. The address decoder of the memory circuit activates the corresponding word line based on the address information determined based on the command sequence and the enable logic signal, for example, activating the computational subunit corresponding to the word line in the computational unit.

[0155] According to some embodiments, the enable logic signal can be transmitted through a through-silicon via (TSV), for example, through a logic layer within the memory circuit. Transmitting the signal via a high-speed TSV provides a low-latency control mechanism, enabling faster response times, such as microsecond-level response. Alternatively, the enable logic signal can pass through a PMOS (P-type metal-oxide-semiconductor) transistor and / or an NMOS (N-type metal-oxide-semiconductor) transistor during transmission to the address decoder. The PMOS transistor acts as a pull-up transistor, and the NMOS transistor acts as a pull-down transistor. However, the embodiments are not limited to this; the enable logic signal may not pass through a TSV, or it may be transmitted to the address decoder via other transmission paths.

[0156] This application does not limit the representation of the enable logic signal. For example, the enable logic signal can be represented in the form of a bitmap, where a bit "1" indicates participation in in-memory computation and a bit "0" indicates non-participation in in-memory computation. Figure 4 For example, suppose the control device instructs the storage circuit to access storage group G. uv Perform in-memory computation, t=9, bitmap=101111110, then compute subunit B. uv2 and B uv9 No activation is required. The storage circuitry can adjust the received input data based on the storage group G. uv The weight data stored in the memory cell array of the currently activated layer in other computational sub-units is multiplied and accumulated. For example, the enable logic signal may include the identifier or address of the computational sub-unit participating in the in-memory computation. Yet another example is that the enable logic signal may include the identifier or address of the computational sub-unit not participating in the in-memory computation, without limitation.

[0157] For example, in in-memory computing, an enable logic signal can be determined based on the input data to be processed, in order to identify and activate the memory block or word line to be enabled related to the in-memory computing. In this way, the enable logic signal can accurately control the opening of the word line, thereby efficiently cooperating with in-memory computing to achieve fast data processing and computation, improving computing efficiency and the performance of the in-memory computing system.

[0158] This application also provides another control device, which can be found in the embodiments described above. Figure 10 . Figure 10 A schematic diagram of a control device according to an exemplary embodiment of this application is shown. The control device includes units (or means) for implementing the above-described control method. For example... Figure 10As shown, the control device 1000 includes a generation unit 1010, a transceiver unit 1020, and a processing unit 1030. The generation unit 1010 generates a first instruction, which instructs a storage circuit to perform a first operation. The first instruction includes first type information indicating the type of the first operation. The transceiver unit 1020 sends the first instruction. The processing unit 1030 parses the first instruction and converts it into a first command sequence based on the first type information. The transceiver unit 1020 also sends the first command sequence and the execution result of the first command sequence.

[0159] Further description of the control device 1000 and its units can be found in the above embodiments.

[0160] It should be understood that the above division of units is only a logical functional division. In actual implementation, all or part of them can be integrated into a single physical entity, or they can be physically separated. Furthermore, the above units can be implemented in the form of a processor calling software; for example, a control device may include a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above control methods. The memory can be internal to the control device or external to it. Alternatively, the above units can be implemented in the form of hardware circuits. The functions of some or all units can be achieved through the design of the hardware circuits, which can be understood as one or more processing circuits. For example, in some embodiments, the hardware circuit may include an application-specific integrated circuit (ASIC), which implements the functions of some or all of the above units through the design of the logical relationships between the devices within the circuit. Furthermore, in some embodiments, the hardware circuit can be implemented using a programmable logic device (PLD) circuit, which may include a large number of logic devices. The logical relationships between the logic devices are configured through a configuration file, thereby achieving the functions of some or all of the above units. The above control devices can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0161] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, such as a central processing unit (CPU), microcontroller unit (MCU), graphics processing unit (GPU), or digital signal processor. Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), deep learning processing unit (DPU), etc.

[0162] In some possible embodiments, the units in the above control device may be integrated in whole or in part, or may be implemented independently. In some embodiments, these units are integrated together and implemented as a system on chip (SOC).

[0163] This application embodiment also provides a control device, which may be located in or include the above-mentioned control circuit, and the control device may be located in Figure 1 or Figure 2 The control circuit 120 / 220 shown, or independent of the control circuit 120 / 220. This control device can be used to execute any of the above control methods.

[0164] This application also provides another control device, which can be found in the embodiments described above. Figure 11 . Figure 11 A schematic diagram of another control device according to an exemplary embodiment of this application is shown. Figure 11As shown, the control device 1100 includes at least one processing circuit 1110 and an interface circuit 1120. The interface circuit 1120 is used to connect to the storage circuit via signals, and the at least one processing circuit 1110 is used to execute any of the control methods provided in the above embodiments.

[0165] This application also provides an in-memory computing system, which can be found in the embodiments described above. Figure 12 . Figure 12 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. Figure 12 As shown, the in-memory computing system 1200 includes: a control device 1220; and a storage circuit 1210 connected to the control device 1220, configured to receive a first command sequence sent by the control device 1220, and perform a first operation based on the first command sequence.

[0166] According to some embodiments, the control device 1220 may include a first control circuit 1221 and a second control circuit 1222. The first control circuit 1221 may be configured to generate and send a first instruction, which instructs the storage circuit 1210 to perform a first operation. The first instruction includes first type information indicating the type of the first operation. The second control circuit 1222 may be connected to the first control circuit 1221, configured to receive and parse the first instruction, convert the first instruction into a first command sequence based on the first type information, and send the first command sequence to the storage circuit 1210. In some possible embodiments, the second control circuit 1222 is further configured to send the execution result of the first command sequence to the first control circuit 1221.

[0167] In some possible embodiments, the storage circuitry is also configured to send the execution results of the first command sequence to the control device.

[0168] Further description of the storage circuit 1210 and the control device 1220 can be found in the above embodiments.

[0169] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0170] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0171] This application also provides an electronic device, which can be found in the embodiments described above. Figure 13 . Figure 13 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 13As shown, the electronic device 1300 may include any of the above-mentioned in-memory computing systems 1310 for processing data from the electronic device. The electronic device may also include an input / output device 1320 for receiving user input or outputting processing results. This application does not limit the input and output types; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 1330, which can process data provided to the in-memory computing system 1310 or process the output data of the in-memory computing system 1310. The output of the input / output device 1320 may be based on the output of the processor 1330 or the output of the in-memory computing system 1310.

[0172] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0173] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control device, characterized in that, include: A first control circuit is configured to generate and send a first instruction, the first instruction being used to instruct a storage circuit to perform a first operation, and the first instruction including first type information, the first type information being used to indicate the type of the first operation; A second control circuit, connected to the first control circuit, is configured to receive and parse the first instruction, convert the first instruction into a first command sequence based on the first type information, and send the first command sequence to the storage circuit.

2. The control device according to claim 1, characterized in that, The second control circuit is also configured to send the execution result of the first command sequence to the first control circuit.

3. The control device according to claim 1 or 2, characterized in that, The first command sequence includes an identification command and an address command. The identification command is used to identify the type of the first operation, and the address command is used to indicate the first storage area of ​​the first operation within the storage circuit.

4. The control device according to claim 3, characterized in that, The first instruction further includes first logical address information, which is used to indicate the first storage area, and the address command includes an initial address command and an address change command group; The second control circuit is further configured to generate the initial address command based on the first logical address information, the initial address command being used to indicate the starting address of the first operation unit of the first storage region; The second control circuit is further configured to generate the address change command group based on the first logical address information and the first type information. The address change command in the address change command group is used to indicate the address change of the first operation unit, and the address change command group is used to indicate the execution order of the first operation in the first storage area.

5. The control device according to any one of claims 1-4, characterized in that, The operation types of the storage circuit include in-memory computation, data reading, data writing, and erasure, wherein the first type information is used to indicate that the type of the first operation includes in-memory computation.

6. The control device according to claim 5, characterized in that, The first instruction further includes input data; the first command sequence further includes an input data command group; the address change command group includes a first address change command group; The second control circuit is further configured to convert the input data into the input data command group based on the first type of information, and to use the combination of the input data command group and the first address change command group to indicate the execution order of the in-memory calculation in the first storage area.

7. The control device according to claim 6, characterized in that, The in-memory computation is performed by computation unit within the first storage area, and the address change command in the first address change command group is used to indicate the address change of the computation unit.

8. The control device according to claim 7, characterized in that, The computing unit includes multiple computing sub-units, and the first command sequence further includes an instruction command, which is used to instruct computing sub-units within the computing unit that do not participate in the in-memory computation.

9. The control device according to claim 7, characterized in that, The computing unit includes multiple computing sub-units, and the second control circuit is further configured to generate a mask for processing the input data on a per-computational-sub-unit basis.

10. The control device according to any one of claims 1-4, characterized in that, The operation types of the storage circuit include in-memory computation, data reading, data writing, and erasing. The first type information is used to indicate the data reading. The address change command group includes a second address change command group, which is used to indicate the execution order of the data reading in the first storage area.

11. The control device according to any one of claims 1-10, characterized in that, The first control circuit is further configured to generate and send a second instruction, the second instruction being used to instruct the storage circuit to perform a second operation, and the second instruction including second type information, the second type information being used to indicate the type of the second operation; The second control circuit is also configured to receive and parse the second instruction, convert the second instruction into a second command sequence based on the second type information, and send the second command sequence to the storage circuit.

12. The control device according to claim 11, characterized in that, The transmission of the second command sequence overlaps with the transmission of the first command sequence in time.

13. The control device according to any one of claims 1-12, characterized in that, The second control circuit is also configured to generate an enable command and send the enable command to the storage circuit, wherein the enable command is generated based on the first instruction or the third instruction.

14. A control method, characterized in that, The method is applied to a control device, the control device including a first control circuit and a second control circuit, the second control circuit being connected to the first control circuit, and includes: The first control circuit generates and sends a first instruction, which instructs the storage circuit to perform a first operation, and the first instruction includes first type information, which instructs the storage circuit to perform a first operation. The second control circuit receives and parses the first instruction, converts the first instruction into a first command sequence based on the first type information, and sends the first command sequence to the storage circuit.

15. The control method according to claim 14, characterized in that, The method further includes: The second control circuit sends the execution result of the first command sequence to the first control circuit.

16. An in-memory computing system, characterized in that, include: The control device as described in any one of claims 1-13; A storage circuit, connected to the control device, is configured to receive a first command sequence sent by the control device and perform a first operation based on the first command sequence.

17. An electronic device, characterized in that, Including the in-memory computing system as described in claim 16.

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