Data processing apparatus, electronic components and computer devices

Abstract

The application provides a data processing device, an electronic component and a computer device, and belongs to the technical field of semiconductors. The device comprises a shared register group connected with a vector processor group, and a plurality of registers in the shared register group are shared by a plurality of vector processors in the vector processor group. After processing vector data in a data processing task, a vector processor in the vector processor group can write the result data obtained by processing into a register in the shared register group. Since the registers in the shared register group are shared by a plurality of vector processors, other vector processors needing to use the result data can directly read the result data from the shared register to use, so that the vector processor can quickly obtain the result data processed by other vector processors without moving the result data from the registers of other vector processors through a plurality of memories, thereby improving the data processing efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a data processing device, electronic components, and computer equipment. Background Technology

[0002] Electronic components typically have multiple vector processors for processing vector data. Each vector processor includes multiple registers to store data obtained during data processing. To complete the data processing task, the data in the registers of these vector processors may be exchanged, meaning that one vector processor may use data from the registers of another vector processor.

[0003] In related technologies, when one vector processor needs to use data in the registers of another vector processor, the data in the registers of the first vector processor is moved to the memory of the first vector processor, and then the data in that memory is moved to a memory shared by multiple vector processors. The second vector processor that needs to use the data reads the data from the shared memory into its own memory, and then loads the data from its own memory into its register. The second vector processor then retrieves the data from that register. This method results in a long data interaction chain, which in turn reduces data processing efficiency. Summary of the Invention

[0004] This application provides a data processing device, electronic components, and computer equipment, which improves data processing efficiency. The technical solution is as follows.

[0005] On one hand, a data processing apparatus is provided, the apparatus including a vector processor group and a shared register group, the vector processor group being connected to the shared register group, the vector processor group including a plurality of vector processors, and the shared register group including a plurality of registers;

[0006] The vector processor in the vector processor group is used to process the vector data in the data processing task, obtain the first result data, and write the first result data into the register in the shared register group.

[0007] The registers in the shared register group are used to receive and write the first result data obtained by the vector processor.

[0008] The vector processor in the vector processor group is also used to read the first result data written in the shared register group and process it to obtain the second result data.

[0009] In some embodiments, the shared register group further includes multiple status registers, one status register corresponding to one register, each status register being used to record the status information of the corresponding register, the status information being used to indicate whether the register is occupied;

[0010] The vector processor in the vector processor group is used to write the first result data into the target register when the status information in the target status register corresponding to the target register indicates that the target register is not occupied. The target register is a register in the shared register group indicated by the data processing task.

[0011] The vector processor in the vector processor group is further configured to read the first result data from the target register when the status information in the target status register indicates that the target register is occupied.

[0012] In some embodiments, the apparatus further includes a state update unit, which is connected to the plurality of state registers respectively;

[0013] The state update unit is used to update the state information in the target state register after reading and writing data to the target register.

[0014] In some embodiments, the apparatus further includes an interface module connected to each of the plurality of vector processors, and each interface module is also connected to the state update unit and the shared register group respectively;

[0015] The vector processor in the vector processor group is used to send a data access request to the interface module connected to the vector processor based on the data processing task.

[0016] The interface module is configured to receive the data access request, and when the data access request requests to write data into the shared register group, detect the status information in the target status register, and when the status information in the target status register indicates that the target register is not occupied, write the first result data into the target register and send an update instruction to the status update unit.

[0017] The interface module is also configured to, when the data access request is for requesting to read data in the shared register group, detect the status information in the target status register, and when the status information in the target status register indicates that the target register is occupied, read the first result data from the target register and send an update instruction to the status update unit;

[0018] The status update unit is used to receive the update instruction and update the status information in the target status register based on the update instruction.

[0019] In some embodiments, each interface module includes a detection unit, a setting unit, and a read / write unit. The detection unit and the read / write unit are respectively connected to the shared register group, and the setting unit is connected to the state update unit.

[0020] The detection unit is used to receive the data access request and detect the status information in the target status register based on the data access request;

[0021] The read / write unit is configured to write the first result data into the target register when the data access request requests to write data into the shared register group and the status information in the target status register indicates that the target register is not occupied.

[0022] The read / write unit is further configured to read the first result data from the target register when the data access request is for requesting to read data in the shared register group and the status information in the target status register indicates that the target register is occupied;

[0023] The set unit is used to send the update instruction to the status update unit after reading or writing data to the target register.

[0024] In some embodiments, the detection unit in each interface module is connected to the read / write unit and the set unit in the interface module, respectively.

[0025] The detection unit is configured to send a read / write signal to the read / write unit and a set signal to the set unit when the data access request requests to write data to the shared register group and the status information in the target status register indicates that the target register is not occupied. The read / write signal is used to indicate that the target register is available, and the set signal is used to indicate that the status information in the target status register is updatable.

[0026] The read / write unit is used to receive the read / write signal and write the first result data into the target register based on the read / write signal;

[0027] The setting unit is used to receive the setting signal and send the update instruction to the state update unit based on the setting signal.

[0028] In some embodiments, the detection unit in each interface module is connected to the read / write unit and the set unit in the interface module, respectively.

[0029] The detection unit is configured to send a read / write signal to the read / write unit and a set signal to the set unit when the data access request requests to read data from the shared register group and the status information in the target status register indicates that the target register is occupied. The read / write signal is used to indicate that the target register is available, and the set signal is used to indicate that the status information in the target status register is updatable.

[0030] The read / write unit is used to receive the read / write signal and read the first result data from the target register based on the read / write signal;

[0031] The setting unit is used to receive the setting signal and send the update instruction to the state update unit based on the setting signal.

[0032] In some embodiments, the vector processor in the vector processor group is configured to detect the state information in the target state register when the data processing task instructs the detection of state information in the target state register;

[0033] The vector processor in the vector processor group is further configured to update the status information in the target status register when the data processing task indicates that the status information in the target status register should be updated.

[0034] In some embodiments, each vector processor in the vector processor group includes a plurality of registers;

[0035] The vector processor in the vector processor group is further configured to read the vector data from the registers of the vector processor or the registers of the shared register group;

[0036] The vector processor in the vector processor group is further configured to write the second result data into a register in the vector processor or a register in the shared register group.

[0037] On the other hand, an electronic component is provided, which includes a data processing device, wherein the data processing device is the data processing device described in any of the above embodiments. When the electronic component is running on a computer device, it is used to implement the data processing process of the data processing device described in any of the above embodiments.

[0038] On the other hand, a computer device is provided, which includes the data processing apparatus in any of the above embodiments.

[0039] This application provides a data processing apparatus, which includes a shared register group connected to a vector processor group. Multiple registers in the shared register group are shared by multiple vector processors within the vector processor group. After processing vector data in a data processing task, a vector processor in the vector processor group can write the processed result data into registers in the shared register group. Since the registers in the shared register group are shared by multiple vector processors, other vector processors that need to use the result data can directly read the result data from the shared registers. This allows vector processors to quickly obtain the result data processed by other vector processors without having to move the result data from the registers of other vector processors through multiple memories, thus avoiding long-link data transmission processes and improving data processing efficiency. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0044] Figure 4 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0045] Figure 5 This is a schematic diagram of a data interaction provided in an embodiment of this application;

[0046] Figure 6 This is a schematic diagram of a data interaction provided in an embodiment of this application;

[0047] Figure 7 This is a block diagram of a terminal provided in an embodiment of this application;

[0048] Figure 8 This is a block diagram of a server provided in an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0050] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "n," nor are they limited in quantity or execution order.

[0051] In this application, the term "at least one" means one or more, and "multiple" means two or more.

[0052] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the data processing tasks involved in this application were all obtained under fully authorized conditions.

[0053] For ease of understanding, the terms used in this application are explained below.

[0054] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0055] Artificial intelligence (AI) is a comprehensive discipline encompassing a wide range of fields, including both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, pre-trained model technology, operating / interaction systems, and mechatronics. Among these, pre-trained models, also known as large models or foundational models, can be widely applied to downstream tasks across various AI fields after fine-tuning. AI software technologies mainly include computer vision, speech processing, natural language processing, and machine learning / deep learning. The instruction processing device provided in this application embodiment can be deployed within an AI chip, enabling the arrangement and execution of instructions that require cyclic execution.

[0056] Electronic components (such as chips) typically have multiple vector processors. When one vector processor needs to use data from the registers of another vector processor, the data in the registers of the first vector processor is moved to its own memory. Then, the data is moved from that memory to a shared memory used by multiple vector processors. The second vector processor that needs the data reads the data from the shared memory into its own memory, then loads the data from its own memory into its register, and finally retrieves the data from its register. This process results in a long data interaction chain, thus reducing data processing efficiency. To address this technical problem, this application provides a data processing device that can be deployed on a chip.

[0057] In this embodiment, the data processing apparatus includes a vector processor group and a shared register group. The vector processor group is connected to the shared register group. The vector processor group includes multiple vector processors, and the shared register group includes multiple registers.

[0058] For example, see Figure 1 , Figure 1 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application. The data processing apparatus includes a vector processor group 10 and a shared register group 20. The vector processor group 10 includes multiple vector processors 101, and the shared register group 20 includes multiple registers 201. The vector processor group 10 is connected to the shared register group 20, meaning that each vector processor 101 in the vector processor group 10 is connected to multiple registers 201 in the shared register group 20, so that these multiple registers 201 are shared by the multiple vector processors 101.

[0059] The number of vector processors in a vector processor group can be set and changed as needed. The number of registers in a shared register group can also be set and changed as needed. Furthermore, the data processing device can include multiple vector processor groups, with a separate shared register group for each vector processor group. For example, if the data processing device includes a large number of vector processors, these multiple vector processors can be divided into multiple vector processor groups, and then separate shared register groups can be set for each vector processor group, further improving the data processing efficiency of the vector processors.

[0060] First, let's introduce the vector processors in the vector processor group. The vector processors in the vector processor group are used to process the vector data in the data processing task, obtain the first result data, and write the first result data into the registers in the shared register group.

[0061] In this embodiment, the data processing task is used to process vector data, and the data processing task can be a data processing task in various scenarios. Optionally, the data processing task is a data processing task related to artificial intelligence. For example, the data processing task can be a data processing task in scenarios such as image recognition and human-computer dialogue. Furthermore, the data processing task can be a data processing task in a robot movement scenario, or a data processing task in a telephone conversation scenario; no specific limitation is made here.

[0062] In some embodiments, a data processing task includes multiple instructions, each of which performs a calculation on one step of vector data. The data processing task is based on these instructions to perform data processing. Multiple vector processors in a vector processor group receive these instructions and perform data processing based on them. The processing of one instruction may depend on the result of another instruction; that is, the vector data used by one vector processor may be the result data processed by another vector processor.

[0063] Each instruction carries multiple pieces of information, such as the identifier of the source register, the identifier of the result register, and the operation method. The vector register reads vector data from the source register and writes the processed result data into the result register. The source register and the result register are registers on the vector processor or registers in a shared register group. The identifier of the register carried by the instruction can be the register number. The operation method can be an algorithm such as addition, subtraction, multiplication, division, inversion, or square root calculation, etc., which is not limited in this embodiment. Therefore, the vector processor performs data processing based on instructions by reading vector data from the source register indicated by the instruction, processing the read vector data according to the operation method indicated by the instruction, and writing the processed result data into the result register indicated by the instruction.

[0064] Each vector processor in the vector processor group includes multiple registers. These registers can be vector registers used to store vector data. Similarly, the registers in the shared register group are also vector registers to store vector data for data processing tasks. When processing vector data, each vector processor in the vector processor group reads vector data from its own registers or registers in the shared register group for processing.

[0065] It should be noted that the result data processed by the vector processor is also vector data. The vector processor can write the result data not only to registers in the shared register set but also to its own registers. Each vector processor can only read data from its own registers and data from registers in the shared register set. Therefore, for each vector processor, if the result data is only used by that vector processor itself, it is written to its own register. If the result data is to be used by other vector processors, it is written to registers in the shared register set. Therefore, writing the first result data to a register in the shared register set indicates that the first result data will be used by other vector processors.

[0066] In this embodiment of the application, the registers in the shared register group are used to receive and write the first result data obtained by the vector processor.

[0067] The registers in the shared register set are shared by multiple vector processors in the vector processor set. That is, each vector processor can write data to the registers in the shared register set, and each vector processor can also read data from the registers in the shared register set.

[0068] In this embodiment of the application, the vector processor in the vector processor group is further configured to read the first result data written in the shared register group and process it to obtain the second result data.

[0069] In this context, the vector processor that reads the first result data and the vector processor that obtains the first result data can be different vector processors or the same vector processor. The vector processor that processes and obtains the first result data is defined as the first vector processor, and the vector processor that reads the first result data is defined as the second vector processor. The first vector processor and the second vector processor are different; that is, after a vector processor writes the processed result data into a shared register group, the result data can be directly read by any other vector processor in the vector processor group.

[0070] It should be noted that the instruction received by the vector processor can indicate one or more source registers. If there is only one source register, it can be a register of the vector processor itself or a register in a shared register set. If there are multiple source registers, all of them can be the vector processor's own registers, all can be registers in a shared register set, or a combination of both. For example, a vector processor in a vector processor group can read first result data from the shared register set while simultaneously reading vector data from its own registers. The vector processor then processes this first result data and the vector data to obtain second result data.

[0071] The second result data is vector data. The result register corresponding to the second result data can be a register in the vector processor or a register in the shared register group. Therefore, the vector processor in the vector processor group is also used to write the second result data into the register in the vector processor or the register in the shared register group.

[0072] In this embodiment, each vector processor can not only read data from its own registers for processing, but also read data from the shared register group for processing. Furthermore, it can not only write the processed result data to its own registers, but also to the registers in the shared register group. In this way, the result data used by the vector processor itself can be written to its own registers, while the result data used by other vector processors can be written to the shared registers. Moreover, the result data of other vector processors can be directly obtained from the shared registers, which improves the convenience and efficiency of data reading and writing during data processing, thereby improving data processing efficiency.

[0073] In some embodiments, the shared register set further includes multiple status registers, one status register corresponding to one register. Each status register records the status information of its corresponding register, indicating whether the register is occupied. Where one register in the shared register set corresponds to one status register, then one register and one status register constitute one entry in the shared register set. For example, if the shared register set includes 32 entries, each entry includes one register and one status register.

[0074] Accordingly, the vector processor in the vector processor group is used to write the first result data into the target register when the status information in the target status register corresponding to the target register indicates that the target register is not occupied. The target register is a register in the shared register group indicated by the data processing task.

[0075] The vector processor in the vector processor group is also used to read first result data from the target register when the status information in the target status register indicates that the target register is occupied.

[0076] The target register is a register in the shared register group indicated by the data processing task. When the vector processor receives an instruction to write data into the shared register group, the target register is also the result register indicated by the instruction. When the vector processor receives an instruction to read data from the shared register group, the target register is also the source register indicated by the instruction.

[0077] The target status register can contain either occupied or unoccupied status information. Occupied status information indicates that the target register is in use, while unoccupied status information indicates that the target register is not in use. Optionally, occupied status information is represented by the letter F, and unoccupied status information is represented by the letter E.

[0078] Specifically, if the vector processor receives an instruction to write data to the shared register set, the target status register will show an unoccupied status, making the target register available for writing data. Conversely, if the vector processor receives an instruction to read data from the shared register set, the target status register will show an occupied status, making the target register available for reading data.

[0079] In this embodiment, since multiple registers in the shared register group are shared by multiple vector processors, a status register is set for each register in the shared register group to record its status information. Data is read and written to the register only when the status register indicates that the register is available. This can avoid multiple vector processors reading and writing data to the same register at the same time, thereby reducing data conflicts and errors.

[0080] In some embodiments, the data processing apparatus further includes a status update unit, which is connected to a plurality of status registers respectively; the status update unit is used to update the status information in the target status register after reading or writing data to the target register.

[0081] The status update unit is connected to multiple status registers, meaning it updates the status information in these registers. For any register that has undergone data read / write operations, the status update unit updates the status information in the corresponding status register.

[0082] Specifically, after writing data to the target register, the status information in the target status register is updated to indicate that it is occupied. After reading data from the target register, the status information in the target status register is updated to indicate that it is unoccupied. It should be noted that after reading data from the register, the data in the register does not need to be deleted; subsequent data written can simply overwrite the data in the register.

[0083] For example, see Figure 2 , Figure 2 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application. The shared register group 20 includes a status register 202 corresponding to each shared register 201, and the apparatus also includes a status update unit 30, which is connected to the multiple status registers 202 respectively. Furthermore, the status update unit 30 is also connected to the vector processor group 10, and updates the status information in the status registers 202 based on instructions from the vector registers 101 in the vector processor group 10. Here, st0 to st31 each represent a status register.

[0084] In this embodiment, a status update unit is set to update the status information in the status register. After the vector processor reads or writes data to the register, the status update unit can update the status information in the corresponding status register in a timely manner. This makes it easier for other vector processors to continue to use the registers in the shared register group based on the indication of the status information, thereby improving data processing efficiency.

[0085] In some embodiments, the data processing task further indicates whether to detect status information in the target status register. Accordingly, the vector processor in the vector processor group is configured to detect the status information in the target status register when the data processing task indicates that the status information in the target status register should be detected.

[0086] The vector processor receives instructions from the data processing task. The instructions can also carry detection indication information to indicate whether to detect the status information in the target status register. The detection indication information can be represented by 0 and 1, where 1 indicates that the status information in the target status register is detected and 0 indicates that the status information in the target status register is not detected.

[0087] In this embodiment, to avoid conflicts arising from multiple vector processors using registers in a shared register set, the register status information is checked before accessing the registers in the shared register set. However, in some special cases, such as when a vector processor in a vector processor set writes data to a register in the shared register set for the first time at the beginning of data processing, there is no need to check the status of the registers in the shared register set since no data has been written to them at this time. Similarly, if the vector processor writing the result data to the register and the vector processor reading the result data from the register are the same vector processor, this vector processor determines that the result data has been written to the register upon receiving feedback that data has been written, and therefore there is no need to check the status of the register.

[0088] In this embodiment of the application, the data processing task also indicates whether to detect the status information in the status register. In this way, for cases where it is not necessary to detect status information, the number of status detections can be reduced through the indication of the data processing task, thereby saving resources and improving data processing efficiency.

[0089] In other embodiments, the data processing task further indicates whether to update the status information in the target status register, and accordingly, the vector processor in the vector processor group updates the status information in the target status register if the data processing task indicates that the status information in the target status register should be updated.

[0090] The vector processor receives instructions from the data processing task. These instructions can also carry update indication information, indicating whether to update the status information in the target status register. The update indication information can be represented by 0 and 1, where 1 indicates updating the status information in the target status register and 0 indicates not updating the status information in the target status register.

[0091] In this embodiment, to avoid conflicts when multiple vector processors use registers in a shared register set, the status information in the corresponding status register needs to be updated after accessing a register in the shared register set. However, in some special cases, such as when data in a register is read and the next vector register also needs to read data from that register, there is no need to update the status information in the relevant status register after that read, and therefore the status information in the relevant status register does not need to be updated.

[0092] In this embodiment, the data processing task also indicates whether to update the status information in the status register. In cases where there is no need to update the status information, the number of status updates can be reduced through the indication of the data processing task, saving resources and improving data processing efficiency. Furthermore, the data in the register that has not been updated can be reused multiple times, reducing the number of data calculations and transmissions, thereby improving data processing efficiency.

[0093] In some embodiments, the vector register group is connected to the shared register group through an interface module. That is, the device also includes an interface module to which multiple vector processors are connected, and each interface module is also connected to the state update unit and the shared register group respectively.

[0094] For example, see Figure 3 , Figure 3 This is a schematic diagram of a data processing apparatus provided in an embodiment of this application. The apparatus also includes multiple vector processors 101, each connected to an interface module 40, such as vector processor 0 connected to interface module 0, and vector processor 1 connected to interface module 1. Each interface module 40 is also connected to a state update unit 30 and a shared register group 20, respectively.

[0095] Accordingly, the vector processors in the vector processor group are used to send data access requests to the interface modules connected to the vector processors based on data processing tasks.

[0096] The interface module is used to receive data access requests. When the data access request requests to write data in the shared register group, it detects the status information in the target status register. If the status information in the target status register indicates that the target register is not occupied, it writes the first result data into the target register and sends an update instruction to the status update unit.

[0097] The interface module is used to detect the status information in the target status register when a data access request is made to read data from the shared register group, and to read the first result data from the target register and send an update instruction to the status update unit when the status information in the target status register indicates that the target register is occupied.

[0098] The status update unit is used to receive update instructions and update the status information in the target status register based on the update instructions.

[0099] In some embodiments, the vector processor includes an execution unit (exu). The vector processor reads data from registers or writes resulting data to registers through the execution unit. These registers can be the vector processor's own registers or registers in a shared register set. The vector processor can access registers through a multiplexer (mux) or pass data access requests to the interface module through the multiplexer. See, for example, further... Figure 3 .

[0100] The vector processor sends a data access request to the interface module based on the received instructions. The data access request requests read or write data to registers in the shared register set. The request includes the identifier of the target register and read / write type information, indicating whether the operation is a write or read operation. The read / write type information can be represented by the value 0 or 1, where 0 represents a read operation and 1 represents a write operation. A read / write type of 1 indicates a request to write data to the shared register set, while a read / write type of 0 indicates a request to read data from the shared register set.

[0101] In some embodiments, the data access request also carries identification information of the registers in the shared register set to be accessed, and the interface module determines the registers to be accessed based on the identification information. Further, when the data access request is used to request writing data to the shared register set, the data access request also carries the data to be written, i.e., it carries first result data, and the read / write unit writes the first result data carried by the data access request into the target register.

[0102] In some embodiments, the data access request also carries detection indication information to indicate whether to detect the status information in the target status register. The data access request also carries update indication information to indicate whether to update the status information in the target status register.

[0103] In some embodiments, the read / write unit includes a write subunit and a read subunit. The write subunit is used to write data into the shared register set, that is, the write subunit is used to write first result data into the target register. The read subunit is used to read data from the shared register set, that is, the read subunit is used to read the first result data from the target register.

[0104] In this embodiment, a dedicated interface module is set up for each vector processor to handle the vector processor's data access requests to the shared register set. This allows the vector processor to execute vector instructions more efficiently, reduces the amount of data exchange between the shared register set and the vector processor, reduces the power consumption and design complexity of the vector processor, and improves the efficiency of data interaction between the vector processor and the shared register set.

[0105] In this embodiment, the update instruction is used to instruct the updating of status information in the target status register. The update instruction carries identification information of the target status register, such as the target status register number. The update instruction may also carry the target status information to be updated in the target status register.

[0106] In this embodiment of the application, in order to more clearly describe the process of the interface module processing data access requests, the structure of the interface module is further introduced.

[0107] In some embodiments, each interface module includes a detection unit, a set unit, and a read / write unit. The detection unit and the read / write unit are respectively connected to a shared register group, and the set unit is connected to a state update unit. For example, see... Figure 4 , Figure 4 This is a schematic diagram of a data processing device provided in an embodiment of this application. The interface module 40 includes a detection unit 401, a setting unit 402, and a read / write unit 403. The detection unit 401 and the read / write unit 403 are respectively connected to the shared register group 20, and the setting unit 402 is connected to the status update unit 30.

[0108] The detection unit is used to receive data access requests and detect the status information in the target status register based on the data access requests.

[0109] The read / write unit is used to write the first result data into the target register when a data access request is made to request the writing of data in the shared register group and the status information in the target status register indicates that the target register is not occupied.

[0110] The read / write unit is also used to read first result data from the target register when a data access request is made to request the reading of data in the shared register group and the status information in the target status register indicates that the target register is occupied.

[0111] The set unit is used to send an update instruction to the status update unit after reading or writing data to the target register.

[0112] In this embodiment, the interface module includes multiple functional units, which respectively perform status detection, data reading and writing, and status updates. Since different tasks often have different computational requirements, dividing the interface module into multiple functional units allows each unit to be optimized for a specific task, thereby improving overall data processing efficiency. Furthermore, multiple functional units can process different types of tasks simultaneously, enabling parallel execution of tasks and further improving processing efficiency.

[0113] In some embodiments, the detection unit in each interface module is connected to the read / write unit and the set unit in the interface module, respectively. For the case where the data access request is used to request the writing of data into the shared register group, the functions of each unit in the interface module are as follows.

[0114] The detection unit is used to send a read / write signal to the read / write unit and a set signal to the set unit when a data access request is made to request writing data in the shared register group and the status information in the target status register indicates that the target register is not occupied. The read / write signal is used to indicate that the target register is available and the set signal is used to indicate that the status information in the target status register can be updated.

[0115] The read / write unit is used to receive read / write signals and write the first result data into the target register based on the read / write signals.

[0116] The set unit is used to receive the set signal and send an update command to the status update unit based on the set signal.

[0117] In this system, the read / write signal can be represented by the value 1, indicating that the target register is available. Upon receiving a read / write signal of value 1, the read / write unit writes the first result data into the target register. Conversely, if a data access request is used to request writing data into the shared register group and the status information in the target status register indicates that the target register is occupied, the detection unit also sends a non-read / write signal to the read / write unit. This non-read / write signal is represented by the value 0, indicating that the target register is unavailable. Upon receiving a non-read / write signal of value 0, the read / write unit needs to wait while the detection unit continuously monitors the status information in the target status register until the status information in the target status register indicates that the target register is not occupied, and only then, upon receiving the read / write signal, does the first result data write into the target register.

[0118] The set signal can be represented by the value 1, indicating that the status information in the status register is updatable. Upon receiving a set signal of 1, the set unit sends an update instruction to the status update unit. When a data access request is used to request writing data to the shared register group and the status information in the target status register indicates that the target register is occupied, the detection unit also sends a non-settable signal to the set unit. The non-settable signal is represented by the value 0, indicating that the status information in the target status register is not updatable. Upon receiving a non-settable signal of 0, the set unit needs to wait until the status information in the target status register indicates that the target register is not occupied, and only then, upon receiving a set signal, does it send an update instruction to the status update unit.

[0119] In this embodiment, when a request is made to write data to the target register, the status information in the target status register indicates that the target register is not occupied, which means that the target register is available and data can be written to it. At this time, the detection unit not only sends a read / write signal to the read / write unit to indicate that data should be written, but also sends a set signal to the set unit to indicate that the status information should be updated. This allows the data writing operation and the status update operation to be performed synchronously. That is, while writing data to the target register, the status information in the target status register is updated simultaneously, which shortens the time consumption and improves efficiency.

[0120] In other embodiments, for cases where a data access request is used to request the reading of data from a shared register set, the functions of each unit in the interface module are as follows.

[0121] The detection unit is used to send a read / write signal to the read / write unit and a set signal to the set unit when a data access request is made to read data from the shared register group and the status information in the target status register indicates that the target register is occupied. The read / write signal is used to indicate that the target register is available and the set signal is used to indicate that the status information in the target status register can be updated.

[0122] The read / write unit is used to receive read / write signals and read the first result data from the target register based on the read / write signals;

[0123] The set unit is used to receive the set signal and send an update command to the status update unit based on the set signal.

[0124] Specifically, when a data access request is made to read data from the shared register group and the status information in the target status register indicates that the target register is not occupied, the detection unit also sends a non-read / write signal to the read / write unit. Upon receiving the non-read / write signal, the read / write unit needs to wait while the detection unit continuously monitors the status information in the target status register until the status information in the target status register indicates that the target register is occupied, and only then, upon receiving the read / write signal, does it read the first result data from the target register.

[0125] Specifically, when a data access request is made to read data from the shared register group and the status information in the target status register indicates that the target register is not occupied, the detection unit is also used to send a non-settable signal to the set unit. Upon receiving the non-settable signal, the set unit needs to wait while the detection unit continuously monitors the status information in the target status register until the status information in the target status register indicates that the target register is occupied, and only then, upon receiving the set signal, does it send an update instruction to the status update unit.

[0126] In this embodiment, when a request is made to read data from the target register, the status information in the target status register indicates that the target register is occupied, which means that the target register is available and data can be read from it. At this time, the detection unit not only sends a read / write signal to the read / write unit to indicate that data should be read, but also sends a set signal to the set unit to indicate that the status information should be updated. This allows the data reading operation and the status update operation to be performed synchronously. That is, while reading data from the target register, the status information in the status register is updated simultaneously, which shortens the time consumption and improves efficiency.

[0127] For example, see Figure 5 , Figure 5 This is a data interaction diagram provided in an embodiment of this application. The example illustrates data interaction between two vector processors in a vector processor group, defined as a first vector processor and a second vector processor. st0 to st31 represent status registers in the shared register group, and svr0 to svr31 represent vector registers in the shared register group. The first vector processor receives a first instruction from the data processing task, instructing it to perform an addition operation. The vector data for the calculation originates from registers vr3 and vr4 in the first vector processor, and the register to be written is register svr1 in the shared register group. The second vector processor receives a second instruction from the data processing task, executed after the first instruction. The second instruction also instructs it to perform an addition operation, with the calculated vector data originating from register svr1 in the shared register group and register vr2 in the second vector processor. In other words, the result data of the first instruction is part of the source operand of the second instruction, indicating data interaction between the two vector processors. In the initial state T0, the status information in the status registers is all unoccupied (E), meaning that none of the shared registers in the shared register group are occupied. Therefore, the detection indication information check_en carried by the first instruction is 0, which means that register SVR1 can be accessed directly without checking the status information in the status register st1 corresponding to register SVR1. The first vector processor completes the access to register SVR1 based on the first instruction, that is, it writes the calculated result data 0x1234 into register SVR1. Since the update indication information set_en carried by the first instruction is 1, the status information in status register st1 also needs to be updated to occupied (F), and enters state T1. The detection indication information check_en of the second instruction is 1, which means that the status information in status register st1 needs to be checked. If the status information in status register st1 is detected as F, a data read operation is performed on register SVR1. Since the update indication information set_en of the second instruction is 1, the status information in status register st1 also needs to be updated to E, and enters state T2.

[0128] See Figure 6 , Figure 6 This is a schematic diagram of data interaction provided in an embodiment of this application. A first vector processor receives a first instruction from a data processing task, instructing it to perform an addition operation. The vector data for the calculation originates from registers vr3 and vr4 in the first vector processor, and the register to be written is register svr1 in the shared register set. A second vector processor receives a second instruction from the data processing task, instructing it to perform an addition operation. The vector data for the calculation originates from register svr1 in the shared register set and register vr2 in the second vector processor. The first vector processor also receives a third instruction from the data processing task, instructing it to perform an addition operation. The vector data for the calculation originates from registers vr5 and vr6 in the first vector processor, and the register to be written is register svr1 in the shared register set. The second vector processor also receives a fourth instruction from the data processing task, instructing it to perform an addition operation. The vector data for the calculation originates from register svr1 in the shared register set and register vr3 in the second vector processor. The first, second, third, and fourth instructions are executed sequentially; that is, the result data of the first instruction is part of the source operands of the second instruction, and the result data of the third instruction is part of the source operands of the fourth instruction. The execution process of the first and second instructions is similar to... Figure 5 The execution process is similar and will not be elaborated here. For the third and fourth instructions, the third instruction carries a detection indication information check_en = 1, which means that the status information in the status register st1 needs to be checked. If the status information in the status register st1 is detected as E, the first vector processor completes the access to the register svr1 based on the third instruction, that is, writes the calculated result data 0x5678 into the register svr1. Since the third instruction carries an update indication information set_en = 1, the status information in the status register st1 also needs to be updated to F, entering the T3 state. The fourth instruction carries a detection indication information check_en = 1, which means that the status information in the status register st1 needs to be checked. If the status information in the status register st1 is detected as F, the second vector processor performs a data read operation on the register svr1. And since the fourth instruction carries an update indication information set_en = 1, the status information in the status register st1 also needs to be updated to E, entering the T4 state. Through the above... Figure 5 and Figure 6 As the example shows, relatively complex data synchronization operations between vector processors can be accomplished through synchronized status registers.

[0129] The data processing apparatus provided in this application introduces a shared register set among multiple vector processors. Each vector processor can access the shared register set via microinstructions, just like accessing its own vector registers. Communication between vector processors only requires passing through this single shared register set level to complete data exchange. Furthermore, each shared register in the shared register set is equipped with a synchronization status register for instruction synchronization, significantly reducing data exchange latency and improving data processing performance. In the field of AI processors, communication performance between multiple vector processors is crucial. The shared register set design provided in this application reduces the number of data exchange links between vector processors, accelerating communication efficiency, thereby reducing communication latency and power consumption during data exchange, resulting in higher performance.

[0130] It should be noted that the data processing apparatus provided in this application embodiment can be applied not only to vector processors, but also to other processors, such as scalar processors, thereby setting up multiple shared scalar registers for multiple scalar processors, without specific limitations here.

[0131] This application provides a data processing apparatus, which includes a shared register group connected to a vector processor group. Multiple registers in the shared register group are shared by multiple vector processors within the vector processor group. After processing vector data in a data processing task, a vector processor in the vector processor group can write the processed result data into registers in the shared register group. Since the registers in the shared register group are shared by multiple vector processors, other vector processors that need to use the result data can directly read the result data from the shared registers. This allows vector processors to quickly obtain the result data processed by other vector processors without having to move the result data from the registers of other vector processors through multiple memories, thus avoiding long-link data transmission processes and improving data processing efficiency.

[0132] In this embodiment, the data processing device described above can be deployed in any computer device. The computer device can be configured as a terminal or a server. When the computer device is configured as a terminal, the terminal can act as the executing entity to control the data processing device provided in this embodiment to process data. When the computer device is configured as a server, the server can act as the executing entity to control the data processing device provided in this embodiment to process data. This embodiment does not limit the scope of the application.

[0133] Figure 7 A structural block diagram of a terminal 700 provided in an exemplary embodiment of this application is shown.

[0134] Typically, terminal 700 includes a processor 701 and a memory 702.

[0135] Processor 701 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 701 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 701 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 701 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 701 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning. This processor may be a vector processor in the data processing apparatus described in any of the above embodiments.

[0136] The memory 702 may include one or more computer-readable storage media, which may be non-transitory. The memory 702 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 702 are used to store at least one program code.

[0137] In some embodiments, the terminal 700 may also optionally include a peripheral device interface 703 and at least one peripheral device. The processor 701, memory 702, and peripheral device interface 703 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 703 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: a radio frequency circuit 704, a display screen 705, a camera assembly 706, an audio circuit 707, and a power supply 708.

[0138] Peripheral device interface 703 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 701 and memory 702. In some embodiments, processor 701, memory 702 and peripheral device interface 703 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 701, memory 702 and peripheral device interface 703 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0139] The radio frequency (RF) circuit 704 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 704 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 704 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 704 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 704 can communicate with other terminals through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 704 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0140] Display screen 705 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 705 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 701 for processing. In this case, display screen 705 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 705, disposed on the front panel of terminal 700; in other embodiments, there may be at least two display screens 705, disposed on different surfaces of terminal 700 or in a folded design; in other embodiments, display screen 705 may be a flexible display screen, disposed on a curved or folded surface of terminal 700. Furthermore, display screen 705 may be configured as a non-rectangular irregular shape, i.e., a non-rectangular screen. Display screen 705 may be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0141] The camera assembly 706 is used to acquire images or videos. Optionally, the camera assembly 706 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 706 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0142] The audio circuit 707 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 701 for processing, or input to the radio frequency circuit 704 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each located at a different part of the terminal 700. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert the electrical signals from the processor 701 or the radio frequency circuit 704 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 707 may also include a headphone jack.

[0143] Power supply 708 is used to power the various components in terminal 700. Power supply 708 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 708 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, while a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0144] In some embodiments, the terminal 700 further includes one or more sensors 709. The one or more sensors 709 include, but are not limited to: an accelerometer 710, a gyroscope 711, a pressure sensor 712, an optical sensor 713, and a proximity sensor 714.

[0145] Accelerometer 710 can detect the magnitude of acceleration along the three coordinate axes of a coordinate system established by terminal 700. For example, accelerometer 710 can be used to detect the components of gravitational acceleration along the three coordinate axes. Processor 701 can control display screen 705 to display the user interface in either a landscape or portrait view based on the gravitational acceleration signal acquired by accelerometer 710. Accelerometer 710 can also be used for games or for acquiring user motion data.

[0146] The gyroscope sensor 711 can detect the orientation and rotation angle of the terminal 700. The gyroscope sensor 711, in conjunction with the accelerometer sensor 710, can collect 3D motion data from the user on the terminal 700. Based on the data collected by the gyroscope sensor 711, the processor 701 can perform the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0147] The pressure sensor 712 can be disposed on the side bezel of the terminal 700 and / or the lower layer of the display screen 705. When the pressure sensor 712 is disposed on the side bezel of the terminal 700, it can detect the user's grip signal on the terminal 700, and the processor 701 can perform left / right hand recognition or quick operation based on the grip signal collected by the pressure sensor 712. When the pressure sensor 712 is disposed on the lower layer of the display screen 705, the processor 701 can control the operable controls on the UI interface based on the user's pressure operation on the display screen 705. The operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0148] An optical sensor 713 is used to collect ambient light intensity. In one embodiment, the processor 701 can control the display brightness of the display screen 705 based on the ambient light intensity collected by the optical sensor 713. Specifically, when the ambient light intensity is high, the display brightness of the display screen 705 is increased; when the ambient light intensity is low, the display brightness of the display screen 705 is decreased. In another embodiment, the processor 701 can also dynamically adjust the shooting parameters of the camera assembly 706 based on the ambient light intensity collected by the optical sensor 713.

[0149] The proximity sensor 714, also known as a distance sensor, is typically located on the front panel of the terminal 700. The proximity sensor 714 is used to detect the distance between the user and the front of the terminal 700. In one embodiment, when the proximity sensor 714 detects that the distance between the user and the front of the terminal 700 is gradually decreasing, the processor 701 controls the display screen 705 to switch from a screen-on state to a screen-off state; when the proximity sensor 714 detects that the distance between the user and the front of the terminal 700 is gradually increasing, the processor 701 controls the display screen 705 to switch from a screen-off state to a screen-on state.

[0150] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on terminal 700, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0151] Figure 8This is a schematic diagram of a server structure according to an embodiment of this application. The server 800 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 801 and one or more memories 802. The memories 802 are used to store executable program code, and the processors 801 are configured to execute the executable program code to process data using the data processing device described in any of the above embodiments. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated here.

[0152] This application also provides an electronic component, which includes a data processing device. The data processing device is any of the data processing devices described in the above embodiments. When the electronic component is running on a computer device, it is used to implement the data processing process performed by the data processing device as described in any of the above embodiments. The electronic component may be a chip.

[0153] This application also provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor of a computer device to perform the operations performed by the computer device in the above embodiments. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0154] In some embodiments, the computer program involved in the present application may be deployed and executed on a computer device, or on multiple computer devices located in one location, or on multiple computer devices distributed in multiple locations and interconnected through a communication network.

[0155] This application also provides a computer program product, including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, enabling the computer device to process data using the data processing apparatus described in any of the above embodiments.

[0156] All the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here. The above are only optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing apparatus, characterized in that, The device includes a vector processor group and a shared register group, the vector processor group being connected to the shared register group, the vector processor group including multiple vector processors, and the shared register group including multiple registers; The vector processor in the vector processor group is used to process the vector data in the data processing task, obtain the first result data, and write the first result data into the register in the shared register group. The registers in the shared register group are used to receive and write the first result data obtained by the vector processor. The vector processor in the vector processor group is also used to read the first result data written in the shared register group and process it to obtain the second result data.

2. The apparatus according to claim 1, characterized in that, The shared register group also includes multiple status registers, one status register corresponds to one register, and each status register is used to record the status information of the corresponding register. The status information is used to indicate whether the register is occupied. The vector processor in the vector processor group is used to write the first result data into the target register when the status information in the target status register corresponding to the target register indicates that the target register is not occupied. The target register is a register in the shared register group indicated by the data processing task. The vector processor in the vector processor group is further configured to read the first result data from the target register when the status information in the target status register indicates that the target register is occupied.

3. The apparatus according to claim 2, characterized in that, The device further includes a state update unit, which is connected to the plurality of state registers respectively; The state update unit is used to update the state information in the target state register after reading and writing data to the target register.

4. The apparatus according to claim 3, characterized in that, The device also includes an interface module connected to each of the plurality of vector processors, and each interface module is also connected to the state update unit and the shared register group respectively. The vector processor in the vector processor group is used to send a data access request to the interface module connected to the vector processor based on the data processing task. The interface module is configured to receive the data access request, and when the data access request requests to write data into the shared register group, detect the status information in the target status register, and when the status information in the target status register indicates that the target register is not occupied, write the first result data into the target register and send an update instruction to the status update unit. The interface module is also configured to, when the data access request is for requesting to read data in the shared register group, detect the status information in the target status register, and when the status information in the target status register indicates that the target register is occupied, read the first result data from the target register and send an update instruction to the status update unit; The status update unit is used to receive the update instruction and update the status information in the target status register based on the update instruction.

5. The apparatus according to claim 4, characterized in that, Each interface module includes a detection unit, a setting unit, and a read / write unit. The detection unit and the read / write unit are respectively connected to the shared register group, and the setting unit is connected to the state update unit. The detection unit is used to receive the data access request and detect the status information in the target status register based on the data access request; The read / write unit is configured to write the first result data into the target register when the data access request requests to write data into the shared register group and the status information in the target status register indicates that the target register is not occupied. The read / write unit is further configured to read the first result data from the target register when the data access request is for requesting to read data in the shared register group and the status information in the target status register indicates that the target register is occupied; The set unit is used to send the update instruction to the status update unit after reading or writing data to the target register.

6. The apparatus according to claim 5, characterized in that, The detection unit in each interface module is connected to the read / write unit and the set unit in the interface module, respectively. The detection unit is configured to send a read / write signal to the read / write unit and a set signal to the set unit when the data access request requests to write data to the shared register group and the status information in the target status register indicates that the target register is not occupied. The read / write signal is used to indicate that the target register is available, and the set signal is used to indicate that the status information in the target status register is updatable. The read / write unit is used to receive the read / write signal and write the first result data into the target register based on the read / write signal; The setting unit is used to receive the setting signal and send the update instruction to the state update unit based on the setting signal.

7. The apparatus according to claim 5, characterized in that, The detection unit in each interface module is connected to the read / write unit and the set unit in the interface module, respectively. The detection unit is configured to send a read / write signal to the read / write unit and a set signal to the set unit when the data access request requests to read data from the shared register group and the status information in the target status register indicates that the target register is occupied. The read / write signal is used to indicate that the target register is available, and the set signal is used to indicate that the status information in the target status register is updatable. The read / write unit is used to receive the read / write signal and read the first result data from the target register based on the read / write signal; The setting unit is used to receive the setting signal and send the update instruction to the state update unit based on the setting signal.

8. The apparatus according to claim 3, characterized in that, The vector processor in the vector processor group is used to detect the status information in the target status register when the data processing task indicates that the status information in the target status register should be detected. The vector processor in the vector processor group is further configured to update the status information in the target status register when the data processing task indicates that the status information in the target status register should be updated.

9. The apparatus according to claim 1, characterized in that, Each vector processor in the vector processor group includes multiple registers; The vector processor in the vector processor group is further configured to read the vector data from the registers of the vector processor or the registers of the shared register group; The vector processor in the vector processor group is further configured to write the second result data into a register in the vector processor or a register in the shared register group.

10. An electronic component, characterized in that, The electronic component includes a data processing device, which is the data processing device according to any one of claims 1 to 9. When the electronic component is running on a computer device, it is used to implement the data processing process of the data processing device according to any one of claims 1 to 9.

11. A computer device, characterized in that, The computer device includes a data processing apparatus as described in any one of claims 1 to 9.

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