A method and device for regulating instruction security check in a multi-instruction concurrent scenario

Abstract

The application provides a method and device for regulating and checking instruction safety in a multi-instruction concurrent scenario, comprising: identifying the intersection range of subgraph nodes between any two switch opening and closing instructions according to the subgraph set, evaluating the overlap area proportion in the intersection using a graph theory algorithm, and determining whether the two switch opening and closing instructions are a high overlap risk instruction pair according to the overlap area proportion; for the high overlap risk instruction pair, extracting the equivalent injection power direction of each node in the intersection range from the real-time operation section of the power grid, mapping it as a positive or negative polarity label, and constructing a polarity distribution vector; adjusting the switching conditions of parallel and serial according to the dynamically adjustable parallel and serial of the parallel release instruction pair and the serial dependent execution chain, grouping the safe combinations according to shared devices and execution windows, and generating a parallel execution group; monitoring the execution of the instruction under the multi-instruction concurrency according to the executable queue, identifying new complementary combinations that appear after updating, and outputting a rolling optimized release sequence.

Description

Technical Field

[0001] This invention relates to the field of information technology, and in particular to a method and apparatus for security verification of control instructions in a multi-instruction concurrent scenario. Background Technology

[0002] In the field of power grid dispatching, ensuring the security of commands in scenarios with multiple concurrent commands is the cornerstone of stable power system operation, and its importance is self-evident. Power grid dispatching systems need to process a large number of commands simultaneously, such as switch opening and closing commands, to ensure the rational allocation of power resources and the smooth operation of the system. However, potential conflicts between commands can lead to serious safety hazards. When the power grid areas involved by two commands overlap, if the electrical polarity distribution of nodes within the area—that is, the positive or negative characteristics of current or voltage—is not fully considered, the risk of conflict may be misjudged. If the electrical polarities are complementary, it means that the effects of the two commands may cancel each other out, forming a safe combined effect rather than a conflict. However, existing methods often overlook this characteristic, leading to biased risk assessments and affecting the rationality of parallel command execution. Specifically, in actual operation, suppose two commands control the opening and closing of adjacent switches in a substation. Although their influence areas highly overlap on the power grid diagram, if one switching command causes current inflow while the other command happens to guide current outflow, the two may reach a balance, and in reality, no overload or short-circuit risk will occur. If overlapping ranges are used to convert conflicting commands into sequential processing, it will unnecessarily prolong dispatching time and affect the grid response speed. For example, in a 110kV substation with a double busbar configuration, two commands are simultaneously issued to adjacent circuit breakers K1 and K2 on busbar A. K1 closing introduces upstream power flow, while K2 opening releases downstream branch power flow. These two commands form power flow vectors of opposite polarities at the busbar node, which should be balanced and risk-free. However, due to overlapping ranges, the system directly determines a conflict and executes commands sequentially, not only prolonging fault recovery time but also potentially amplifying regional voltage fluctuations. Therefore, how to fully consider the complementary characteristics of electrical polarities in command conflict determination and accurately distinguish between seemingly high-risk and actually safe command combinations has become a key issue in improving the efficiency and safety of grid dispatching. Summary of the Invention

[0003] The purpose of this invention is to provide a method and apparatus for security verification of control instructions in a multi-instruction concurrent scenario, so as to solve the aforementioned technical problems.

[0004] This invention provides a method for security verification of control instructions in a multi-instruction concurrent scenario, comprising: Collect the target devices associated with each switch opening and closing command from the power grid dispatching system, and perform multi-hop electrical connectivity traversal starting from each target device to generate an electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set; The intersection range of subgraph nodes between any two switch opening and closing commands is identified based on the subgraph set. A graph theory algorithm is used to evaluate the overlap area ratio within the intersection. Based on the overlap area ratio, it is determined whether the two switch opening and closing commands are a high-overlap risk command pair. For high-overlap risk command pairs, the equivalent injected power direction of each node within the intersection range is extracted from the real-time operation section of the power grid, mapped to positive or negative polarity labels, and a polarity distribution vector is constructed. For each pair of high-overlapping-risk instruction pairs, calculate the polarity complementarity of the polarity distribution vectors within the intersection region. High-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold are marked as safe combinations and included in parallel execution instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity below the preset threshold are marked as high-risk pairs and included in the serial dependency execution chain. Based on the parallel release instruction pairs and the serial dependent execution chain, the switching conditions between parallel and serial execution are dynamically adjusted, and the security combination is grouped according to the shared device and execution window to generate parallel execution groups. Parallel execution groups and serial dependent execution chains are integrated into a pass queue. The sequential dependencies of instructions in the pass queue are identified, the queue order is determined, and the electrical connectivity subgraph compatibility of instructions within each parallel execution group is evaluated. If the compatibility meets the safe combination condition, the parallel execution group is allowed to proceed. If the compatibility does not meet the safe combination condition, it is rolled back to the serial dependent execution chain, resulting in an executable queue. Based on the execution queue, monitor the concurrent issuance and execution of multiple instructions, identify new complementary combinations that appear after the update, and output a rolling optimized release sequence.

[0005] Furthermore, the target devices associated with each switch opening and closing command are collected from the power grid dispatching system, and a multi-hop electrical connectivity traversal is performed starting from each target device to generate an electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set, including: Extract switch opening and closing instructions from the instruction buffer of the power grid dispatching system, parse the device identification field in the switch opening and closing instructions, and obtain the associated target device; Starting from the target device, query the static topology database of the power grid to determine the directly connected starting node and record the attribution mapping relationship; Based on the starting node, perform a breadth-first traversal in the power grid topology adjacency table, visit adjacent nodes, and filter and disconnect branches according to their conduction status. Connected nodes and branches are selected based on a preset hop count threshold, spliced ​​together to form an electrical connectivity subgraph, and boundary ports are marked. These subgraphs are then aggregated to form the subgraph set.

[0006] Furthermore, each element in the subgraph set carries an instruction identifier, a node list, a branch list, and boundary port information.

[0007] Furthermore, the step of identifying the intersection range of subgraph nodes between any two switch opening / closing commands based on the subgraph set, evaluating the overlap area ratio within the intersection using graph theory algorithms, and determining whether the two switch opening / closing commands are a high-overlap risk command pair based on the overlap area ratio includes: From the set of subgraphs, extract the electrically connected subgraphs by pairing them up, extract the node list and the branch list, and find their intersection; Based on the intersection, a sub-graph of the transaction set is spliced ​​together, and the similarity coefficient is used to measure the proportion of overlapping area. The overlap ratio is adjusted by assigning weights based on the node voltage level to obtain the overlap index. If the overlap index exceeds the preset threshold, the two switch opening and closing instructions corresponding to the paired electrical connection sub-diagrams will be marked as the high overlap risk instruction pair and written into the review queue. Traverse all pairings in the subgraph set to generate a queue of pending reviews containing the high-overlap risk instruction pairs.

[0008] Furthermore, for high-overlap risk command pairs, the equivalent injected power direction of each node within the intersection range is extracted from the real-time operation section of the power grid, mapped to positive or negative polarity labels, and a polarity distribution vector is constructed, including: Obtain the intersection subgraph of the high-overlap risk command pairs, and obtain the active power injection value of the nodes from the real-time operation section of the power grid; Calculate the equivalent injected power of the bus node connecting multiple branches in each node of the intersection subgraph and determine the direction identifier; Based on the polarity of the direction identifier mapping node, assign positive, negative, or zero polarity labels; The polarity labels are arranged according to a preset sorting rule to construct the polarity distribution vector that is consistent with the number of nodes.

[0009] Furthermore, the step of calculating the polarity complementarity of the polarity distribution vectors within the intersection region for each pair of high-overlapping-risk instruction pairs, marking high-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold as safe combinations and classifying them into parallel-release instruction pairs, and marking high-overlapping-risk instruction pairs with polarity complementarity below the preset threshold as high-risk pairs and classifying them into a serial dependency execution chain, includes: Extract the polarity distribution vector corresponding to each pair of high-overlapping-risk instructions from the set of polarity distribution vectors, and compare the polarity signs bit by bit; The positions with one positive and one negative symbol are denoted as complementary positions, and the polarity complementarity is obtained by calculating the proportion of complementary positions. If the polarity complementarity exceeds a preset threshold, the current high-overlap risk instruction pair is marked as the safe combination and classified into a parallel release instruction pair; If the polarity complementarity does not reach the threshold, the current high-overlap risk instruction pair is marked as the high-risk pair and included in the serial dependency execution chain; Iterate through all high-overlap risk instruction pairs to generate a set of instruction pairs that can be released in parallel and a set of sequentially dependent execution chains.

[0010] Furthermore, the step of dynamically adjusting the switching conditions between parallel and serial execution based on parallel release instruction pairs and serial dependent execution chains, and grouping the security combination according to shared devices and execution windows to generate parallel execution groups, includes: For safe combinations of parallel release instruction pairs, obtain the target device list and execution time window, and compute device shared identifiers and time overlap identifiers; Update the switching conditions between parallel and serial operations based on the identifier, and group the security combinations according to preset grouping rules; Filter out instruction conflicts involving the same target device within the same group and generate grouping results without resource contention; Based on the grouping results, the instruction numbers and time windows are integrated to form the parallel execution groups, and the quantity and interval are marked. The high-risk pairs are maintained in a serial arrangement to generate a set of parallel execution groups.

[0011] Furthermore, the process of integrating parallel execution groups and serially dependent execution chains into a pass queue, identifying the sequential dependencies of instructions in the pass queue, determining the queue order, evaluating the electrical connectivity subgraph compatibility of instructions within each parallel execution group, allowing the parallel execution group to proceed when the compatibility meets the safe combination condition, and rolling back to the serially dependent execution chain when the compatibility does not meet the safe combination condition, results in an executable queue, including: The parallel execution group and the high-risk pair are written into the queue. The dependency is compared with the target device and the time window to generate an inter-group dependency graph and sort it to obtain the queue order. Verify the polarity symbol compatibility of the electrical connectivity subgraph within the parallel execution group according to the queue order; If the polarity signs are complementary and the shared branch directions are opposite, then the condition is met and passage is allowed; If the polarity symbol or the direction of the shared branch is in the same direction, roll back to the serial dependency execution chain and generate the executable queue.

[0012] Furthermore, the step of monitoring the concurrent issuance and execution of multiple instructions based on the executable queue, identifying new complementary combinations after updates, and outputting a rolling optimized release sequence includes: According to the executable queue, switch opening and closing commands are issued, the command arrival signal is monitored, and the operating section is updated. Based on the updated operational section, the polarity distribution vector and polarity complementarity are recalculated for the remaining high-overlap risk instructions. High-overlapping-risk instruction pairs that did not reach the complementarity threshold before the update but exceeded the complementarity threshold after the update are identified as new complementary combinations; high-overlapping-risk instruction pairs that exceeded the complementarity threshold before the update but did not reach the complementarity threshold after the update are identified as failed complementary combinations. Based on the new complementary combination and the failed complementary combination, the sequence of the untriggered portion in the executable queue is adjusted, and the rolling optimized release sequence is generated based on the adjustment result.

[0013] This invention provides a control instruction security verification device for multi-instruction concurrency scenarios, comprising: The subgraph generation module is used to collect the target devices associated with each switch opening and closing command from the power grid dispatching system, and perform multi-hop electrical connectivity traversal starting from each target device to generate the electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set; The intersection risk assessment module is used to identify the intersection range of subgraph nodes between any two switch opening and closing commands based on the subgraph set, use graph theory algorithms to evaluate the overlap area ratio within the intersection, and determine whether the two switch opening and closing commands are a high-overlap risk command pair based on the overlap area ratio. The polarity vector construction module is used to extract the equivalent injected power direction of each node within the intersection range from the real-time operation section of the power grid for high-overlap risk command pairs, map them as positive or negative polarity labels, and construct a polarity distribution vector. The complementarity calculation module is used to calculate the polarity complementarity of the polarity distribution vector in the intersection region for each pair of high-overlapping-risk instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold are marked as safe combinations and included in parallel release instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity not reaching the preset threshold are marked as high-risk pairs and included in the serial dependency execution chain. The grouping adjustment module is used to dynamically adjust the switching conditions between parallel and serial execution based on parallel instruction pairs and serial dependent execution chains, and to group the security combination according to the shared device and execution window to generate parallel execution groups. The queue integration module is used to integrate parallel execution groups and serial dependent execution chains into a pass queue, identify the sequential dependencies of instructions in the pass queue, determine the queue order, evaluate the electrical connectivity subgraph compatibility of instructions within each parallel execution group, and allow the parallel execution group to proceed if the compatibility meets the safe combination conditions; otherwise, it rolls back to the serial dependent execution chain to obtain an executable queue. The execution monitoring module is used to monitor the issuance and execution of multiple concurrent instructions based on the executable queue, identify new complementary combinations that appear after updates, and output a rolling optimized release sequence.

[0014] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: This invention discloses a method and apparatus for security verification of control commands in multi-command concurrency scenarios. It proposes a systematic solution to the electrical connectivity conflicts and resource contention problems that may arise from concurrent multi-command operations in power grid dispatching. The method constructs an electrical connectivity subgraph set, identifies the risk of overlap between commands, and evaluates complementarity using polarity distribution vectors. It then classifies safe combinations and high-risk pairs for processing, dynamically optimizing parallel and serial execution strategies. This invention focuses on the compatibility of electrical connectivity subgraphs, integrating parallel execution groups and serial dependency chains to form an executable queue. Through real-time monitoring and rolling optimization, it continuously updates the release sequence to ensure safe and efficient command issuance. Ultimately, this invention achieves security verification and execution optimization in multi-command concurrency scenarios, significantly reducing the risk of command conflicts and improving the reliability and operational efficiency of power grid dispatching. Attached Figure Description

[0015] Figure 1 This is a flowchart of a method for verifying the security of control instructions in a multi-instruction concurrent scenario according to the present invention.

[0016] Figure 2 This is a schematic diagram of the structure of a control instruction security verification device in a multi-instruction concurrent scenario according to the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0018] like Figure 1 This embodiment of a method for security verification of control instructions in a multi-instruction concurrent scenario specifically includes: Step S101: Collect the target devices associated with each switch opening and closing command from the power grid dispatching system, and perform multi-hop electrical connectivity traversal starting from each target device to generate an electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set.

[0019] Switch opening and closing instructions in the pre-release stage are obtained from the instruction buffer of the power grid dispatching system. For each switch opening and closing instruction, the device identification field carried in the instruction is parsed to obtain at least one target device associated with the instruction. The target device includes circuit breakers, disconnectors, or bus sectionalizing switches. For each target device, the bus nodes and line ports directly connected to it in the static topology library are queried as starting nodes, and the mapping relationship between the starting nodes and the original instruction is recorded to obtain a list of corresponding instructions and starting nodes. Based on the starting nodes in the corresponding list, a breadth-first traversal is performed in the pre-established power grid topology adjacency table, sequentially visiting adjacent nodes directly connected by conductors, transformer windings, or bus segments, and filtering out switch branches in the open position according to their conduction status. For each visited adjacent node, it is determined whether the number of hops between it and the starting node falls within a preset hop count threshold. If it falls within the threshold, it is included in the connected node set; otherwise, the expansion in that direction is truncated, resulting in a connected node set and a corresponding branch set. Based on the set of connected nodes and the corresponding set of branches, the electrical connectivity subgraph of the instruction is formed by splicing together the original target device as the root node, and the access port connected to the external power grid is marked at the boundary of the subgraph. For all switch opening and closing instructions in the pre-release stage, the above traversal and splicing actions are repeated. According to the mapping relationship between the instruction number and the subgraph, the electrical connectivity subgraphs corresponding to each instruction are gathered into a subgraph set. Each element in the subgraph set carries an instruction identifier, a node list, a branch list, and boundary port information.

[0020] When processing multiple switching commands, the power grid dispatching system first characterizes the power grid scope affected by each command during the command pre-release phase. Taking a regional power grid dispatching master station as an application scenario, switching operation commands issued by dispatchers or higher-level automated decision-making modules enter a pre-release buffer before formal execution. This buffer may simultaneously contain dozens of switching operation requests for different substations and voltage levels. In one implementation, the message of each command to be executed is retrieved from the command buffer. This message typically adopts a general dispatching automation message structure, including command number, operation type field, equipment identification field, operation time window, and priority.

[0021] Specifically, parsing the device identifier field reveals the target device directly affected by the instruction, such as a circuit breaker numbered 2201, a disconnector numbered 220G1, or a busbar sectionalizing switch within a 220 kV substation. After obtaining the target device, its connection location within the power grid needs to be determined. One possible implementation is to query a pre-established static power grid topology database. This database uses substations, buses, lines, and transformer windings as nodes and electrical connections as edges, recording which busbar segment or line each primary device's two sides are connected to. For each target device, the busbar nodes and line ports connected to its two sides are read from the topology database and used as the starting nodes for subsequent traversals.

[0022] Specifically, the traversal process employs a breadth-first search approach on the adjacency list of the power grid topology. This adjacency list is one of the storage formats for the static topology library of the power grid, with each node corresponding to a row listing all directly connected adjacent nodes and their connecting media. Starting from the initial node, the first hop visits adjacent nodes directly connected via conductors, transformer windings, or busbar segments; the second hop continues expanding outwards from the newly added node in the first hop; and so on, expanding outwards hop by hop. During the expansion process, the conduction status of the switches at both ends of each traversed branch is read; branches with switches in the off position do not participate in the expansion, effectively dynamically shielding the corresponding edges on the adjacency list. The hop count threshold is related to the power grid voltage level and the radius of influence of the operation.

[0023] Preferably, for main grid operations of 500 kV and above, the hop count threshold is 4 hops; for regional grid operations of 220 kV, it is 3 hops; and for distribution side operations of 110 kV and below, it is 2 hops.

[0024] In one embodiment, for a bus section switch closing command of a 110 kV substation, taking the section switch as the root, two outward jumps can cover the near-end ports of the two bus sections and their outgoing lines in the same station.

[0025] It should be noted that the switch position information used for conduction status filtering comes from real-time remote signaling of the power grid. Switch branches with the remote signaling set to the "closed" position are considered conducting, while those set to the "open" position are considered disconnected. For the target switch to be operated by the instruction itself, the expected position after the operation is completed is used for traversal to reflect the connectivity state after the operation takes effect.

[0026] Specifically, if the number of hops between the adjacent nodes visited in each hop and the starting node falls within the hop count threshold, the node is included in the connected node set of the instruction, and the corresponding branch is included in the branch set. If the number of hops exceeds the threshold, the expansion in that direction stops. After traversal, with the original target device as the root node, the connected node set and the branch set are pieced together according to the original topology to form a tree-like or network-like electrical connectivity subgraph. At the boundary of the subgraph, ports whose expansion is truncated by the hop count threshold are marked. These ports are the access ports of the subgraph connecting to the external power grid, such as the bus-side port of a substation on the opposite side of an outgoing line or the grid connection point of the upstream power grid.

[0027] In one embodiment, the dispatching system has three switch opening and closing commands at the same time, which are respectively operated on circuit breaker 2201 of substation A, circuit breaker 2202 of substation B and bus tie switch of substation C. According to the above process, three electrical connection subgraphs are established respectively. Each subgraph carries the command number, node list, branch list and boundary port information. The three are aggregated into the subgraph set output in this stage.

[0028] Step S102: Identify the intersection range of subgraph nodes between any two switch opening and closing commands based on the subgraph set, use graph theory algorithm to evaluate the overlap area ratio within the intersection, and determine whether the two switch opening and closing commands are a high-overlap risk command pair based on the overlap area ratio.

[0029] From the set of subgraphs, at least one pair of electrically connected subgraphs are extracted by pairing them according to instruction number. For each pair of subgraphs, the node list and branch list of both are extracted. A set intersection operation is performed on the node list to obtain the node intersection, and a set intersection operation is performed on the branch list to obtain the branch intersection. For each node in the node intersection, its access position and voltage level in the original two instruction subgraphs are marked. The node intersection and branch intersection are then concatenated into a subgraph based on the original topology. Based on the subgraph, the Jaccard similarity coefficient is used to measure the overlap area ratio of each pair of instructions. The Jaccard similarity coefficient is the ratio of the number of nodes in the subgraph to the number of nodes in the union of the two instruction subgraphs. The nodes are assigned decreasing weights according to their voltage levels from high to low, and the ratio is weighted and adjusted. Nodes with higher voltage levels contribute more to the ratio, resulting in a weighted overlap index. The overlap index is compared with a pre-established overlap risk threshold. If the overlap index exceeds the threshold, the two corresponding instructions are marked as high overlap risk instruction pairs, and the high overlap risk instruction pairs, along with the node list, branch list, and voltage level label in their intersection subgraph, are written into the review queue. If the overlap index does not exceed the threshold, they are classified as low overlap candidates and no longer participate in subsequent judgments. After traversing all pairwise combinations in the subgraph set, a review queue containing high overlap risk instruction pairs is obtained.

[0030] In one implementation, the pre-release buffer of the dispatch master station contains multiple switch opening and closing instructions for a certain 220 kV regional power grid. Each switch opening and closing instruction corresponds to an electrical connectivity sub-graph carrying a node list, branch list, and boundary port information.

[0031] Specifically, the subgraph sets are paired up according to the instruction number. The pairing rules are enumerated, and for each pair of subgraphs, the node list and branch list of both parties are extracted. Each element in the node list is uniquely identified by the substation number, busbar segment number, or line port number. Each branch in the branch list is identified by the node numbers at both ends plus a branch type field. The branch type field can take values ​​such as conductor segment, transformer winding, and busbar segment.

[0032] In one possible implementation, when performing a set intersection operation on the node list, a hash table-based set instruction is used. The node identifiers of the first instruction subgraph are written into the hash table, and then the node identifiers of the second instruction subgraph are checked one by one to see if they match. Nodes that match are included in the node intersection. The branch intersection is obtained in the same way. For example, the node intersection of the subgraphs corresponding to a 2201 circuit breaker closing instruction and a 2202 circuit breaker closing instruction includes nodes of bus A, bus B, and a section of tie line nodes. Further, for each node in the node intersection, the voltage level field recorded in the power grid static topology library is retrieved and annotated. The node intersection and branch intersection are then concatenated into a set subgraph according to the original topology relationship. This set subgraph retains the connection order and voltage level between nodes, serving as the carrying structure for overlap measurement.

[0033] It should be noted that the core element of the overlap index is the value of the Jaccard similarity coefficient. The Jaccard similarity coefficient is a classic metric in set similarity measurement, and its value is defined as the ratio of the number of elements in the intersection of two sets to the number of elements in the union of two sets. Let the node set of the first instruction subgraph be A and the node set of the second instruction subgraph be B, then the original similarity coefficient is the number of nodes in the intersection of A and B divided by the number of nodes in the union of A and B, denoted as J.

[0034] In one embodiment, A contains 32 nodes, B contains 28 nodes, and their intersection contains 18 nodes. Therefore, the union of A and B is 32 plus 28 minus 18 nodes, and the value of J is 18 divided by 42. The value of J falls between 0 and 1, where 0 indicates that the nodes of the two subgraphs do not intersect at all, and 1 indicates that the nodes of the two subgraphs completely overlap.

[0035] Specifically, the original similarity coefficient J is corrected by voltage level weighting.

[0036] Preferably, a weight of 1.0 is assigned to 500 kV nodes, a weight of 0.7 to 220 kV nodes, a weight of 0.4 to 110 kV nodes, and a weight of 0.2 to 35 kV and below nodes. The weights of each node in the intersection are summed and then divided by the sum of the weights of the union of the nodes in the two subgraphs to obtain the weighted overlap index, denoted as J*. If 6 of the 18 nodes in the intersection are 220 kV nodes and 12 are 110 kV nodes, then the sum of the intersection weights is 6 × 0.7 plus 12 × 0.4 equals 9.0. The sum of the union weights is accumulated in the same way to obtain approximately 18.6, so J* is approximately 0.48. Further, the overlap index J is compared with a pre-established overlap risk threshold.

[0037] Preferably, the threshold value is 0.35. If J exceeds 0.35, the corresponding two instructions are recorded as a high-overlap risk instruction pair; if J* does not exceed 0.35, it is classified as a low-overlap candidate and will not participate in subsequent determination.

[0038] It is understandable that after traversing all pairwise combinations in the subgraph set, a queue to be reviewed is obtained. Each element in the queue to be reviewed carries a pair of instruction numbers, the corresponding intersection subgraph, node list, branch list and voltage level label, which serve as input data for subsequent electrical polarity complementarity determination.

[0039] Step S103: For high-overlap risk command pairs, extract the equivalent injected power direction of each node within the intersection range from the real-time operation section of the power grid, map it as a positive or negative polarity label, and construct a polarity distribution vector.

[0040] The intersection subgraph associated with each high-overlap risk instruction pair is read from the queue to be reviewed to obtain a real-time operating profile of the power grid. The operating profile includes the active power injection value of each node. For each node in the intersection subgraph, the corresponding record is retrieved in the operating profile according to the node number. For bus nodes connecting multiple branches, the active power injection values ​​of each branch at that node are algebraically summed to obtain the equivalent injected power of the node. The sign of the algebraic sum is used as the direction identifier to obtain a node power list. Based on the equivalent injected power and direction identifier of each node in the node power list, the power direction of each node is mapped. If the equivalent injected power flows along the node to an external branch, the node is marked as outflow polarity and assigned a positive polarity label. If the equivalent injected power flows into the node along an external branch, the node is marked as inflow polarity and assigned a negative polarity label. For nodes with an absolute power value lower than a preset zero tolerance, they are marked as neutral polarity and assigned a zero polarity label to obtain a polarity label list corresponding one-to-one with the node number. According to the polarity label list, the nodes in the intersection subgraph are expanded according to a preset sorting rule, which is arranged in order of voltage level from high to low and busbar priority over line port. The polarity label corresponding to each node is sequentially filled into the vector component position to obtain a polarity distribution vector consistent with the number of nodes in the intersection subgraph. For each high-overlap risk instruction pair, the above mapping and arrangement operations are performed to bind the constructed polarity distribution vector with the corresponding instruction number and intersection subgraph identifier to obtain a set of polarity distribution vectors.

[0041] Each element in the queue to be reviewed carries a pair of high-overlap risk instructions, a corresponding intersection subgraph, a node list, a branch list, and a voltage level label. In one implementation, the dispatch master station retrieves a real-time operating section of the power grid. This operating section originates from telemetry data transmitted by the power grid dispatch automation acquisition system at 4-5 second intervals. This data includes the active power injection value for each bus node and line port node, recorded in megawatts, with the positive power flow direction of the power grid as the positive reference direction. For each node in the intersection subgraph, the corresponding record is retrieved in the operating section according to the node number.

[0042] Specifically, for bus nodes connecting multiple branches, the equivalent injected power is obtained by algebraic summation. Let a bus node connect to m branches, and let Pi be the active power injected by the i-th branch at that node. The value is negative along the direction the branch flows out of the node, and positive along the direction it flows into the node. Then, the equivalent injected power Peq of that node is equal to the algebraic sum of P1, P2, ..., Pm. For example, in a 110 kV substation, bus node A connects three outgoing lines and the low-voltage winding of one main transformer. The active power injected into the bus by the main transformer winding is positive, and the active power carried away by the three outgoing lines is negative. The equivalent injected power Peq of the bus node is obtained by algebraic summation of these four components. The sign of Peq is used as the directional indicator, and the results are summarized into a node power list.

[0043] It should be noted that the positive or negative direction of the equivalent injected power of a node reflects the power flow role that node plays in the overlapping region. A positive value indicates that the node sends active power out of the region, while a negative value indicates that the node absorbs active power from the region. Furthermore, the power direction of each node is mapped according to the equivalent injected power and direction identifier of each node in the node power list.

[0044] In one possible implementation, if Peq is greater than a preset zero tolerance ε, the node is marked as outflow polarity and assigned a positive polarity label, denoted as +1; if Peq is less than a negative preset zero tolerance ε, the node is marked as inflow polarity and assigned a negative polarity label, denoted as -1; if the absolute value of Peq does not exceed ε, the node is marked as neutral polarity and assigned a zero polarity label, denoted as 0.

[0045] Preferably, the value of the zero tolerance ε is related to the telemetry accuracy of the operating section. It is 0.5 MW for 220 kV regional power grid, 0.2 MW for 110 kV regional power grid, and 0.05 MW for 35 kV and below. After traversing all nodes in the intersection subgraph, a list of polarity labels is obtained.

[0046] Specifically, the preset sorting rules are arranged in order of voltage level from high to low, with busbars taking priority over line ports.

[0047] Preferably, the rules are executed by first dividing the nodes in the intersection subgraph into buckets according to their voltage levels, with 500 kV nodes at the top, followed by 220 kV, 110 kV, and 35 kV nodes; within the same voltage level, busbar nodes are placed before line port nodes; and then, under the same conditions, nodes are arranged in ascending order by node number.

[0048] In one embodiment, the intersection subgraph corresponding to a high-overlap risk instruction pair contains 6 nodes, including 2 nodes for 220 kV busbars, 2 nodes for 110 kV busbars, and 2 nodes for 110 kV outgoing line ports. These nodes are arranged in a fixed order according to the above rules. The corresponding polarity labels are then filled into the vector component positions in sequence to obtain a polarity distribution vector in the form of [+1,-1,+1,-1,0,+1].

[0049] Understandably, for each high-overlap risk instruction pair in the review queue, the aforementioned equivalent injected power algebraic summation, polarity mapping, and sorting filling operations are performed. The constructed polarity distribution vector is then bound to the corresponding instruction number and intersection subgraph identifier to obtain a set of polarity distribution vectors. This set of polarity distribution vectors reflects the power flow direction distribution characteristics of each node in the overlapping region for each high-overlap risk instruction pair, providing a quantitative basis for subsequent complementarity determination.

[0050] Step S104: For each pair of high-overlapping-risk instruction pairs, calculate the polarity complementarity of the polarity distribution vectors in the intersection region. Mark high-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold as safe combinations and classify them into parallel release instruction pairs. Mark high-overlapping-risk instruction pairs with polarity complementarity not reaching the preset threshold as high-risk pairs and classify them into the serial dependency execution chain.

[0051] Based on the set of polarity distribution vectors, for each pair of high-overlap risk instruction pairs, the polarity distribution vectors corresponding to the two instructions are extracted. The two vectors are compared bit by bit according to the polarity signs of the components at the same position. Positions with one positive and one negative polarity are marked as complementary positions, and positions with the same polarity sign or containing zero polarity are marked as non-complementary positions. The number of complementary positions is divided by the total number of vector components to obtain the polarity complementarity of each pair of high-overlap risk instruction pairs. The polarity complementarity is compared with a preset complementarity threshold. If the polarity complementarity exceeds the threshold, the corresponding two instructions are marked as a safe combination and included in the parallel execution instruction pair; if the polarity complementarity does not reach the threshold, the corresponding two instructions are marked as a high-risk pair and included in the serial dependency execution chain. After traversing all high-overlap risk instruction pairs in the set of polarity distribution vectors, the set of parallel execution instruction pairs and the set of serial dependency execution chains are obtained.

[0052] In one implementation, two polar distribution vectors corresponding to each pair of high-overlap risk instructions are extracted from the set of polar distribution vectors according to the instruction number, denoted as V1 and V2, and the lengths of both are consistent with the number of nodes in the corresponding intersection subgraph.

[0053] Specifically, V1 and V2 are compared bit-by-bit according to the polarity signs of their components at the same position. When the component of V1 is +1 and the component of V2 is -1 at a certain position, or V1 is -1 and V2 is +1, it is recorded as a complementary bit; when the two components have the same sign or at least one of them is 0 polarity, it is recorded as a non-complementary bit. Let the number of complementary bits be nc and the total number of vector components be nt, then the polarity complementarity C is nc divided by nt, falling between 0 and 1. For example, if the intersection subgraph of a high-overlap risk instruction pair contains 8 nodes, and after bit-by-bit comparison, 5 complementary bits are obtained, then the polarity complementarity C of this instruction pair is 5 divided by 8, with a value of 0.625. Further, the polarity complementarity C is compared with a preset complementarity threshold T.

[0054] Preferably, the complementarity threshold T is set to 0.6. If C exceeds T, the corresponding two instructions are marked as a safe combination and included in the parallel release instruction pair; if C does not reach T, the corresponding two instructions are marked as a high-risk pair and included in the serial dependency execution chain. After traversing all high-overlap risk instruction pairs in the polarity distribution vector set, a set of parallel release instruction pairs and a set of serial dependency execution chains are obtained. Each element in the set of parallel release instruction pairs carries a pair of instruction numbers, corresponding polarity complementarity, and a safe combination identifier. Each element in the set of serial dependency execution chains carries a pair of instruction numbers, polarity complementarity, and a high-risk identifier, which serve as the basis for subsequent release scheduling.

[0055] Step S105: Based on the parallel release instruction pairs and the serial dependent execution chain, dynamically adjust the switching conditions between parallel and serial execution, group the security combination according to the shared device and execution window, and generate a parallel execution group.

[0056] Based on the set of parallelizable instruction pairs and the set of serial dependent execution chains, for each security combination of parallelizable instruction pairs, the associated target device list and execution time window are retrieved for each of the two instructions. The execution time window includes a start time and an end time. An intersection operation is performed on the target device list to obtain a device sharing identifier, and an interval intersection operation is performed on the execution time window to obtain a time overlap identifier. The parallel and serial switching conditions are updated using the device sharing identifier and the time overlap identifier, resulting in a security combination table to be grouped with device sharing identifiers and execution window labels. Based on the device sharing identifiers and execution window labels in the security combination table to be grouped, security combinations that meet the preset grouping rule (device sharing identifier value is empty and execution window intervals do not overlap) are grouped into the same group, while those that do not meet the rule are split into different groups. For each group, instruction conflicts involving the same target device are further merged, and conflicting instructions are split into new groups again, resulting in a security combination grouping result without resource contention. Based on the security combination grouping results, all instruction numbers, target device lists, and execution time windows in each group are integrated into a parallel execution group, and the number of instructions and combination time intervals covered by each parallel execution group are marked. For high-risk pairs in the set of serial dependency execution chains, they are arranged serially according to their original order of dependency and are not merged into any parallel execution group. After traversing all security combinations in the set of parallelizable instruction pairs, a set of parallel execution groups is obtained.

[0057] In one implementation, the scheduling master station retrieves each safety combination from the set of parallel release instruction pairs one by one according to their numbers. Each safety combination contains a pair of instruction numbers. Then, it retrieves the target equipment list and execution time window associated with the instruction number. The target equipment list is derived from the parsing result of the equipment identification field in the switch opening and closing instruction. The execution time window is derived from the instruction time field in the switch opening and closing instruction, which includes the start time and the end time.

[0058] Specifically, when performing an intersection operation on the target device list, the target device list of the first instruction is written into a hash table, and then the target devices of the second instruction are checked item by item to see if they match the hash table. Matching items are aggregated into a shared device subset, which serves as the value of the device sharing identifier. If the shared device subset is empty, the device sharing identifier for that security combination is an empty set. For example, in one instruction pair, two instructions operate on the 2201 circuit breaker and the 220G1 disconnector respectively; after intersection, the shared device subset is an empty set. In another security combination, two instructions both involve the same A busbar disconnection operation; after intersection, the shared device subset includes A busbar nodes. Further, an interval intersection operation is performed on the execution time window. The start and end times of the first instruction time window and the second instruction time window are compared at their endpoints. If the two time windows have a common time interval, the time overlap identifier is set to overlap; if the endpoints of the two time windows do not intersect, the time overlap identifier is set to non-overlap. The switching conditions between parallel and serial operations are jointly determined by the device sharing identifier and the time overlap identifier.

[0059] In one possible implementation, the corresponding security combination only meets the precondition for parallel execution when the device shared identifier is an empty set and the time overlap identifier is an overlap; other combinations are placed in a serial order. The result of the switching condition is recorded together with the original security combination in the security combination table to be grouped.

[0060] Specifically, based on the equipment sharing identifier and execution window label in the safety combination table to be grouped, the safety combinations are grouped according to preset grouping rules: safety combinations with an empty set of equipment sharing identifiers and execution windows falling within the same time interval are grouped into the same group; safety combinations with non-empty equipment sharing identifiers or non-overlapping execution window intervals are split into different groups. For example, if the safety combination table to be grouped contains 5 safety combinations, 3 of which involve switching operations in different substations and whose execution time windows all fall within a certain maintenance window, they are grouped into Group 1; of the remaining 2 safety combinations, 1 involves a disconnecting switch shared with Group 1, and is separately split into Group 2; the last one, whose execution time window is earlier than the maintenance window, is grouped into Group 3.

[0061] In one embodiment, for each group, instruction conflicts involving the same target device within the group are further merged. An intra-group conflict refers to two instructions within the same group simultaneously operating on the same disconnector or the same busbar segment.

[0062] Preferably, conflicting instructions are split into new groups, and the groups that pass the verification are included in the safe combination grouping results.

[0063] Understandably, based on the security combination grouping results, all instruction numbers, target device lists, and execution time windows in each group are integrated into a parallel execution group, and each parallel execution group is labeled with the number of instructions it covers and the combination time interval. For high-risk pairs in the set of serial dependency execution chains, their original sequential dependencies are maintained in a serial arrangement, and they are not merged into any parallel execution group.

[0064] In one embodiment, after traversing all safe combinations in the set of parallel release instruction pairs, an optimized set of parallel execution groups is obtained. Each element in the set of parallel execution groups carries a set of instruction numbers, a list of target devices, and a combination time interval, which is submitted together with the set of serial dependent execution chains to the subsequent release scheduling stage.

[0065] Step S106: Integrate the parallel execution group and the serial dependent execution chain into the pass queue, identify the sequential dependencies of instructions in the pass queue, determine the queue order, evaluate the electrical connectivity subgraph compatibility of instructions in each parallel execution group, and allow the parallel execution group to pass if the compatibility meets the safe combination condition, and roll back to the serial dependent execution chain if the compatibility does not meet the safe combination condition, thus obtaining the executable queue.

[0066] Each parallel execution group is retrieved from the set of parallel execution groups by group number. High-risk pairs from both the set of parallel execution groups and the set of serial dependency execution chains are written into a pre-established pass queue. For any parallel execution group or execution chain in the pass queue, a dependency comparison is performed on the target device list and execution time window involved in each. If the state change result of the former's target device is a prerequisite for the latter's target device to conduct, the former is determined as the predecessor node of the latter, resulting in an inter-group dependency graph. A topological sort is performed on the inter-group dependency graph to obtain the queue order. Based on the queue order, the electrical connectivity subgraph corresponding to all instructions within each parallel execution group in the pass queue is retrieved. For any two instructions within the group, the polarity signs at the intersection nodes are checked. If the polarity signs at all nodes within the group are complementary and the polarity signs at the two ends of a shared branch are opposite, the parallel execution group is deemed to meet the safe combination condition. If any pair of instructions has polarity signs in the same direction at both ends of a shared branch, the safe combination condition is not met, resulting in a list of parallel execution groups with compatibility indicators. Based on the list of parallel execution groups with compatibility identifiers, parallel execution groups that meet the safe combination conditions are allowed to pass through the queue in the order of the queue, and all instructions in the group are placed into the waiting buffer in a concurrent manner; parallel execution groups that do not meet the safe combination conditions are rolled back, and all instructions in the group are disassembled and merged into the tail of the corresponding serial dependent execution chain to participate in the delivery in sequence. After traversal, an executable queue is obtained by sequentially splicing the allowed parallel execution groups and the rolled-back serial dependent execution chains.

[0067] In one implementation, the scheduling master station retrieves each parallel execution group from the set of parallel execution groups by group number, and writes all high-risk pairs in the set of parallel execution groups and the set of serial dependent execution chains into a pre-established pass queue.

[0068] Specifically, the queue is used to organize the units to be released in a linear structure from the head to the tail. Each unit carries either a parallel execution group or a serial dependent execution chain. The parallel execution group unit contains a set of instruction numbers, a list of target devices, and a combined time interval. The serial dependent execution chain unit contains instruction numbers arranged in sequence and the corresponding list of target devices.

[0069] It should be noted that the core of dependency comparison is to determine whether there is a state prerequisite relationship between two units in the queue.

[0070] In one possible implementation, for any parallel execution group and execution chain in the pass queue, the target device list and execution time window involved in each are retrieved respectively. First, it is compared whether there are overlapping devices in the target device lists of both sides. If overlapping devices exist, it is further checked whether the state of the overlapping devices after the former's operation constitutes the conduction prerequisite for the latter's operation. For example, if a parallel execution group contains an instruction to close a 2201 circuit breaker, and the execution chain contains an instruction to close a 220G1 disconnector switch, in a double busbar connection mode, the closing result of the 2201 circuit breaker is that the corresponding busbar is energized, constituting the conduction prerequisite for closing the 220G1 disconnector switch. Then, the parallel execution group is determined as the predecessor node of the execution chain. Further, all predecessor relationships identified in the pass queue are organized into a directed acyclic graph, denoted as an inter-group dependency graph. Nodes in the inter-group dependency graph correspond to parallel execution groups or execution chains in the pass queue, and directed edges point from predecessor nodes to successor nodes.

[0071] Preferably, a topological sort is performed on the inter-group dependency graph. After traversal, the order of each unit in the queue is obtained and recorded as the queue order. Units without predecessor relationships retain their relative positions according to their original enqueue order.

[0072] Specifically, according to the queue order, the electrical connectivity subgraphs corresponding to all instructions in each parallel execution group in the queue are retrieved, and the polarity symbols at the intersection nodes of any two instructions in the group are checked.

[0073] In one embodiment, a parallel execution group contains a closing operation instruction M and a opening operation instruction N. Their electrical connection sub-diagrams intersect at bus node A, bus node B, and bus tie node. The polarity symbol pairing verification is performed by retrieving the constructed polarity distribution vector and checking the polarity labels of instruction M and instruction N at each intersection node according to their node numbers. If instruction M is assigned a value of +1 at bus node A and instruction N is assigned a value of -1 at bus node A, then bus node A is considered complementary. The same method is used to verify bus node B and bus tie node. If the polarity symbols of all intersection nodes in the group are one positive and one negative, and no pair of instructions exhibits the same polarity and sign at any intersection node, then the compatibility of the parallel execution group is determined to meet the safe combination conditions.

[0074] It should be noted that the opposite polarity signs of the nodes at both ends of a shared branch refer to the situation where, when the electrical connectivity subgraphs of two instructions within the group simultaneously cover a certain branch, the polarity labels of the nodes at both ends of the branch are retrieved from the polarity distribution vectors corresponding to instructions M and N. If one end of the polarity label of the nodes at both ends is +1 and the other end is -1, then the power flow on that branch forms a mutually canceling reverse vector through the merging effect of the two instructions. If the polarity labels of the nodes at both ends are both +1 or both are both -1, then the power flow is superimposed, and the compatibility of the parallel execution group is determined to have failed to meet the safe combination conditions.

[0075] Specifically, for parallel execution groups that meet the safety combination conditions according to compatibility judgment, the release is performed in the pass queue according to the queue order: all instruction numbers, target equipment list and corresponding switch action signals in the group are encapsulated into a concurrent batch, placed in the buffer to be sent, and the buffer to be sent sends switch opening and closing instructions to each substation monitoring and control device at the same time.

[0076] It is understandable that a rollback operation is performed on parallel execution groups that are deemed to have failed to meet the safety combination conditions in terms of compatibility. In one implementation, the rollback is performed by disassembling all instructions within the group one by one according to their original instruction numbering order and merging them into the tail of the corresponding serial dependency execution chain. In the serial dependency execution chain, each instruction is arranged in sequence, and the next instruction is triggered only after the previous instruction has been executed and returned to its correct position. After traversing all parallel execution groups and serial dependency execution chains in the queue, an executable queue is obtained, which is formed by sequentially splicing the released parallel execution groups and the rolled-back serial dependency execution chains. Each element in the executable queue carries a batch identifier, an instruction number list, and a trigger time, serving as the basis for direct execution by the power grid dispatch automation system.

[0077] Step S107: Based on the execution queue monitoring of the concurrent issuance and execution of multiple instructions, identify the new complementary combinations that appear after the update, and output the rolling optimized release sequence.

[0078] According to the executable queue, each batch of commands is issued to the monitoring and control devices of each substation at the trigger time. The tracking signal of each command in the executable queue is monitored. For each tracking signal, the latest location identifier of the corresponding target device and the active power injection tracking value of the node are retrieved. The tracking value is substituted into the equivalent injection power field of the corresponding node in the real-time operation section of the power grid for overlay and update, so as to obtain the updated operation section reflecting the actual effect of the issued commands. According to the updated operation section, the active power injection algebraic summation and polarity sign mapping are re-executed for the nodes involved in the intersection subgraph of the remaining high-overlap risk commands that are still in the pending execution state, so as to obtain the updated polarity distribution vector. The updated polarity distribution vector is re-executed bit-by-bit comparison and the updated polarity complementarity is obtained by dividing the number of complementary bits by the total number of components. Command pairs that did not reach the complementarity threshold before the update but exceeded the threshold after the update are identified as new complementary combinations, and command pairs that exceeded the threshold before the update but did not reach it after the update are identified as failed complementary combinations. Based on the new complementary combination and the failed complementary combination, the sequence of the untriggered parts in the executable queue is adjusted: the two instructions corresponding to the new complementary combination are extracted from the original serial dependent execution chain and merged into a new parallel execution group, and inserted according to the connection position of the queue order; the two instructions corresponding to the failed complementary combination are disassembled from their original parallel execution group, arranged serially and merged into the tail of the corresponding execution chain to obtain a rolling optimized release sequence.

[0079] In one implementation, the dispatch master station sends switch opening and closing commands to each substation measurement and control device according to the trigger time recorded in each batch of the executable queue. After the switch opening and closing commands are sent to the substation bay layer through the remote control channel, they drive the primary equipment to open and close. The measurement and control device then sends back remote signal change and telemetry refresh as the data acquisition status signal.

[0080] Specifically, after each switch opening and closing command is issued, there is a corresponding tracking signal. The tracking signal includes the latest location identifier of the target equipment and the active power injection tracking value of the node to which it belongs. The active power injection tracking value is collected by the substation energy meter and instrument transformer and then transmitted through the four-remote protocol.

[0081] Preferably, for a circuit breaker closing command, the acquired signal includes a closing indicator and the active power measurement value of the interval after closing; for a circuit breaker opening command, the acquired signal includes an opening indicator and feedback that the active power measurement value on the line side has dropped below the threshold after opening.

[0082] Specifically, the active power injection value is substituted into the equivalent injection power field of the corresponding node in the real-time operation section of the power grid to perform a coverage update. The algebraic summation of the active power injection values ​​of each branch is re-executed for the bus node connecting multiple branches to obtain the updated operation section reflecting the actual effect of the issued instructions.

[0083] It should be noted that there will be a local offset between the updated running section values ​​and the original section values. The offset range is limited to the subset of nodes affected by the completed issued instructions. Fields of nodes that did not participate in this round of issuance retain their original values. Furthermore, based on the updated running section, the active injection algebraic summation and polarity sign mapping are re-executed on the intersection subgraph nodes corresponding to the remaining high-overlap risk instructions that are still in the pending execution state, to obtain the updated polarity distribution vector.

[0084] Specifically, a bit-by-bit comparison is performed on the updated polarity distribution vector: the two vectors V1 and V2 corresponding to each pair of remaining high-overlap risk instructions are extracted, and the polarity signs of the components at the same position are checked. The positions with one positive and one negative are recorded as complementary positions, the number of complementary positions is recorded as nc*, the total number of vector components is recorded as nt*, and the updated polarity complementarity C* is obtained by dividing nc* by nt*.

[0085] In one embodiment, the intersection subgraph of a certain remaining high-overlap risk instruction pair contains 8 nodes. Before the update, the number of complementary bits is 4 and the complementarity is 0.5, which does not reach the complementarity threshold of 0.6. After the update, the number of complementary bits increases to 6 and the complementarity C* value is 0.75, which exceeds the complementarity threshold of 0.6.

[0086] Understandably, instruction pairs that did not reach the complementarity threshold before the update but exceeded the threshold after the update are identified as new complementary combinations, and instruction pairs that exceeded the threshold before the update but did not reach it after the update are identified as failed complementary combinations. After traversing through all the pairs, a list of new complementary combinations and a list of failed complementary combinations are formed.

[0087] Specifically, for the two instructions corresponding to the new complementary combination, their positions are retrieved from the serial dependent execution chain that has not yet been triggered in the executable queue according to the instruction number. The two instructions are extracted from the original execution chain and merged into a new parallel execution group. The new parallel execution group is inserted into the position adjacent to its predecessor node according to the connection position of the queue order. The new parallel execution group adopts the batch encapsulation method of the original parallel execution group, carrying the instruction number, target device list and combination time interval.

[0088] In one embodiment, for the two instructions corresponding to the failure complement combination, they are separated from their respective parallel execution groups and merged into the tail of the corresponding execution chain in the order of instruction number. If only a single instruction remains after the original parallel execution group is separated, it is retained in its original position as a single instruction execution unit; they are arranged serially and participate in the issuance in sequence.

[0089] It is understandable that after traversing the untriggered portions of the executable queue and completing the above extraction, merging, dismantling, and incorporation actions, a rolling optimized release sequence is obtained. The release sequence is updated once after each round of data collection and distribution, and the arrangement of untriggered batches is adjusted rollingly according to the evolution of the real-time operation section of the power grid.

[0090] like Figure 2 This invention provides a control instruction security verification device for multi-instruction concurrency scenarios, comprising: The subgraph generation module 21 is used to collect the target devices associated with each switch opening and closing command from the power grid dispatching system, and perform multi-hop electrical connectivity traversal starting from each target device to generate an electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set. The intersection risk assessment module 22 is used to identify the intersection range of subgraph nodes between any two switch opening and closing commands based on the subgraph set, use graph theory algorithm to evaluate the overlapping area ratio within the intersection, and determine whether the two switch opening and closing commands are a high-overlap risk command pair based on the overlapping area ratio. The polarity vector construction module 23 is used to extract the equivalent injected power direction of each node within the intersection range from the real-time operation section of the power grid for high-overlap risk command pairs, map them as positive or negative polarity labels, and construct a polarity distribution vector. The complementarity calculation module 24 is used to calculate the polarity complementarity of the polarity distribution vector in the intersection region for each pair of high-overlapping-risk instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold are marked as safe combinations and included in parallel release instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity not reaching the preset threshold are marked as high-risk pairs and included in the serial dependency execution chain. The grouping adjustment module 25 is used to dynamically adjust the switching conditions between parallel and serial execution based on parallel release instruction pairs and serial dependent execution chains, and to group the security combination according to the shared device and execution window to generate parallel execution groups. The queue integration module 26 is used to integrate parallel execution groups and serial dependent execution chains into a pass queue, identify the sequential dependencies of instructions in the pass queue, determine the queue order, evaluate the electrical connectivity subgraph compatibility of instructions in each parallel execution group, and allow the parallel execution group to pass if the compatibility meets the safe combination condition, and roll back to the serial dependent execution chain if the compatibility does not meet the safe combination condition, thus obtaining an executable queue. The execution monitoring module 27 is used to monitor the issuance and execution of multiple concurrent instructions based on the executable queue, identify new complementary combinations that appear after the update, and output a rolling optimized release sequence.

[0091] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for security verification of control instructions in a multi-instruction concurrent scenario, characterized in that, The method includes: Collect the target devices associated with each switch opening and closing command from the power grid dispatching system, and perform multi-hop electrical connectivity traversal starting from each target device to generate an electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set; The intersection range of subgraph nodes between any two switch opening and closing commands is identified based on the subgraph set. A graph theory algorithm is used to evaluate the overlap area ratio within the intersection. Based on the overlap area ratio, it is determined whether the two switch opening and closing commands are a high-overlap risk command pair. For high-overlap risk command pairs, the equivalent injected power direction of each node within the intersection range is extracted from the real-time operation section of the power grid, mapped to positive or negative polarity labels, and a polarity distribution vector is constructed. For each pair of high-overlapping-risk instruction pairs, calculate the polarity complementarity of the polarity distribution vectors within the intersection region. High-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold are marked as safe combinations and included in parallel execution instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity below the preset threshold are marked as high-risk pairs and included in the serial dependency execution chain. Based on the parallel release instruction pairs and the serial dependent execution chain, the switching conditions between parallel and serial execution are dynamically adjusted, and the security combination is grouped according to the shared device and execution window to generate parallel execution groups. Parallel execution groups and serial dependent execution chains are integrated into a pass queue. The sequential dependencies of instructions in the pass queue are identified, the queue order is determined, and the electrical connectivity subgraph compatibility of instructions within each parallel execution group is evaluated. If the compatibility meets the safe combination condition, the parallel execution group is allowed to proceed. If the compatibility does not meet the safe combination condition, it is rolled back to the serial dependent execution chain, resulting in an executable queue. Based on the execution queue, monitor the concurrent issuance and execution of multiple instructions, identify new complementary combinations that appear after the update, and output a rolling optimized release sequence.

2. The method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, The process involves collecting the target devices associated with each switch opening / closing command from the power grid dispatching system, and performing a multi-hop electrical connectivity traversal starting from each target device to generate an electrical connectivity subgraph corresponding to each switch opening / closing command, forming a subgraph set, including: Extract switch opening and closing instructions from the instruction buffer of the power grid dispatching system, parse the device identification field in the switch opening and closing instructions, and obtain the associated target device; Starting from the target device, query the static topology database of the power grid to determine the directly connected starting node and record the attribution mapping relationship; Based on the starting node, perform a breadth-first traversal in the power grid topology adjacency table, visit adjacent nodes, and filter and disconnect branches according to their conduction status. Connected nodes and branches are selected based on a preset hop count threshold, spliced ​​together to form an electrical connectivity subgraph, and boundary ports are marked. These subgraphs are then aggregated to form the subgraph set.

3. The method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, Each element in the subgraph set carries an instruction identifier, a node list, a branch list, and boundary port information.

4. The method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, The step of identifying the intersection range of subgraph nodes between any two switch opening / closing commands based on the subgraph set, evaluating the overlap area ratio within the intersection using graph theory algorithms, and determining whether the two switch opening / closing commands are a high-overlap risk command pair based on the overlap area ratio includes: From the set of subgraphs, extract the electrically connected subgraphs by pairing them up, extract the node list and the branch list, and find their intersection; Based on the intersection, a sub-graph of the transaction set is spliced ​​together, and the similarity coefficient is used to measure the proportion of overlapping area. The overlap ratio is adjusted by assigning weights based on the node voltage level to obtain the overlap index. If the overlap index exceeds the preset threshold, the two switch opening and closing instructions corresponding to the paired electrical connection sub-diagrams will be marked as the high overlap risk instruction pair and written into the review queue. Traverse all pairings in the subgraph set to generate a queue of pending reviews containing the high-overlap risk instruction pairs.

5. A method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, For high-overlap risk command pairs, the equivalent injected power direction of each node within the intersection range is extracted from the real-time operation section of the power grid, mapped to positive or negative polarity labels, and a polarity distribution vector is constructed, including: Obtain the intersection subgraph of the high-overlap risk command pairs, and obtain the active power injection value of the nodes from the real-time operation section of the power grid; Calculate the equivalent injected power of the bus node connecting multiple branches in each node of the intersection subgraph and determine the direction identifier; Based on the polarity of the direction identifier mapping node, assign positive, negative, or zero polarity labels; The polarity labels are arranged according to a preset sorting rule to construct the polarity distribution vector that is consistent with the number of nodes.

6. The method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, The step of calculating the polarity complementarity of the polarity distribution vectors within the intersection region for each pair of high-overlapping-risk instruction pairs, marking high-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold as safe combinations and classifying them into parallel-allowable instruction pairs, and marking high-overlapping-risk instruction pairs with polarity complementarity below the preset threshold as high-risk pairs and classifying them into a serial dependency execution chain, includes: Extract the polarity distribution vector corresponding to each pair of high-overlapping-risk instructions from the set of polarity distribution vectors, and compare the polarity signs bit by bit; The positions with one positive and one negative symbol are denoted as complementary positions, and the polarity complementarity is obtained by calculating the proportion of complementary positions. If the polarity complementarity exceeds a preset threshold, the current high-overlap risk instruction pair is marked as the safe combination and classified into a parallel release instruction pair; If the polarity complementarity does not reach the threshold, the current high-overlap risk instruction pair is marked as the high-risk pair and included in the serial dependency execution chain; Iterate through all high-overlap risk instruction pairs to generate a set of instruction pairs that can be released in parallel and a set of sequentially dependent execution chains.

7. The method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, The method of dynamically adjusting the switching conditions between parallel and serial execution based on parallelizable instruction pairs and serial dependent execution chains, and grouping security combinations according to shared devices and execution windows to generate parallel execution groups includes: For safe combinations of parallel release instruction pairs, obtain the target device list and execution time window, and compute device shared identifiers and time overlap identifiers; Update the switching conditions between parallel and serial operations based on the identifier, and group the security combinations according to preset grouping rules; Filter out instruction conflicts involving the same target device within the same group and generate grouping results without resource contention; Based on the grouping results, the instruction numbers and time windows are integrated to form the parallel execution groups, and the quantity and interval are marked. The high-risk pairs are maintained in a serial arrangement to generate a set of parallel execution groups.

8. A method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, The process involves integrating parallel execution groups and serially dependent execution chains into a pass queue, identifying the sequential dependencies of instructions in the pass queue, determining the queue order, evaluating the electrical connectivity subgraph compatibility of instructions within each parallel execution group, allowing the parallel execution group to proceed if the compatibility meets the safe combination condition, and rolling back to the serially dependent execution chain if the compatibility does not meet the safe combination condition, resulting in an executable queue, including: The parallel execution group and the high-risk pair are written into the queue. The dependency is compared with the target device and the time window to generate an inter-group dependency graph and sort it to obtain the queue order. Verify the polarity symbol compatibility of the electrical connectivity subgraph within the parallel execution group according to the queue order; If the polarity signs are complementary and the shared branch directions are opposite, then the condition is met and passage is allowed; If the polarity symbol or the direction of the shared branch is in the same direction, roll back to the serial dependency execution chain and generate the executable queue.

9. A method for security verification of control instructions in a multi-instruction concurrent scenario according to claim 1, characterized in that, The step of monitoring the concurrent issuance and execution of multiple instructions based on the executable queue, identifying new complementary combinations after updates, and outputting a rolling optimized release sequence includes: According to the executable queue, switch opening and closing commands are issued, the command arrival signal is monitored, and the operating section is updated. Based on the updated operational section, the polarity distribution vector and polarity complementarity are recalculated for the remaining high-overlap risk instructions. High-overlapping-risk instruction pairs that did not reach the complementarity threshold before the update but exceeded the complementarity threshold after the update are identified as new complementary combinations; high-overlapping-risk instruction pairs that exceeded the complementarity threshold before the update but did not reach the complementarity threshold after the update are identified as failed complementary combinations. Based on the new complementary combination and the failed complementary combination, the sequence of the untriggered portion in the executable queue is adjusted, and the rolling optimized release sequence is generated based on the adjustment result.

10. A control instruction security verification device for multi-instruction concurrent scenarios, characterized in that, The device includes: The subgraph generation module is used to collect the target devices associated with each switch opening and closing command from the power grid dispatching system, and perform multi-hop electrical connectivity traversal starting from each target device to generate the electrical connectivity subgraph corresponding to each switch opening and closing command, forming a subgraph set; The intersection risk assessment module is used to identify the intersection range of subgraph nodes between any two switch opening and closing commands based on the subgraph set, use graph theory algorithms to evaluate the overlap area ratio within the intersection, and determine whether the two switch opening and closing commands are a high-overlap risk command pair based on the overlap area ratio. The polarity vector construction module is used to extract the equivalent injected power direction of each node within the intersection range from the real-time operation section of the power grid for high-overlap risk command pairs, map them as positive or negative polarity labels, and construct a polarity distribution vector. The complementarity calculation module is used to calculate the polarity complementarity of the polarity distribution vector in the intersection region for each pair of high-overlapping-risk instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity exceeding a preset threshold are marked as safe combinations and included in parallel release instruction pairs. High-overlapping-risk instruction pairs with polarity complementarity not reaching the preset threshold are marked as high-risk pairs and included in the serial dependency execution chain. The grouping adjustment module is used to dynamically adjust the switching conditions between parallel and serial execution based on parallel instruction pairs and serial dependent execution chains, and to group the security combination according to the shared device and execution window to generate parallel execution groups. The queue integration module is used to integrate parallel execution groups and serial dependent execution chains into a pass queue, identify the sequential dependencies of instructions in the pass queue, determine the queue order, evaluate the electrical connectivity subgraph compatibility of instructions within each parallel execution group, and allow the parallel execution group to proceed if the compatibility meets the safe combination conditions; otherwise, it rolls back to the serial dependent execution chain to obtain an executable queue. The execution monitoring module is used to monitor the issuance and execution of multiple concurrent instructions based on the executable queue, identify new complementary combinations that appear after updates, and output a rolling optimized release sequence.

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