A hardware-aware adaptive synthesis and closed-loop re-execution method and system for a boolean function quantum oracle, a terminal, and a storage medium

Abstract

The application relates to the technical field of quantum circuit design, and discloses a hardware-aware adaptive synthesis and closed-loop re-execution method, system, terminal and storage medium of a Boolean function quantum oracle. The method comprises the following steps: obtaining a Boolean function and a quantum processor hardware description; generating a plurality of candidate circuit blocks and corresponding cover vectors of each candidate circuit block according to the Boolean function; decomposing and mapping each candidate circuit block according to the hardware description and calculating a candidate cost; under the constraint that the cover vector XOR combination is equal to the Boolean function, selecting a candidate circuit block according to the candidate cost and combining the candidate circuit block into a Boolean oracle circuit; and compiling the Boolean oracle circuit according to the hardware description to generate executable instructions. The application integrates hardware physical parameters into logic synthesis and combines closed-loop re-execution feedback, thereby improving the execution success rate of the oracle circuit on a real quantum processor.

Description

Technical Field

[0001] This invention relates to the field of quantum circuit design technology, and in particular to a hardware-aware adaptive synthesis and closed-loop re-execution method, system, terminal, and computer-readable storage medium for a Boolean function quantum oracle. Background Technology

[0002] Quantum query algorithms typically encode the problem to be solved as a Boolean oracle. In existing technologies, the logical synthesis methods for Boolean oracles usually optimize logical-level metrics such as the number of CNOT (Controlled-NOT gates), circuit depth, or the number of auxiliary qubits. Gate decomposition and qubit mapping are only performed by the compiler after logical synthesis. This sequential process of logical optimization followed by physical implementation prevents the synthesis stage from acquiring physical information such as the target quantum processor's native gate set, coupling topology, and real-time calibration parameters. This leads to logically optimal oracle circuits failing to execute on real hardware due to accumulated double-qubit gate errors, excessive routing overhead, or coupling edge limitations. Furthermore, existing methods lack feedback mechanisms for hardware execution results, making it impossible to iteratively optimize the circuit based on measured distributions and calibration drift, further hindering the reliable execution of quantum query algorithms on real quantum processors.

[0003] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0004] The main objective of this invention is to provide a hardware-aware adaptive synthesis and closed-loop re-execution method, system, terminal, and computer-readable storage medium for Boolean function quantum oracles. This aims to solve the problem in the prior art where the logic synthesis of Boolean oracles is disconnected from the physical implementation of the target quantum processor, and the lack of hardware awareness results in a low success rate of the synthesized oracle circuit on a real quantum processor.

[0005] To achieve the above objectives, this invention provides a hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles. The method includes the following steps: Obtain the Boolean function to be implemented and the hardware description of the target quantum processor; Based on the Boolean function, multiple candidate circuit blocks are generated, and a corresponding coverage vector is generated for each candidate circuit block. Based on the hardware description, each of the plurality of candidate circuit blocks is subjected to native gate decomposition and quantum bit mapping; Based on the results of the native gate decomposition and qubit mapping, the candidate cost corresponding to each candidate circuit block is calculated; Under the constraint that the coverage vectors corresponding to the plurality of candidate circuit blocks are combined by XOR operation and equal to the Boolean function, one or more candidate circuit blocks are selected from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, and the selected candidate circuit blocks are combined into a Boolean oracle circuit. Based on the hardware description, the Boolean oracle circuit is compiled to generate executable instructions for the target quantum processor.

[0006] Furthermore, the acquisition of the Boolean function to be implemented and the hardware description of the target quantum processor specifically includes: Obtain a Boolean function, wherein the Boolean function is represented in at least one of the following forms: truth table, hexadecimal encoding, Boolean expression, ESOP, XAG, BDD, gate-level network, or reversible logic network; Obtain the hardware description of the target quantum processor, wherein the hardware description includes the native gate set and the qubit coupling topology.

[0007] Furthermore, the step of generating multiple candidate circuit blocks according to the Boolean function and generating a corresponding coverage vector for each candidate circuit block specifically includes: The input space of the Boolean function is constructed as a hypercube. Base points and direction vectors are determined in the hypercube. Candidate space structures are extracted based on the base points and direction vectors to obtain multiple candidate space structures. Each of the candidate spatial structures is converted into candidate circuit blocks to obtain multiple candidate circuit blocks. The mapping relationship between each candidate circuit block and each input minterm is calculated, and the coverage vector corresponding to each candidate circuit block is generated according to the mapping relationship.

[0008] Furthermore, the step of performing native gate decomposition and qubit mapping on each of the plurality of candidate circuit blocks according to the hardware description specifically includes: Based on the native gate set in the hardware description, each logic gate in each of the plurality of candidate circuit blocks is decomposed into a combination of single-bit gates and double-bit gates contained in the native gate set; Based on the quantum bit coupling topology in the hardware description, physical quantum bits are allocated to each of the decomposed candidate circuit blocks, such that the connection relationship between the allocated physical quantum bits satisfies the connectivity requirements of the quantum bit coupling topology, and routing operations are inserted between quantum bit pairs that do not meet the connectivity requirements.

[0009] Furthermore, the step of calculating the candidate cost corresponding to each candidate circuit block based on the results of the native gate decomposition and qubit mapping specifically includes: The structural parameters corresponding to each candidate circuit block are extracted from the results of the native gate decomposition and qubit mapping. The structural parameters include the number of native two-bit gates, the number of routing operations, the critical path depth, the gate sequence duration, and the number of auxiliary qubits. The physical parameters corresponding to each candidate circuit block are extracted from the hardware description, wherein the physical parameters include error rate, decoherence parameter and crosstalk parameter, and the candidate cost corresponding to each candidate circuit block is calculated based on the structural parameters and the physical parameters.

[0010] Furthermore, under the constraint that the covering vectors corresponding to each of the plurality of candidate circuit blocks, when combined by an XOR operation, equal the Boolean function, one or more candidate circuit blocks are selected from the plurality of candidate circuit blocks based on the candidate cost corresponding to each candidate circuit block, and the selected candidate circuit blocks are combined into a Boolean oracle circuit, specifically including: Establish selection variables for each candidate circuit block, and establish constraint relationships based on the selection variables and coverage vectors of each candidate circuit block. The constraint relationships stipulate that the XOR operation result of the coverage vectors of all selected candidate circuit blocks is equal to the Boolean function. Under the constraints, based on the candidate cost corresponding to each candidate circuit block, the selection variable of each candidate circuit block is solved by an optimization algorithm. The corresponding candidate circuit block is selected based on the solved selection variable value, and the selected candidate circuit blocks are combined into a Boolean oracle circuit.

[0011] Furthermore, the step of compiling the Boolean oracle circuit according to the hardware description to generate executable instructions for the target quantum processor specifically includes: Based on the native gate set in the hardware description, perform native gate decomposition, gate cancellation, routing, pulse timing arrangement, and measurement bit mapping operations on the Boolean oracle circuit to obtain the target circuit; Each operation in the target circuit is converted into a pulse sequence or gate operation instruction that can be recognized by the target quantum processor to obtain the executable instruction.

[0012] Furthermore, to achieve the above objectives, the present invention also provides a hardware-aware adaptive synthesis and closed-loop re-execution system for Boolean function quantum oracles. This system is used to implement the hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles as described above. The system comprises: The function acquisition module is used to acquire the Boolean function to be implemented and the hardware description of the target quantum processor; The candidate generation module is used to generate multiple candidate circuit blocks according to the Boolean function, and generate a corresponding coverage vector for each candidate circuit block; The decomposition and mapping module is used to perform native gate decomposition and quantum bit mapping on each of the plurality of candidate circuit blocks according to the hardware description. The cost calculation module is used to calculate the candidate cost corresponding to each candidate circuit block based on the results of the original gate decomposition and qubit mapping. The selection and combination module is used to select one or more candidate circuit blocks from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, under the constraint that the coverage vectors corresponding to each of the plurality of candidate circuit blocks are combined by XOR operation and equal to the Boolean function, and to combine the selected candidate circuit blocks into a Boolean oracle circuit. The compilation module is used to compile the Boolean oracle circuit according to the hardware description to generate executable instructions for the target quantum processor.

[0013] Furthermore, to achieve the above objectives, the present invention also provides a terminal, wherein the terminal includes: a memory, a processor, and a hardware-aware adaptive synthesis and closed-loop re-execution program for a Boolean function quantum oracle stored in the memory and executable on the processor, wherein when the hardware-aware adaptive synthesis and closed-loop re-execution program for the Boolean function quantum oracle is executed by the processor, it implements the steps of the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle as described above.

[0014] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a hardware-aware adaptive synthesis and closed-loop re-execution program for a Boolean function quantum oracle, wherein when the hardware-aware adaptive synthesis and closed-loop re-execution program for the Boolean function quantum oracle is executed by a processor, it implements the steps of the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle as described above.

[0015] The beneficial effects of this invention are as follows: By obtaining the hardware description of the target quantum processor, the subsequent synthesis and compilation process can be based on real physical parameters rather than idealized models; by generating multiple candidate circuit blocks and their corresponding coverage vectors, the Boolean function can be flexibly decomposed at the spatial structure level, providing rich alternative units for subsequent combinatorial optimization. Performing native gate decomposition and qubit mapping on each candidate circuit block transforms the logical-level candidate structure into a physical implementation scheme that can be directly carried by the target hardware, exposing structural features affecting execution quality such as the number of double-qubit gates, routing overhead, and critical path depth; based on this, calculating the candidate cost corresponding to each candidate circuit block allows for a quantitative evaluation of the execution cost of each candidate scheme based on hardware calibration data and physical error parameters. Under the constraint that the coverage vector, after being combined through XOR operation, equals the target Boolean function, the optimal combination of candidate circuit blocks is selected based on the candidate cost. This allows for the selection of the circuit structure with the lowest hardware execution cost while ensuring functional correctness, and simultaneously utilizes the overlap cancellation characteristic to avoid redundant operations. The combined Boolean oracle circuit is compiled and executable instructions are generated. The selected optimization scheme can be transformed into pulse sequences or gate operation instructions that can be directly executed by the quantum processor, thereby completing the entire process from logic synthesis to physical execution. This ensures that the entire oracle circuit is guaranteed in terms of functional correctness, hardware compatibility and execution efficiency. Attached Figure Description

[0016] Figure 1 This is a flowchart of a preferred embodiment of the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle of the present invention; Figure 2 This is a schematic diagram of the candidate structures and covering vectors within the three-variable Boolean hypercube in this invention; Figure 3 This is a structural diagram of a preferred embodiment of the hardware-aware adaptive synthesis and closed-loop re-execution system of the Boolean function quantum oracle of the present invention; Figure 4 This is a structural diagram of a preferred embodiment of the terminal of the present invention. Detailed Implementation

[0017] This application provides a hardware-aware adaptive synthesis and closed-loop re-execution method, system, terminal, and storage medium for Boolean function quantum oracles. To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.

[0018] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0019] In this application, the Boolean oracle refers to a bit-flipping oracle, a phase oracle, or a quantum operation semantically equivalent to the target algorithm's decision. Algorithm decision events refer to the set of measurement events used to determine the algorithm's output category, such as "measured all-zero state" and "measured non-all-zero state" in the Deutsch-Jossa algorithm. Equivalence classes refer to the set of functions formed under group actions that preserve the specified algorithm decision quantity, including input variable permutation, input inversion, output inversion, or other actions. Transformation descriptors refer to data structures that record permutations, input translation vectors, input inversion vectors, output inversion bits, and optional output label mappings between the target function and its canonical representation. Candidate structures refer to parallel polyhedra, affine subspaces, subcubes, Exclusive Sum of Products (ESOP), XOR-AND-Inverter Graph (XAG) subnetworks, or other structures that can be mapped to invertible circuit blocks or phase circuit blocks within a Boolean hypercube. Cover vectors refer to the action vectors of the candidate structures on each input minterm; the target Boolean function is obtained by superimposing the cover vectors corresponding to multiple candidate structures modulo 2. Hardware description refers to the target quantum processor's native gate set, coupling graph, calibration parameters, gate duration, decoherence parameters, crosstalk parameters, readout error parameters, and resource constraints. Reliability metrics refer to the algorithm's success probability, output distribution fidelity, output distribution distance, confidence interval, expected failure rate or measured failure rate, and combinations thereof.

[0020] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0021] The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles described in the preferred embodiment of the present invention, such as... Figure 1 As shown, the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle includes the following steps: S10. Obtain the Boolean function to be implemented and the hardware description of the target quantum processor.

[0022] The purpose of this step is to obtain the input data required for subsequent logic synthesis and compilation processes, providing a data foundation for candidate circuit block generation, hardware-aware cost calculation, and compilation optimization.

[0023] Furthermore, the acquisition of the Boolean function to be implemented and the hardware description of the target quantum processor specifically includes: S11. Obtain a Boolean function, wherein the Boolean function is represented in at least one of the following forms: truth table, hexadecimal encoding, Boolean expression, ESOP, XAG, binary decision diagram (BDD), gate network, or reversible logic network. S12. Obtain the hardware description of the target quantum processor, wherein the hardware description includes the native gate set and the qubit coupling topology.

[0024] In this embodiment, the classical processor obtains the Boolean function to be implemented through the function and task interface module. This Boolean function is a single-output Boolean function, representing the problem encoded by the quantum query algorithm to be solved. The Boolean function can be input in various forms: for example, the user can directly input a truth table, which is of length 2... n The input format can accept binary or hexadecimal strings; Boolean algebra expressions; ESOP format (exclusive OR sum of multiple product terms); XAG format directed acyclic graphs; and gate-level netlists or reversible logic networks. Different input formats accommodate different user habits and upstream toolchains, enhancing the compatibility of this invention.

[0025] The classical processor simultaneously obtains the hardware description of the target quantum processor through function and task interface modules. This hardware description includes at least the native gate set of the target quantum processor (e.g., a basic gate library consisting of controlled NOT gates, Hadamard gates, Pauli X gates, etc., or a gate library consisting of controlled phase gates, Pauli Z gates, etc.) and the coupling topology between qubits, indicating which physical qubits can directly perform two-qubit gate operations. Furthermore, the hardware description may include: calibration timestamps indicating the timeliness of hardware parameters; error rates for each qubit and each coupling edge; execution times for various gate types; decoherence times for qubits; crosstalk parameters; readout errors; a list of disabled resources; and the maximum allowed line depth. These physical parameters provide accurate data support for subsequent hardware-aware cost calculations and mapping optimizations.

[0026] It should be noted that the calibration data in the hardware description is time-sensitive. The physical parameters of the quantum processor drift over time, therefore a calibration timestamp is recorded each time the hardware description is acquired. When the calibration data exceeds a preset validity period (e.g., 2 hours), the system re-acquires the latest hardware calibration data in subsequent steps to ensure the accuracy of cost calculations. The hardware description can be stored in JSON format or Protocol Buffers format for easy transfer and parsing between different modules.

[0027] S20. Generate multiple candidate circuit blocks according to the Boolean function, and generate a corresponding coverage vector for each candidate circuit block.

[0028] The purpose of this step is to decompose the Boolean function into multiple composable candidate circuit blocks at the spatial structure level, and to provide a quantitative basis for the subsequent selection of parity coverage constraints.

[0029] Furthermore, the step of generating multiple candidate circuit blocks according to the Boolean function and generating a corresponding coverage vector for each candidate circuit block specifically includes: S21. Construct the input space of the Boolean function as a hypercube, determine the base point and direction vector in the hypercube, and extract candidate space structures based on the base point and direction vector to obtain multiple candidate space structures; S22. Convert each of the candidate spatial structures into candidate circuit blocks to obtain multiple candidate circuit blocks, calculate the mapping relationship between each candidate circuit block and each input minterm, and generate the coverage vector corresponding to each candidate circuit block according to the mapping relationship.

[0030] In this embodiment, the candidate generation module treats the input space of the n-variable Boolean function as an n-dimensional hypercube, where each vertex of the hypercube corresponds to an input minterm. Given a base point and a set of direction vectors, the candidate generation module constructs a candidate structure, which represents a parallel polyhedron spanned by the base point along each direction vector, i.e., a sub-cube or affine subspace. For example, in a three-variable Boolean hypercube, the candidate structure corresponding to one direction vector is an edge (containing two vertices), the candidate structure corresponding to two direction vectors is a face (containing four vertices), and the candidate structure corresponding to three direction vectors is a complete sub-cube (containing eight vertices). Furthermore, the candidate structure is not limited to the aforementioned parallel polyhedron; the candidate generation module can also extract affine subspaces, sub-cubes, symmetric function orbitals, ESOP product terms (i.e., a set of minterms covered by a single term), or XAG subnetworks, etc.

[0031] The candidate generation module converts each candidate spatial structure into a candidate circuit block. In one implementation, the candidate circuit block adopts a "computation-use-inverse computation" structure: first, a controlled NOT gate is used to compute the linear relationship associated with the candidate structure on the input qubit, i.e., a linear combination of direction vectors is generated; then, a Pauli X operation or virtualization is applied to the conditions requiring zero control; next, a multi-controlled target flip operation (corresponding to a bit-flip oracle) or a multi-controlled phase operation (corresponding to a phase oracle) is applied; finally, the aforementioned linear relationship is reversed to restore the original state of the input qubit. This structure can save qubit resources by eliminating the need for additional auxiliary qubits.

[0032] For each candidate circuit block, the candidate generation module calculates its relationship to all 2 n The mapping relationship between each input minterm is determined, and a corresponding covering vector is generated based on this mapping relationship. The covering vector has a length of 2. n The binary vector represents whether the corresponding candidate structure applies to the corresponding input minterm: if the minterm belongs to the set covered by the candidate structure, the component is 1; otherwise, it is 0. Each candidate circuit block corresponds to a unique coverage vector. The coverage vectors of multiple candidate circuit blocks can be combined modulo 2 to obtain the target Boolean function.

[0033] It should be noted that the extraction method of the candidate spatial structure is not limited to the "base point-direction vector" method described above. In an alternative embodiment, the candidate generation module can directly use each product term in the ESOP expression as a candidate structure, and the set of input minterms covered by each product term is the coverage vector of the candidate structure. In another alternative embodiment, the candidate generation module can use the sub-networks in the XAG as candidate structures, and obtain multiple candidate circuit blocks by sub-dividing the XAG. The common point of various candidate structure extraction methods is that the target Boolean function is decomposed into a set of spatially or logically regular basic units, and each unit can be independently mapped to a quantum circuit block and participate in the subsequent coverage optimization selection.

[0034] like Figure 2 As shown, in the input space of a three-variable Boolean function (i.e., a three-dimensional Boolean hypercube), each vertex represents an input minterm. Figure 2 The set of vertices covered by a candidate block is marked with black dots. Specifically, the candidate block covers vertices 110, 011, and 001, which are connected by the same dashed circular line, indicating that they belong to the same candidate spatial structure. This candidate structure is spanned by a base point and a set of direction vectors, containing 2 m Each vertex has a geometric shape that is a parallel polyhedron (i.e., a sub-cube or affine subspace) within a hypercube.

[0035] Figure 2 The diagram simultaneously illustrates the coverage relationship of two candidate blocks. The first candidate block covers vertices 110, 011, and 001; the second candidate block covers vertices 010, 011, 100, and 101. The two candidate blocks overlap at vertex 011. According to the principle of modulo-2 parity superposition of coverage vectors of the present invention, the effects of the two candidate blocks on the overlapping vertex 011 cancel each other out. Therefore, the value of this vertex in the final oracle output is determined by the coverage state of the other selected candidate blocks on that vertex. By combining multiple candidate blocks according to modulo-2 parity superposition, the desired output of the target Boolean function on all input minterms can be accurately achieved.

[0036] Each candidate spatial structure is converted into a quantum circuit block according to a "computation-use-inverse computation" model: first, a controlled NOT gate is used to compute the linear relationship related to the candidate structure on the input qubit; then, a multi-controlled target flip operation or a multi-controlled phase operation is applied; finally, the linear relationship is reversed to restore the original state of the input qubit. This circuit block structure can complete the quantum operations corresponding to the candidate structure without using additional auxiliary qubits, thus effectively saving qubit resources. The covering vector XOR combination constraint described in step S50 is based on... Figure 2 The candidate block spatial coverage relationship and its overlap cancellation principle are shown.

[0037] S30. Based on the hardware description, perform native gate decomposition and quantum bit mapping on each of the plurality of candidate circuit blocks.

[0038] The purpose of this step is to map the candidate circuit blocks at the logic level to the physical level of the target quantum processor, thereby obtaining a physical implementation scheme for each candidate circuit block.

[0039] Further, the step of performing native gate decomposition and qubit mapping on each of the plurality of candidate circuit blocks according to the hardware description specifically includes: S31. Based on the native gate set in the hardware description, decompose each logic gate in each of the plurality of candidate circuit blocks into a combination of single-bit gates and double-bit gates contained in the native gate set. S32. Based on the quantum bit coupling topology in the hardware description, allocate physical quantum bits to each of the decomposed candidate circuit blocks, so that the connection relationship between the allocated physical quantum bits satisfies the connectivity requirements of the quantum bit coupling topology, and insert routing operations between quantum bit pairs that do not meet the connectivity requirements.

[0040] In this embodiment, the decomposition and mapping module performs independent native gate decomposition and qubit mapping on each candidate circuit block generated in step S20. First, the decomposition and mapping module reads the native gate set in the hardware description and decomposes each logic gate in the candidate circuit block into combinations of single-bit gates and two-bit gates supported by the native gate set. For example, if the native gate set of the target processor includes controlled phase gates, Pauli X gates, Hadamard gates, and Pauli S gates, and the candidate circuit block contains Tofri gates (i.e., controlled-controlled-NOT gates), then the decomposition and mapping module decomposes the Tofri gates into combinations of multiple controlled phase gates, Hadamard gates, and Pauli T gates; if the candidate circuit block contains switching gates and the hardware coupling topology does not support direct switching operations, then the decomposition and mapping module decomposes the switching gates into combinations of three controlled-NOT gates.

[0041] Then, the decomposition and mapping module assigns physical qubits to each candidate circuit block after decomposition based on the qubit coupling topology in the hardware description, i.e., determining which physical qubit corresponds to each logical qubit. During allocation, the decomposition and mapping module ensures that the physical qubits assigned to any two logical qubits that need to execute two-bit gates have a direct connection edge in the coupling topology, meaning they are adjacent. For qubit pairs that do not meet the connectivity requirement, the decomposition and mapping module inserts routing operations, such as swap gates, to gradually migrate the quantum state to a position that meets the connectivity requirement. The insertion of routing operations increases the number of two-bit gates and the line depth, but it enables circuits that were originally inoperable on the restricted topology to become executable.

[0042] In one implementation, the decomposition and mapping module generates multiple alternative decomposition and mapping schemes for each candidate circuit block, rather than generating a single scheme. For example, for the same candidate circuit block, the decomposition and mapping module may employ different Tofrigate decomposition strategies or different initial qubit allocation strategies, thereby generating multiple physical implementation variants for subsequent cost calculation modules to evaluate and select.

[0043] It should be noted that the results of native gate decomposition and qubit mapping include not only the final gate sequence and qubit allocation, but also the following structural information: the total number of native two-qubit gates, the number of routing operations, the gate sequence depth of the critical path, the execution time of the entire gate sequence, and the number of auxiliary qubits required. This structural information will be passed to step S40 for candidate cost calculation.

[0044] S40. Based on the results of the original gate decomposition and qubit mapping, calculate the candidate cost corresponding to each candidate circuit block.

[0045] The purpose of this step is to quantify the execution cost of each physical implementation scheme for each candidate circuit block on the target hardware, providing a numerical basis for subsequent optimal selection.

[0046] Further, the step of calculating the candidate cost corresponding to each candidate circuit block based on the results of the native gate decomposition and qubit mapping specifically includes: S41. Extract the structural parameters corresponding to each candidate circuit block from the results of the original gate decomposition and qubit mapping, wherein the structural parameters include the number of original two-bit gates, the number of routing operations, the critical path depth, the gate sequence duration, and the number of auxiliary qubits. S42. Extract the physical parameters corresponding to each candidate circuit block from the hardware description, wherein the physical parameters include error rate, decoherence parameter and crosstalk parameter, and calculate the candidate cost corresponding to each candidate circuit block based on the structural parameters and the physical parameters.

[0047] In this embodiment, the cost calculation module receives the native gate decomposition and qubit mapping results output by the decomposition and mapping module, and extracts the structural parameters corresponding to each candidate circuit block, including: the number of native two-qubit gates, the number of routing operations, the critical path depth, the gate sequence duration, and the number of auxiliary qubits. These structural parameters reflect the resource consumption of the candidate circuit block at the physical implementation level.

[0048] Simultaneously, the cost calculation module extracts the physical parameters corresponding to each candidate circuit block from the hardware description, including: the error rate of each gate, which is based on the fidelity data of single-qubit and two-qubit gates; the decoherence time of the qubits; and the crosstalk parameters between adjacent qubits. The cost calculation module combines the structural parameters and physical parameters to calculate the candidate cost.

[0049] ; in, Representing candidate structure In hardware description Quantum bit mapping Oracle representation The candidate cost; Indicates the number of native double-bit gates; Indicates the critical path depth or gate sequence duration; Indicates the number of routing operations; Indicates the number of auxiliary qubits; Indicates the duration of the gate sequence; This represents the failure cost based on gate fidelity and decoherence estimation; Indicates the cost of crosstalk; Indicates the cost of readout error; Weighting coefficients representing the number of native two-bit gates; Weighting coefficients representing the depth of the critical path; Weighting coefficients representing the number of routing operations; Weighting coefficients representing the number of auxiliary qubits; Weighting coefficients representing the duration of the gate sequence; Weighting coefficients representing the cost of failure; The weighting coefficients representing the cost of crosstalk; This represents the weighting coefficients for the readout error cost. Each weighting coefficient can be set by the user according to specific needs. For example, if the user chooses to optimize only the number of two-bit gates, then this weight is set to 1, and the other weights are 0. Each weight can also be automatically determined by hardware calibration data, or obtained through regression analysis based on historical execution data, or determined comprehensively through a multi-objective Pareto strategy.

[0050] Each term in the above cost formula has a clear physical meaning. The number of native two-bit gates directly affects the cumulative probability of two-bit errors; the critical path depth affects the cumulative degree of decoherence effects; the number of routing operations reflects the additional operational overhead introduced by the constraints of coupled topology; the number of auxiliary qubits reflects the occupancy of qubit resources; and the expected failure cost combines the impact of gate error rate and decoherence parameters on the probability of successful execution. All these parameters have calibration timestamps, and the candidate cost needs to be recalculated when the hardware calibration data is updated.

[0051] It should be noted that the cost calculation module calculates the candidate cost for each candidate circuit block's multiple physical implementation variants separately, and records each variant and its corresponding candidate cost for selection in subsequent steps. In an alternative implementation, the cost calculation module can iteratively interact with the decomposition mapping module in step S30: the decomposition mapping module adjusts the mapping scheme based on the cost information fed back by the cost calculation module until the physical implementation with the lowest cost is found.

[0052] S50. Under the constraint that the coverage vectors corresponding to the plurality of candidate circuit blocks are combined by XOR operation and equal to the Boolean function, one or more candidate circuit blocks are selected from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, and the selected candidate circuit blocks are combined into a Boolean oracle circuit.

[0053] The purpose of this step is to select the optimal combination from multiple candidate circuit blocks, minimize the hardware execution cost while ensuring functional correctness, and obtain the final Boolean oracle circuit.

[0054] Further, under the constraint that the covering vectors corresponding to each of the plurality of candidate circuit blocks, when combined by an XOR operation, equal the Boolean function, one or more candidate circuit blocks are selected from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, and the selected candidate circuit blocks are combined into a Boolean oracle circuit, specifically including: S51. Establish selection variables for each candidate circuit block, and establish constraint relationships based on the selection variables and coverage vectors of each candidate circuit block. The constraint relationships stipulate that the XOR operation result of the coverage vectors of all selected candidate circuit blocks is equal to the Boolean function. S52. Under the constraints, based on the candidate cost corresponding to each candidate circuit block, the selection variable of each candidate circuit block is solved by an optimization algorithm. The corresponding candidate circuit block is selected based on the solved selection variable value, and the selected candidate circuit blocks are combined into a Boolean oracle circuit.

[0055] In this embodiment, the hardware cost optimization module obtains the coverage vector of each candidate circuit block from step S20, and the candidate cost of each candidate circuit block under each physical mapping from steps S30 and S40. The hardware cost optimization module establishes a binary selection variable for each candidate circuit block. The variable takes a value of 1 to indicate that the candidate circuit block is selected, and a value of 0 indicates that it is not selected. Let... Indicates candidate circuit block The covering vector in the minterm The value of . To accurately implement the target Boolean function. The hardware cost optimization module applies the following modulo 2 parity constraint: ; in, Representing candidate structure Does it apply to the input minterm? , An equal value of 1 indicates that the action applies to that minterm. An equal value of 0 indicates that it does not apply to that minterm; Representing candidate structure Binary choice variables, A value of 1 indicates that the candidate structure is selected. A value of 0 indicates that the candidate structure is not selected; This represents the target Boolean function in response to the input minterm. The value of is either 0 or 1; n represents the number of input variables for the Boolean function. This represents the input minterm, whose value range is... This constraint requires that for each input minterm, the remainder of the sum of the coverage values ​​of all selected candidate circuit blocks on that minterm divided by 2 is equal to the value of the target Boolean function on that minterm. In other words, the bitwise XOR of the coverage vectors of all selected candidate circuit blocks must be exactly equal to the truth table of the target Boolean function. This constraint guarantees that the combined oracle circuit is functionally completely equivalent to the target Boolean function.

[0056] Among all solutions satisfying the above constraints, the hardware cost optimization module calculates the optimal value of the selection variable based on the candidate costs of each candidate circuit block under each physical mapping using an optimization algorithm. The optimization objective is to minimize the sum of the candidate costs of all selected candidate circuit blocks. This optimization problem can be solved using at least one of the following methods: integer linear programming, zero-one programming, pseudo-Boolean optimization, satisfiability problem solving, satisfiability modular theory solving, maximum satisfiability problem solving, dynamic programming, branch and bound algorithm, or heuristic search algorithm. Integer linear programming and zero-one programming are suitable for scenarios with a small number of candidate circuit blocks and moderate constraint scale; satisfiability problem solving and satisfiability modular theory solving methods are suitable for scenarios with strong constraint logic; dynamic programming and branch and bound are suitable for problems with special structures (such as tree structures); heuristic search (such as simulated annealing and genetic algorithms) is suitable for quickly finding approximate optimal solutions in large-scale problems.

[0057] After the solution is obtained, the hardware cost optimization module selects the corresponding candidate circuit blocks from multiple candidate circuit blocks based on the values ​​of the selection variables obtained from the solution. The selected candidate circuit blocks are then combined into a complete Boolean oracle circuit according to the logical relationship of their coverage vectors. During the combination process, when multiple selected candidate circuit blocks overlap on the input minterms, the overlapping parts are automatically canceled out due to the property of modulo 2 addition, thereby accurately reproducing the truth table of the target Boolean function.

[0058] It should be noted that the above optimization process can be executed in one of two modes. In the independent optimization mode, each candidate circuit block first completes physical mapping and cost calculation, and then the mapped candidate costs are input into the optimization model. After solving the selection variables, they are directly combined. In the joint optimization mode, the mapping variables, edge occupancy variables, and oracle representation selection variables are included in the same optimization model for joint solution along with the selection variables. The joint optimization mode can usually obtain a globally better solution, but the solution complexity is higher. In addition, after this step, the system can perform at least one of the following on the combined Boolean oracle circuit: formal verification, truth table verification, state vector verification, or random input verification, to ensure the correctness of the circuit function and output a traceable record from the target Boolean function to the canonical representative, candidate circuit blocks, physical mapping, and measurement decoding rules.

[0059] S60. Based on the hardware description, compile the Boolean oracle circuit to generate executable instructions for the target quantum processor.

[0060] The purpose of this step is to convert the selected Boolean oracle circuit into an instruction format that the target quantum processor can directly execute, thus completing the entire process from logic synthesis to physical execution.

[0061] Furthermore, the step of compiling the Boolean oracle circuit according to the hardware description to generate executable instructions for the target quantum processor specifically includes: S61. Based on the native gate set in the hardware description, perform native gate decomposition, gate cancellation, routing, pulse timing arrangement, and measurement bit mapping operations on the Boolean oracle circuit to obtain the target circuit; S62. Convert each operation in the target circuit into a pulse sequence or gate operation instruction that can be recognized by the target quantum processor to obtain the executable instruction.

[0062] In this embodiment, the selection and compilation module receives the Boolean oracle circuit output by the hardware cost optimization module. This circuit includes a selected combination of candidate circuit blocks and their corresponding physical mapping, qubit allocation, and oracle representation. The selection and compilation module compiles this circuit to generate executable instructions that can be executed by the target quantum processor. The selection and compilation module first performs a native gate decomposition operation on each logic gate in the Boolean oracle circuit based on the native gate set in the hardware description, decomposing the remaining multi-bit gates that have not yet been decomposed into combinations of native single-bit and double-bit gates. Then, it performs a gate cancellation operation to merge adjacent redundant gates or gate pairs that are inverse operations to reduce the number of gates. It then performs a routing operation to insert swap gates or equivalent operations between qubits that need to be connected across distances. Finally, it performs a pulse timing arrangement operation to arrange the gate operations in chronological order to optimize the timing of parallel execution. Finally, it performs a measurement bit mapping operation to map logical measurement bits to physical readout bits.

[0063] After completing the above compilation and optimization operations, the selection and compilation module obtains the target circuit. This target circuit consists of a series of native gate operations and measurement operations, all of which are mapped to specific physical qubits and time slots. The selection and compilation module then converts each operation in the target circuit into a pulse sequence recognizable by the target quantum processor. For example, for a superconducting quantum processor, this is converted into a microwave pulse parameter sequence of the corresponding frequency; or into gate operation instructions, such as for an ion trap quantum processor, into corresponding laser pulse sequence parameters. Finally, it generates executable instructions that can be directly executed on the target quantum processor. These executable instructions are submitted to the target quantum processor for execution through the quantum processor interface module.

[0064] After execution, the quantum processor interface module returns the measurement count. The measurement evaluation module calculates reliability metrics based on the measurement count. Reliability metrics include the algorithm's success probability and the consistency between the measured distribution and the ideal distribution. The success probability is defined as the frequency of correctly classified events. For constant functions, a correct event is a measured all-zero state; for equilibrium functions, a correct event is a measured non-all-zero state. The consistency between the measured distribution and the ideal distribution is evaluated using at least one of Bavarian fidelity or total variation distance. Bavarian fidelity is calculated using the following formula: ; in, Represents the measured distribution Compared with the ideal distribution The Paasche fidelity between the two distributions ranges from 0 to 1, with the value being closer to 1 indicating that the two distributions are more consistent. The index represents the base state of the calculation, and its value range covers all possible measurement output states; Represents the state in the measured distribution The frequency of occurrence; Represents the state in an ideal distribution The theoretical probability; Represents all possible output states Summation. Total variation distance. Calculated by the following formula: ; in, Represents the measured distribution Compared with the ideal distribution The total variation distance between the two distributions ranges from 0 to 1, with values ​​closer to 0 indicating greater consistency. Dual-indicator evaluation avoids masking distribution degradation by using only a single success rate indicator, and also avoids the shortcomings of evaluating only the maximum probability state when certain ideal distributions are not unimodal.

[0065] If the success probability is below a threshold, the distribution consistency is below a threshold, or the confidence interval does not meet the requirements, the feedback control module performs at least one update operation: read the latest calibration data; increase the cost of abnormal coupling edges or qubits; shield abnormal resources; switch bit flipping or phase oracles; select another NPN representative candidate; change the physical mapping; change the circuit block order; increase error mitigation; or resolve the parity constraint. Measured data can be used to update the candidate cost in reverse, for the . Based on round costs and measurement-based estimated costs, the feedback control module calculates updated costs using an exponential update method: ; in, Indicates the first The updated candidate cost; Indicates the first The candidate cost used during round optimization; Indicates based on the first Candidate costs estimated from wheel measurement results; This represents the learning rate or update step size, with a value range of [value missing]. , The larger the value of , the greater the impact of the measurement results on cost updates.

[0066] Schemes that reach the threshold are written to the template cache. The cache key includes the function specification representative, transform descriptor, algorithm type, processor model, calibration time window, qubit map, oracle representation, and compiler version. When the same type of function is executed again, the cache is reused and verified first.

[0067] In one implementation, the representation selection and compilation module performs an adaptive selection operation for the bit-flip oracle and phase oracle before compilation. For scenarios where the target algorithm only requires the function phase, such as the Deutsch-Jossa algorithm and phase estimation algorithms, the representation selection and compilation module generates candidate implementations of the bit-flip oracle and phase oracle respectively, calculates the candidate cost of each on the target processor, and selects the oracle representation with the lower candidate cost or higher expected success rate. The standard form of the bit-flip oracle is: keeping the first register state unchanged, and outputting the second register state after XORing with the function value. When the target qubit is prepared in a specific state, the bit-flip oracle generates a phase factor equivalently through phase kickback. The standard form of the phase oracle is: applying a phase factor to the input state based on the function value. The phase oracle directly applies a phase related to the function value to the input register, without setting the output target qubit. On platforms where controlled phase gates, controlled phase rotation gates, or other diagonally entangled operations are the native gates, direct phase oracles can omit the target qubit, reducing the number of Hadamard gate transformations and two-qubit gates; while on platforms where controlled NOT gates or fully connected controlled operations are advantageous, bit-flip oracles may be superior. The representation selection and compilation module automatically selects the optimal oracle representation based on the target processor's native gate set and physical parameters, and can also output multiple candidate schemes for actual comparison in subsequent execution stages.

[0068] It should be noted that the Boolean oracle synthesis and compilation method of this invention is not only applicable to the Deutsch-Chosa algorithm, but can also be extended to the Bernstein-Wazlani algorithm, Grover search algorithm, periodic search algorithm, amplitude estimation algorithm, quantum counting algorithm, and quantum optimization algorithm based on Boolean constraints. For different algorithms, the system records the algorithm type, input state preparation method, oracle query position, measurement basis, and correct decision event through the task object, and adjusts the virtualizable transformation set and decision event accordingly. For example, for the Bernstein-Wazlani algorithm, the system can further optimize the synthesis result by utilizing the linear function structure and output label mapping.

[0069] Based on the above steps S10 to S60, the method of the present invention will be further described below through specific embodiments.

[0070] Example 1: Implementation of the complete family of functions for the three-variable Doyche-Chosa algorithm.

[0071] In this embodiment, the goal is to implement all 70 balance functions of the three-variable Deutsch-Chosa algorithm on a real quantum processor. There are 2^(2³) = 256 three-variable Boolean functions, of which the number of balance functions is C(8,4), which equals 70. These 70 balance functions are classified using Negation-Permutation-Negation (NPN), resulting in six canonical representations corresponding to hexadecimal values ​​0x0F, 0x17, 0x1B, 0x1E, 0x66, and 0x69; constant functions 0x00 and 0xFF are also added.

[0072] The specific execution steps are as follows: First, the classical processor obtains the truth table of each objective function through the function and task interface module, and calculates the canonical representation and transformation descriptor of each objective function through the equivalence class processing module. The transformation descriptor includes the input permutation matrix, the input inverted vector, and the output inverted bit. Second, the classical processor reads the native gate set, available four-qubit subgraph, gate error rate, gate duration, decoherence parameters, and readout parameters of the target processor to obtain a complete hardware description. Then, the candidate generation module generates multiple candidate circuit blocks for the six representative functions, including candidate circuit blocks consisting only of controlled NOT gates, candidate circuit blocks containing one Tofri gate, bit-flip oracle candidate circuit blocks, and phase oracle candidate circuit blocks. Each candidate circuit block generates a corresponding coverage vector. Next, the decomposition and mapping module and the cost calculation module perform native gate decomposition, qubit mapping, and candidate cost calculation on each candidate circuit block according to the hardware description. Under the constraint that the XOR combination of the coverage vectors of each candidate circuit block equals the objective function, the hardware cost optimization module selects the optimal combination scheme from multiple candidate circuit blocks based on the candidate cost.

[0073] During the compilation phase, the representation selection and compilation module prioritizes converting input permutations into the initial layout of physical qubits to avoid inserting swap gates; it converts input inversion into Pauli frames or boundary Pauli X-gate processing; and it treats output inversion as a global phase omission in phase oracle mode without physical implementation. Then, the representation selection and compilation module embeds the selected circuit into the Deutsch-Jossa algorithm framework, which includes a Hadamard gate preparation layer for the input qubits, an oracle query layer, a second Hadamard gate layer, and measurement operations. After compilation, the quantum processor interface module submits the executable instructions to the target quantum processor, performs a predetermined number of measurements, and records the measurement counts for each computational basis state. The measurement evaluation module calculates the classification success probability and distribution fidelity based on the measurement counts. If the success probability or distribution fidelity is lower than a preset threshold, the feedback control module triggers a resynthesis operation: changing the physical mapping scheme of the candidate circuit block, switching the bit flip or phase oracle representation, or selecting another equivalence class to represent the candidate scheme, and repeating the above synthesis and execution process.

[0074] Through the above process, the minimum success probability of each representative function can exceed 91.3%, the average success probability of the six balanced functions exceeds 94%, and the average success probability of the eight functions (including constant functions) is about 93.7%, which verifies the effectiveness, scalability and hardware adaptability of the present invention on the complete function family.

[0075] Example 2: Implementation of a direct phase oracle on a controlled phase gate native platform.

[0076] In this embodiment, the target processor uses controlled phase gates as the native entanglement gates. For the representative function 0x17 in the Deutsch-Jossa algorithm, this indicates the selection and compilation module to construct a direct phase oracle instead of a bit-flipping oracle. The input register directly performs phase operations related to the function value, without setting the output target qubit. For the output inversion bit in the NPN transform, since multiplying the phase factor by -1 does not change the measurement probability distribution, the output inversion bit is only written to the transform descriptor without any physical gate implementation. Input permutation is achieved through the initial qubit layout, avoiding the insertion of swap gates. The hardware cost optimization module compares the number of native two-qubit gates, critical path time, and expected failure rate of the three-qubit direct phase circuit and the four-qubit bit-flipping circuit on the target processor. When the direct phase circuit passes functional verification and has a lower candidate cost, the selection and compilation module selects this scheme; otherwise, it reverts to the bit-flipping mode. This embodiment demonstrates that the present invention can adaptively select the optimal oracle representation based on the native gate set of the target processor, thereby effectively saving qubit resources and reducing the number of entanglement gates.

[0077] Example 3: Calibration-driven mapping and resynthesis.

[0078] In this embodiment, it is assumed that the candidate circuit block requires two frequently used coupling edges. The system reads the current hardware calibration data through the hardware cost optimization module and finds that the error rate of one coupling edge in the default mapping scheme is significantly increased or the crosstalk parameter is abnormal. The system automatically increases the weight of the failure cost and crosstalk cost of this coupling edge and re-evaluates the candidate costs of candidate circuit blocks B and C on other available connected subgraphs. After the first execution, if the measurement evaluation module finds that the theoretically concentrated measurement state probability is significantly flattened, for example, the total variation distance is too large, it is marked as "high probability of entanglement gate or routing operation cumulative error", triggering the feedback control module to perform the following operations: shielding abnormal coupling edges, reducing the critical depth of the line, switching the phase oracle representation, or selecting another equivalence class to represent the candidate scheme. The second scheme that reaches the reliability threshold is written into the template cache together with the current calibration time window. This embodiment demonstrates the rapid adaptability of the closed-loop feedback mechanism of the present invention to hardware calibration drift and abnormal states.

[0079] Example 4: Extending to other quantum query algorithms.

[0080] The synthesis and compilation methods of this invention are not limited to the Deutsch-Chosa algorithm. For the Bernstein-Wazlani algorithm, the system utilizes the structural characteristics of linear functions, namely, the Walsh transform coefficients of all minterms are concentrated at a non-zero point, further simplifying the generation and optimization selection of candidate structures. For the Grover search algorithm, the system synthesizes the Boolean tagging function into a phase oracle and optimizes the phase oracle and Grover diffusion operator separately, reducing the hardware cost per iteration while maintaining search accuracy. For periodic search, amplitude estimation, quantum counting, and Boolean-constrained quantum optimization algorithms, the system writes the decision invariants, allowed symmetry groups, and hardware cost weights corresponding to each algorithm into the task object, and adaptively adjusts the candidate structure generation and optimization strategies according to the configuration of the task object. The set of virtualizable transformations differs in different quantum algorithms. For example, the Deutsch-Chosa algorithm allows virtualization of complete NPN equivalent transformations, while the Bernstein-Wazlani algorithm only allows virtualization of input permutation and output inversion. Input inversion may change the coefficients of the objective linear function, therefore it cannot be fully virtualized. The system limits parameters by using the equivalence group in the task object to avoid improper generalization of probability invariants specific to a certain algorithm to other algorithms.

[0081] Furthermore, such as Figure 3 As shown, based on the above-mentioned hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles, this invention also provides a hardware-aware adaptive synthesis and closed-loop re-execution system for Boolean function quantum oracles. The hardware-aware adaptive synthesis and closed-loop re-execution system for Boolean function quantum oracles includes: The function acquisition module 51 is used to acquire the Boolean function to be implemented and the hardware description of the target quantum processor; The candidate generation module 52 is used to generate multiple candidate circuit blocks according to the Boolean function, and generate a corresponding coverage vector for each candidate circuit block; The decomposition and mapping module 53 is used to perform native gate decomposition and quantum bit mapping on each of the plurality of candidate circuit blocks according to the hardware description. The cost calculation module 54 is used to calculate the candidate cost corresponding to each candidate circuit block based on the results of the original gate decomposition and quantum bit mapping. The selection and combination module 55 is used to select one or more candidate circuit blocks from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, under the constraint that the coverage vectors corresponding to each of the plurality of candidate circuit blocks are combined by XOR operation and equal to the Boolean function, and to combine the selected candidate circuit blocks into a Boolean oracle circuit. The compilation module 56 is used to compile the Boolean oracle circuit according to the hardware description to generate executable instructions for the target quantum processor.

[0082] Furthermore, such as Figure 4 As shown, based on the above-mentioned hardware-aware adaptive synthesis and closed-loop re-execution method and system for Boolean function quantum oracle, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 4 Only some of the terminal components are shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0083] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory. In other embodiments, the memory 20 may be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Further, the memory 20 may include both internal and external storage devices. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code installed on the terminal. The memory 20 can also be used to temporarily store data that has been output or will be output. In one embodiment, the memory 20 stores a hardware-aware adaptive synthesis and closed-loop re-execution program 40 for a Boolean function quantum oracle. This hardware-aware adaptive synthesis and closed-loop re-execution program 40 can be executed by the processor 10, thereby implementing the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle in this application.

[0084] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run program code stored in the memory 20 or process data, such as executing the hardware-aware adaptive synthesis and closed-loop re-execution method of the Boolean function quantum oracle.

[0085] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display 30 is used to display information on the terminal and to display a visual user interface. The components of the terminal communicate with each other via a system bus.

[0086] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a hardware-aware adaptive synthesis and closed-loop re-execution program for a Boolean function quantum oracle, and the hardware-aware adaptive synthesis and closed-loop re-execution program for the Boolean function quantum oracle, when executed by a processor, implements the steps of the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle as described above.

[0087] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal. Unless otherwise specified, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or terminal that includes that element.

[0088] Of course, those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0089] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A hardware-aware adaptive synthesis and closed-loop re-execution method for a Boolean function quantum oracle, characterized in that, The hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle includes the following steps: Obtain the Boolean function to be implemented and the hardware description of the target quantum processor; Based on the Boolean function, multiple candidate circuit blocks are generated, and a corresponding coverage vector is generated for each candidate circuit block. Based on the hardware description, each of the plurality of candidate circuit blocks is subjected to native gate decomposition and quantum bit mapping; Based on the results of the native gate decomposition and qubit mapping, the candidate cost corresponding to each candidate circuit block is calculated; Under the constraint that the coverage vectors corresponding to the plurality of candidate circuit blocks are combined by XOR operation and equal to the Boolean function, one or more candidate circuit blocks are selected from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, and the selected candidate circuit blocks are combined into a Boolean oracle circuit. Based on the hardware description, the Boolean oracle circuit is compiled to generate executable instructions for the target quantum processor.

2. The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles according to claim 1, characterized in that, The acquisition of the Boolean function to be implemented and the hardware description of the target quantum processor specifically includes: Obtain a Boolean function, wherein the Boolean function is represented in at least one of the following forms: truth table, hexadecimal encoding, Boolean expression, ESOP, XAG, BDD, gate-level network, or reversible logic network; Obtain the hardware description of the target quantum processor, wherein the hardware description includes the native gate set and the qubit coupling topology.

3. The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles according to claim 1, characterized in that, The step of generating multiple candidate circuit blocks according to the Boolean function and generating a corresponding coverage vector for each candidate circuit block specifically includes: The input space of the Boolean function is constructed as a hypercube. Base points and direction vectors are determined in the hypercube. Candidate space structures are extracted based on the base points and direction vectors to obtain multiple candidate space structures. Each of the candidate spatial structures is converted into candidate circuit blocks to obtain multiple candidate circuit blocks. The mapping relationship between each candidate circuit block and each input minterm is calculated, and the coverage vector corresponding to each candidate circuit block is generated according to the mapping relationship.

4. The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles according to claim 1, characterized in that, The step of performing native gate decomposition and qubit mapping on each of the plurality of candidate circuit blocks according to the hardware description specifically includes: Based on the native gate set in the hardware description, each logic gate in each of the plurality of candidate circuit blocks is decomposed into a combination of single-bit gates and double-bit gates contained in the native gate set; Based on the quantum bit coupling topology in the hardware description, physical quantum bits are allocated to each of the decomposed candidate circuit blocks, such that the connection relationship between the allocated physical quantum bits satisfies the connectivity requirements of the quantum bit coupling topology, and routing operations are inserted between quantum bit pairs that do not meet the connectivity requirements.

5. The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles according to claim 1, characterized in that, The step of calculating the candidate cost for each candidate circuit block based on the results of the native gate decomposition and qubit mapping specifically includes: The structural parameters corresponding to each candidate circuit block are extracted from the results of the native gate decomposition and qubit mapping. The structural parameters include the number of native two-bit gates, the number of routing operations, the critical path depth, the gate sequence duration, and the number of auxiliary qubits. The physical parameters corresponding to each candidate circuit block are extracted from the hardware description, wherein the physical parameters include error rate, decoherence parameter and crosstalk parameter, and the candidate cost corresponding to each candidate circuit block is calculated based on the structural parameters and the physical parameters.

6. The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles according to claim 1, characterized in that, Under the constraint that the coverage vectors corresponding to the plurality of candidate circuit blocks, when combined by an XOR operation, equal the Boolean function, one or more candidate circuit blocks are selected from the plurality of candidate circuit blocks based on the candidate cost corresponding to each candidate circuit block, and the selected candidate circuit blocks are combined into a Boolean oracle circuit, specifically including: Establish selection variables for each candidate circuit block, and establish constraint relationships based on the selection variables and coverage vectors of each candidate circuit block. The constraint relationships stipulate that the XOR operation result of the coverage vectors of all selected candidate circuit blocks is equal to the Boolean function. Under the constraints, based on the candidate cost corresponding to each candidate circuit block, the selection variable of each candidate circuit block is solved by an optimization algorithm. The corresponding candidate circuit block is selected based on the solved selection variable value, and the selected candidate circuit blocks are combined into a Boolean oracle circuit.

7. The hardware-aware adaptive synthesis and closed-loop re-execution method for Boolean function quantum oracles according to claim 1, characterized in that, The step of compiling the Boolean oracle circuit according to the hardware description to generate executable instructions for the target quantum processor specifically includes: Based on the native gate set in the hardware description, perform native gate decomposition, gate cancellation, routing, pulse timing arrangement, and measurement bit mapping operations on the Boolean oracle circuit to obtain the target circuit; Each operation in the target circuit is converted into a pulse sequence or gate operation instruction that can be recognized by the target quantum processor to obtain the executable instruction.

8. A hardware-aware adaptive synthesis and closed-loop re-execution system for a Boolean function quantum oracle, characterized in that, The hardware-aware adaptive synthesis and closed-loop re-execution system for the Boolean function quantum oracle is used to implement the hardware-aware adaptive synthesis and closed-loop re-execution method for the Boolean function quantum oracle as described in any one of claims 1-7. The hardware-aware adaptive synthesis and closed-loop re-execution system for the Boolean function quantum oracle comprises: The function acquisition module is used to acquire the Boolean function to be implemented and the hardware description of the target quantum processor; The candidate generation module is used to generate multiple candidate circuit blocks according to the Boolean function, and generate a corresponding coverage vector for each candidate circuit block; The decomposition and mapping module is used to perform native gate decomposition and quantum bit mapping on each of the plurality of candidate circuit blocks according to the hardware description. The cost calculation module is used to calculate the candidate cost corresponding to each candidate circuit block based on the results of the original gate decomposition and qubit mapping. The selection and combination module is used to select one or more candidate circuit blocks from the plurality of candidate circuit blocks according to the candidate cost corresponding to each candidate circuit block, under the constraint that the coverage vectors corresponding to each of the plurality of candidate circuit blocks are combined by XOR operation and equal to the Boolean function, and to combine the selected candidate circuit blocks into a Boolean oracle circuit. The compilation module is used to compile the Boolean oracle circuit according to the hardware description to generate executable instructions for the target quantum processor.

9. A terminal, characterized in that, The terminal includes: a memory, a processor, and a hardware-aware adaptive synthesis and closed-loop re-execution program for a Boolean function quantum oracle stored in the memory and executable on the processor. When the hardware-aware adaptive synthesis and closed-loop re-execution program for the Boolean function quantum oracle is executed by the processor, it implements the steps of the hardware-aware adaptive synthesis and closed-loop re-execution method for a Boolean function quantum oracle as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a hardware-aware adaptive synthesis and closed-loop re-execution program for a Boolean function quantum oracle, which, when executed by a processor, implements the steps of the hardware-aware adaptive synthesis and closed-loop re-execution method for a Boolean function quantum oracle as described in any one of claims 1-7.

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