Display apparatus and electronic device including the same

Abstract

A display device and an electronic apparatus including the same are provided. The display device includes a substrate including a first display area and a second display area, the second display area including a circuit area and a transmissive area; a first pixel circuit in the first display area and a first light emitting diode electrically connected to the first pixel circuit; and a second pixel circuit in the second display area and a second light emitting diode electrically connected to the second pixel circuit, wherein each of the first pixel circuit and the second pixel circuit includes a driving transistor including a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; and a data write transistor electrically connected between a data line and the first node.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0039696, filed on March 27, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device and an electronic device including the display device. Background Technology

[0003] The display device includes a display panel, and the display panel includes display elements that realize pixels and pixel circuitry for controlling electrical signals applied to the display elements. The pixel circuitry may include transistors, at least one capacitor, and multiple wirings.

[0004] Recently, the applications of display devices have become more diversified. Furthermore, display devices have become thinner and lighter, and their applications have expanded. As display devices are used in various electronic devices, the functions integrated into or linked to display devices are increasing. Summary of the Invention

[0005] The area where a component (e.g., an electronic component) is located may include a transmissive region through which light emitted from and / or directed towards the component can be transmitted. Therefore, fewer pixels are arranged in the area where the component is located compared to the surrounding display area, and thus the brightness difference may be perceived by the user.

[0006] One or more embodiments of this disclosure include a display device for displaying high-quality images by improving the brightness of an area where components are disposed, and an electronic device including the display device. However, such aspects are exemplary, and the scope of this disclosure is not limited thereto.

[0007] Additional aspects and features will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments given in this disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including a first display area and a second display area, the second display area including a circuit area and a transmissive area; a first pixel circuit and a first light-emitting diode, the first pixel circuit being in the first display area and the first light-emitting diode being electrically connected to the first pixel circuit; and a second pixel circuit and a second light-emitting diode, the second pixel circuit being in the second display area and the second light-emitting diode being electrically connected to the second pixel circuit, wherein each of the first pixel circuit and the second pixel circuit includes: a driving transistor including a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; a data writing transistor electrically connected between a data line and the first node; a first emission control transistor electrically connected between a driving voltage line and the second node; and a second emission control transistor electrically connected between the third node and a corresponding light-emitting diode among the first and second light-emitting diodes, and wherein the second emission control transistor of the second pixel circuit remains in an on state during a frame.

[0009] According to one or more embodiments, the first emission control transistor of each of the first pixel circuit and the second pixel circuit is turned on or off according to a first emission control signal; the second emission control transistor of the first pixel circuit is turned on or off according to a second emission control signal different from the first emission control signal; and the second emission control transistor of the second pixel circuit is turned on according to a third emission control signal.

[0010] According to one or more embodiments, a frame includes a first scan period and at least one second scan period; the first scan period includes a first period in which a second transmit control signal is supplied as a cutoff voltage; and during at least one second scan period, the second transmit control signal is supplied as an on voltage.

[0011] According to one or more embodiments, a third transmit control signal is supplied as an on-state voltage during a first scan period and at least one second scan period.

[0012] According to one or more embodiments, the driving transistor includes an oxide semiconductor layer.

[0013] According to one or more embodiments, the first emitter control transistor includes a silicon semiconductor layer.

[0014] According to one or more embodiments, each of the first pixel circuit and the second pixel circuit further includes: a first initialization transistor electrically connected between a reference voltage line and a driving transistor; and a second initialization transistor electrically connected between the initialization voltage line and a corresponding light-emitting diode among the first light-emitting diode and the second light-emitting diode.

[0015] According to one or more embodiments, a display device includes: a substrate including a first display area and a second display area, the second display area including a circuit area and a transmissive area; a first pixel circuit and a first light-emitting diode, the first pixel circuit being in the first display area and the first light-emitting diode being connected to the first pixel circuit; and a second pixel circuit and a second light-emitting diode, the second pixel circuit being in the second display area and the second light-emitting diode being electrically connected to the second pixel circuit, wherein each of the first pixel circuit and the second pixel circuit includes: a driving transistor including a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; a data writing transistor electrically connected between a data line and the first node; and a first emission control transistor electrically connected between a driving voltage line and the second node, wherein the first pixel circuit further includes a second emission control transistor electrically connected between the first light-emitting diode and the third node, and wherein the third node and the second light-emitting diode of the second pixel circuit are electrically connected via a wire.

[0016] According to one or more embodiments, the second pixel circuit further includes a third emission control transistor electrically connected between the second light-emitting diode and the third node, and includes a gate electrode and a semiconductor layer disposed below the gate electrode.

[0017] According to one or more embodiments, the semiconductor layer of the third emitter control transistor includes a channel region superimposed on the gate electrode and source and drain regions on opposite sides of the channel region; and wires electrically connect the source and drain regions of the third emitter control transistor.

[0018] According to one or more embodiments, the second emitter control transistor in the first pixel circuit includes a first semiconductor layer, the first semiconductor layer including a gate electrode, a channel region superimposed on the gate electrode, and source and drain regions on opposite sides of the channel region; and the wires in the second pixel circuit include a second semiconductor layer having a shape corresponding to the first semiconductor layer.

[0019] According to one or more embodiments, the display device further includes: an emission control line configured to transmit an emission control signal to the gate electrode of a second emission control transistor, wherein the emission control line intersects with a second semiconductor layer.

[0020] According to one or more embodiments, the display device further includes: an emission control line configured to transmit an emission control signal to the gate electrode of a second emission control transistor; and an auxiliary emission control line between the substrate and the second semiconductor layer, wherein the emission control line is electrically connected to the auxiliary emission control line.

[0021] According to one or more embodiments, the driving transistor includes an oxide semiconductor layer.

[0022] According to one or more embodiments, the first emitter control transistor includes a silicon semiconductor layer.

[0023] According to one or more embodiments, each of the first pixel circuit and the second pixel circuit further includes: a first initialization transistor electrically connected between a reference voltage line and a driving transistor; and a second initialization transistor electrically connected between the initialization voltage line and a corresponding light-emitting diode among the first light-emitting diode and the second light-emitting diode.

[0024] According to one or more embodiments, an electronic device includes: a display device configured to display an image; a memory for storing an application; and a processor configured to execute the application and transmit image data signals or control signals to the display device, wherein the display device includes: a substrate including a first display area and a second display area, the second display area including a circuit area and a transmissive area; a first pixel circuit and a first light-emitting diode, the first pixel circuit being in the first display area and the first light-emitting diode being connected to the first pixel circuit; and a second pixel circuit and a second light-emitting diode, the second pixel circuit being in the second display area and the second light-emitting diode being electrically connected to the second pixel circuit, wherein each of the first pixel circuit and the second pixel circuit includes: a driving transistor including a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; a data writing transistor electrically connected between a data line and the first node; and a first emission control transistor electrically connected between a driving voltage line and the second node, wherein the first pixel circuit further includes a second emission control transistor electrically connected between the first light-emitting diode and the third node, and wherein the third node and the second light-emitting diode of the second pixel circuit are electrically connected through a conductive path.

[0025] According to one or more embodiments, the second pixel circuit further includes a third emission control transistor electrically connected between the second light-emitting diode and a third node of the second pixel circuit; and the third emission control transistor remains in an on state.

[0026] According to one or more embodiments, the third node of the second pixel circuit and the second light-emitting diode are electrically connected via wires.

[0027] According to one or more embodiments, the driving transistor includes an oxide semiconductor layer. Attached Figure Description

[0028] The above and other aspects and features of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 It is a schematic block diagram of a display device according to one or more embodiments; Figure 2It is a schematic plan view of a display panel according to one or more embodiments; Figure 3 This is a schematic cross-sectional view of a display device according to one or more embodiments; Figure 4 It is a schematic plan view of a portion of a display panel according to one or more embodiments; Figure 5 It is a schematic plan view of the pixel arrangement in a first display area according to one or more embodiments; Figure 6 It is a schematic plan view of the pixel arrangement in a second display area according to one or more embodiments; Figure 7 It is an equivalent circuit diagram of the main pixel according to one or more embodiments; Figure 8 It is an equivalent circuit diagram of an auxiliary pixel according to one or more embodiments; Figure 9 It is a schematic representation of the supply to Figure 7 A diagram of the signals of the main pixels; Figure 10 It is a schematic representation of the supply to Figure 8 A diagram of the signals of the auxiliary pixels; Figure 11 It is an equivalent circuit diagram of an auxiliary pixel according to one or more embodiments; Figure 12A This is a schematic cross-sectional view of the first display area of ​​a display panel according to one or more embodiments. Figure 12B This is a schematic cross-sectional view of the second display area of ​​a display panel according to one or more embodiments; Figure 13 It is an equivalent circuit diagram of an auxiliary pixel according to one or more embodiments; Figure 14 and Figure 15 Each of these is a schematic cross-sectional view showing a second display area of ​​a display panel according to one or more embodiments; Figure 16A , Figure 16B and Figure 16C It is a graph showing the drive current of the main pixel circuit and the auxiliary pixel circuit relative to the data voltage according to one or more embodiments; Figure 17 It is a schematic block diagram of an electronic device according to one or more embodiments; and Figure 18 , Figure 19 and Figure 20 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0029] Referring now to embodiments in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain aspects of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0030] The effects, aspects, and features of this disclosure, as well as the methods for achieving them, will be illustrated by referring to the embodiments described in detail below with reference to the accompanying drawings.

[0031] In the instruction manual, terms such as "first" and "second" are not used in a restrictive sense, but rather to distinguish one component from another.

[0032] In the specification, unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0033] The terms “comprising” and “having” as used in this specification mean that the features or components described in the specification are present, and do not exclude the possibility that one or more other features or components may be added.

[0034] In the specification, it will also be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, the layer, region, or component may be directly on the other layer, region, or component, or may be indirectly on the other layer, region, or component, and an intermediary layer, region, or component is located between the layer, region, or component and the other layer, region, or component.

[0035] In this specification, it will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, the layer, region, or component may be "directly connected" to the other layer, region, or component, and / or may be "indirectly connected" to the other layer, region, or component, with other layers, regions, or components situated between the layer, region, or component and the other layer, region, or component. For example, when a layer, region, or component is referred to as being "electrically connected," the layer, region, or component may be directly electrically connected, and / or may be indirectly electrically connected, with an intermediary layer, region, or component situated between the layers, regions, or components.

[0036] In this specification, the x, y, and z directions are not limited to directions along the three axes of an orthogonal coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0037] In the specification, when viewing the component in a "plan view," it means viewing the component from above (e.g., in a direction perpendicular to the top surface of the base), and when viewing the component in a "sectional view," it means that the component is vertically cut and viewed from the side.

[0038] In the specification, when the first component is "overlapped" with the second component, it means that the first component is located above or below the second component such that at least a portion of the first component overlaps with the second component in a plan view.

[0039] In the specification, "on" or "on" used in association with the state of a component can be referred to as the active state of the component, and "off" or "closed" can be referred to as the deactivated (disabled) state of the component. "On" or "on" used in association with a signal received by the component can be referred to as the signal used to activate the component, and "off" or "closed" can be referred to as the signal used to deactivated (disable) the component. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it is important to understand that the "on" voltages of P-type and N-type transistors are opposite (low to high) voltage levels.

[0040] In this specification, when an embodiment can be implemented differently, the specific process sequence may be performed in a manner different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0041] Furthermore, for ease of explanation, the components in the accompanying drawings may have exaggerated or reduced dimensions. For example, for ease of explanation, the dimensions and thickness of each component shown in the drawings are arbitrarily shown, and therefore this disclosure is not necessarily limited to what is shown.

[0042] In view of the full contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0043] In the following description, embodiments of the present disclosure are illustrated with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic block diagram of a display device 1 according to one or more embodiments.

[0045] Reference Figure 1 The display device 1 may include a pixel unit 110, a gate driver 120, a first emission control driver 130, a second emission control driver 140, a data driver 150, a power supply 170, and a controller 190.

[0046] Multiple scan lines SL, multiple first emission control lines EL1, multiple second emission control lines EL2, multiple data lines DL, multiple voltage lines, and multiple pixels P connected to these lines can be disposed in pixel unit 110. Pixels P can be arranged in various configurations according to specific rules to display an image. For example, pixels P can be configured in various ways (such as pentiles). ® (Rhombus) arrangement, striped arrangement, mosaic arrangement, or triangular arrangement. PENTILE ® "Illustrated" is a registered trademark of Samsung Display Co., Ltd. of South Korea. Each pixel P may include an organic light-emitting diode (OLED) as a display element (e.g., a light-emitting diode), and the OLED may be electrically connected to pixel circuitry. Pixel circuitry may include multiple transistors and at least one capacitor. Pixel P may emit red, green, blue, or white light via the OLED. Each pixel P may be electrically connected to at least one corresponding scan line in scan lines SL, a corresponding first emission control line in first emission control lines EL1, a corresponding second emission control line in second emission control lines EL2, and a corresponding data line in data lines DL.

[0047] Scan lines SL can all extend in the row direction and can be electrically connected to pixels P arranged in the same row. Each scan line SL can transmit a scan signal SS to pixel P located in the same row. Each of the first transmit control line EL1 and the second transmit control line EL2 can extend in the row direction and can be electrically connected to pixel P arranged in the same row. The first transmit control line EL1 can transmit a first transmit control signal ES1 to pixel P arranged in the same row, and the second transmit control line EL2 can transmit a second transmit control signal ES2 to pixel P arranged in the same row.

[0048] Data lines DL can all extend in the column direction and can be electrically connected to pixels P arranged in the same column. Each data line DL can transmit a corresponding data signal DATA to each pixel P located in the same column, synchronously with the scan signal SS.

[0049] Gate drivers 120, electrically connected to multiple scan lines SL, can generate scan signals SS in response to control signals GCS from controller 190, and can sequentially supply scan signals SS to scan lines SL. Scan lines SL can be electrically connected to the gates of data write transistors included in each pixel P. Scan signals SS can be gate control signals that control the on and off states of the data write transistors. Data write transistors refer to transistors electrically connected between data lines DL and the driving transistors of the pixel circuit (e.g., ...). Figure 7 The second transistor T2).

[0050] A first emitter control driver 130, electrically connected to multiple first emitter control lines EL1, can generate a first emitter control signal ES1 in response to a control signal ECS1 from a controller 190, and can sequentially supply the first emitter control signal ES1 to the first emitter control lines EL1. The first emitter control signal ES1 can be a gate control signal that controls the on / off state of a first emitter control transistor included in each pixel P. The first emitter control transistor refers to a transistor electrically connected between the drive voltage line transmitting the first drive voltage ELVDD and the drive transistor of the pixel circuit (e.g., ...). Figure 7 The fifth transistor T5).

[0051] A second emitter control driver 140, electrically connected to multiple second emitter control lines EL2, can generate a second emitter control signal ES2 in response to a control signal ECS2 from a controller 190, and can sequentially supply the second emitter control signal ES2 to the second emitter control lines EL2. The second emitter control signal ES2 can be a gate control signal that controls the on / off state of a second emitter control transistor included in each pixel P. The second emitter control transistor refers to a transistor electrically connected between the driving transistor and the light-emitting diode in the pixel circuit (e.g., ...). Figure 7 The sixth transistor T6).

[0052] Each of the scan signal SS, the first transmit control signal ES1, and the second transmit control signal ES2 can be a square wave signal that includes a turn-on voltage that can turn on the corresponding transistor and a cut-off voltage that can turn off the corresponding transistor.

[0053] exist Figure 1 In the diagram, pixel P is shown connected to scan line SL, first transmit control line EL1, and second transmit control line EL2. However, this is only an example, and pixel P may be electrically connected to more gate control lines. The display device 1 may also include a driver that outputs gate control signals with different timings of applied turn-on voltages.

[0054] The data driver 150, electrically connected to multiple data lines DL, can supply a data signal DATA to the data lines DL in response to a control signal DCS from the controller 190. The data signal DATA supplied to the data lines DL can also be supplied to pixels P of a scan signal SS that has an on-state voltage. The data driver 150 can convert input image data with grayscale information from the controller 190 into a data signal DATA in the form of voltage or current.

[0055] Power supply 170 can generate a voltage for driving pixel P in response to a control signal PCS from controller 190. Power supply 170 can generate a first driving voltage ELVDD and a second driving voltage ELVSS, and supply the first driving voltage ELVDD and the second driving voltage ELVSS to pixel P. The first driving voltage ELVDD can be a high-level voltage supplied to a first electrode (e.g., a pixel electrode or anode) of the light-emitting diode included in pixel P. The second driving voltage ELVSS can be a low-level voltage supplied to a second electrode (e.g., a counter electrode or cathode) of the light-emitting diode included in pixel P.

[0056] The controller 190 can generate control signals GCS, ECS1, ECS2, DCS, and PCS based on signals input from an external source (e.g., a processor), and supply these control signals to the gate driver 120, the first transmit control driver 130, the second transmit control driver 140, the data driver 150, and the power supply 170, respectively. Each of the control signals GCS, ECS1, and ECS2 output to the gate driver 120, the first transmit control driver 130, and the second transmit control driver 140 may include multiple clock signals and a gate start signal. The control signal DCS output to the data driver 150 may include a clock signal and a source start signal.

[0057] Figure 2 It is a schematic plan view of a display panel DP according to one or more embodiments.

[0058] Reference Figure 2 Display device 1 (see Figure 1The display panel DP may include a substrate 100. Various components forming the display panel DP may be disposed on the substrate 100. The substrate 100 includes a display area DA and a non-display area NDA (e.g., a peripheral area) surrounding the display area DA along its edge or periphery (e.g., around the display area DA). The display area DA may include a first display area DA1 for displaying a main image and a second display area DA2 for displaying an auxiliary image and including a transmissive area TA. The auxiliary image may form a single integral image together with the main image, or the auxiliary image may be an image independent of the main image.

[0059] The second display area DA2 may be an area superimposed on a component such as a camera or sensor disposed below the display panel DP. The second display area DA2 may be disposed inside the first display area DA1 and may be at least partially surrounded by the first display area DA1. In one or more embodiments, the second display area DA2 may be disposed on one side of the first display area DA1.

[0060] Multiple pixels P can be disposed in the display area DA. Pixel P may include multiple main pixels Pm disposed in the first display area DA1 and multiple auxiliary pixels Pa disposed in the second display area DA2. Each of the main pixels Pm and auxiliary pixels Pa may include a light-emitting diode that emits red, green, blue, or white light, and the light-emitting diode may be electrically connected to the pixel circuit.

[0061] The second display area DA2 may have a transmissive area TA through which light is transmitted. The transmissive area TA may be a region in the second display area DA2 where no light-blocking elements are provided. For example, transistors, capacitors, etc., may not be provided in the transmissive area TA. The transmissive area TA may also be a region in the second display area DA2 where pixel circuitry for auxiliary pixels Pa is not provided.

[0062] Pixel P can be electrically connected to drivers and lines disposed in the non-display area NDA. Gate driver 120, first emit control driver 130, second emit control driver 140, first voltage supply line VSL1, second voltage supply line VSL2, and pad (or "soldering pad") unit PAD can be disposed in the non-display area NDA.

[0063] Part or all of each of the gate driver 120, the first emitter control driver 130, and the second emitter control driver 140 may be formed directly in the non-display area NDA during the process of forming pixel circuits in the display area DA.

[0064] Gate driver 120 can transmit scan signal SS (see scan line SL) via scan line SL. Figure 1The first transmit control driver 130 can transmit the first transmit control signal ES1 (see first transmit control line EL1) to each of the pixel circuits driving pixel P. Figure 1 The second transmit control driver 140 can supply the second transmit control signal ES2 (see EL2) to each of the pixel circuits driving pixel P. Figure 1 ) is supplied to each of the pixel circuits that drive pixel P.

[0065] In one or more embodiments, gate drivers 120 may be disposed on opposite sides of the display area DA located between the non-display area NDA and the display area DA. Some pixels P may be electrically connected to the gate driver 120 disposed on the left side (-x direction, i.e., the direction opposite to the x direction) of the non-display area NDA, and the remaining pixels P may be electrically connected to the gate driver 120 disposed on the right side (+x direction, i.e., the x direction) of the non-display area NDA. In one or more embodiments, gate drivers 120 may be disposed only on one side of the non-display area NDA.

[0066] In one or more embodiments, each of the first transmit control driver 130 and the second transmit control driver 140 may be disposed on one side of the non-display area NDA. In one or more embodiments, each of the first transmit control driver 130 and the second transmit control driver 140 may be disposed on either side of the display area DA located between the non-display area NDA. In one or more embodiments, the first transmit control driver 130 may be disposed on one side of the non-display area NDA, and the second transmit control driver 140 may be disposed on the opposite side of the non-display area NDA.

[0067] The pad unit PAD can be disposed on one side of the substrate 100. The pad unit PAD is exposed and not covered by an insulating layer, so it can be connected to the circuit board CB. In one or more embodiments, the circuit board CB can be a flexible printed circuit board (FPCB). Data driver 150, power supply 170 (see...) Figure 1 ) and controller 190 (see Figure 1 Each of the components can be formed as a discrete integrated circuit chip or as a single integrated circuit chip and disposed on the circuit board CB. In one or more embodiments, some or all of the data driver 150, power supply 170 and controller 190 can be directly disposed on the substrate 100 using the chip-on-glass (COG) method or the chip-on-plastic (COP) method.

[0068] Data driver 150 can output data signal DATA (see Figure 1Furthermore, the data signal DATA can be transmitted to the pixel circuit of pixel P via the fan-out line FW and the data line DL electrically connected to the fan-out line FW.

[0069] Power supply 170 can supply a first driving voltage ELVDD to a first voltage supply line VSL1 and a second driving voltage ELVSS to a second voltage supply line VSL2. The first driving voltage ELVDD can be transmitted to the pixel circuit of pixel P through the driving voltage line PL electrically connected to the first voltage supply line VSL1, and the second driving voltage ELVSS can be transmitted to the second electrode (counter electrode) of the light-emitting diode of pixel P through the second voltage supply line VSL2.

[0070] The first voltage supply line VSL1 may extend from the lower side of the display area DA (in the -y direction, i.e., the direction opposite to the y direction) in the first direction (x direction). The second voltage supply line VSL2 may have an annular shape with an opening on one side and may at least partially surround the display area DA (e.g., around the display area DA).

[0071] The second display area DA2 can have a circular, elliptical, or polygonal shape in a planar view (e.g., when viewed from a direction approximately perpendicular to the base 100). Although Figure 2 An embodiment with a single second display area DA2 is shown, but multiple second display areas DA2 can be provided. The multiple second display areas DA2 can be arranged to be separated from each other. The multiple second display areas DA2 can have different shapes and sizes.

[0072] Figure 3 It is a schematic cross-sectional view of a display device 1 according to one or more embodiments.

[0073] Reference Figure 3 The display device 1 may include a display panel DP and a component 40 superimposed on the display panel DP and disposed on the lower surface of the display panel DP. The component 40 may be configured to correspond to a second display area DA2. That is, in a plan view, the component 40 may be configured to be superimposed on the second display area DA2.

[0074] The display panel DP may include a substrate 100, pixel circuits PCm and PCa disposed on the substrate 100, light-emitting diodes EDm and EDa disposed on the pixel circuits PCm and PCa, and a thin film encapsulation layer 300 covering the light-emitting diodes EDm and EDa.

[0075] The substrate 100 may include glass or polymer resin. The substrate 100 comprising polymer resin may be flexible, foldable, rollable, and / or bendable. The substrate 100 may have a multilayer structure comprising a layer containing polymer resin and an inorganic layer.

[0076] The lower protective film 175 can be disposed on the lower surface of the substrate 100 (the surface in the -z direction (i.e., the direction opposite to the z direction)). The lower protective film 175 can be attached to the lower surface of the substrate 100. An adhesive layer can be disposed between the lower protective film 175 and the substrate 100. Alternatively, the lower protective film 175 can be formed directly on the lower surface of the substrate 100, in which case the adhesive layer may not be disposed between the lower protective film 175 and the substrate 100.

[0077] The lower protective film 175 can be used to support and protect the substrate 100. The lower protective film 175 can define an opening 175OP corresponding to the second display area DA2. In a plan view, the opening 175OP of the lower protective film 175 can be configured to overlap with the second display area DA2. The lower protective film 175 can include an organic insulating material such as polyethylene terephthalate (PET) or polyimide (PI).

[0078] The main pixel Pm and auxiliary pixel Pa can be disposed on the upper surface of the substrate 100 (the surface in the +z direction (i.e., the z direction)). The main pixel Pm can be disposed in the first display area DA1, and each of the main pixels Pm can include a main pixel circuit PCm (e.g., a first pixel circuit) and a main light-emitting diode EDm (e.g., a first light-emitting diode) electrically connected to the main pixel circuit PCm. The auxiliary pixel Pa can be disposed in the second display area DA2, and each of the auxiliary pixels Pa can include an auxiliary pixel circuit PCa (e.g., a second pixel circuit) and an auxiliary light-emitting diode EDa (e.g., a second light-emitting diode) electrically connected to the auxiliary pixel circuit PCa.

[0079] Each of the main light-emitting diode (EDm) and the auxiliary light-emitting diode (EDa) can be an organic light-emitting diode (OLED) comprising organic materials. Optionally, each of the main light-emitting diode (EDm) and the auxiliary light-emitting diode (EDa) can be an inorganic light-emitting diode comprising inorganic materials. The inorganic light-emitting diode can include a PN junction diode comprising inorganic semiconductor materials. When a forward voltage is applied to the PN junction diode, holes and electrons are injected, and the recombination of holes and electrons generates energy converted into light energy, enabling the emission of light of a specific color. The width of the aforementioned light-emitting diode can range from a few micrometers to hundreds of micrometers or from a few nanometers to hundreds of nanometers. In one or more embodiments, each of the main light-emitting diode (EDm) and the auxiliary light-emitting diode (EDa) can include a quantum dot light-emitting diode. The emitting layer of each of the main light-emitting diode (EDm) and the auxiliary light-emitting diode (EDa) can include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0080] The main light-emitting diode EDm can be electrically connected to the main pixel circuit PCm disposed below the main light-emitting diode EDm, and the auxiliary light-emitting diode EDa can be electrically connected to the auxiliary pixel circuit PCa disposed below the auxiliary light-emitting diode EDa. An insulating layer IL can be disposed between components (such as semiconductor layers and conductive layers) constituting each of the main pixel circuit PCm and the auxiliary pixel circuit PCa.

[0081] The second display area DA2 may include a transmissive area TA. The transmissive area TA may be an area without pixel circuit elements such as transistors and capacitors, and may be an area with high light transmittance.

[0082] In one or more embodiments, the auxiliary pixel circuit PCa and the auxiliary light-emitting diode EDa may not be arranged in the transmissive region TA. The transmissive region TA can be a region for transmitting light emitted from component 40 and / or light directed towards component 40. In the display panel DP, the transmittance of the transmissive region TA can be about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 70% or more, about 75% or more, about 80% or more, about 85% or more, or about 90% or more.

[0083] Component 40 may include sensors such as proximity sensors, light sensors, iris sensors, facial recognition sensors, and cameras (or image sensors). Component 40 may be configured to emit or receive light in the infrared, ultraviolet, and visible light bands.

[0084] The thin-film encapsulation layer 300 may cover the light-emitting diodes EDm and EDA. The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one or more embodiments, the thin-film encapsulation layer 300 may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0085] An input sensing layer and / or an optical functional layer may be disposed on the thin-film encapsulation layer 300. The input sensing layer can sense external inputs such as touch from an object like a finger or stylus. The input sensing layer may be configured to sense external inputs using mutual capacitance and / or self-capacitance methods. The optical functional layer may include an anti-reflective layer for reducing the reflectivity of light incident on the display device 1. In one or more embodiments, the optical functional layer may include a black matrix and a color filter.

[0086] Figure 4 It is a schematic plan view of a portion of a display panel DP according to one or more embodiments.

[0087] Reference Figure 4 The display panel DP may include a display area DA. The display area DA may include a first display area DA1 and a second display area DA2 including a circuit area PCA and a transmission area TA. Because the components of the display panel DP are disposed on the substrate 100 (see...), Figure 2 Therefore, it can be said that the substrate 100 includes a first display area DA1 and a second display area DA2 including a circuit area PCA and a transmission area TA.

[0088] The main pixel circuit PCm can be disposed in the first display area DA1. The main pixel circuit PCm can be disposed in matrix form along the first direction (x direction) and the second direction (y direction). For example, the main pixel circuit PCm can be disposed along the rows and columns of the matrix along the first direction (x direction) and the second direction (y direction).

[0089] At least a portion of the second display area DA2 may be surrounded by the first display area DA1. The second display area DA2 may have various shapes in the plan view, such as a circle, an ellipse, or a polygon. In this respect, Figure 4 The second display area DA2 is shown to have a rectangular shape in the plan view.

[0090] The second display area DA2 may include a circuit area PCA with auxiliary pixel circuitry PCa and a transmissive area TA outside the circuit area PCA. The pixel circuitry may not be disposed within the transmissive area TA. In one or more embodiments, the circuit areas PCA may be spaced apart (e.g., separated), and the transmissive areas TA are located between the circuit areas PCA. Each of the circuit areas PCA may be surrounded by the transmissive areas TA. In one or more embodiments, multiple transmissive areas TA are provided. The circuit areas PCA and transmissive areas TA may be alternately arranged along a first direction (x-direction) and / or a second direction (y-direction). In this way, the arrangement of the circuit areas PCA and transmissive areas TA can be designed in various ways.

[0091] In one or more embodiments, the main pixel circuit PCm and the auxiliary pixel circuit PCa may be constructed identically (e.g., substantially identically). In one or more embodiments, the main pixel circuit PCm and the auxiliary pixel circuit PCa may be constructed differently.

[0092] Figure 5 It is a schematic plan view of the pixel arrangement in the first display area DA1 according to one or more embodiments. Figure 6 It is a schematic plan view of the pixel arrangement in the second display area DA2 according to one or more embodiments.

[0093] Reference Figure 5 The main pixel Pm can be set in the first display area DA1. In the specification, each of the main pixels Pm represents a sub-pixel as the smallest element realizing an image. Each of the main pixels Pm may include a main light-emitting diode EDm and a main pixel circuit PCm electrically connected to the main light-emitting diode EDm. Figure 5 The boundary of each of the main pixels Pm shown represents the emission region of the main light-emitting diode EDm included in the main pixel Pm.

[0094] The main pixel Pm may include a first red pixel Pr1, a first blue pixel Pb1, and a first green pixel Pg1. The first red pixel Pr1 can emit red light, the first blue pixel Pb1 can emit blue light, and the first green pixel Pg1 can emit green light.

[0095] In one or more embodiments, the size (or area) of the first blue pixel Pb1 may be larger than the size (or area) of the first red pixel Pr1 and the size (or area) of the first green pixel Pg1. The size (or area) of the first red pixel Pr1 may be greater than or equal to the size (or area) of the first green pixel Pg1.

[0096] The primary pixel Pm can be in Pentyl ®The pixels are arranged in a specific pattern. For example, the first green pixel Pg1 can be placed in the first row, the first blue pixel Pb1 and the first red pixel Pr1 can be alternately placed in the second row, the first green pixel Pg1 can be placed in the third row, and the first red pixel Pr1 and the first blue pixel Pb1 can be alternately placed in the fourth row. This arrangement of pixels can be repeated in units of four rows.

[0097] In this configuration, the first green pixel Pg1 in odd-numbered rows can be interleaved with the first blue pixel Pb1 and the first red pixel Pr1 in even-numbered rows. For example, the first blue pixel Pb1 and the first red pixel Pr1 can be alternately placed in the first column, the first green pixel Pg1 can be placed in the second column, the first red pixel Pr1 and the first blue pixel Pb1 can be alternately placed in the third column, and the first green pixel Pg1 can be arranged in the fourth column. This arrangement of pixels can be repeated in units of four columns.

[0098] For example, in the vertices of a virtual square VS with the center point of the first green pixel Pg1 as the center point of the square, the first blue pixel Pb1 can be placed at the first and third vertices facing each other, and the first red pixel Pr1 can be placed at the remaining vertices (the second and fourth vertices). Here, the virtual square VS can be changed to various shapes such as rectangles, rhombuses, and squares.

[0099] Although Figure 5 The primary pixel Pm is shown in PENTILE. ® The arrangement can be varied, but this disclosure is not limited thereto. For example, the main pixel Pm can be set in various configurations such as stripe arrangement, mosaic arrangement, and triangle arrangement.

[0100] In one or more embodiments, the primary pixel Pm may have a circular shape in the planar view. In one or more embodiments, the primary pixel Pm may have various shapes in the planar view, such as polygonal or elliptical shapes.

[0101] Reference Figure 6 Auxiliary pixels Pa can be set in the second display area DA2. Here, each of the auxiliary pixels Pa represents a sub-pixel as the smallest element for realizing an image. Each of the auxiliary pixels Pa may include an auxiliary light-emitting diode EDa and an auxiliary pixel circuit PCa electrically connected to the auxiliary light-emitting diode EDa. Figure 6 The boundary of each of the auxiliary pixels Pa shown represents the emission region of the auxiliary light-emitting diode EDa included in the auxiliary pixel Pa.

[0102] The auxiliary pixel Pa may include a second red pixel Pr2, a second blue pixel Pb2, and a second green pixel Pg2. The second red pixel Pr2 can emit red light, the second blue pixel Pb2 can emit blue light, and the second green pixel Pg2 can emit green light.

[0103] In one or more embodiments, the size (or area) of the second blue pixel Pb2 may be larger than the size (or area) of the second red pixel Pr2 and the second green pixel Pg2. The size (or area) of the second red pixel Pr2 may be greater than or equal to the size (or area) of the second green pixel Pg2.

[0104] The second display area DA2 may include a circuit area PCA and a transmission area TA. In one or more embodiments, the auxiliary light-emitting diode EDa of the auxiliary pixel Pa may be disposed in the circuit area PCA. In one or more embodiments, some of the auxiliary light-emitting diodes EDa of the auxiliary pixel Pa may be disposed in the circuit area PCA, and the remaining auxiliary light-emitting diodes EDa may be disposed in the transmission area TA.

[0105] The auxiliary pixel Pa set in the second display area DA2 can be PENTILE ® Arrangement is key. For example, within the vertices of a virtual square VS with the center point of the second green pixel Pg2 as the center point of the square, the second blue pixel Pb2 can be placed at the first and third vertices facing each other, and the second red pixel Pr2 can be placed at the remaining vertices (the second and fourth vertices). Here, the virtual square VS can be changed to various shapes such as rectangles, rhombuses, and squares.

[0106] Although Figure 5 and Figure 6 The illustration shows that the auxiliary pixel Pa and the main pixel Pm are arranged in the same pixel arrangement, but this disclosure is not limited thereto. For example, the auxiliary pixel Pa can be arranged in various configurations such as stripe arrangement, mosaic arrangement, and triangular arrangement.

[0107] In one or more embodiments, the auxiliary pixel Pa may have a circular shape in the planar view. In another embodiment, the auxiliary pixel Pa may have various shapes in the planar view, such as polygonal shapes, elliptical shapes, etc.

[0108] Because the second display area DA2 includes a transmissive area TA without auxiliary pixel circuits PCa, the number of auxiliary pixels Pa per unit area in the second display area DA2 can be less than the number of main pixels Pm per unit area in the first display area DA1. For example, the number of auxiliary pixels Pa per unit area in the second display area DA2 can be approximately 1 / 2, 1 / 3, 1 / 4, 1 / 8, or 1 / 16 of the number of main pixels Pm per unit area in the first display area DA1. Therefore, in order to reduce the brightness difference between the second display area DA2 and the first display area DA1, the brightness of the auxiliary pixels Pa can be greater than the brightness of the main pixels Pm.

[0109] Figure 7 It is an equivalent circuit diagram of the main pixel Pm according to one or more embodiments. Figure 8 It is an equivalent circuit diagram of an auxiliary pixel Pa according to one or more embodiments. Figure 9 It is a schematic representation of the supply to Figure 7 The signal diagram of the main pixel Pm, and Figure 10 It is a schematic representation of the supply to Figure 8 The diagram shows the signal of the auxiliary pixel Pa.

[0110] Reference Figure 7 The main pixel Pm may include a main light-emitting diode EDm and a main pixel circuit PCm electrically connected to the main light-emitting diode EDm.

[0111] The main pixel circuit PCm can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GRL for transmitting the second gate signal GR, the third gate line GIL for transmitting the third gate signal GI, the first transmit control line EL1 for transmitting the first transmit control signal EM1, the second transmit control line EL2 for transmitting the second transmit control signal EM2, and the data line DL for transmitting the data voltage Vdata.

[0112] The first gate signal GW and the first gate line GGL can respectively correspond to reference Figure 1 The scan signal SS and scan line SL are described. Similarly, the first transmit control signal EM1 and the second transmit control signal EM2 can respectively correspond to the first transmit control signal ES1 (see...). Figure 1 ) and the second transmit control signal ES2 (see Figure 1 ), and the data voltage Vdata can correspond to the data signal DATA (see Figure 1 ).

[0113] Additionally, the main pixel circuit PCm can be electrically connected to the drive voltage line PL that transmits the first drive voltage ELVDD, the reference voltage line VRL that transmits the reference voltage VREF, and the initialization voltage line VIL that transmits the initialization voltage Vaint.

[0114] The voltage level of the first drive voltage ELVDD can be higher than the voltage level of the second drive voltage ELVSS. The voltage level of the reference voltage VREF can be lower than the voltage level of the first drive voltage ELVDD. The voltage level of the initialization voltage Vaint can be equal to or higher than the voltage level of the second drive voltage ELVSS.

[0115] The main pixel circuit PCm may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a first capacitor Cst, a second capacitor Chd, and a third capacitor Ced. The first transistor T1 (e.g., a driving transistor) may be an N-type transistor. At least one of the second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be an N-type transistor. In one or more embodiments, the fifth transistor T5 (e.g., a first emitter control transistor) may be a P-type transistor. In one or more embodiments, the fifth transistor T5 and the sixth transistor T6 (e.g., a second emitter control transistor) may be P-type transistors. In one or more embodiments, the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may all be N-type transistors. In one or more embodiments, the N-type transistor may be an oxide-based thin-film transistor including a metal-oxide-semiconductor layer, and the P-type transistor may be a silicon-based thin-film transistor including a silicon semiconductor layer.

[0116] The first transistor T1 is a drive transistor that outputs a drive current corresponding to the data voltage Vdata, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be switching transistors that are turned on or off according to their respective gate signals. Each of the first terminal (e.g., the first electrode) and the second terminal (e.g., the second electrode) of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a source or a drain. For example, the first terminal can be a source and the second terminal can be a drain, or the first terminal can be a drain and the second terminal can be a source.

[0117] A node connected to the first gate of the first transistor T1 can be defined as a first node N1, a node connected to the first terminal of the first transistor T1 can be defined as a second node N2, and a node connected to the second terminal of the first transistor T1 can be defined as a third node N3. A node connected to the first electrode (e.g., pixel electrode) of the main light-emitting diode EDm can be defined as a fourth node N4.

[0118] The first transistor T1 can be electrically connected between the drive voltage line PL and the main light-emitting diode EDm. The first gate of the first transistor T1 can be electrically connected to the first node N1, the first terminal of the first transistor T1 can be electrically connected to the second node N2, and the second terminal of the first transistor T1 can be electrically connected to the third node N3. According to the switching operation of the second transistor T2, the first transistor T1 can control the drive current flowing to the main light-emitting diode EDm based on the data voltage Vdata.

[0119] The second transistor T2 is a data write transistor and can be electrically connected between the data line DL and the first transistor T1. The second transistor T2 may include a gate electrically connected to the first gate line GWL, a first terminal electrically connected to the data line DL, and a second terminal electrically connected to the first node N1. The second transistor T2 can be turned on by a first gate signal GW transmitted via the first gate line GWL to electrically connect the data line DL and the first node N1, and can transmit the data voltage Vdata from the data line DL to the first node N1.

[0120] The third transistor T3 is the first initialization transistor and can be electrically connected between the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate electrically connected to the second gate line GRL, a first terminal electrically connected to the reference voltage line VRL, and a second terminal electrically connected to the first node N1. The third transistor T3 can be turned on by a second gate signal GR transmitted via the second gate line GRL, and can transmit the reference voltage VREF from the reference voltage line VRL to the first node N1.

[0121] The fourth transistor T4 is the second initialization transistor and can be electrically connected between the first transistor T1 and the initialization voltage line VIL. The fourth transistor T4 may include a gate electrically connected to the third gate line GIL, a first terminal electrically connected to the initialization voltage line VIL, and a second terminal electrically connected to the fourth node N4. The fourth transistor T4 can be turned on by the third gate signal GI transmitted via the third gate line GIL and can transmit the initialization voltage Vaint from the initialization voltage line VIL to the fourth node N4.

[0122] The fifth transistor T5 is the first emitter control transistor and can be electrically connected between the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate electrically connected to the first emitter control line EL1, a first terminal electrically connected to the drive voltage line PL, and a second terminal electrically connected to the second node N2. The fifth transistor T5 can be turned on or off by a first emitter control signal EM1 transmitted via the first emitter control line EL1.

[0123] The sixth transistor T6 is the second emitter control transistor and can be electrically connected between the first transistor T1 and the main light-emitting diode EDm. The sixth transistor T6 may include a gate electrically connected to the second emitter control line EL2, a first terminal electrically connected to the third node N3, and a second terminal electrically connected to the fourth node N4. The sixth transistor T6 can be turned on or off by the second emitter control signal EM2 transmitted via the second emitter control line EL2.

[0124] The first capacitor Cst can be electrically connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor Cst can be electrically connected to the first node N1, and the second electrode of the first capacitor Cst can be electrically connected to the third node N3. The first capacitor Cst is a storage capacitor and can store charge corresponding to the threshold voltage and data voltage Vdata of the first transistor T1.

[0125] The second capacitor Chd can be electrically connected between the drive voltage line PL and the second terminal of the first transistor T1. The first electrode of the second capacitor Chd can be electrically connected to the drive voltage line PL, and the second electrode of the second capacitor Chd can be electrically connected to the third node N3.

[0126] The third capacitor Ced can be electrically connected between the fourth node N4 and the auxiliary voltage line or the counter electrode of the main light-emitting diode EDm. Both the auxiliary voltage line and the counter electrode of the main light-emitting diode EDm are supplied with the second driving voltage ELVSS.

[0127] The capacitance of each of the first capacitor Cst, the second capacitor Chd, and the third capacitor Ced can be formed differently depending on the color of the light emitted by the main pixel Pm.

[0128] The main light-emitting diode EDm can be electrically connected to the first transistor T1 via a sixth transistor T6. The main light-emitting diode EDm may include a pixel electrode (e.g., anode) electrically connected to a fourth node N4 and a counter electrode (e.g., cathode) opposite the pixel electrode, and the counter electrode may receive a second driving voltage ELVSS. The counter electrode may be a common electrode shared by multiple main pixels Pm.

[0129] Reference Figure 8The auxiliary pixel Pa may include an auxiliary light-emitting diode EDa and an auxiliary pixel circuit PCa electrically connected to the auxiliary light-emitting diode EDa.

[0130] The auxiliary pixel circuit PCa can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GRL for transmitting the second gate signal GR, the third gate line GIL for transmitting the third gate signal GI, the first transmit control line EL1 for transmitting the first transmit control signal EM1, the third transmit control line EL2a for transmitting the third transmit control signal EM2a, and the data line DL for transmitting the data voltage Vdata.

[0131] Additionally, the auxiliary pixel circuit PCa can be electrically connected to the drive voltage line PL that transmits the first drive voltage ELVDD, the reference voltage line VRL that transmits the reference voltage VREF, and the initialization voltage line VIL that transmits the initialization voltage Vaint.

[0132] The auxiliary pixel circuit PCa may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a first capacitor Cst, a second capacitor Chd, and a third capacitor Ced. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5, the first capacitor Cst, the second capacitor Chd, and the third capacitor Ced of the auxiliary pixel circuit PCa can correspond to the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5, the first capacitor Cst, the second capacitor Chd, and the third capacitor Ced of the main pixel circuit PCm. In the following description, the descriptions of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5, the first capacitor Cst, the second capacitor Chd, and the third capacitor Ced of the main pixel circuit PCm are modified as necessary to apply to the descriptions of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5, the first capacitor Cst, the second capacitor Chd, and the third capacitor Ced of the auxiliary pixel circuit PCa.

[0133] The sixth transistor T6 of the auxiliary pixel circuit PCa is the second emitter control transistor and can be electrically connected between the first transistor T1 and the auxiliary light-emitting diode EDa. The sixth transistor T6 may include a gate electrically connected to the third emitter control line EL2a, a first terminal electrically connected to the third node N3, and a second terminal electrically connected to the fourth node N4. The sixth transistor T6 of the auxiliary pixel circuit PCa can remain in an on-state according to the third emitter control signal EM2a transmitted via the third emitter control line EL2a.

[0134] Common Reference Figure 7 and Figure 9 The main pixel Pm can be driven during a frame 1F, which includes a first scan period AS and at least one second scan period. Figure 9 The example illustrates that a frame 1F includes a first scan period AS and three second scan periods SS1, SS2 and SS3.

[0135] Each of the first gate signal GW, the second gate signal GR, the third gate signal GI, the first transmit control signal EM1, and the second transmit control signal EM2 may have a high-level voltage VGH (e.g., a first-level voltage) for some periods of a frame 1F and a low-level voltage VGL (e.g., a second-level voltage) for the remaining periods of a frame 1F. Here, the high-level voltage VGH can turn on the N-type transistor and turn off the P-type transistor. The low-level voltage VGL can turn off the N-type transistor and turn on the P-type transistor.

[0136] In the following text, when the transistor receiving the gate control signal is an N-type transistor, the on-state voltage refers to the high-level voltage VGH; when the transistor is a P-type transistor, the on-state voltage refers to the low-level voltage VGL. Conversely, when the transistor receiving the gate control signal is an N-type transistor, the off-state voltage refers to the low-level voltage VGL; when the transistor is a P-type transistor, the off-state voltage refers to the high-level voltage VGH.

[0137] The first scanning period AS can include a non-emission period when the main pixel Pm does not emit light and an emission period when the main pixel Pm emits light. The non-emission period can include a first initialization period, a compensation period, a data writing period, and a second initialization period.

[0138] The first initialization period can be the period during which a third gate signal GI with a turn-on voltage is supplied to the third gate line GIL, and the fourth transistor T4 can be turned on by the third gate signal GI. During the first initialization period, the first gate signal GW and the first transmit control signal EM1 can be supplied with turn-off voltages. With the fourth transistor T4 turned on, the fourth node N4 (i.e., the pixel electrode of the main light-emitting diode EDm) can be initialized to the initialization voltage Vaint.

[0139] The compensation period can be the period during which the second gate signal GR with an on-state voltage is supplied to the second gate line GRL, and the third transistor T3 can be turned on by the second gate signal GR. During the compensation period, the first transmit control signal EM1 with an on-state voltage can be supplied to the first transmit control line EL1, and the second transmit control signal EM2 with a cut-off voltage can be supplied to the second transmit control line EL2. The first gate signal GW can be supplied with a cut-off voltage. The on-state voltage periods of the third gate signal GI and the second gate signal GR can be partially superimposed. The fifth transistor T5 can be turned on by the first transmit control signal EM1 with an on-state voltage, and the sixth transistor T6 can be turned off by the second transmit control signal EM2 with a cut-off voltage.

[0140] Therefore, a reference voltage VREF is supplied to the first node N1, and a first drive voltage ELVDD is supplied to the first terminal of the first transistor T1, enabling the first transistor T1 to conduct. When the voltage at the second terminal of the first transistor T1 drops to the difference (VREF-Vth) between the reference voltage VREF and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off. The charge corresponding to the threshold voltage of the first transistor T1 can be stored in the first capacitor Cst, thereby compensating for the threshold voltage of the first transistor T1.

[0141] The data writing period can be the period during which a first gate signal GW with an on-state voltage is supplied to the first gate line GWL, and the second transistor T2 can be turned on by the first gate signal GW. During the data writing period, the first transmit control signal EM1, the second transmit control signal EM2, the second gate signal GR, and the third gate signal GI can be supplied with off-state voltages.

[0142] Through the conducting second transistor T2, the data voltage Vdata can be transmitted from the data line DL to the first gate of the first transistor T1. Therefore, the voltage of the first node N1 can be changed to a voltage corresponding to the data voltage Vdata. The voltage of the third node N3 can be changed in response to the change in the voltage of the first node N1.

[0143] The second initialization period can be the period during which a third gate signal GI with a conduction voltage is supplied to the third gate line GIL, and the fourth transistor T4 can be turned on by the third gate signal GI. The first gate signal GW, the second gate signal GR, the first transmit control signal EM1, and the second transmit control signal EM2 can be supplied as cutoff voltages. The fourth node N4 (i.e., the pixel electrode of the main light-emitting diode EDm) can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4. By initializing the fourth node N4 between the data writing period and the transmit period, the brightness variation of the main light-emitting diode EDm during low grayscale (e.g., grayscale value) display can be reduced or minimized, thereby further improving image quality.

[0144] The non-transmission period may include a second transmit control signal cutoff period (EOP) where the second transmit control signal EM2 is supplied with a cutoff voltage. The second transmit control signal cutoff period (EOP) may be superimposed with a compensation period, a data write period, and a second initialization period. Because the sixth transistor T6 is off during the second transmit control signal cutoff period (EOP), the voltage of the third node N3 can be changed according to the capacitance ratio of the first capacitor Cst and the second capacitor Chd, and is not affected by the capacitance of the third capacitor Ced.

[0145] The transmission period is the time during which a first transmission control signal EM1 with a conduction voltage is supplied to the first transmission control line EL1, and a second transmission control signal EM2 with a conduction voltage is supplied to the second transmission control line EL2. The fifth transistor T5 and the sixth transistor T6 can be turned on by the first transmission control signal EM1 and the second transmission control signal EM2. The first gate signal GW, the second gate signal GR, and the third gate signal GI can be supplied with cutoff voltages.

[0146] The first drive voltage ELVDD can be supplied to the first terminal of the first transistor T1 through the conducting fifth transistor T5. The first transistor T1 can output the main drive current I corresponding to the data voltage Vdata stored in the first capacitor Cst. dm Main drive current I dm Follow the expression below.

[0147] Expression 1: .

[0148] Main drive current I dm The current can flow to the main light-emitting diode EDm through the sixth transistor T6, which is turned on by the second transmit control signal EM2, and the main light-emitting diode EDm can emit light with a current I = 1. dm The corresponding brightness of light.

[0149] like Figure 9 As shown, the second scan periods SS1, SS2, and SS3 may include a non-transmission period during which the first transmit control signal EM1 with a cutoff voltage is supplied to the first transmit control line EL1, and a transmission period during which the first transmit control signal EM1 with a conduction voltage is supplied to the first transmit control line EL1. During the second scan periods SS1, SS2, and SS3, the second transmit control signal EM2 may be supplied with a conduction voltage.

[0150] The second scan periods SS1, SS2, and SS3 may exclude the first initialization period, compensation period, data writing period, and second initialization period. The second scan period SS2 may include a third initialization period where a third gate signal GI with an on-state voltage is supplied to the third gate line GIL. During the third initialization period, the first gate signal GW, the second gate signal GR, and the first transmit control signal EM1 may be supplied with off-state voltages, and the second transmit control signal EM2 may be supplied with on-state voltages. The fourth transistor T4 may be turned on by the third gate signal GI, and the pixel electrode of the main light-emitting diode EDm may be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4. Therefore, even when a frame 1F may include multiple second scan periods SS1, SS2, and SS3, the brightness deviation based on the driving frequency can be reduced or minimized.

[0151] During the transmission period of each of the second scan periods SS1, SS2, and SS3, the first drive voltage ELVDD can be supplied to the first terminal of the first transistor T1 through the fifth transistor T5, which is turned on by the first transmission control signal EM1. The first transistor T1 can output the main drive current I corresponding to the data voltage Vdata stored in the first capacitor Cst. dm Main drive current I dm The current can flow to the main light-emitting diode EDm through the sixth transistor T6, which is turned on by the second transmit control signal EM2, and the main light-emitting diode EDm can emit light with a current I = 1. dm The corresponding brightness of the light. The data voltage Vdata stored in the first capacitor Cst during the second scan periods SS1, SS2, and SS3 can be represented as the data voltage Vdata supplied to the main pixel Pm during the data writing period of the first scan period AS.

[0152] Common Reference Figure 8 and Figure 10 The auxiliary pixel Pa can be driven during a frame 1F, which includes a first scan period AS and at least one second scan period. Figure 10 The example illustrates that a frame 1F includes a first scan period AS and three second scan periods SS1, SS2 and SS3.

[0153] The first scanning period AS may include a non-emission period where the auxiliary pixel Pa does not emit light and an emission period where the auxiliary pixel Pa emits light. The non-emission period may include a first initialization period, a compensation period, a data writing period, and a second initialization period.

[0154] The first initialization period can be the period during which a third gate signal GI with a conduction voltage is supplied to the third gate line GIL, and the fourth transistor T4 can be turned on by the third gate signal GI. During the first initialization period, the first gate signal GW and the first transmit control signal EM1 can be supplied as cutoff voltages, and the third transmit control signal EM2a can be supplied as a conduction voltage. The third node N3 and the fourth node N4 (i.e., the pixel electrode of the auxiliary light-emitting diode EDa) can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4 and the sixth transistor T6.

[0155] The compensation period can be the time during which the second gate signal GR, with a turn-on voltage, is supplied to the second gate line GRL, and the third transistor T3 can be turned on via the second gate signal GR. During the compensation period, the first transmit control signal EM1 and the third transmit control signal EM2a can be supplied as turn-on voltages, and the first gate signal GW can be supplied as a cut-off voltage. The turn-on voltage period of the third gate signal GI and the turn-on voltage period of the second gate signal GR can be partially superimposed. The fifth transistor T5 and the sixth transistor T6 can be turned on via the first transmit control signal EM1 and the third transmit control signal EM2a.

[0156] The data writing period can be the period during which a first gate signal GW with an on-state voltage is supplied to the first gate line GWL, and the second transistor T2 can be turned on by the first gate signal GW. During the data writing period, the first transmit control signal EM1, the second gate signal GR, and the third gate signal GI can be supplied with off-state voltages, and the third transmit control signal EM2a can be supplied with an on-state voltage.

[0157] Through the conducting second transistor T2, the data voltage Vdata can be transmitted from the data line DL to the first gate of the first transistor T1. Therefore, the voltage of the first node N1 can be changed to a voltage corresponding to the data voltage Vdata. The voltage of the third node N3 can be changed in response to the change in the voltage of the first node N1.

[0158] The second initialization period can be the period during which a third gate signal GI with a conduction voltage is supplied to the third gate line GIL, and the fourth transistor T4 can be turned on by the third gate signal GI. During the second initialization period, the first gate signal GW, the second gate signal GR, and the first transmit control signal EM1 can be supplied as cutoff voltages, and the third transmit control signal EM2a can be supplied as a conduction voltage. The third node N3 and the fourth node N4 can be initialized to the initialization voltage Vaint by the turned-on fourth transistor T4 and sixth transistor T6. By initializing the fourth node N4 between the data writing period and the transmit period, the brightness variation of the auxiliary light-emitting diode EDa during low grayscale (e.g., grayscale value) display can be reduced or minimized, thereby further improving image quality.

[0159] During frame 1F, the third transmit control signal EM2a can be supplied as a turn-on voltage to the auxiliary pixel Pa. Because the sixth transistor T6 remains on during the non-transmit period, the voltage of the third node N3 before the transmit period can be changed according to the capacitance ratio of the first capacitor Cst, the second capacitor Chd, and the third capacitor Ced.

[0160] The transmission period is the time during which a first transmission control signal EM1 with a conduction voltage is supplied to the first transmission control line EL1, and a third transmission control signal EM2a with a conduction voltage is supplied to the third transmission control line EL2a. The fifth transistor T5 and the sixth transistor T6 can be turned on by the first transmission control signal EM1 and the third transmission control signal EM2a. The first gate signal GW, the second gate signal GR, and the third gate signal GI can be supplied with cutoff voltages.

[0161] The first drive voltage ELVDD can be supplied to the first terminal of the first transistor T1 through the conducting fifth transistor T5. The first transistor T1 can output an auxiliary drive current I corresponding to the data voltage Vdata stored in the first capacitor Cst. da Auxiliary drive current I da Follow expression 2 below.

[0162] Expression 2 .

[0163] Auxiliary drive current I da The current can flow to the auxiliary light-emitting diode EDA through the sixth transistor T6, which is turned on by the third transmit control signal EM2a, and the auxiliary light-emitting diode EDA can emit light with a current I = 1. da The corresponding brightness of light.

[0164] like Figure 10As shown, the second scan periods SS1, SS2, and SS3 may include a non-transmission period during which the first transmit control signal EM1 with a cutoff voltage is supplied to the first transmit control line EL1, and a transmission period during which the first transmit control signal EM1 with a conduction voltage is supplied to the first transmit control line EL1. During the second scan periods SS1, SS2, and SS3, a third transmit control signal EM2a with a conduction voltage may be supplied to the third transmit control line EL2a.

[0165] The second scan periods SS1, SS2, and SS3 may exclude the first initialization period, the compensation period, the data writing period, and the second initialization period. The second scan period SS2 may include a third initialization period in which a third gate signal GI with a conduction voltage is supplied to the third gate line GIL.

[0166] During the transmission period of each of the second scan periods SS1, SS2, and SS3, the first drive voltage ELVDD can be supplied to the first terminal of the first transistor T1 through the fifth transistor T5, which is turned on by the first transmission control signal EM1. The first transistor T1 can output an auxiliary drive current I corresponding to the data voltage Vdata stored in the first capacitor Cst. da Auxiliary drive current I da The current can flow to the auxiliary light-emitting diode EDA through the sixth transistor T6, which is turned on by the third transmit control signal EM2a, and the auxiliary light-emitting diode EDA can emit light with a current I = 1. da The corresponding brightness of the light. The data voltage Vdata stored in the first capacitor Cst during the second scan periods SS1, SS2 and SS3 can be represented as the data voltage Vdata supplied to the auxiliary pixel Pa during the data writing period of the first scan period AS.

[0167] The sixth transistor T6 of the main pixel circuit PCm can be turned off during the second transmit control signal cutoff period EOP when the second transmit control signal EM2 is supplied with a cutoff voltage, and turned on during periods other than the second transmit control signal cutoff period EOP. On the other hand, since the third transmit control signal EM2a is supplied with an on voltage for frame 1F, the sixth transistor T6 of the auxiliary pixel circuit PCa can remain on for frame 1F.

[0168] As described above, the main drive current I output by the main pixel circuit PCm dm The auxiliary drive current I output by the auxiliary pixel circuit PCa is based on the capacitance of the first capacitor Cst and the capacitance of the second capacitor Chd. daBased on the capacitance of the first capacitor Cst, the capacitance of the second capacitor Chd, and the capacitance of the third capacitor Ced (Chd + Ced), the main drive current I... dm It can be less than the auxiliary drive current I. da Therefore, the brightness of the auxiliary pixel Pa can be greater than the brightness of the main pixel Pm, so that the resulting brightness difference compensates for the difference in the number of pixels per unit area between the second display area DA2 and the first display area DA1.

[0169] Figure 11 It is an equivalent circuit diagram of an auxiliary pixel Pa according to one or more embodiments.

[0170] Reference Figure 11 The auxiliary pixel Pa may include an auxiliary light-emitting diode EDa and an auxiliary pixel circuit PCa electrically connected to the auxiliary light-emitting diode EDa.

[0171] The auxiliary pixel circuit PCa can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GRL for transmitting the second gate signal GR, the third gate line GIL for transmitting the third gate signal GI, the first transmit control line EL1 for transmitting the first transmit control signal EM1, the second transmit control line EL2 for transmitting the second transmit control signal EM2, and the data line DL for transmitting the data voltage Vdata.

[0172] Additionally, the auxiliary pixel circuit PCa can be electrically connected to the drive voltage line PL that transmits the first drive voltage ELVDD, the reference voltage line VRL that transmits the reference voltage VREF, and the initialization voltage line VIL that transmits the initialization voltage Vaint.

[0173] The auxiliary pixel circuit PCa may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, a first capacitor Cst, a second capacitor Chd and a third capacitor Ced. Figure 11 The auxiliary pixel circuit PCa has the same characteristics as Figure 8 The auxiliary pixel circuit PCa has a similar structure, but differs in that the gate of the sixth transistor T6 is electrically connected to the second emitter control line EL2, and the auxiliary pixel circuit PCa also includes a wire BRL that electrically connects the third node N3 and the fourth node N4. In the following description, similar components will be omitted, and the focus will be on the differences.

[0174] The sixth transistor T6 of the auxiliary pixel circuit PCa is the second emitter control transistor and can be electrically connected between the first transistor T1 and the auxiliary light-emitting diode EDa. The sixth transistor T6 may include a gate electrically connected to the second emitter control line EL2, a first terminal electrically connected to the third node N3, and a second terminal electrically connected to the fourth node N4. (See the sixth transistor T6 of the main pixel circuit PCm...) Figure 7 Similarly, the sixth transistor T6 of the auxiliary pixel circuit PCa can be turned on or off by the second transmit control signal EM2.

[0175] The wire BRL can electrically connect the third node N3 and the fourth node N4. That is, the wire BRL can electrically connect the first terminal of the sixth transistor T6 to the second terminal of the sixth transistor T6, or electrically connect the first terminal of the sixth transistor T6 to the pixel electrode of the auxiliary light-emitting diode EDa. Therefore, even when the sixth transistor T6 is turned off by the second emitter control signal EM2 with a cutoff voltage, the third node N3 and the fourth node N4 can still be electrically connected through the wire BRL. In other words, even when the sixth transistor T6 is turned off, the wire BRL can maintain the conductive path through which current flows between the third node N3 and the auxiliary light-emitting diode EDa. Therefore, the brightness of the auxiliary pixel Pa can be increased without using a separate emitter control line and emitter control signal to control the sixth transistor T6 of the auxiliary pixel circuit PCa.

[0176] Figure 12A This is a schematic cross-sectional view of the first display area DA1 of the display panel DP according to one or more embodiments. Figure 12B It is a schematic cross-sectional view of the second display area DA2 of the display panel DP according to one or more embodiments.

[0177] Common Reference Figure 12A and Figure 12B The display panel DP may include a substrate 100, a main light-emitting diode EDm and an auxiliary light-emitting diode EDa. The substrate 100 includes a first display area DA1 and a second display area DA2. The main light-emitting diode EDm is disposed in the first display area DA1 and electrically connected to the main pixel circuit PCm. The auxiliary light-emitting diode EDa is disposed in the circuit area PCA of the second display area DA2 and electrically connected to the auxiliary pixel circuit PCa.

[0178] The substrate 100 may comprise various materials such as glass, metal, or polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate. The substrate 100 may be provided with a multilayer structure laminating polymer resin and inorganic insulating material. For example, the substrate 100 may have a multilayer structure in which a matrix layer comprising a polymer resin and a barrier layer comprising an inorganic insulating material are alternately laminated.

[0179] A buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may reduce or block the penetration of moisture and other substances from below the substrate 100. The buffer layer 101 may comprise an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride, and may be configured as a single-layer or multi-layer structure comprising the aforementioned materials.

[0180] The main pixel circuit PCm and the auxiliary pixel circuit PCa can be disposed on the buffer layer 101. Both the main pixel circuit PCm and the auxiliary pixel circuit PCa can include a first transistor T1, a fifth transistor T5, a sixth transistor T6, a first capacitor Cst, and a second capacitor Chd.

[0181] The fifth transistor T5 may include a first semiconductor layer and a fifth gate electrode G5 disposed on the first semiconductor layer. In one or more embodiments, the fifth gate electrode G5 may be part of a first emitter control line EL1. The first semiconductor layer may include a fifth channel region A5 superimposed on the fifth gate electrode G5 in a planar view (e.g., in the +z direction or in the thickness direction of the substrate 100), and a fifth drain region D5 and a fifth source region S5 disposed at opposite ends of the fifth channel region A5 and doped with impurities. The first semiconductor layer may be a silicon semiconductor layer comprising a silicon semiconductor material. For example, the first semiconductor layer may include polysilicon.

[0182] The first gate insulating layer 102 may be disposed between the first semiconductor layer and the fifth gate electrode G5, and may be disposed on the buffer layer 101. The first gate insulating layer 102 may include inorganic insulating materials such as silicon oxide, silicon oxynitride and / or silicon nitride, and may be configured as a single layer or multilayer structure including the above materials.

[0183] The first electrode CEs1 of the first capacitor Cst and the first electrode CEh1 of the second capacitor Chd can be disposed on the first gate insulating layer 102. The fifth gate electrode G5 of the fifth transistor T5, the first electrode CEs1 of the first capacitor Cst, and the first electrode CEh1 of the second capacitor Chd can include low-resistance conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can be configured as a single-layer or multi-layer structure including the above materials.

[0184] The first interlayer insulating layer 103 may be configured to cover the fifth gate electrode G5 of the fifth transistor T5, the first electrode CEs1 of the first capacitor Cst, and the first electrode CEh1 of the second capacitor Chd, and may be disposed on the first gate insulating layer 102. The first interlayer insulating layer 103 may include inorganic insulating materials such as silicon oxide, silicon oxynitride, and / or silicon nitride, and may be configured as a single-layer or multi-layer structure including the above materials.

[0185] The second electrode CEs2 of the first capacitor Cst and the second electrode CEh2 of the second capacitor Chd can be disposed on the first interlayer insulating layer 103. The first electrode CEs1 and the second electrode CEs2 of the first capacitor Cst can be stacked on top of each other in a planar view (e.g., in the +z direction or in the thickness direction of the substrate 100). The first electrode CEh1 and the second electrode CEh2 of the second capacitor Chd can also be stacked on top of each other in a planar view (e.g., in the +z direction or in the thickness direction of the substrate 100). The second electrode CEs2 of the first capacitor Cst and the second electrode CEh2 of the second capacitor Chd can be integrally disposed. The second electrode CEs2 of the first capacitor Cst and the second electrode CEh2 of the second capacitor Chd can comprise low-resistance conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can be configured as a single-layer or multi-layer structure comprising the aforementioned materials.

[0186] The second interlayer insulating layer 104 can be disposed on the second electrode CEs2 of the first capacitor Cst and the second electrode CEh2 of the second capacitor Chd, and can also be disposed on the first interlayer insulating layer 103. The second interlayer insulating layer 104 may include inorganic insulating materials such as silicon oxide, silicon oxynitride and / or silicon nitride, and can be configured as a single-layer or multi-layer structure including the above materials.

[0187] The first transistor T1 may include a second semiconductor layer and a first gate electrode G1 disposed on the second semiconductor layer. The second semiconductor layer may include a first channel region A1 superimposed on the first gate electrode G1 in a planar view (e.g., in the +z direction or in the thickness direction of the substrate 100), and a first drain region D1 and a first source region S1 disposed at opposite ends of the first channel region A1 and doped with impurities.

[0188] The sixth transistor T6 may include a third semiconductor layer and a sixth gate electrode G6 disposed on the third semiconductor layer. In one or more embodiments, the sixth gate electrode G6 may be part of a second emitter control line EL2. The third semiconductor layer may include a sixth channel region A6 superimposed on the sixth gate electrode G6 in a planar view (e.g., in the +z direction or in the thickness direction of the substrate 100), and a sixth drain region D6 and a sixth source region S6 disposed at opposite ends of the sixth channel region A6 and doped with impurities.

[0189] In one or more embodiments, each of the second and third semiconductor layers may be an oxide semiconductor layer comprising an oxide semiconductor material. The oxide semiconductor material may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). In one or more embodiments, the second semiconductor layer may be an oxide semiconductor layer, and the third semiconductor layer may be a silicon semiconductor layer.

[0190] The second gate insulating layer 105 may be disposed between the second semiconductor layer and the first gate electrode G1, and between the third semiconductor layer and the sixth gate electrode G6. The second gate insulating layer 105 may comprise an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride, and may be configured as a single-layer or multi-layer structure comprising the aforementioned materials. In one or more embodiments, the second gate insulating layer 105 may have a shape corresponding to the first gate electrode G1 and the sixth gate electrode G6.

[0191] The first gate electrode G1 of the first transistor T1 and the sixth gate electrode G6 of the sixth transistor T6 may include low-resistance conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be configured as a single-layer or multi-layer structure including the above materials.

[0192] The third interlayer insulating layer 106 may be disposed on the first gate electrode G1 of the first transistor T1 and the sixth gate electrode G6 of the sixth transistor T6, and may also be disposed on the second interlayer insulating layer 104. The third interlayer insulating layer 106 may comprise inorganic insulating materials such as silicon oxide, silicon oxynitride, and / or silicon nitride, and may be configured as a single-layer or multi-layer structure comprising the aforementioned materials.

[0193] The first connecting electrode 501, the second connecting electrode 502, the third connecting electrode 503, the fourth connecting electrode 504, the fifth connecting electrode 505, and the sixth connecting electrode 506 can be disposed on the third interlayer insulating layer 106. A first planarization layer 107 can be disposed on the first connecting electrode 501, the second connecting electrode 502, the third connecting electrode 503, the fourth connecting electrode 504, the fifth connecting electrode 505, the sixth connecting electrode 506, and the third interlayer insulating layer 106. A seventh connecting electrode 507 and the driving voltage line PL can be disposed on the first planarization layer 107. The first planarization layer 107 may include organic insulating materials such as acrylic acid, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO). The first connecting electrode 501, the second connecting electrode 502, the third connecting electrode 503, the fourth connecting electrode 504, the fifth connecting electrode 505, the sixth connecting electrode 506, and the seventh connecting electrode 507, as well as the driving voltage line PL, may include low-resistance conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be configured as a single-layer or multi-layer structure including the aforementioned materials. For example, the first connecting electrode 501, the second connecting electrode 502, the third connecting electrode 503, the fourth connecting electrode 504, the fifth connecting electrode 505, the sixth connecting electrode 506, and the seventh connecting electrode 507, as well as the driving voltage line PL, may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0194] The first connection electrode 501 can electrically connect the first source region S1 of the first transistor T1, the second electrode CEs2 of the first capacitor Cst, and the second electrode CEh2 of the second capacitor Chd to form the third node N3 (see...). Figure 7 and Figure 11 ).

[0195] The second connection electrode 502 can be electrically connected to the first drain region D1 of the first transistor T1. The third connection electrode 503 can be electrically connected to the fifth drain region D5 of the fifth transistor T5. The second connection electrode 502 and the third connection electrode 503 can be electrically connected to each other to electrically connect the first drain region D1 of the first transistor T1 and the fifth drain region D5 of the fifth transistor T5.

[0196] The fourth connection electrode 504 can be electrically connected to the fifth source region S5 of the fifth transistor T5 and the drive voltage line PL. The fifth connection electrode 505 can be electrically connected to the sixth source region S6 of the sixth transistor T6 and the seventh connection electrode 507.

[0197] The sixth connection electrode 506 may be electrically connected to the sixth drain region D6 of the sixth transistor T6. In one or more embodiments, the sixth connection electrode 506 may be electrically connected to the first connection electrode 501. In one or more embodiments, the sixth connection electrode 506 may be omitted, and the first source region S1 of the first transistor T1 and the sixth drain region D6 of the sixth transistor T6 may be connected to each other.

[0198] The auxiliary pixel circuit PCa disposed in the second display area DA2 may further include a wire BRL. In one or more embodiments, the wire BRL can electrically connect the fifth connection electrode 505 and the sixth connection electrode 506. The sixth source region S6 and the sixth drain region D6 of the sixth transistor T6 can be electrically connected via the wire BRL. In one or more embodiments, because the sixth connection electrode 506 can be electrically connected to the first connection electrode 501, the wire BRL can electrically connect the fifth connection electrode 505 and the first connection electrode 501. That is, the wire BRL can electrically connect the pixel electrode 210 of the auxiliary light-emitting diode EDa to the first source region S1 of the first transistor T1, and can maintain the function for the third node N3 (see Figure 11 The conductive path for current flow between the pixel electrode 210 of the auxiliary light-emitting diode EDa.

[0199] The second planarization layer 108 may be disposed on the seventh connecting electrode 507, the driving voltage line PL, and the first planarization layer 107. The second planarization layer 108 may include organic insulating materials such as acrylic acid, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO).

[0200] The main light-emitting diode EDm and the auxiliary light-emitting diode EDa can be disposed on the second planarization layer 108. The main light-emitting diode EDm can be disposed on the main pixel circuit PCm, and the auxiliary light-emitting diode EDa can be disposed on the auxiliary pixel circuit PCa. Each of the main light-emitting diode EDm and the auxiliary light-emitting diode EDa may include a pixel electrode 210, an emitter layer 220, and a counter electrode 230.

[0201] Pixel electrode 210 may be disposed on the second planarization layer 108. Pixel electrode 210 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or compounds or mixtures thereof. Pixel electrode 210 may include a reflective film comprising the above-mentioned materials and a transparent conductive film disposed on or / and below the reflective film. The transparent conductive film may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). For example, pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0202] The pixel defining layer (PDL) may cover the edge of each of the pixel electrodes 210 and may define openings OPm and OPa that expose the center of each of the pixel electrodes 210. The main pixel opening OPm of the pixel defining layer PDL may be superimposed on the pixel electrode 210 of the main light-emitting diode EDm in a planar view. The main pixel opening OPm may define the emission region of the main light-emitting diode EDm. The auxiliary pixel opening OPa of the pixel defining layer PDL may be superimposed on the pixel electrode 210 of the auxiliary light-emitting diode EDa in a planar view. The auxiliary pixel opening OPa may define the emission region of the auxiliary light-emitting diode EDa. The pixel defining layer PDL may comprise organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin, and may be formed by methods such as spin coating.

[0203] The emitting layer 220 can be disposed in each of the main pixel opening OPm and auxiliary pixel opening OPa corresponding to each of the pixel electrodes 210 in the pixel defining layer PDL. The emitting layer 220 may include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color. A first functional layer may be disposed between the pixel electrode 210 and the emitting layer 220, and a second functional layer may be disposed between the emitting layer 220 and the counter electrode 230. The first functional layer may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Unlike the emitting layer 220, the first functional layer and / or the second functional layer may be integrally disposed on the substrate 100. In other words, the first functional layer and / or the second functional layer may cover the first display area DA1 and the second display area DA2.

[0204] The counter electrode 230 may be disposed on the emitting layer 220. The counter electrode 230 may include a conductive material with low work function. For example, the counter electrode 230 may include a transparent or translucent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, the counter electrode 230 may also include a layer such as ITO, IZO, ZnO, and / or In2O3 on the transparent or translucent layer comprising the above-mentioned materials. The counter electrode 230 may be integrally formed to correspond to the main light-emitting diode EDm disposed in the first display area DA1 and the auxiliary light-emitting diode EDa disposed in the second display area DA2.

[0205] Thin film encapsulation layer 300 (see) Figure 3 The light-emitting diode (LED) can be disposed on the counter electrode 230. The thin-film encapsulation layer 300 can cover the main LED EDm and the auxiliary LED EDa.

[0206] Although Figure 12A and Figure 12B The fifth transistor T5 is shown to be a silicon-based thin-film transistor including a silicon semiconductor layer and the sixth transistor T6 is an oxide-based thin-film transistor including an oxide semiconductor layer, but this disclosure is not limited thereto.

[0207] In one or more embodiments, the fifth transistor T5 may be an oxide-based thin-film transistor including an oxide semiconductor layer. In this case, the first semiconductor layer of the fifth transistor T5 may be disposed in the same layer as the second semiconductor layer of the first transistor T1, and the fifth gate electrode G5 of the fifth transistor T5 may be disposed in the same layer as the first gate electrode G1 of the first transistor T1.

[0208] In one or more embodiments, the fifth transistor T5 and the sixth transistor T6 may be silicon-based thin-film transistors including silicon semiconductor layers. In this case, the third semiconductor layer of the sixth transistor T6 may be disposed in the same layer as the first semiconductor layer of the fifth transistor T5, and the sixth gate electrode G6 of the sixth transistor T6 may be disposed in the same layer as the fifth gate electrode G5 of the fifth transistor T5.

[0209] Figure 13 It is an equivalent circuit diagram of an auxiliary pixel Pa according to one or more embodiments. Figure 14 and Figure 15 These are schematic cross-sectional views showing the second display area DA2 of the display panel DP according to an embodiment.

[0210] Reference Figure 13The auxiliary pixel Pa may include an auxiliary light-emitting diode EDa and an auxiliary pixel circuit PCa electrically connected to the auxiliary light-emitting diode EDa.

[0211] The auxiliary pixel circuit PCa can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GRL for transmitting the second gate signal GR, the third gate line GIL for transmitting the third gate signal GI, the first transmit control line EL1 for transmitting the first transmit control signal EM1, and the data line DL for transmitting the data voltage Vdata. The second transmit control line EL2 (see...) Figure 7 The component can pass through the auxiliary pixel circuit PCa, but can be unconnected to the auxiliary pixel circuit PCa. That is, components of the auxiliary pixel circuit PCa can be excluded from the second transmit control signal EM2 transmitted by the second transmit control line EL2 (see...). Figure 7 () Enables or disables conduction.

[0212] The auxiliary pixel circuit PCa can be electrically connected to the drive voltage line PL that transmits the first drive voltage ELVDD, the reference voltage line VRL that transmits the reference voltage VREF, and the initialization voltage line VIL that transmits the initialization voltage Vaint.

[0213] The auxiliary pixel circuit PCa may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5, a first capacitor Cst, a second capacitor Chd and a third capacitor Ced. Figure 13 The auxiliary pixel circuit PCa has the same characteristics as Figure 8 The auxiliary pixel circuit PCa has a similar structure, but the sixth transistor T6 can be omitted (see Figure 8 The third node N3 of the auxiliary pixel circuit PCa can be electrically connected to the fourth node N4 via a wire BRL, without using a transistor.

[0214] For example, such as Figure 14 and Figure 15 As shown, the auxiliary pixel circuit PCa may include circuits having similar characteristics to the main pixel circuit PCm (see...). Figure 12A The sixth transistor T6 (see) Figure 12A A fourth semiconductor layer of the same shape as the third semiconductor layer. The fourth semiconductor layer may include the sixth channel region A6 of the sixth transistor T6 of the main pixel circuit PCm (see...). Figure 12A The fourth semiconductor layer includes a corresponding conductive region A6' and a sixth drain region D6 and a sixth source region S6 located at both ends of the conductive region A6'. The conductive region A6', the sixth drain region D6, and the sixth source region S6 may be doped with impurities to become conductive. The fourth semiconductor layer may form a wire BRL that electrically connects the fifth connecting electrode 505 and the sixth connecting electrode 506.

[0215] Reference Figure 14 The second emitter control line EL2 can intersect with the fourth semiconductor layer. This is related to the main pixel circuit PCm (see...). Figure 12A Similarly, the second emitter control line EL2 can be disposed above the fourth semiconductor layer. The second emitter control line EL2 can be superimposed on the conductive region A6' in a planar view (e.g., in the +z direction or in the thickness direction of the substrate 100). The conductive region A6' can be made conductive by a process using a mask. Even when the second emitter control line EL2 transmits the second emitter control signal EM2 with a cutoff voltage (see...), Figure 7 When the conductive region A6' is in operation, it can also maintain the conductive path that electrically connects the fifth connecting electrode 505 and the sixth connecting electrode 506.

[0216] Reference Figure 15 An auxiliary emission control line EL2b can be disposed between the fourth semiconductor layer and the substrate 100. The auxiliary emission control line EL2b can be disposed in the second display area DA2 and can be electrically connected to the second emission control line EL2 in the same row. That is, the second emission control line EL2 can be separated into two parts, with the second display area DA2 located between the two parts, and the two parts of the second emission control line EL2 can be electrically connected through the auxiliary emission control line EL2b disposed in the second display area DA2 to transmit the second emission control signal EM2 (see...) Figure 7 Transmitted to the main pixel Pm.

[0217] When an oxide semiconductor layer is doped, the portion of the oxide semiconductor layer that overlaps with the gate electrode can be left undoped and can form the channel region of a transistor. In the main pixel circuit PCm (see...) Figure 12A In this configuration, the second emitter control line EL2 can be disposed on the third semiconductor layer. Therefore, the portion of the third semiconductor layer overlapping with the second emitter control line EL2 can be undoped and can constitute the sixth channel region A6 of the sixth transistor T6. Figure 15 In the auxiliary pixel circuit PCa, the auxiliary emission control line EL2b can be set below the fourth semiconductor layer. Therefore, the conductive region A6' can be doped together with the sixth source region S6 and the sixth drain region D6, and a wire BRL can be formed.

[0218] The wire BRL can (for example, because the sixth connection electrode 506 can be electrically connected to the first connection electrode 501) electrically connect the pixel electrode 210 of the auxiliary light-emitting diode EDa and the first source region S1 of the first transistor T1, and can maintain a conductive path for current flow between the first connection electrode 501 corresponding to the third node N3 and the pixel electrode 210 of the auxiliary light-emitting diode EDa.

[0219] Although Figure 15The auxiliary emission control line EL2b is shown to be disposed in the same layer as the second electrode CEs2 of the first capacitor Cst and the second electrode CEh2 of the second capacitor Chd, but this disclosure is not limited thereto. For example, the auxiliary emission control line EL2b may be disposed in the same layer as the fifth gate electrode G5 of the fifth transistor T5, the first electrode CEs1 of the first capacitor Cst, and the first electrode CEh1 of the second capacitor Chd.

[0220] Figure 16A , Figure 16B and Figure 16C It is a graph showing the drive current of the main pixel circuit and the auxiliary pixel circuit relative to the data voltage according to one or more embodiments.

[0221] Figure 16A The image shows the first green pixel Pg1 (see...) Figure 5 The driving current output by the first main pixel circuit PCm_g and the current generated by the second green pixel Pg2 (see...) Figure 6 The simulation results of the drive current output by the first auxiliary pixel circuit PCa_g. Figure 16B The image shows the first red pixel Pr1 (see...) Figure 5 The driving current output by the second main pixel circuit PCm_r and the current generated by the second red pixel Pr2 (see...) Figure 6 The simulation results of the driving current output by the second auxiliary pixel circuit PCa_r. Figure 16C The image shows the first blue pixel Pb1 (see...) Figure 5 The driving current output by the third main pixel circuit PCm_b and the current generated by the second blue pixel Pb2 (see...) Figure 6 The simulation results of the driving current output by the third auxiliary pixel circuit PCa_b.

[0222] Each of the first main pixel circuit PCm_g, the second main pixel circuit PCm_r, and the third main pixel circuit PCm_b can have the same characteristics as... Figure 7 The diagram shows the construction corresponding to the main pixel circuit PCm. Each of the first auxiliary pixel circuit PCa_g, the second auxiliary pixel circuit PCa_r, and the third auxiliary pixel circuit PCa_b can have the same structure as... Figure 8 The auxiliary pixel circuit PCa shown corresponds to the construction of the third transmit control signal EM2a (see...). Figure 10 The sixth transistor T6 (see) can be supplied to each of the first auxiliary pixel circuit PCa_g, the second auxiliary pixel circuit PCa_r, and the third auxiliary pixel circuit PCa_b. Figure 8The gate of the sixth transistor T6 is such that it can remain in the on state for a frame 1F. That is, in each of the first auxiliary pixel circuit PCa_g, the second auxiliary pixel circuit PCa_r, and the third auxiliary pixel circuit PCa_b, the gate of the third node N3 (see Figure 8 The current is maintained between the LED and the light-emitting diode through the conductive path through which it flows.

[0223] Reference Figure 16A , Figure 16B and Figure 16C In the data voltage Vdata region corresponding to grayscale representation, the current output by the first auxiliary pixel circuit PCa_g can be approximately 4 to 10 times the current of the first main pixel circuit PCm_g. The current output by the second auxiliary pixel circuit PCa_r can be approximately 5 to 7 times the current of the second main pixel circuit PCm_r. The current output by the third auxiliary pixel circuit PCa_b can be approximately 10 times the current of the third main pixel circuit PCm_b.

[0224] According to one or more embodiments of this disclosure, the drive current output by the auxiliary pixel circuit PCa can be increased by keeping the sixth transistor T6 of the auxiliary pixel circuit PCa in a conducting state or by forming a conductive path through which current flows between the third node N3 and the auxiliary light-emitting diode EDa via a wire BRL. When the drive current output from the auxiliary pixel circuit PCa increases, the brightness of the auxiliary light-emitting diode EDa increases, thereby reducing the brightness difference caused by the difference in the number of pixels per unit area between the first display area DA1 and the second display area DA2.

[0225] The display device 1 according to one or more embodiments of the present disclosure can be employed by various electronic devices. The electronic device according to one or more embodiments includes the aforementioned display device 1, and may also include modules or devices with additional functions in addition to the display device 1.

[0226] Figure 17 This is a schematic block diagram of an electronic device 10 according to one or more embodiments.

[0227] Reference Figure 17 The electronic device 10 according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 10 may also include an input module 15, a non-image output module 16, and / or a communication module 17.

[0228] Electronic device 10 can output various information in the form of images through display module 11. When processor 12 executes an application stored in memory 13, it can provide the user with image information provided by the application through display module 11. Power module 14 may include a power module (such as a power adapter or battery device) and a power conversion module configured to convert the power supplied from the power module and generate the power required for the operation of electronic device 10. Input module 15 can provide input information to processor 12 and / or display module 11. Non-image output module 16 can receive information other than images (such as sound, touch, and / or light) from processor 12 and provide such information to the user. Communication module 17 can be configured to perform the sending and receiving of information between electronic device 10 and external devices, and may include a receiver and / or transmitter.

[0229] Processor 12 can be configured as two or more processors from a functional or structural perspective. For example, processor 12 may include a main processor as a first driver chip including a CPU and an auxiliary processor as a second driver chip including a controller configured to receive image signals from the main processor and process the image signals according to the interface specifications of display module 11.

[0230] The memory 13 may include at least one of non-volatile memory and volatile memory. The memory 13 may store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals may be transmitted to the display module 11, and the display module 11 may be configured to process the received signals and output image information through the display screen.

[0231] The power module 14 may include a power supply module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10. The power conversion through the power conversion module may include, but is not limited to, direct current (DC) to DC conversion, alternating current (AC) to DC conversion, and DC to AC conversion.

[0232] Input module 15 can provide input information to processor 12 and / or display module 11. Input module 15 may include not only physical buttons, keyboards, and microphones, but also various sensor modules. Examples of sensor modules may include touch sensors, pressure sensors, proximity sensors, position sensors, digitizers, motion recognition sensors, camera sensors, photodetectors, photoelectric conversion sensors, temperature sensors, and biosensors (such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, and / or heart rate sensors).

[0233] The non-image output module 16 can receive information other than images from the processor 12 and provide that information to the user. Examples of the non-image output module 16 may include a sound module, a tactile module, a light-emitting module, etc., and may also include other functional modules inherent to the electronic device 10 (e.g., a cooling module of a refrigerator, etc.).

[0234] The communication module 17 can be configured to perform the sending and receiving of information between the electronic device 10 and an external device, and may include a receiver and a transmitter. The communication module 17 may include various wireless communication modules (such as mobile communication modules, WiFi modules, Bluetooth modules, etc.) or various wired communication modules.

[0235] At least one of the components of the electronic device 10 described above may be included in the display device 1 according to the above embodiment (see Figure 1 Furthermore, some modules that are functionally included in a single module may be included in display device 1, while other modules may be disposed separately from display device 1. For example, display device 1 may include display module 11, and processor 12, memory 13, and power module 14 may be disposed as other devices in electronic device 10, instead of display device 1. In the example, power module 14 may be disposed in display device 1 and may provide power to processor 12 and memory 13 in electronic device 10. However, this disclosure is not limited thereto.

[0236] Figures 18 to 20 These are schematic diagrams of electronic devices according to various embodiments.

[0237] Figure 18 Examples of electronic devices 10 are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a monitor 10_1e for a table.

[0238] In addition to the display module 11, the smartphone 10_1a may also include an input module such as a touch sensor and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the processed information through the display module 11 of the electronic device 10.

[0239] Similar to the smartphone 10_1a, the tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and table monitor 10_1e may also include a display module 11 and an input module, and may also include a communication module as appropriate.

[0240] Figure 19An example of an electronic device 10, including a display module 11, being applied to a wearable electronic device is shown. Wearable electronic devices may include smart glasses 10_2a, an HMD 10_2b, a smartwatch 10_2c, etc.

[0241] The smart glasses 10_2a and HMD 10_2b may include a display module 11 configured to project a display image and a reflector configured to reflect the projected display image and provide the display image to the user's eyes, so as to provide the user with a virtual reality (VR) or augmented reality (AR) image.

[0242] The smartwatch 10_2c may include a biometric sensor as an input device and may provide the user with biometric information identified by the biometric sensor through the display module 11.

[0243] Figure 20 An example of an electronic device 10, including a display module 11, being applied to a vehicle is shown. For example, the electronic device 10_3 can be used as a vehicle's instrument panel or central dashboard, or as a central information display (CID) arranged on the vehicle's dashboard or as an interior mirror display that replaces the side mirrors.

[0244] In one or more embodiments, display device 1 (see one or more embodiments) is used. Figure 1 The electronic device 10 can include not only devices primarily used for screen display (such as billboards, electronic display panels, game consoles, etc.), but also various household appliances (such as refrigerators, washing machines, dryers, air conditioners, robotic cleaners, etc.) for displaying information via the display module 11. Furthermore, when the display module 11 has a light-transmitting function, it can be employed by the electronic device 10 (such as a smart window or transparent display device for simultaneously displaying a background and an image). The type of electronic device 10 according to one or more embodiments is not limited to the examples described above, and various other electronic devices may also be provided.

[0245] According to one or more embodiments described above, by enhancing the brightness of the area where the components are disposed, a display device for displaying high-quality images and an electronic device including the display device can be realized. However, the spirit and scope of this disclosure are not limited to these effects, aspects, and features.

[0246] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display device, the display device comprising: The substrate includes a first display area and a second display area, wherein the second display area includes a circuit area and a transmissive area; A first pixel circuit and a first light-emitting diode, wherein the first pixel circuit is located in the first display area and the first light-emitting diode is electrically connected to the first pixel circuit; as well as A second pixel circuit and a second light-emitting diode, wherein the second pixel circuit is located in the second display area, and the second light-emitting diode is electrically connected to the second pixel circuit. Each of the first pixel circuit and the second pixel circuit includes: a driving transistor, comprising a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; a data writing transistor, electrically connected between a data line and the first node; a first emission control transistor, electrically connected between a driving voltage line and the second node; and a second emission control transistor, electrically connected between the third node and a corresponding light-emitting diode among the first and second light-emitting diodes. In this process, the second emission control transistor of the second pixel circuit remains in the on state within one frame.

2. The display device according to claim 1, wherein: The first emission control transistor of each of the first pixel circuit and the second pixel circuit is turned on or off according to the first emission control signal; The second emission control transistor of the first pixel circuit is turned on or off according to a second emission control signal that is different from the first emission control signal; and The second emission control transistor of the second pixel circuit is turned on according to the third emission control signal.

3. The display device according to claim 2, wherein: The frame includes a first scanning period and at least one second scanning period; The first scanning period includes a first time period in which the second transmit control signal is supplied as a cutoff voltage; and During the at least one second scan period, the second transmit control signal is supplied as an on-state voltage.

4. The display device according to claim 3, wherein, The third transmit control signal is supplied as the turn-on voltage during the first scan period and the at least one second scan period.

5. The display device according to claim 1, wherein, The driving transistor includes an oxide semiconductor layer.

6. The display device according to claim 5, wherein, The first emitter control transistor includes a silicon semiconductor layer.

7. The display device according to claim 1, wherein, Each of the first pixel circuit and the second pixel circuit further includes: A first initialization transistor is electrically connected between a reference voltage line and the driving transistor; and The second initialization transistor is electrically connected between the initialization voltage line and the corresponding LED among the first LED and the second LED.

8. A display device, the display device comprising: The substrate includes a first display area and a second display area, wherein the second display area includes a circuit area and a transmissive area; A first pixel circuit and a first light-emitting diode, wherein the first pixel circuit is located in the first display area and the first light-emitting diode is connected to the first pixel circuit; as well as A second pixel circuit and a second light-emitting diode, wherein the second pixel circuit is located in the second display area, and the second light-emitting diode is electrically connected to the second pixel circuit. Each of the first pixel circuit and the second pixel circuit includes: a driving transistor, comprising a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; a data writing transistor electrically connected between a data line and the first node; and a first emitter control transistor electrically connected between a driving voltage line and the second node. The first pixel circuit further includes a second emission control transistor electrically connected between the first light-emitting diode and the third node, and The third node of the second pixel circuit and the second light-emitting diode are electrically connected via wires.

9. The display device according to claim 8, wherein: The second pixel circuit further includes a third emission control transistor, which is electrically connected between the second light-emitting diode and the third node, and includes a gate electrode and a semiconductor layer disposed below the gate electrode.

10. The display device according to claim 9, wherein: The semiconductor layer of the third emitter control transistor includes a channel region stacked with the gate electrode and source and drain regions on opposite sides of the channel region; and The wire electrically connects the source region and the drain region of the third emitter control transistor.

11. The display device according to claim 8, wherein: The second emission control transistor in the first pixel circuit includes a first semiconductor layer, the first semiconductor layer including a gate electrode, a channel region superimposed on the gate electrode, and source and drain regions on opposite sides of the channel region; and The wires in the second pixel circuit include a second semiconductor layer having a shape corresponding to the first semiconductor layer.

12. The display device according to claim 11, further comprising: The transmit control line is configured to transmit the transmit control signal to the gate electrode of the second transmit control transistor. The emission control line intersects with the second semiconductor layer.

13. The display device according to claim 11, further comprising: The transmit control line is configured to transmit the transmit control signal to the gate electrode of the second transmit control transistor; as well as An auxiliary emission control line is located between the substrate and the second semiconductor layer. The transmission control line is electrically connected to the auxiliary transmission control line.

14. The display device according to claim 8, wherein, The driving transistor includes an oxide semiconductor layer.

15. The display device according to claim 14, wherein, The first emitter control transistor includes a silicon semiconductor layer.

16. The display device according to claim 8, wherein, Each of the first pixel circuit and the second pixel circuit further includes: A first initialization transistor is electrically connected between a reference voltage line and the driving transistor; and The second initialization transistor is electrically connected between the initialization voltage line and the corresponding LED among the first LED and the second LED.

17. An electronic device, the electronic device comprising: A display device is configured to display an image; Memory, used to store applications; as well as The processor is configured to execute the application and transmit image data signals or control signals to the display device. The display device includes: a substrate comprising a first display area and a second display area, the second display area including a circuit area and a transmissive area; a first pixel circuit and a first light-emitting diode, the first pixel circuit being located in the first display area and the first light-emitting diode being connected to the first pixel circuit; and a second pixel circuit and a second light-emitting diode, the second pixel circuit being located in the second display area and the second light-emitting diode being electrically connected to the second pixel circuit. Each of the first pixel circuit and the second pixel circuit includes: a driving transistor, comprising a gate electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node; a data writing transistor electrically connected between a data line and the first node; and a first emitter control transistor electrically connected between a driving voltage line and the second node. The first pixel circuit further includes a second emission control transistor electrically connected between the first light-emitting diode and the third node, and The third node of the second pixel circuit and the second light-emitting diode are electrically connected through a conductive path.

18. The electronic device according to claim 17, wherein: The second pixel circuit further includes a third emission control transistor electrically connected between the second light-emitting diode and the third node of the second pixel circuit; and The third emitter control transistor remains in the ON state.

19. The electronic device according to claim 17, wherein, The third node of the second pixel circuit and the second light-emitting diode are electrically connected via wires.

20. The electronic device according to claim 17, wherein, The driving transistor includes an oxide semiconductor layer.

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