Multilayer electronic component

Abstract

This disclosure provides a multilayer electronic component, comprising: a body including a laminate and a cover, wherein an dielectric layer and an inner electrode are stacked in a first direction in the laminate, and the cover is disposed on each of a plurality of surfaces of the laminate that are opposite to each other in the first direction; the body includes a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in the third direction; and an outer electrode disposed on each of the third surface and the fourth surface and connected to the inner electrode. The cover includes a second region adjacent to the third surface or the fourth surface and a first region disposed between the second regions, wherein the average hardness of the second region is greater than the average hardness of the first region.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0039511, filed on March 27, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs, a type of multilayer electronic component) are chip capacitors mounted on printed circuit boards of various electronic products, such as video devices like liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, mobile phones, and infotainment systems, to charge or discharge them.

[0004] MLCCs may include a cover and side edges to prevent damage to the internal electrodes due to physical and / or chemical stress.

[0005] Typically, the cover and side edges undergo a sintering process, which can lead to uneven stress distribution across the entire area. As a result, the toughness of the areas of the cover and side edges adjacent to the exposed inner electrode surface of the body may decrease, increasing the likelihood of edge chipping.

[0006] Since such edge chipping can reduce the moisture-proof reliability of MLCCs, structural improvements are needed to reduce the frequency of edge chipping in the areas of the cover and side edges adjacent to the surface of the exposed inner electrode of the body. Summary of the Invention

[0007] One aspect of this disclosure is to reduce the edge chipping frequency in the area of ​​the cover adjacent to the main body surface of the exposed inner electrode.

[0008] One aspect of this disclosure is to reduce the edge chipping frequency in the region of the side edge adjacent to the main body surface of the exposed inner electrode.

[0009] According to one aspect of this disclosure, a multilayer electronic component includes: a body comprising a laminate and a cover, wherein an dielectric layer and an inner electrode are stacked in a first direction, the cover being disposed on two surfaces of the laminate opposite to each other in the first direction, the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in a second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in a third direction; and an outer electrode disposed on each of the third surface and the fourth surface and connected to the inner electrode. The cover includes a second region adjacent to the third surface or the fourth surface and a first region disposed between the second region, wherein the average hardness of the second region is greater than the average hardness of the first region.

[0010] According to one aspect of this disclosure, a multilayer electronic component includes: a body comprising a laminate and side edges, wherein an dielectric layer and an inner electrode are stacked in a first direction in the laminate, the side edges being disposed on two surfaces of the laminate that are opposite to each other in a third direction, the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in the third direction; and an outer electrode disposed on each of the third surface and the fourth surface and connected to the inner electrode. The side edges include a fourth region adjacent to the third surface or the fourth surface and a third region disposed between the fourth regions, and the average hardness of the fourth region may be greater than the average hardness of the third region. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 A perspective view of a multilayer electronic assembly according to an embodiment is schematically shown; Figure 2 schematically showing along Figure 1 A cross-sectional view taken from line I-I'; Figure 3 schematically showing along Figure 1 A cross-sectional view taken from line II-II'; Figure 4 schematically showing along Figure 1 A cross-sectional view taken from line III-III'; Figure 5 schematically showing along Figure 1 A cross-sectional view taken from line IV-IV'; Figure 6 A perspective view of the main body according to an embodiment is schematically shown; and Figure 7 It is a graph showing the hardness of the cover and side edge portions at each location according to an embodiment. Detailed Implementation

[0012] In the following description, embodiments will be referenced to the accompanying drawings. However, embodiments may be modified in various other forms, and the scope of this disclosure is not limited to the embodiments described below. Furthermore, embodiments are provided to more fully explain this disclosure to those skilled in the art. Therefore, for clarity, the shape and size of elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings are the same elements.

[0013] Furthermore, for clarity of description, parts irrelevant to the description have been omitted. The dimensions (e.g., thickness) of each component shown in the figures are arbitrarily indicated for ease of explanation. Therefore, the disclosure is not necessarily limited to what is shown. Moreover, components having the same function within the scope of the same concept are described using the same reference numerals. Furthermore, throughout the specification, when a part is referred to as "comprising" a component, this does not exclude other components but rather implicitly includes them, unless otherwise stated.

[0014] Figure 1 A perspective view of a multilayer electronic assembly according to an embodiment is shown schematically.

[0015] Figure 2 schematically showing along Figure 1 The cross-sectional view taken from line I-I'.

[0016] Figure 3 schematically showing along Figure 1 The cross-sectional view taken from line II-II'.

[0017] Figure 4 schematically showing along Figure 1 The cross-sectional view taken from line III-III'.

[0018] Figure 5 schematically showing along Figure 1 The cross-sectional view taken from line IV-IV'.

[0019] Figure 6 A perspective view of the main body according to an embodiment is shown schematically.

[0020] Figure 7It is a graph showing the hardness of the cover and side edge portions at each location according to an embodiment.

[0021] In the accompanying drawings, the X direction can refer to the thickness direction, the Y direction can refer to the length direction, and the Z direction can refer to the width direction. The stacking direction of the internal electrodes or dielectric layers can be either the thickness direction or the width direction.

[0022] In the following text, reference will be made to Figures 1 to 7 A detailed description is provided of the multilayer electronic assembly 1000 according to embodiments and its various embodiments.

[0023] The multilayer electronic component 1000 according to an embodiment may include: a body 110 including a laminate 100 and covers 112 and 113, wherein an dielectric layer 111 and inner electrodes 121 and 122 are stacked in a first direction in the laminate 100, and covers 112 and 113 are respectively disposed on two surfaces of the laminate 100 that are opposite to each other in the first direction; the body 110 includes a first surface 1 and a second surface 2 that are opposite to each other in the first direction, a third surface 3 and a fourth surface 4 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in the second direction, and a fifth surface 5 and a sixth surface 6 that are connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and are opposite to each other in the third direction; and outer electrodes 130 and 140 that are respectively disposed on the third surface 3 and the fourth surface 4 and respectively connected to the inner electrodes 121 and 122. The covering portions 112 and 113 may include second regions 112b and 113b adjacent to the third surface 3 or the fourth surface 4, and first regions 112a and 113a disposed between the second regions 112b and 113b, wherein the average hardness of the second regions 112b and 113b may be greater than the average hardness of the first regions 112a and 113a.

[0024] The multilayer electronic assembly 1000 according to an embodiment may include: a body 110 including a laminate 100 and side edges 114 and 115, wherein an dielectric layer 111 and inner electrodes 121 and 122 are stacked in a first direction in the laminate 100, and the side edges 114 and 115 are respectively disposed on two surfaces of the laminate 100 that are opposite to each other in a third direction; the body 110 includes a first surface 1 and a second surface 2 that are opposite to each other in the first direction, a third surface 3 and a fourth surface 4 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in the second direction, and a fifth surface 5 and a sixth surface 6 that are connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and are opposite to each other in a third direction; and outer electrodes 130 and 140 that are respectively disposed on the third surface 3 and the fourth surface 4 and respectively connected to the inner electrodes 121 and 122. The side edge portions 114 and 115 may include fourth regions 114b and 115b adjacent to the third surface 3 or the fourth surface 4, and third regions 114a and 115a disposed between the fourth regions 114b and 115b, and the average hardness of the fourth regions 114b and 115b may be greater than the average hardness of the third regions 114a and 115a.

[0025] The body 110 may include a stack 100 in which a dielectric layer 111 and internal electrodes 121 and 122 are stacked in a first direction.

[0026] There are no particular restrictions on the specific shape of the main body 110, but as Figure 1 and Figure 6 As shown, the body 110 can be formed into a hexahedral shape or a shape similar to a hexahedron. Because the ceramic powder included in the body 110 shrinks during the firing process, the body 110 may not have a hexahedral shape with perfect straight lines, but may have a roughly hexahedral shape.

[0027] Reference Figure 1 and Figure 6 The main body 110 may include: a first surface 1 and a second surface 2, which are opposite to each other in a first direction; a third surface 3 and a fourth surface 4, which are connected to the first surface 1 and the second surface 2 and are opposite to each other in a second direction; and a fifth surface 5 and a sixth surface 6, which are connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and are opposite to each other in a third direction.

[0028] Reference Figure 2 and Figure 3 The main body 110 may include a laminate 100, in which inner electrodes 121 and 122 and a dielectric layer 111 are stacked in a first direction. The laminate 100 may include a capacitor forming portion Ac and a region other than the capacitor forming portion Ac, which is the region where the first inner electrode 121 and the second inner electrode 122 are stacked in the first direction.

[0029] The dielectric layers 111 forming the stacked body 100 are in a sintered state, and adjacent dielectric layers 111 may be integrated such that it is difficult to identify the boundary between adjacent dielectric layers 111 without using a scanning electron microscope (SEM).

[0030] The raw material for forming the dielectric layers 111 is not particularly limited as long as sufficient capacitance can be obtained therefrom. For example, barium titanate-based materials, lead composite perovskite-based materials, strontium titanate-based materials, etc. can be used. The barium titanate-based material may include BaTiO3-based ceramic powder. Examples of the BaTiO3-based ceramic powder may include BaTiO3 or (Ba 1-x Ca x )TiO3(0<x<1), Ba(Ti 1-y Ca y )O3(0<y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0<x<1, 0<y<1) or Ba(Ti 1-y Zr y )O3(0<y<1), etc.

[0031] In addition, according to an aspect of the present disclosure, the raw material for forming the dielectric layers 111 may include barium titanate (BaTiO3) powder added with various ceramic additives such as organic solvents, binders, dispersants and the like.

[0032] The average thickness td of the dielectric layers 111 is not particularly limited. For example, if miniaturization and high capacitance of the multilayer electronic component 1000 are required, the average thickness td of the dielectric layers 111 can be 0.35 μm or less. If it is required to improve the reliability of the multilayer electronic component 1000 under high temperature and high voltage, the average thickness td of the dielectric layers 111 can be 1 μm or more.

[0033] The average thickness td of the dielectric layers 111 may refer to the average thickness of one or more dielectric layers among the plurality of dielectric layers in a first direction.

[0034] The average thickness of dielectric layer 111 in the first direction can be measured by scanning an image of the cross-section of the multilayer electronic assembly 1000 in the first and second directions using a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the average thickness of dielectric layer 111 in the first direction can be an average value calculated by measuring the thickness of dielectric layer 111 in the first direction at four or more equally spaced points in the second direction of the scanned image. Four or more equally spaced points can be specified in the capacitor forming section Ac. Furthermore, the average thickness of dielectric layer 111 in the first direction can be further generalized by extending this average value measurement to four or more dielectric layers 111.

[0035] The inner electrodes 121 and 122 may be alternately disposed with the dielectric layer 111 in a first direction, and may include a first inner electrode 121 connected to the first outer electrode 130 and a second inner electrode 122 connected to the second outer electrode 140.

[0036] The first inner electrode 121 and the second inner electrode 122 can be electrically isolated from each other by a dielectric layer 111 disposed between them.

[0037] There are no particular limitations on the materials used to form the internal electrodes 121 and 122, and any material with excellent conductivity can be used. For example, the internal electrodes 121 and 122 may include at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0038] Furthermore, the internal electrodes 121 and 122 can be formed by printing a conductive paste for the internal electrodes, comprising at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, onto a ceramic green sheet. The printing method for the conductive paste for the internal electrodes can be screen printing or gravure printing, but this disclosure is not limited thereto.

[0039] The thickness te of the inner electrodes 121 and 122 does not need to be specially limited.

[0040] If miniaturization and high capacitance are required for the multilayer electronic component 1000, the average thickness te of the inner electrodes 121 and 122 can be 0.35 μm or less. If improved reliability of the multilayer electronic component 1000 at high temperatures and high voltages is required, the average thickness te of the inner electrodes 121 and 122 can be 1 μm or greater.

[0041] The average thickness te of the inner electrodes 121 and 122 may refer to the average thickness of one or more of the inner electrodes 121 and 122 in the first direction.

[0042] The first-direction average thickness of the inner electrodes 121 and 122 can be measured by scanning images of the first and second-direction cross sections of the multilayer electronic assembly 1000 at 10,000x magnification using a scanning electron microscope (SEM). More specifically, the first-direction average thickness of an inner electrode can be an average calculated by measuring the first-direction thickness of an inner electrode at four or more equally spaced points in the second direction in the scanned image. Four or more equally spaced points can be specified in the capacitor forming section Ac. Furthermore, the first-direction average thickness of the inner electrodes 121 and 122 can be further generalized by extending this average measurement to four or more inner electrodes 121 and 122 and measuring the average value.

[0043] Reference Figure 2 and Figure 3 Covers 112 and 113 may be disposed on each of a plurality of surfaces of the laminate 100 that are opposite to each other in a first direction. Covers 112 and 113 do not include inner electrodes 121 and 122 and may contain the same dielectric material as dielectric layer 111, but their specific composition may be different.

[0044] The average thickness tc of the covers 112 and 113 does not need to be particularly limited. However, in order to promote miniaturization and high capacitance of multilayer electronic components, the average thickness tc of the covers 112 and 113 can be 15 μm or less. In this case, the average thickness tc of the covers 112 and 113 can refer to the average thickness of the first cover 112 and the average thickness of the second cover 113, respectively.

[0045] The average thickness tc of the covers 112 and 113 may refer to the dimension in the first direction, and may be the average of the dimensions in the first direction of the covers 112 and 113 measured at five equally spaced points above or below the capacitor forming portion Ac.

[0046] Reference Figure 3 Side edge portions 114 and 115 may be disposed on two surfaces of the laminate 100 in the third direction.

[0047] like Figure 3 As shown, the side edges 114 and 115 may refer to the area between the two ends of the first inner electrode 121 and the second inner electrode 122 and the outer surface of the body 110 in the cross section along the width-thickness (WT) direction of the body 110.

[0048] The side edges 114 and 115 are primarily used to prevent damage to the internal electrode due to physical and / or chemical stress.

[0049] To suppress the step difference caused by the inner electrodes 121 and 122, the side edge portions 114 and 115 can be formed by cutting the laminate 100 such that the inner electrodes are exposed on the two side surfaces of the capacitor forming portion Ac that are opposite to each other in the third direction, and then stacking a single dielectric layer or two or more dielectric layers on the two side surfaces of the capacitor forming portion Ac in the third direction.

[0050] The width wm of the side edges 114 and 115 does not need to be particularly limited. However, in order to facilitate the miniaturization and high capacitance of multilayer electronic components, the average width of the side edges 114 and 115 can be 15 μm or less.

[0051] The average width wm of the side edges 114 and 115 can refer to the average dimension of the side edges 114 and 115 in the third direction, and can be the average value of the third-direction dimension of the side edges 114 and 115 measured at five equally spaced points on the side surface of the capacitor forming part Ac.

[0052] External electrodes 130 and 140 are disposed on the main body 110.

[0053] External electrodes 130 and 140 can be disposed on the third surface 3 and the fourth surface 4, which are surfaces opposite to each other in a second direction perpendicular to the first direction. External electrodes 130 and 140 can be connected to internal electrodes 121 and 122. Specifically, the first external electrode 130 can be connected to the first internal electrode 121 by being disposed on the third surface 3, which is a surface of the body 110 perpendicular to the second direction perpendicular to the first direction. The second external electrode 140 can be connected to the second internal electrode 122 by being disposed on the fourth surface 4, which is another surface of the body 110 perpendicular to the second direction perpendicular to the first direction.

[0054] Although this embodiment describes the structure of a multilayer electronic assembly 1000 having two external electrodes 130 and 140, the number and shape of the external electrodes 130 and 140 may vary depending on the shape or other uses of the internal electrodes 121 and 122.

[0055] The external electrodes 130 and 140 may include electrode layers 131 and 141 in contact with the third surface 3 and the fourth surface 4, and plating layers 132 and 142 disposed on the electrode layers 131 and 141.

[0056] Electrode layers 131 and 141 may comprise a conductive metal. There are no particular limitations on the conductive metal, as long as it is electrically connectable to the inner electrodes 121 and 122 to form a capacitor. For example, the conductive metal may comprise at least one selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0057] More specifically, electrode layers 131 and 141 may be sintered electrodes comprising conductive metal and glass, or resin-based electrodes comprising conductive metal and resin.

[0058] In addition, electrode layers 131 and 141 can be formed by sequentially forming sintered electrodes and resin-based electrodes on the body 110.

[0059] Alternatively, electrode layers 131 and 141 can be formed by transferring a sheet containing conductive metal onto the body 110 or by transferring a sheet containing conductive metal onto a sintered electrode.

[0060] Coatings 132 and 142 can be used to improve mounting characteristics.

[0061] There are no particular restrictions on the type of plating layers 132 and 142, and plating layers 132 and 142 may be a single layer containing at least one of nickel (Ni), tin (Sn), silver (Ag), palladium (Pd) and alloys thereof, or may be formed by multiple layers.

[0062] More specifically, for example, plating layers 132 and 142 may be nickel (Ni) plating layers or tin (Sn) plating layers, or they may be in the form of nickel plating layers and tin plating layers sequentially formed on electrode layers 131 and 141, or they may be in the form of tin plating layers, nickel plating layers and tin plating layers formed sequentially. Furthermore, plating layers 132 and 142 may include multiple nickel plating layers or multiple tin plating layers.

[0063] There are no particular restrictions on the size of the multilayer electronic component 1000.

[0064] However, in order to achieve both miniaturization and high capacitance, the thickness of the dielectric layer and the internal electrode should be reduced, and the number of stacked layers should be increased. Therefore, the size of the multilayer electronic component 1000 can be equal to or less than the size of 1005 (length × width: 1.0 mm × 0.5 mm, with the error range of length and width within ±5%) and 0603 (length × width: 0.6 mm × 0.3 mm, with the error range of length and width within ±5%).

[0065] Typically, the various regions of the covers 112 and 113 and the side edges 114 and 115 may be subjected to uneven stress during the firing process. As a result, the toughness of the regions of the side edges 114 and 115 and the covers 112 and 113 adjacent to the third surface 3 and the fourth surface 4 of the exposed inner electrodes 121 and 122 of the body 110 may be reduced, thereby increasing the possibility of edge chipping. Edge chipping that occurs in this way may reduce the moisture resistance reliability of the multilayer electronic assembly 1000.

[0066] Reference Figure 6 and Figure 7 The hardness values ​​of the locations ① and ③ of the cover portions 112 and 113 and the side edge portions 114 and 115 that are adjacent to the third surface 3 or the fourth surface 4 of the exposed inner electrodes 121 and 122 of the body 110 and where chipping is likely to occur frequently can be at least 1.5 times the hardness values ​​of the locations ② and ④ that are not adjacent to the third surface 3 and the fourth surface 4. Even when a dielectric sheet with a uniform composition is used to form the cover portions 112 and 113 or a dielectric sheet with a uniform composition is used to form the side edge portions 114 and 115, such differences in hardness can occur due to differences in the shrinkage rate at different locations within the body 110.

[0067] On the other hand, refer to Figure 4 and Figure 6 In the multilayer electronic assembly 1000 according to an embodiment, the second cover 113 includes a second region 113b adjacent to the third surface 3 or the fourth surface 4 and a first region 113a disposed between the second regions 113b. The average hardness of the second region 113b can be controlled to be higher than the average hardness of the first region 113a, thereby reducing the possibility of edge chipping in the second region 113b of the second cover 113 (which is the region adjacent to the third surface 3 or the fourth surface 4 of the exposed inner electrodes 121 and 122 of the body 110) and improving the moisture-proof reliability of the multilayer electronic assembly 1000. The above description of the second cover 113 also applies to the first cover 112, for example, referring to... Figure 2 The first cover 112 includes a second region 112b adjacent to the third surface 3 or the fourth surface 4 and a first region 112a disposed between the second regions 112b. The average hardness of the second region 112b can be controlled to be higher than the average hardness of the first region 112a, thereby reducing the possibility of edge chipping in the second region 112b of the first cover 112 (which is the region adjacent to the third surface 3 or the fourth surface 4 of the exposed inner electrodes 121 and 122 of the body 110) and improving the moisture-proof reliability of the multilayer electronic assembly 1000.

[0068] In addition, on the other hand, referring to Figure 5 and Figure 6In the multilayer electronic assembly 1000 according to an embodiment, the side edges 114 and 115 include fourth regions 114b and 115b adjacent to the third surface 3 or the fourth surface 4, and third regions 114a and 115a disposed between the fourth regions 114b and 115b. The average hardness of the fourth regions 114b and 115b is controlled to be higher than the average hardness of the third regions 114a and 115a, thereby reducing the possibility of edge chipping in the fourth regions 114b and 115b of the side edges 114 and 115 (which are regions adjacent to the third surface 3 or the fourth surface 4 of the exposed inner electrodes 121 and 122 of the body 110) and improving the moisture resistance reliability of the multilayer electronic assembly 1000.

[0069] When the ratio of the average hardness of the second regions 112b and 113b of the covers 112 and 113 to the average hardness of the first regions 112a and 113a is less than 1.5, the present disclosure can be effective in reducing the frequency of edge chipping in the second regions 112b and 113b of the covers 112 and 113. Furthermore, there is no particular limitation on the lower limit of the ratio of the average hardness of the second regions 112b and 113b of the covers 112 and 113 to the average hardness of the first regions 112a and 113a, and it can exceed, for example, 1.0. For example, in an embodiment, the ratio of the average hardness of the second regions 112b and 113b of the covers 112 and 113 to the average hardness of the first regions 112a and 113a can be greater than 1.0 and less than 1.5, thereby reducing the frequency of edge chipping in the second regions 112b and 113b of the covers 112 and 113, and thus further improving the moisture-proof reliability of the multilayer electronic assembly 1000.

[0070] Examples of methods for measuring the average hardness of various regions of the covers 112 and 113 are shown below. However, this disclosure is not limited to the measurement methods described below.

[0071] First, the multilayer electronic assembly 1000 is polished along the first surface 1 or the second surface 2 in a first direction to expose the covers 112 and 113. Then, an image of the exposed surfaces of the covers 112 and 113 is observed using an optical device such as an optical microscope. Using an image processing program, the regions between the points 1 / 10 to 3 / 20 (e.g., 1 / 10 to 3 / 20 of the length of the covers 112 and 113 in the second direction) at one end of the covers 112 and 113 in the second direction and the regions between the points 1 / 10 to 3 / 20 (e.g., 1 / 10 to 3 / 20 of the length of the covers 112 and 113 in the second direction) at the other end of the covers 112 and 113 in the second direction and the other end of the covers 112 and 113 in the second direction are designated as second regions 112b and 113b, and the regions located between the second regions 112b and 113b are designated as first regions 112a and 113a.

[0072] Subsequently, refer to Figure 4 The average hardness of the first region 113a can be determined by taking hardness measurements at three or more equally spaced points to the left and right in the second direction and at three or more equally spaced points to the top and bottom in the third direction, based on the center of the first region 113a in the second and third directions. Similarly, the average hardness of the first region 112a can be determined.

[0073] In addition, refer to Figure 4 Based on the center of the second region 113b in the second direction and the third direction, the hardness of one second region 113b can be measured at three or more equally spaced points to the left and right in the second direction and at two or more equally spaced points above and below in the third direction. These measurements can be repeated in another second region 113b, and the average value can then be calculated to obtain the average hardness value of the second region 113b. Similarly, the average hardness of the second region 112b can be determined.

[0074] Furthermore, the hardness of each region of the covers 112 and 113 can be measured using a device such as a microindenter or nanoindenter under the following conditions: maximum load: 50 mN, maximum depth: 0.9 μm, load-unload rate: 300 mN / min, pause: 5 seconds, indenter: Berkovich, and temperature: 25 °C, but this disclosure is not limited thereto.

[0075] The second regions 112b and 113b of the covers 112 and 113 are areas where edge chipping may occur. Therefore, it is desirable that the second regions 112b and 113b do not excessively occupy the entire area of ​​the covers 112 and 113. Specifically, the ratio of the average length LC1 of the second regions 112b and 113b in the second direction to the average length LC0 of the covers 112 and 113 in the second direction may be 0.15 or less. Furthermore, because the second regions 112b and 113b are adjacent to the third surface 3 or the fourth surface 4 of the exposed inner electrodes 121 and 122, shrinkage force is applied during the firing process. Even if the second regions 112b and 113b are formed to a minimum, there may be technical limitations in reducing the shrinkage force to zero. Therefore, the ratio of the average length LC1 of the second regions 112b and 113b in the second direction to the average length LC0 of the covers 112 and 113 in the second direction may be 0.10 or greater. For example, in an embodiment, the ratio of the average length LC1 of the second regions 112b and 113b in the second direction to the average length LC0 of the covering portions 112 and 113 in the second direction may be greater than or equal to 0.10 and less than or equal to 0.15.

[0076] The method for measuring the average length LC0 of the second direction of the covers 112 and 113 is not particularly limited. After polishing the multilayer electronic assembly 1000 along the first surface 1 or the second surface 2 in the first direction to expose the covers 112 and 113, the exposed surfaces of the covers 112 and 113 are observed in an image obtained using an optical device such as an optical microscope. The second direction length of the covers 112 and 113 from one end to the other in the second direction can be measured using an image processing program or the like. The average length LC0 of the second direction of the covers 112 and 113 can be measured when the measurement is performed at two or more points above and below the center of the covers 112 and 113 in the third direction and the average value is taken. Furthermore, the average length LC1 of the second direction of the second regions 112b and 113b can be the length measured along the second direction from one end or the other end of the covers 112 and 113 in the second direction. In this case, the average hardness of the second regions 112b and 113b can have the same size as in the previously described embodiment.

[0077] During the firing process of the body 110, shrinkage forces arising from the difference in the stacking degree of the inner electrodes 121 and 122 may be applied from the second-direction ends of the covers 112 and 113 towards the entire third direction (e.g., the Z direction and the direction opposite to the Z direction). Therefore, in the embodiment, by continuously providing the second regions 112b and 113b from one end of the body 110 in the third direction to the other end of the body 110 in the third direction, the toughness against shrinkage forces applied from the second-direction ends of the covers 112 and 113 towards the entire third direction can be improved, thereby further reducing the frequency of edge chipping in the second regions 112b and 113b.

[0078] In an embodiment, the second regions 112b and 113b may be regions formed at both ends of the covers 112 and 113 in the second direction, and thus may be regions in contact with the outer electrodes 130 and 140.

[0079] Furthermore, the second regions 112b and 113b may be configured to extend beyond the ends of the inner electrodes 121 and 122 in the second direction. Specifically, in an embodiment, a portion of the second regions 112b and 113b may be superimposed on the capacitor forming portion Ac in the first direction.

[0080] In an embodiment, the ratio of the average hardness of the fourth regions 114b and 115b of the side edge portions 114 and 115 to the average hardness of the third regions 114a and 115a may be greater than 1.0 and less than 2.0.

[0081] When the ratio of the average hardness of the fourth regions 114b and 115b of the side edges 114 and 115 to the average hardness of the third regions 114a and 115a is less than 2.0, the present disclosure can be effective in reducing the frequency of edge chipping in the fourth regions 114b and 115b of the side edges 114 and 115. Furthermore, there is no particular limitation on the lower limit of the ratio of the average hardness of the fourth regions 114b and 115b of the side edges 114 and 115 to the average hardness of the third regions 114a and 115a; for example, it can exceed 1.0. For example, in an embodiment, the ratio of the average hardness of the fourth regions 114b and 115b of the side edges 114 and 115 to the average hardness of the third regions 114a and 115a can be greater than 1.0 and less than 1.5. Therefore, the frequency of edge chipping in the fourth regions 114b and 115b of the side edges 114 and 115 can be reduced, thereby further improving the moisture-proof reliability of the multilayer electronic assembly 1000.

[0082] An example of a method for measuring the average hardness of each region of the side edges 114 and 115 is shown below.

[0083] First, the multilayer electronic assembly 1000 is polished in a third-direction upward direction along the fifth surface 5 or the sixth surface 6 to expose the side edges 114 and 115. Then, in an image of the exposed surfaces of the side edges 114 and 115 observed using an optical device such as an optical microscope, an image processing program is used to distinguish fourth regions 114b and 115b and third regions 114a and 115a disposed between the fourth regions 114b and 115b. The fourth regions 114b and 115b are defined as being a distance from the side edges 114 and 115. The region between the point 1 / 10 to 3 / 20 of one end of the side edge portions 114 and 115 in the second direction (e.g., 1 / 10 to 3 / 20 of the length of the side edge portions 114 and 115 in the second direction) and the other end of the side edge portions 114 and 115 in the second direction, and the region between the point 1 / 10 to 3 / 20 of the distance from the other end of the side edge portions 114 and 115 in the second direction (e.g., 1 / 10 to 3 / 20 of the length of the side edge portions 114 and 115 in the second direction) and the other end of the side edge portions 114 and 115 in the second direction.

[0084] Subsequently, refer to Figure 5 The average hardness of the third regions 114a and 115a can be the average hardness of the third regions 114a and 115a, which are located at the center of the third region in the first and second directions, at three or more equally spaced points above and below in the first direction, and at three or more equally spaced points to the left and right in the second direction.

[0085] In addition, refer to Figure 5 Based on the center of a fourth region 114b or 115b in the first and second directions, hardness can be measured at three or more equally spaced points above and below in the first direction and at two or more equally spaced points to the left and right in the second direction. This measurement can be repeated in another fourth region 114b or 115b, and an average value can be obtained, which can be the average hardness value of the fourth regions 114b and 115b.

[0086] Furthermore, the hardness of specific areas of the side edges 114 and 115 can be measured using a device such as a microindenter or nanoindenter under the following conditions: maximum load: 50 mN, maximum depth: 0.9 μm, load-unload rate: 300 mN / min, pause: 5 seconds, indenter: Berkovich, and temperature: 25 °C, but this disclosure is not limited thereto.

[0087] Because the fourth regions 114b and 115b of the side edges 114 and 115 are areas where edge chipping may occur, it is desirable that the second regions 112b and 113b do not excessively occupy the entire area of ​​the side edges 114 and 115. Specifically, the ratio of the average length LM1 of the fourth regions 114b and 115b to the average length LM0 of the side edges 114 and 115 in the second direction can be 0.15 or less. Furthermore, because the fourth regions 114b and 115b are adjacent to the third surface 3 or the fourth surface 4 of the exposed inner electrodes 121 and 122, shrinkage forces are applied during the firing process, and even if the fourth regions 114b and 115b are formed to a minimum, there may be technical limitations to achieving zero shrinkage forces. Therefore, the ratio of the average length LM1 of the fourth regions 114b and 115b to the average length LM0 of the side edges 114 and 115 in the second direction can be 0.10 or greater. For example, in an embodiment, the ratio of the average length LM1 of the fourth regions 114b and 115b to the second-direction average length LM0 of the side edges 114 and 115 can be greater than or equal to 0.10 and less than or equal to 0.15.

[0088] The method for measuring the average length LM0 of the side edges 114 and 115 in the second direction is not particularly limited. After polishing the multilayer electronic assembly 1000 along the fifth surface 5 or the sixth surface 6 in the third direction to expose the side edges 114 and 115, the exposed surfaces of the side edges 114 and 115 are observed in an image obtained using an optical device such as an optical microscope. The second-direction length of the side edges 114 and 115 from one end to the other in the second direction can be measured using an image processing program, etc. (Refer to...) Figure 5 If the measurement is performed at two or more points above and below the center of the side edges 114 and 115 in the first direction, and then the average value is taken, the average length LM0 of the side edges 114 and 115 in the second direction can be measured. Furthermore, the average length LM1 of the fourth regions 114b and 115b in the second direction can be the length measured in the second direction from one end or the other end of the side edges 114 and 115. In this case, the average hardness of the fourth regions 114b and 115b can have the same size as in the previously described embodiment.

[0089] During the firing process of the body 110, shrinkage forces generated due to the difference in the stacking degree of the inner electrodes 121 and 122 may be applied from the second-direction ends of the side edges 114 and 115 in the entire first direction (e.g., the X direction and the direction opposite to the X direction). Therefore, in the embodiment, by continuously providing the fourth regions 114b and 115b from one end of the body 110 in the first direction to the other end of the body 110 in the first direction, the toughness against shrinkage forces applied from the second-direction ends of the side edges 114 and 115 in the entire first direction can be improved, thereby further reducing the frequency of edge chipping in the fourth regions 114b and 115b.

[0090] In an embodiment, the fourth regions 114b and 115b may be regions formed at both ends of the side edges 114 and 115 in the second direction, and thus may be regions in contact with the external electrodes 130 and 140.

[0091] Furthermore, the fourth regions 114b and 115b can be configured to extend beyond one end of the inner electrodes 121 and 122 in the second direction.

[0092] In an embodiment, an example of a method for controlling the hardness of the respective regions of the covers 112 and 113 and the side edges 114 and 115 may include: forming high-hardness regions at both ends of the dielectric sheets forming the covers 112 and 113 and the side edges 114 and 115, attaching these dielectric sheets to the laminate 100, and firing them. These high-hardness regions of the dielectric sheets can be formed by forming a prior art dielectric sheet at the center and printing high-hardness dielectric sheets at both ends. Alternatively, dye may be added to the high-hardness regions, but such dye may evaporate during firing.

[0093] In embodiments, the dielectric sheets used in the low-hardness and high-hardness regions may have different sintering aid contents or different average dielectric particle diameters. Therefore, after sintering the multilayer electronic assembly 1000, the average dielectric grain size of each region of the covers 112 and 113 and the side edge portions 114 and 115 may be different. In this way, by making the average dielectric grain size of each region of the covers 112 and 113 and the side edge portions 114 and 115 different, the hardness of each region of the covers 112 and 113 and the side edge portions 114 and 115 can be adjusted differently, but this disclosure is not limited thereto.

[0094] (Experimental Example) Table 1 below shows the frequency of edge chipping defects and the evaluation of moisture resistance reliability of samples in a multilayer electronic assembly 1000 according to an embodiment. The multilayer electronic assembly 1000 according to an embodiment includes a laminate 100 and covers 112 and 113, wherein the covers 112 and 113 include second regions 112b and 113b adjacent to a third surface 3 or a fourth surface 4 and first regions 112a and 113a disposed between the second regions 112b and 113b, and wherein the ratio (H2 / H1) of the average hardness H2 of the second regions 112b and 113b to the average hardness H1 of the first regions 112a and 113a varies.

[0095] Furthermore, Table 2 below shows the evaluation of edge chipping defect frequency and moisture resistance reliability in samples such as those in the multilayer electronic assembly 1000 according to the embodiment. The multilayer electronic assembly 1000 according to the embodiment includes a laminate 100 and side edge portions 114 and 115, wherein the side edge portions 114 and 115 include fourth regions 114b and 115b adjacent to the third surface 3 or the fourth surface 4 and third regions 114a and 115a disposed between the fourth regions 114b and 115b, and wherein the ratio (H4 / H3) of the average hardness H4 of the fourth regions 114b and 115b to the average hardness H3 of the third regions 114a and 115a is different.

[0096] The average hardness H1, H2, H3, and H4 are determined by polishing the multilayer electronic component 1000 along the first surface 1 in a first direction to expose the first cover portion 112, or by polishing the multilayer electronic component 1000 along the fourth surface 4 in a second direction to expose the side edge portion 115, and by observing the image using an optical microscope using the ImageJ program to distinguish the individual regions. The method for distinguishing the individual regions is as described above.

[0097] The average hardness H1 of the first regions 112a and 113a is based on the average hardness values ​​measured at three equally spaced points above and below the center of the first regions 112a and 113a in the second and third directions, and at three equally spaced points to the left and right in the second direction (e.g., Figure 4 (As shown in the figure). The average hardness H2 of the second regions 112b and 113b is the average of the hardness values ​​measured at three equally spaced points above and below the center of the second region 112b and 113b in the third direction and at two equally spaced points to the left and right in the second direction (as shown in the figure). Figure 4 (As shown in the figure). The average hardness H3 of the third regions 114a and 115a is the average of the hardness values ​​measured at three equally spaced points above and below the center of the third regions 114a and 115a in the first and second directions, and at three equally spaced points to the left and right in the second direction (as shown in the figure). Figure 5 (As shown in the figure). The average hardness H4 of the fourth regions 114b and 115b is the average of the hardness values ​​measured at three equally spaced points above and below the center of the fourth regions 114b and 115b in the first and second directions, and at two equally spaced points to the left and right in the second direction (as shown in the figure). Figure 5 As shown in the image).

[0098] The chipping defect rate was assessed for 1200 samples for each test number. If chipping was observed in the cover or side edge during visual inspection, the sample was identified as defective.

[0099] Moisture resistance reliability was evaluated for 1200 samples of each test number under the following conditions. If the insulation resistance value decreased to 10... 6 If the value is Ω or smaller, the sample is determined to be defective.

[0100] (Moisture-proof reliability evaluation conditions): Temperature: 85℃, relative humidity: 85%, applied voltage: 9.45V, voltage application time: 48 hours.

[0101] [Table 1]

[0102] Referring to Table 1, for test numbers 4 to 7 where H2 / H1 is 1.5 or greater, the frequency of edge chipping defects increases and the moisture-proof reliability decreases. On the other hand, for test numbers 1 to 3 where H2 / H1 is less than 1.5, the frequency of edge chipping defects decreases and the moisture-proof reliability improves.

[0103] Therefore, as in the embodiments, it can be confirmed that when the ratio of the average hardness of the second regions 112b and 113b of the cover portions 112 and 113 to the average hardness of the first regions 112a and 113a is greater than 1.0 and less than 1.5, the frequency of edge chipping defects in the multilayer electronic assembly 1000 can be reduced and the moisture-proof reliability can be improved.

[0104] [Table 2]

[0105] Referring to Table 2, for test numbers 12 to 14 with an H4 / H3 ratio of 2.0 or greater, the frequency of edge chipping defects increases sharply and the moisture-proof reliability decreases sharply. On the other hand, it can be confirmed that for test numbers 8 to 11 with an H4 / H3 ratio less than 2.0, the frequency of edge chipping defects decreases and the moisture-proof reliability improves.

[0106] Therefore, as in the embodiment, it can be confirmed that when the ratio of the average hardness of the fourth regions 114b and 115b of the side edges 114 and 115 to the average hardness of the third regions 114a and 115a is greater than 1.0 and less than 2.0, the frequency of edge chipping defects in the multilayer electronic assembly 1000 can be reduced and the moisture resistance reliability can be improved.

[0107] As described above, according to the embodiments, the moisture resistance reliability of multilayer electronic components can be improved by reducing the chipping frequency in the area of ​​the cover adjacent to the main body surface of the exposed inner electrode.

[0108] According to an embodiment, the moisture resistance reliability of multilayer electronic components can be improved by reducing the edge chipping frequency in the region adjacent to the body surface of the exposed inner electrode at the side edge.

[0109] While the embodiments have been described in detail above, this disclosure is not limited to the above embodiments and drawings, but is intended to be defined by the appended claims. Therefore, those skilled in the art will understand that various substitutions, modifications, and variations can be made without departing from the technical spirit of this disclosure as defined in the claims, and such modifications are also within the scope of this disclosure.

[0110] Furthermore, the term "embodiment" as used herein does not mean the same embodiment, but is provided to emphasize and explain the unique features of each embodiment. However, the presented embodiments do not preclude implementations in combination with features of other embodiments. For example, even if a description in a particular embodiment is not described in another embodiment, it may be understood to relate to that other embodiment unless there is a description in that other embodiment that contradicts or contradicts the description.

[0111] The terminology used in this disclosure is for descriptive purposes only and is not intended to limit the scope of this disclosure. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0112] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A multilayer electronic component, comprising: A main body includes a laminate and a cover portion, wherein an dielectric layer and an inner electrode are stacked in a first direction in the laminate, and the cover portion is disposed on two surfaces of the laminate that are opposite to each other in the first direction. The main body includes a first surface and a second surface that are opposite to each other in the first direction, a third surface and a fourth surface that are connected to the first surface and the second surface and are opposite to each other in the second direction, and a fifth surface and a sixth surface that are connected to the first surface, the second surface, the third surface and the fourth surface and are opposite to each other in the third direction. as well as An outer electrode is disposed on each of the third and fourth surfaces and connected to the inner electrode. The covering portion includes a second region adjacent to the third surface or the fourth surface and a first region disposed between the second region. The average hardness of the second region is greater than that of the first region.

2. The multilayer electronic component according to claim 1, wherein, The ratio of the average hardness of the second region to the average hardness of the first region is greater than 1.0 and less than 1.

5.

3. The multilayer electronic component according to claim 1, wherein, The ratio of the average length of the second region in the second direction to the average length of the covering portion in the second direction is greater than or equal to 0.10 and less than or equal to 0.

15.

4. The multilayer electronic component according to claim 1, wherein, The second region is continuously provided from one end of the body in the third direction to the other end of the body in the third direction.

5. The multilayer electronic component according to claim 1, wherein, The second region is in contact with the external electrode.

6. The multilayer electronic assembly according to claim 1, wherein, The internal electrode includes a first internal electrode exposed on the third surface and a second internal electrode exposed on the fourth surface. The laminate includes a capacitor forming portion, which is the region where the first inner electrode and the second inner electrode are stacked in the first direction. A portion of the second region overlaps with the capacitor forming portion in the first direction.

7. The multilayer electronic assembly according to claim 1, wherein, The main body also includes side edge portions disposed on two opposing surfaces of the laminate in the third direction. The side edge portion includes a fourth region adjacent to the third surface or the fourth surface, and a third region disposed between the fourth regions. The average hardness of the fourth region is greater than that of the third region.

8. The multilayer electronic component according to claim 7, wherein, The ratio of the average hardness of the fourth region to the average hardness of the third region is greater than 1.0 and less than 2.

0.

9. The multilayer electronic assembly according to claim 7, wherein, The ratio of the average length of the fourth region in the second direction to the average length of the side edge in the second direction is greater than or equal to 0.10 and less than or equal to 0.

15.

10. The multilayer electronic assembly according to claim 7, wherein, The fourth region is continuously provided from one end of the body in the first direction to the other end of the body in the first direction.

11. The multilayer electronic assembly according to claim 7, wherein, The fourth region is in contact with the external electrode.

12. A multilayer electronic component, comprising: The main body includes a laminate and side edge portions, wherein an dielectric layer and an inner electrode are stacked in a first direction in the laminate, and the side edge portions are disposed on two surfaces of the laminate that are opposite to each other in a third direction. The main body includes a first surface and a second surface that are opposite to each other in the first direction, a third surface and a fourth surface that are connected to the first surface and the second surface and are opposite to each other in the second direction, and a fifth surface and a sixth surface that are connected to the first surface, the second surface, the third surface and the fourth surface and are opposite to each other in the third direction. as well as An outer electrode is disposed on each of the third and fourth surfaces and connected to the inner electrode. The side edge portion includes a fourth region adjacent to the third surface or the fourth surface, and a third region disposed between the fourth regions. The ratio of the average hardness of the fourth region to the average hardness of the third region is greater than 1.0 and less than 2.

0.

13. The multilayer electronic assembly according to claim 12, wherein, The ratio of the average length of the fourth region in the second direction to the average length of the side edge in the second direction is greater than or equal to 0.10 and less than or equal to 0.

15.

14. The multilayer electronic assembly according to claim 12, wherein, The fourth region is continuously provided from one end of the body in the first direction to the other end of the body in the first direction.

15. The multilayer electronic assembly according to claim 12, wherein, The fourth region is in contact with the external electrode.

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