Multilayer electronic component

Abstract

This disclosure provides a multilayer electronic component. The multilayer electronic component includes: a body having a capacitor forming portion, in which a dielectric layer and an inner electrode are stacked in a first direction; a cover portion disposed on an opposing surface of the capacitor forming portion in the first direction; and a side edge portion disposed on an opposing surface of the capacitor forming portion in a third direction perpendicular to the first direction. An outer electrode is disposed on an opposing surface of the body in a second direction and is electrically connected to the inner electrode. When the average thickness of the cover portion in the first direction is Tc and the average width of the side edge portion in the third direction is Wm, Wm is greater than or equal to 18 μm and less than 200 μm, and Wm / Tc is greater than or equal to 0.86 and less than or equal to 1.71.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0039506, filed on March 27, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs, a type of multilayer electronic component) are chip capacitors mounted on printed circuit boards of various types of electronic products, such as video display devices (such as liquid crystal displays (LCDs) and plasma display panels (PDPs)), computers, smartphones, mobile phones, and on-board chargers (OBCs) for electric vehicles, to charge or discharge them.

[0004] Recently, with the development of smartphones, wearable devices, 5G communication modules, electric vehicles (EVs), and other technologies, the demand for thinner and more compact internal components is increasing. Therefore, it is extremely important to develop low-profile ceramic capacitors (LPCCs) that maintain the performance of existing MLCCs while reducing their thickness.

[0005] In addition, compared with existing MLCCs, LPCCs have an asymmetrical shape, which may make them more prone to edge chipping, cracking, and reduced moisture resistance.

[0006] Furthermore, as the thickness of LPCC decreases, the proportion of corner areas that are relatively prone to chipping increases, which may exacerbate chipping defects, cracking defects, and reduced moisture resistance reliability.

[0007] Furthermore, if an edgeless design is applied to expose the inner electrode in the width direction of the body to maximize the area of ​​the inner electrode in the width direction, and the individual side edges are attached to the inner electrode surface exposed in the width direction after the unit sheet is manufactured but before firing, the corners of the side edges may become more susceptible to damage. Summary of the Invention

[0008] One aspect of this disclosure is to alleviate the phenomenon of edge chipping defects occurring at the corners of the side edges.

[0009] One aspect of this disclosure is to address the problem that corners at side edges become the main pathways for external moisture penetration, thereby reducing the moisture resistance reliability of multilayer electronic components.

[0010] One aspect of this disclosure is to alleviate the increasingly severe vulnerability of the side edges in low-profile ceramic capacitors.

[0011] According to one aspect of this disclosure, a multilayer electronic component includes: a body including a capacitor forming portion, in which a dielectric layer and an inner electrode are stacked in a first direction; and an outer electrode disposed on two surfaces of the body opposite to each other in a second direction perpendicular to the first direction and connected to the inner electrode. The body further includes: a cover portion disposed on the two surfaces of the capacitor forming portion opposite to each other in the first direction; and a side edge portion disposed on two surfaces of the capacitor forming portion opposite to each other in a third direction perpendicular to both the first and second directions. When the average thickness of the cover portion in the first direction is Tc and the average width of the side edge portion in the third direction is Wm, Wm is greater than or equal to 18 μm and less than 200 μm, and Wm / Tc is greater than or equal to 0.86 and less than or equal to 1.71.

[0012] According to one aspect of this disclosure, a multilayer electronic component includes: a body including a capacitor forming portion, in which a dielectric layer and an inner electrode are stacked in a first direction; and an outer electrode disposed on two surfaces of the body opposite to each other in a second direction perpendicular to the first direction and connected to the inner electrode. The body further includes: a cover portion disposed on the two surfaces of the capacitor forming portion opposite to each other in the first direction; and a side edge portion disposed on two surfaces of the capacitor forming portion opposite to each other in a third direction perpendicular to both the first and second directions. When the average thickness of the cover portion in the first direction is Tc and the average width of the side edge portion in the third direction is Wm, Wm / Tc is greater than or equal to 1.47 and less than or equal to 1.71. Attached Figure Description

[0013] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 A perspective view of a multilayer electronic assembly according to an embodiment is schematically shown; Figure 2 A perspective view of the main body according to an embodiment is schematically shown; Figure 3 Schematic illustration along Figure 1 A cross-sectional view taken from line I-I'; Figure 4 Schematic illustration along Figure 1 The cross-sectional view taken from line II-II'; and Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10A method for manufacturing a multilayer electronic component according to an embodiment is illustrated schematically. Detailed Implementation

[0014] In the following description, embodiments will be illustrated with reference to specific examples and accompanying drawings. However, embodiments may be modified in various other forms, and the scope of this disclosure is not limited to the embodiments described below. Furthermore, embodiments are provided to more fully explain this disclosure to those skilled in the art. Therefore, for clarity, the shape and size of elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings are the same elements.

[0015] Furthermore, for clarity of description, parts irrelevant to the description have been omitted. The dimensions and thicknesses of each component shown in the drawings are arbitrarily indicated for ease of explanation. Therefore, this disclosure is not necessarily limited to what is shown. Additionally, the same reference numerals are used to describe components having the same function within the scope of the same concept. Furthermore, throughout the specification, when a component is referred to as "comprising" a component, it does not exclude other components, but rather implies the inclusion of other components, unless otherwise stated.

[0016] Furthermore, in the accompanying drawings, the X direction may refer to the thickness direction or a first direction, the Y direction may refer to the length direction or a second direction, the Z direction may refer to the width direction or a third direction, and the stacking direction of the inner electrode or dielectric layer may be the thickness direction or the width direction.

[0017] Figure 1 A perspective view of a multilayer electronic assembly according to an embodiment is schematically shown.

[0018] Figure 2 A perspective view of the main body according to an embodiment is shown schematically.

[0019] Figure 3 Schematic illustration along Figure 1 The cross-sectional view taken from line I-I'.

[0020] Figure 4 Schematic illustration along Figure 1 The cross-sectional view taken from line II-II'.

[0021] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 A method for manufacturing a multilayer electronic component according to an embodiment is illustrated schematically.

[0022] In the following text, refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 The following describes the multilayer electronic assembly 100 according to embodiments and various embodiments thereof.

[0023] The multilayer electronic assembly 100 according to an embodiment may include: a body 110 including a capacitor forming portion Ac, in which a dielectric layer 111 is stacked with inner electrodes 121 and 122 in a first direction; and outer electrodes 130 and 140 disposed on two surfaces of the body 110 that are opposite to each other in a second direction perpendicular to the first direction and connected to the inner electrodes 121 and 122. The body 110 may also include: cover portions 112 and 113 disposed on two surfaces of the capacitor forming portion Ac that are opposite to each other in the first direction; and side edge portions 114 and 115 disposed on two surfaces of the capacitor forming portion Ac that are opposite to each other in a third direction perpendicular to the first and second directions.

[0024] Reference Figure 2 and Figure 3 The main body 110 may include a dielectric layer 111, a first inner electrode 121, and a second inner electrode 122, wherein the first inner electrode 121 and the second inner electrode 122 are alternately disposed and the dielectric layer 111 is located between the first inner electrode 121 and the second inner electrode 122.

[0025] Although there are no particular restrictions on the specific shape of the main body 110, however... Figure 2 As shown, the body 110 can be formed into a hexahedral shape or a similar shape. Due to the shrinkage of the ceramic powder contained in the body 110 during the firing process, the body 110 may not be a perfect right hexahedral shape, but may have a generally hexahedral shape.

[0026] The main body 110 may have a first surface 1 and a second surface 2 opposite to each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2, as well as the third surface 3 and the fourth surface 4 and opposite to each other in a third direction. In this case, the first direction may refer to the direction along which the first inner electrode 121 and the second inner electrode 122 are disposed and the dielectric layer 111 is disposed between the first inner electrode 121 and the second inner electrode 122, but this disclosure is not limited thereto. For example, the direction along which the first inner electrode 121 and the second inner electrode 122 are disposed and the dielectric layer 111 is disposed between the first inner electrode 121 and the second inner electrode 122 may be the second direction or the third direction.

[0027] A raw material for forming the dielectric layer 111 is not particularly limited as long as sufficient electrostatic capacitance can be obtained therefrom. For example, barium titanate-based materials, lead composite perovskite-based materials, strontium titanate-based materials, etc. can be used. The barium titanate-based material may include BaTiO3-based ceramic powder. Examples of the BaTiO3-based ceramic powder may include BaTiO3 or those in which calcium (Ca), zirconium (Zr) and the like are partially solid dissolved in BaTiO3 (Ba 1-x Ca x )TiO3 (0<x<1), Ba(Ti 1-y Ca y )O3 (0<y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0<x<1, 0<y<1), Ba(Ti 1-y Zr y )O3 (0<y<1), and the like.

[0028] In addition, according to the embodiments of the present disclosure, the raw material for forming the dielectric layer 111 may be powder of barium titanate (BaTiO3) or the like, to which various ceramic additives, organic solvents, binders, dispersants and the like may be added.

[0029] The average thickness td of the dielectric layer 111 is not particularly limited. For example, if miniaturization and high capacity of the multilayer electronic component 1000 are required, the average thickness td of the dielectric layer 111 may be 0.35 μm or less. If it is required to improve the reliability of the multilayer electronic component 1000 under high temperature and high voltage, the average thickness td of the dielectric layer 111 may be 1 μm or more.

[0030] The average thickness td of the dielectric layer 111 may refer to the average thickness in a first direction of one or more dielectric layers among the plurality of dielectric layers.

[0031] The average thickness of the dielectric layer 111 in the first direction can be measured by scanning a cross section of the multilayer electronic component 1000 in the first direction and a second direction at a magnification of 10000 times using a scanning electron microscope (SEM). More specifically, the average thickness of one dielectric layer 111 in the first direction may refer to an average value calculated by measuring the thickness of one dielectric layer 111 in the first direction at four or more equally spaced points in the second direction in the scanned image. Four or more equally spaced points can be specified in the capacitance forming portion Ac. Further, by extending the average value measurement to four or more dielectric layers 111 and calculating the average value, the average thickness of the dielectric layer 111 in the first direction can be more generalized.

[0032] The inner electrodes 121 and 122 may be alternately disposed with the dielectric layer 111 in a first direction, and may include a first inner electrode 121 connected to the first outer electrode 130 and a second inner electrode 122 connected to the second outer electrode 140.

[0033] The first inner electrode 121 and the second inner electrode 122 can be electrically isolated from each other by a dielectric layer 111 disposed between them.

[0034] There are no particular limitations on the materials used to form the internal electrodes 121 and 122, and any material with excellent conductivity can be used. For example, the internal electrodes 121 and 122 may include at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0035] In addition, the thickness te of the inner electrodes 121 and 122 does not need to be specifically limited.

[0036] If a miniaturized and high-capacity multilayer electronic component 1000 is required, the average thickness te of the inner electrodes 121 and 122 can be 0.35 μm or less. If improved reliability of the multilayer electronic component 1000 is required at high temperatures and high voltages, the average thickness te of the inner electrodes 121 and 122 can be 1 μm or greater.

[0037] The average thickness te of the inner electrodes 121 and 122 may refer to the average thickness of one or more of the inner electrodes 121 and 122 in the first direction.

[0038] The first-direction average thickness of the inner electrodes 121 and 122 can be measured by scanning the cross-section of the multilayer electronic assembly 1000 in the first and second directions using a scanning electron microscope (SEM) at a magnification of 10,000x. More specifically, the first-direction average thickness of an inner electrode can be an average value calculated in the scanned image by measuring the first-direction thickness of an inner electrode at four or more equally spaced points in the second direction. Four or more equally spaced points can be specified in the capacitor forming section Ac. Furthermore, the first-direction average thickness of the inner electrodes 121 and 122 can be further generalized by extending this average value measurement to four or more inner electrodes 121 and 122 and calculating the average value.

[0039] Reference Figure 4 The main body 110 may include a capacitor forming portion Ac, which is a region where the dielectric layer 111 and the inner electrodes 121 and 122 are stacked in a first direction. Specifically, the capacitor forming portion Ac may be a region where the first inner electrode 121, the dielectric layer 111, and the second inner electrode 122 are stacked in a first direction to form an electrostatic capacitor.

[0040] Reference Figure 2 , Figure 3 and Figure 4 Cover portions 112 and 113 may be disposed on two surfaces opposite to each other in a first direction of the capacitor forming portion Ac. Cover portions 112 and 113 do not include inner electrodes 121 and 122, and may include the same dielectric material as the dielectric material of dielectric layer 111, but may have different specific compositions.

[0041] Reference Figure 2 and Figure 4 Side edge portions 114 and 115 may be provided on two surfaces of the capacitor forming portion Ac that are opposite to each other in the third direction.

[0042] like Figure 4 As shown, the side edges 114 and 115 may refer to the region between the outer surface of the body 110 and the two ends of the first inner electrode 121 and the second inner electrode 122 in a cross section cut along the first direction and the third direction of the body 110.

[0043] The side edges 114 and 115 are designed to prevent damage to the internal electrode due to physical and / or chemical stress.

[0044] Examples of the methods for forming the side edges 114 and 115 will be described later.

[0045] According to the embodiment, when the average thickness of the cover portions 112 and 113 in the first direction is Tc and the average width of the side edge portions 114 and 115 in the third direction is Wm, Wm can be greater than or equal to 18 μm and less than 200 μm, and Wm / Tc can be greater than or equal to 0.86 and less than or equal to 1.71.

[0046] In a multilayer electronic assembly where the third-direction average width of the side edges 114 and 115 is Wm, and Wm is greater than or equal to 18 μm and less than 200 μm, the ratio (Wm / Tc) of the third-direction average width Wm of the side edges 114 and 115 to the first-direction average thickness Tc of the covering portions 112 and 113 can have a significant impact on the edge chipping defect rate and moisture-proof reliability of the multilayer electronic assembly 100.

[0047] Specifically, existing multilayer electronic components with a Wm value of less than 18μm have a high incidence of edge chipping defects due to insufficient width of the side edges. In addition, the moisture resistance reliability may be reduced because the penetration path of external moisture and plating solution is shortened.

[0048] Therefore, in the multilayer electronic assembly 100 according to the embodiments of the present disclosure, by ensuring that Wm is greater than or equal to 18 μm and less than 200 μm (more specifically, greater than or equal to 18 μm and less than or equal to 25 μm), edge chipping defects can be suppressed and the length of the penetration path of external moisture can be sufficiently increased, thereby reducing edge chipping defects and improving the moisture-proof reliability of the multilayer electronic assembly 100.

[0049] However, in the case of multilayer electronic components 100 with Wm greater than or equal to 18 μm and less than 200 μm, the side edges 114 and 115 occupy a large proportion of the overall size of the multilayer electronic component 100. Therefore, compared with existing multilayer electronic components, the corner areas of the side edges 114 and 115 may be larger. Consequently, there may be limitations in reducing edge chipping defects in the multilayer electronic component 100 and improving its moisture-proof reliability.

[0050] Specifically, in multilayer electronic components 100 with Wm greater than or equal to 18 μm and less than 200 μm, when Wm / Tc is less than 0.86, the frequency of edge chipping defects increases and the moisture resistance reliability may deteriorate. Conversely, when Wm / Tc is 0.86 or greater, the frequency of edge chipping defects can be significantly reduced and the moisture resistance reliability can also be improved.

[0051] Therefore, in the embodiments of this disclosure, in the multilayer electronic assembly 100 with Wm greater than or equal to 18 μm and less than 200 μm, by adjusting Wm / Tc to 0.86 or greater, the proportion of the side edges 114 and 115 in the entire assembly can be appropriately adjusted, thereby significantly reducing the frequency of edge chipping defects and improving the moisture resistance reliability of the multilayer electronic assembly 100.

[0052] Furthermore, in multilayer electronic components 100 with Wm greater than or equal to 18 μm and less than 200 μm, there is no particular upper limit on the Wm / Tc value that significantly reduces the frequency of edge chipping defects and improves moisture resistance reliability. The upper limit of Wm / Tc can be set at a level that ensures an appropriate capacitance per unit volume of the multilayer electronic component 100. For example, Wm / Tc can be 1.71 or less.

[0053] Furthermore, according to the embodiment, the multilayer electronic assembly 100 may have a Wm / Tc greater than or equal to 1.47 and less than or equal to 1.71, and in this case, the third-dimensional average width Wm of the side edges 114 and 115 is not particularly limited.

[0054] Specifically, as in the embodiment, when Wm / Tc is greater than or equal to 1.47 and less than or equal to 1.71, the frequency of edge chipping defects in the multilayer electronic assembly 100 can be significantly reduced, and the moisture resistance reliability can be significantly improved. In addition, when Wm / Tc is greater than or equal to 1.47 and less than or equal to 1.71, the third-dimensional average width Wm of the side edges 114 and 115 does not need to be specifically limited.

[0055] There is no specific upper limit to the Wm / Tc value that can significantly reduce the frequency of edge chipping defects and significantly improve moisture resistance reliability. The upper limit of Wm / Tc can be set at a level that ensures an appropriate capacitance per unit volume of the multilayer electronic component 100. For example, in an embodiment, Wm / Tc can be 1.71 or less.

[0056] The average thickness Tc of the covers 112 and 113 in the first direction can be measured by scanning the cross-section of the body 110 in the first and third directions using a scanning electron microscope (SEM) at a magnification of 10,000x. Specifically, the average thickness Tc of the covers 112 and 113 in the first direction can refer to the average value calculated in the scanned image by measuring the first direction dimension of an edge at five or more equally spaced points in the third direction, but this disclosure is not limited thereto.

[0057] The third-direction average width Wm of the side edges 114 and 115 can be measured by scanning the first and third-direction sections of the body 110 at a magnification of 10,000 using a scanning electron microscope (SEM). More specifically, the third-direction average width Wm of the side edges 114 and 115 can refer to the average value calculated by measuring the third-direction dimension of an edge at five or more equally spaced points in the first direction in the scanned image, but this disclosure is not limited thereto.

[0058] In the embodiments, Wm / Tc can be 1.00 or greater, 1.06 or greater, 1.19 or greater, 1.24 or greater, or 1.47 or greater. Therefore, the chipping defect reduction effect and moisture-proof reliability improvement effect of the multilayer electronic assembly 100 according to the embodiments can be further enhanced.

[0059] In the embodiments, the average thickness Tc in the first direction of the covering portions 112 and 113 can be 17 μm or greater. Therefore, the range of Wm / Tc according to the embodiments can be easily adjusted. There is no particular upper limit to the average thickness Tc in the first direction of the covering portions 112 and 113. For example, the average thickness Tc in the first direction of the covering portions 112 and 113 can be less than 200 μm; more specifically, the average thickness Tc in the first direction of the covering portions 112 and 113 can be 21 μm or less.

[0060] Furthermore, in the multilayer electronic assembly 100 according to the embodiment, where the side edges 114 and 115 occupy a larger proportion of the entire assembly compared to the prior art multilayer electronic assemblies, the area of ​​the corner regions of the side edges 114 and 115 that are susceptible to edge chipping defects and external moisture penetration is also increased.

[0061] Furthermore, when adjusting the ratio (Wm / R) of the average width Wm of the side edges 114 and 115 in the third direction to the average radius of curvature R of the corners of the side edges 114 and 115, the vulnerability of the corners of the side edges 114 and 115 can be compensated by organically adjusting the average radius of curvature R of the corners of the side edges 114 and 115 and the average width Wm of the side edges 114 and 115 in the third direction.

[0062] Specifically, in the embodiments, when Wm / R is adjusted to 1.32 or less, the effect of reducing edge chipping defects and improving moisture resistance of the multilayer electronic component 100 can be more significantly enhanced.

[0063] Furthermore, there is no need to specifically limit the lower limit of Wm / R, and the lower limit of Wm / R can be adjusted according to the machining process of the corners of the side edges 114 and 115. For example, Wm / R can be 0.47 or greater.

[0064] The average radius of curvature R of the corners of the side edges 114 and 115 can be measured by scanning the body 110 at a magnification of 10,000 in the first and third directions using a scanning electron microscope (SEM). More specifically, the average radius of curvature R of the corners of the side edges 114 and 115 can refer to the average value obtained by measuring the radius of curvature of each corner in the images obtained by scanning the four corners respectively.

[0065] In an embodiment, the maximum thickness T of the body 110 in the first direction can be 250 μm or less. Therefore, a low-profile ceramic capacitor (LPCC) with a thin first-direction thickness can be achieved for the multilayer electronic assembly 100. In this case, Wm can be greater than or equal to 18 μm and less than or equal to 25 μm, or Tc can be greater than or equal to 17 μm and less than or equal to 21 μm, but is not limited thereto.

[0066] In an embodiment, the main body 110 may include an interface between the side edge portions 114 and 115 and the capacitance forming portion Ac. As in the embodiment, when an interface is formed between the side edge portions 114 and 115 and the capacitance forming portion Ac, it may involve a process of separately forming the side edge portions 114 and 115 on the capacitance forming portion Ac, which makes the corners of the side edge portions 114 and 115 more susceptible to chipping defects or penetration by external moisture. However, according to embodiments of the present disclosure, in the multilayer electronic component 100 where Wm is greater than or equal to 18 μm and less than 200 μm, regardless of the range of Wm, Wm / Tc is adjusted to 0.86 or greater, or Wm / Tc is adjusted to 1.47 or greater. Therefore, even when an interface is formed between the side edge portions 114 and 115 and the capacitance forming portion Ac, an increase in the chipping defect rate or a decrease in moisture resistance reliability of the multilayer electronic component 100 can be alleviated.

[0067] The interface between the side edge portions 114 and 115 and the capacitance forming portion Ac may be caused by differences in composition or microstructure between the dielectric layers 111 of the capacitance forming portion Ac and the side edge portions 114 and 115.

[0068] Specifically, in an embodiment, when the average porosity of the dielectric layers 111 is P0 and the average porosity of the side edge portions 114 and 115 is P1, the relationship P0 < P1 can be satisfied. The interface between the side edge portions 114 and 115 and the capacitance forming portion Ac can be formed based on the porosity difference between the dielectric layers 111 and the side edge portions 114 and 115.

[0069] In addition, in an embodiment, the dielectric layer 111 and the side edge portions 114 and 115 may each include a plurality of dielectric grains. When the average size of the dielectric grains included in the dielectric layer 111 is G0 and the average size of the dielectric grains included in the side edge portions 114 and 115 is G1, the relationship G0 < G1 can be satisfied. The interface between the side edge portions 114 and 115 and the capacitance forming portion Ac can be formed based on the difference in average size of the dielectric grains included in the dielectric layer 111 and the side edge portions 114 and 115.

[0070] In an embodiment, the side edge portions 114 and 115 may cover two side surfaces of the covering portions 112 and 113 opposite to each other in the third direction. Therefore, since the boundary between the covering portions 112 and 113, which are susceptible to external moisture penetration, and the capacitance forming portion Ac can be covered, the moisture resistance reliability of the multilayer electronic component 100 can be improved.

[0071] With reference to Figure 1 , the external electrodes 130 and 140 are disposed on the main body 110.

[0072] Specifically, the outer electrodes 130 and 140 are respectively disposed on the third surface 3 and the fourth surface 4, which are two surfaces of the body 110 that are opposite to each other in the second direction, and the outer electrodes 130 and 140 can be connected to the inner electrodes 121 and 122.

[0073] The external electrodes 130 and 140 can be formed using any conductive material, such as metal. The specific material of the external electrodes can be determined based on electrical properties, structural stability, and other factors. Furthermore, the external electrodes can have a multilayer structure.

[0074] For example, the external electrodes 130 and 140 may include electrode layers 131 and 141 disposed on the body 110 and plating layers 132 and 142 disposed on the electrode layers 131 and 141.

[0075] In a more specific example of electrode layers 131 and 141, electrode layers 131 and 141 may be sintered electrodes comprising conductive metal and glass, or resin-based electrodes comprising conductive metal and resin.

[0076] Furthermore, electrode layers 131 and 141 can be formed by transferring a sheet containing conductive metal onto the body 110, or by transferring a sheet containing conductive metal onto a sintered electrode.

[0077] The conductive metal used in electrode layers 131 and 141 is not particularly limited, as long as it can be electrically connected to the inner electrodes 121 and 122 to form an electrostatic capacitance. For example, the conductive metal may include at least one selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. Electrode layers 131 and 141 may be formed by coating a conductive paste prepared by adding glass frit to conductive metal particles, and then firing the conductive paste.

[0078] Coatings 132 and 142 can be used to improve mounting characteristics.

[0079] There are no particular restrictions on the type of plating 132 and 142, and they can both be single-layer plating 132 and 142 (containing at least one of nickel (Ni), tin (Sn), silver (Ag), palladium (Pd) and their alloys), or they can be formed by multiple layers.

[0080] In a more specific example of plating layers 132 and 142, plating layers 132 and 142 may be Ni plating layers or Sn plating layers, or may be in the form of Ni plating layers and Sn plating layers sequentially formed on electrode layers 131 and 141, or may be in the form of Sn plating layers, Ni plating layers, and Sn plating layers sequentially formed. Additionally, plating layers 132 and 142 may include multiple Ni plating layers and / or multiple Sn plating layers.

[0081] Hereinafter, a method for manufacturing a multilayer electronic component 100 according to an embodiment will be described. However, this disclosure is not intended to limit the multilayer electronic component 100 manufactured using the manufacturing method described below.

[0082] like Figure 5 As shown, a plurality of strip-shaped first inner electrode patterns 221 are formed on the ceramic green sheet 211 at predetermined intervals. The plurality of strip-shaped first inner electrode patterns 221 may be formed parallel to each other.

[0083] In addition, although not shown, a plurality of strip-shaped second inner electrode patterns 222 may be formed at predetermined intervals on another ceramic green sheet 211.

[0084] In the following text, the ceramic green sheet on which the first inner electrode pattern 221 is formed may be referred to as the first ceramic green sheet, and the ceramic green sheet on which the second inner electrode pattern 222 is formed may be referred to as the second ceramic green sheet.

[0085] Next, as Figure 6 As shown, the first ceramic green sheet and the second ceramic green sheet can be stacked alternately, such that the strip-shaped first inner electrode pattern 221 and the strip-shaped second inner electrode pattern 222 are stacked alternately.

[0086] Subsequently, the first inner electrode pattern 221 can be transformed into the first inner electrode 121, and the second inner electrode pattern 222 can be transformed into the second inner electrode 122.

[0087] Figure 7 This is a cross-sectional view showing a ceramic green sheet laminate 220 in which a first ceramic green sheet and a second ceramic green sheet are stacked. Figure 8 This is a perspective view showing a ceramic green sheet laminate 220 in which a first ceramic green sheet and a second ceramic green sheet are stacked.

[0088] A first ceramic green sheet with multiple parallel strip first inner electrode patterns 221 printed on it and a second ceramic green sheet with multiple parallel strip second inner electrode patterns 222 printed on it are alternately stacked.

[0089] Although not shown in the accompanying drawings, cover sheets capable of being formed into cover portions 112 and 113 according to the embodiment may be provided on the upper and lower surfaces of the ceramic green sheet laminate 220. The average thickness of the cover portions 112 and 113 in the first direction can be adjusted by changing the thickness of the cover sheets or the degree of lamination of the sheets.

[0090] Next, as Figure 8As shown, the ceramic green sheet laminate 220 can be cut across multiple strip-shaped first inner electrode patterns 221 and multiple strip-shaped second inner electrode patterns 222. For example, the ceramic green sheet laminate 220 can be cut into laminated blocks 210 by cutting along orthogonal cutting lines C1-C1 and C2-C2.

[0091] For example, a rod-shaped laminate obtained by cutting a ceramic green sheet laminate 220 along cutting line C1-C1 can be cut as follows: a predetermined gap formed between the center of the first inner electrode and the second inner electrode stacked in the thickness direction is cut along the same cutting line, and a predetermined gap formed between the center of the second inner electrode and the first inner electrode stacked in the thickness direction is cut along the same cutting line. Therefore, one end of the first inner electrode and one end of the second inner electrode can be alternately exposed on the cutting surface.

[0092] Subsequently, side edge pieces can be formed on the first and second side surfaces of the stacked block 210.

[0093] Next, as Figure 9 and Figure 10 As shown, a first side edge piece 212 can be formed on the first side surface of the stacked block 210. The first side edge piece 212 can be formed by stamping using an elastic material 300. Subsequently, by rotating the stacked block 210, a second side edge piece can be formed on the second side surface of the stacked block 210. Figures 7 to 10 The number of layers in the internal electrode pattern is only a schematic representation.

[0094] Next, the laminated body (in which a first side edge sheet and a second side edge sheet are formed on two side surfaces of the laminated block 210) can be pre-fired and fired to form a body including a dielectric layer and a first inner electrode 121 and a second inner electrode 122. After this process, the first side edge sheet and the second side edge sheet can form side edge portions 114 and 115 according to the embodiment.

[0095] At this time, by adjusting the thickness of the first side edge piece and the second side edge piece or the number of stacked pieces, the average width Wm of the side edge portions 114 and 115 in the third direction according to the embodiment can be adjusted.

[0096] Next, a process for polishing the corners of the side edges 114 and 115 can be performed. The average radius of curvature R of the side edges 114 and 115 according to the embodiment can be adjusted by adjusting variables such as polishing pressure and polishing time during the polishing process.

[0097] Subsequently, external electrodes 130 and 140 can be formed on the third surface 3 of the exposed first internal electrode 121 of the main body 110 and on the fourth surface 4 of the exposed second internal electrode 122 of the main body 110, respectively.

[0098] (Experimental Example) Tables 1 and 2 below show the chipping frequency and moisture-proof reliability evaluation results of multilayer electronic component samples with varying average thickness Tc of the cover in the first direction, average width Wm of the side edge in the third direction, and average radius of curvature R of the corner of the side edge.

[0099] Except for adjusting the thickness and number of layers of the cover sheet, the thickness and number of layers of the side edge sheet, and the polishing pressure and time of the side edge, each sample is manufactured using the same method described above for manufacturing multilayer electronic components.

[0100] In addition, the frequency of edge chipping was measured by mounting the samples and observing them with an optical microscope to see if chipping or breakage occurred at the corners of the side edges. If each sample experienced at least one chipping or breakage, the sample was considered defective.

[0101] For moisture-proof reliability evaluation, under the following conditions, when the insulation resistance value decreases to 10... 5 A value of Ω or lower is considered unqualified.

[0102] (Moisture-proof reliability evaluation conditions): temperature 85℃, relative humidity 85%, applied voltage 1~1.5Vr, applied voltage duration 8 hours or longer.

[0103] [Table 1]

[0104] Referring to Table 1, Comparative Example 1, with Wm / Tc less than 0.86, exhibited a chipping frequency of 2000 ppm or greater and a deterioration in moisture-proof reliability.

[0105] In contrast, Examples 4 to 6, with Wm / Tc of 0.86 or greater, showed a significant improvement in edge chipping frequency from 2000 ppm or greater to 1000 ppm or less, indicating improved moisture resistance reliability.

[0106] Furthermore, in Example 3 with Wm / Tc of 1.47, it can be confirmed that the chipping frequency is 500 ppm or less, and the moisture resistance reliability rating is 1 / 1200, thus demonstrating a significant improvement in both chipping defects and moisture resistance reliability.

[0107] [Table 2]

[0108] Referring to Table 2, for Comparative Example 3 with Wm / R greater than 1.32, the frequency of edge chipping was 2000 ppm or greater, and the moisture-proof reliability deteriorated.

[0109] On the other hand, for Examples 7 to 14 with Wm / R of 1.32 or less, the chipping frequency was 1000 ppm or less, and the moisture resistance reliability rating was 4 / 1200 or less, confirming that chipping defects and moisture resistance reliability were improved.

[0110] As described above, according to the embodiments, the phenomenon of edge chipping defects occurring at the corners of the side edges can be alleviated.

[0111] According to the embodiments, the moisture resistance reliability of multilayer electronic components can be improved.

[0112] According to the embodiments, edge chipping defects in multilayer electronic components with low-profile ceramic capacitor structures can be mitigated, and the moisture resistance reliability of multilayer electronic components can be improved.

[0113] While the embodiments have been described in detail above, this disclosure is not limited to the above embodiments and drawings, but is intended to be defined by the appended claims. Therefore, those skilled in the art will understand that various substitutions, modifications, and variations can be made without departing from the technical spirit of this disclosure as defined in the claims, and such modifications are also within the scope of this disclosure.

[0114] Furthermore, the term "embodiment" as used herein does not mean the same embodiment, but is provided to emphasize and explain the unique features of various embodiments. However, the presented embodiments do not preclude implementation in combination with features of other embodiments. For example, even if a description in a particular embodiment is not described in another embodiment, the description may be understood to be related to the other embodiment unless there is a description in the other embodiment that contradicts or contradicts it.

[0115] The terminology used in this disclosure is for descriptive purposes only and is not intended to limit the scope of this disclosure. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0116] While exemplary embodiments have been shown and described above, those skilled in the art will understand that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A multilayer electronic component, comprising: The main body includes a capacitor forming portion, in which a dielectric layer and an internal electrode are stacked in a first direction; as well as The outer electrodes are disposed on two surfaces of the body that are opposite each other in a second direction perpendicular to the first direction, and are connected to the inner electrodes. The main body further includes a covering portion and side edge portions. The covering portion is disposed on two surfaces of the capacitor forming portion that are opposite to each other in the first direction. The side edge portions are disposed on two surfaces of the capacitor forming portion that are opposite to each other in a third direction perpendicular to the first and second directions. Wherein, when the average thickness of the covering portion in the first direction is Tc and the average width of the side edge portion in the third direction is Wm, Wm is greater than or equal to 18μm and less than 200μm, and Wm / Tc is greater than or equal to 0.86 and less than or equal to 1.

71.

2. The multilayer electronic component according to claim 1, wherein, Wm / Tc is greater than or equal to 1.47 and less than or equal to 1.

71.

3. The multilayer electronic component according to claim 1, wherein, Tc is 17 μm or larger.

4. The multilayer electronic assembly according to claim 1, wherein, When the average radius of curvature of the corner of the side edge is R, Wm / R is 1.32 or less.

5. The multilayer electronic component according to claim 1, wherein, Wm is greater than or equal to 18 μm and less than or equal to 25 μm, and The maximum thickness of the body in the first direction is 250 μm or less.

6. The multilayer electronic component according to claim 1, wherein, The main body includes an interface located between the capacitor forming portion and the side edge portion.

7. The multilayer electronic assembly according to claim 1, wherein, When the average porosity of the dielectric layer is P0 and the average porosity of the side edge is P1, P0 is satisfied. <P1。 8. The multilayer electronic component according to claim 1, wherein, When the average size of the dielectric grains included in the dielectric layer is G0 and the average size of the dielectric grains included in the side edge portion is G1, G0 is satisfied. <G1。 9. A multilayer electronic component, comprising: The main body includes a capacitor forming portion, in which a dielectric layer and an internal electrode are stacked in a first direction; as well as The outer electrodes are disposed on two surfaces of the body that are opposite each other in a second direction perpendicular to the first direction, and are connected to the inner electrodes. The main body further includes a covering portion and side edge portions. The covering portion is disposed on two surfaces of the capacitor forming portion that are opposite to each other in the first direction. The side edge portions are disposed on two surfaces of the capacitor forming portion that are opposite to each other in a third direction perpendicular to the first and second directions. When the average thickness of the covering portion in the first direction is Tc and the average width of the side edge portion in the third direction is Wm, Wm / Tc is greater than or equal to 1.47 and less than or equal to 1.

71.

10. The multilayer electronic component according to claim 9, wherein, Tc is 17 μm or larger.

11. The multilayer electronic assembly according to claim 9, wherein, When the average radius of curvature of the corner of the side edge is R, Wm / R is 1.32 or less.

12. The multilayer electronic assembly according to claim 9, wherein, Wm is greater than or equal to 18 μm and less than or equal to 25 μm, and The maximum thickness of the body in the first direction is 250 μm or less.

13. The multilayer electronic assembly according to claim 9, wherein, The main body includes an interface located between the capacitor forming portion and the side edge portion.

14. The multilayer electronic assembly according to claim 9, wherein, When the average porosity of the dielectric layer is P0 and the average porosity of the side edge is P1, P0 is satisfied. <P1。 15. The multilayer electronic assembly according to claim 9, wherein, When the average size of the dielectric grains included in the dielectric layer is G0 and the average size of the dielectric grains included in the side edge portion is G1, G0 is satisfied. <G1。

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