Insulated gate bipolar transistor type electric power router fault current limiting protection method and system

Abstract

The application provides an insulated gate bipolar transistor type electric energy router fault current limiting protection method and system, and relates to the technical field of electric energy routers. The method comprises the following steps: when a hardware protection circuit of an insulated gate bipolar transistor type electric energy router triggers a fault shutdown signal, data acquisition across an electrical measurement node is performed to obtain a fault feature multidimensional snapshot; a multi-branch fault timing relationship diagram is constructed; cross-channel current and voltage causal correlation analysis is performed to output a preliminary fault branch and a preliminary fault type; fault reasoning based on multi-source data fusion is performed in a fault diagnosis model to output a structured diagnosis report; a recovery strategy is matched to perform self-healing restart of the insulated gate bipolar transistor type electric energy router. The application solves the technical problem that the fault detection of the prior art usually relies on a threshold setting mechanism, lacks flexibility, cannot cope with complex and variable fault conditions, leads to false triggering or missed triggering of fault protection, and further affects the stability of the system.

Description

Technical Field

[0001] This invention relates to the field of power router technology, specifically to a fault current limiting protection method and system for insulated gate bipolar transistor type power routers. Background Technology

[0002] Power routers play a crucial role in power systems, their primary task being the efficient transmission and distribution of electrical energy. Therefore, fault prevention and handling of power routers are key to ensuring the stable operation of power systems. Existing fault detection technologies typically rely on traditional threshold setting mechanisms. Protection is only triggered when the current or voltage exceeds a set threshold. This fixed-threshold-based protection method lacks flexibility and cannot cope with complex and variable fault conditions. Furthermore, the selection of threshold settings usually requires experience; improper selection may lead to false triggering or missed triggering of fault protection, thereby affecting system stability. Summary of the Invention

[0003] This application provides a fault current limiting protection method and system for insulated gate bipolar transistor type power routers, aiming to solve the technical problem that the fault detection of existing technologies usually relies on threshold setting mechanisms, which lacks flexibility and cannot cope with complex and changing fault conditions, resulting in false triggering or missed triggering of fault protection, thereby affecting the stability of the system.

[0004] The first aspect disclosed in this application provides a fault current limiting protection method for an insulated gate bipolar transistor (IGBT) power router. The method includes: when the hardware protection circuit of the IGBT power router triggers a fault shutdown signal, a deterministic data acquisition window is synchronously activated through the main controller to collect data across electrical measurement nodes, obtaining a multi-dimensional snapshot of fault features; after aligning the multi-channel timing of the multi-dimensional snapshot of fault features, a multi-branch fault timing relationship diagram is constructed; cross-channel current-voltage causal correlation analysis is performed on the multi-branch fault timing relationship diagram to output preliminary fault branches and preliminary fault types; feature extraction and fusion are performed on the multi-dimensional snapshot of fault features to obtain a dimensionality-reduced fault feature vector; combined with the preliminary fault branches and preliminary fault types, fault reasoning based on multi-source data fusion is performed in a fault diagnosis model to output a structured diagnostic report, wherein the structured diagnostic report includes fault type, fault location, fault severity level, and potential cause inference; and a self-healing restart of the IGBT power router is performed based on a matching recovery strategy according to the structured diagnostic report.

[0005] The second aspect of this application discloses a fault current limiting protection system for an insulated gate bipolar transistor (IGBT) power router. The system is used in the aforementioned IGBT power router fault current limiting protection method. The system includes: a data acquisition module, used to synchronously start a deterministic data acquisition window through the main controller to acquire data across electrical measurement nodes when the hardware protection circuit of the IGBT power router triggers a fault shutdown signal, obtaining a multi-dimensional snapshot of fault characteristics; a relationship graph construction module, used to construct a multi-branch fault time sequence relationship graph after synchronously aligning the multi-channel time sequence of the fault characteristics snapshot; and a causal correlation analysis module, used to analyze the multi-branch fault time sequence relationship graph. The fault timing relationship diagram of the branch is used to perform cross-channel current and voltage causal correlation analysis, and output the preliminary fault branch and preliminary fault type. The fault reasoning module is used to extract and fuse features from the multi-dimensional snapshot of the fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branch and preliminary fault type, fault reasoning based on multi-source data fusion is performed in the fault diagnosis model to output a structured diagnostic report. The structured diagnostic report includes fault type, fault location, fault severity level and potential cause inference. The self-healing restart module is used to perform self-healing restart of the insulated gate bipolar transistor type power router based on the structured diagnostic report and matching recovery strategy.

[0006] One or more technical solutions provided in this application have at least the following beneficial effects: When a fault occurs, the main controller synchronously initiates a deterministic data capture window to ensure accurate capture of data from multiple electrical measurement nodes at the moment the fault is triggered. The generated multi-dimensional fault feature snapshots provide the foundational data for subsequent fault analysis and diagnosis. By aligning the multi-channel timing of the multi-dimensional fault feature snapshots, the electrical signals from multiple different channels are aligned to a unified time reference, ensuring the timing consistency of data from different channels. The construction of a multi-branch fault timing relationship diagram helps to clearly show the propagation process and interrelationships of the fault among the branches. Through feature extraction and fusion of the multi-dimensional fault feature snapshots, key features can be extracted from complex time-series data. The fault diagnosis model first identifies and reduces the dimensionality of fault features to generate a dimensionality-reduced fault feature vector. This dimensionality reduction process reduces computational and storage requirements while ensuring information integrity, thereby improving the efficiency of fault reasoning. Combining preliminary fault branches and types, the fault diagnosis model performs accurate fault reasoning through multi-source data fusion. This process not only improves the speed of fault diagnosis but also enhances the accuracy of fault inference. Through structured diagnostic reports, corresponding recovery strategies are matched, and self-healing restart is achieved, avoiding manual intervention. Automatic restart not only improves the efficiency of fault recovery but also reduces system downtime, ensuring the high reliability and continuous operation capability of the power router.

[0007] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0008] Figure 1 This is a schematic flowchart of the fault current limiting protection method for an insulated gate bipolar transistor type power router provided in an embodiment of this application.

[0009] Figure 2 This is a schematic diagram of the fault current limiting protection system for an insulated gate bipolar transistor type power router provided in an embodiment of this application.

[0010] Figure labeling: Data acquisition module 10, Relationship graph construction module 20, Causal association analysis module 30, Fault reasoning module 40, Self-healing restart module 50. Detailed Implementation

[0011] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0012] Example 1, as Figure 1 As shown in the embodiment of this application, a fault current limiting protection method for an insulated gate bipolar transistor (IGBT) power router is provided. The method includes: A100: When the hardware protection circuit of the insulated gate bipolar transistor type power router triggers the fault shutdown signal, the main controller synchronously starts the deterministic data capture window to collect data across electrical measurement nodes and obtain a multi-dimensional snapshot of the fault characteristics.

[0013] When a circuit fault occurs, such as overcurrent or overvoltage, the hardware protection circuit triggers a fault shutdown signal. At this point, the fault is detected, and the main controller initiates a data acquisition mechanism. After responding to the fault shutdown signal, the main controller synchronously starts a deterministic data capture window. This window accurately records the electrical measurement data of the equipment before and after the fault occurred, including key signals such as current, voltage, and temperature. Within the deterministic data capture window, electrical signals from different points are collected through multiple electrical measurement nodes, such as current sensors and voltage sensors. The signal provided by each electrical measurement node contains detailed information about the equipment status. All collected data forms a multi-dimensional snapshot of the fault characteristics, representing the electrical characteristics at the time of the fault.

[0014] A200: After aligning the multi-channel timing synchronization with the multi-dimensional snapshots of the fault features, a multi-branch fault timing relationship diagram is constructed.

[0015] Because data from different electrical measurement nodes have time delays, it's necessary to align them on the timeline when processing this data. This ensures synchronization of data from different channels on the timeline, guaranteeing the accuracy of subsequent analysis. By setting a common time reference point, such as the fault shutdown signal trigger time, the data from each channel is time-series aligned. Timestamps are used to synchronize the data collected from each channel to a unified timeline. The synchronized data is then graphically displayed to construct a multi-branch fault time-series diagram. This diagram describes the interrelationships between different branches during the fault occurrence process, helping to analyze the fault propagation paths and possible locations of fault sources in different branches.

[0016] A300: Perform cross-channel current-voltage causal correlation analysis on the multi-branch fault timing relationship diagram, and output the preliminary fault branch and preliminary fault type.

[0017] By analyzing the timing relationship diagrams of multi-branch faults, cross-channel current and voltage causal correlation analysis is performed. The aim is to identify the causal relationships between current waveforms, voltage waveforms, and equipment status. These relationships allow for the deduction of how a fault propagates from one branch to others. Causal analysis initially identifies which branches are the source of the fault or affected by it, marking these branches as initially faulty branches. Analysis of current and voltage waveforms and equipment status changes in different branches identifies the nature of the fault, such as short circuit, overload, or open circuit. This determines the initial fault type, laying the foundation for further diagnostics.

[0018] A400: Perform feature extraction and fusion on the multi-dimensional snapshot of the fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branch and preliminary fault type, perform fault reasoning based on multi-source data fusion in the fault diagnosis model and output a structured diagnostic report. The structured diagnostic report includes fault type, fault location, fault severity level, and potential cause inference.

[0019] Multiple features, such as time-domain and frequency-domain features, are extracted from different signals in multidimensional snapshots and fused into a dimensionality-reduced fault feature vector. This vector contains key information about the fault occurrence and effectively represents the fault state. The preliminary fault branch and type are combined with the dimensionality-reduced fault feature vector and input into a fault diagnosis model for inference. This model, through the fusion analysis of multi-source data, arrives at detailed fault conclusions. The model's inference results are output in the form of a structured report, including the following: fault type (e.g., short circuit, overload); fault location (e.g., fault branch, device location); fault severity level (e.g., minor fault, severe fault); and potential cause inference for quickly locating the root cause of the problem.

[0020] A500: Based on the structured diagnostic report matching recovery strategy, perform self-healing reboot of the insulated gate bipolar transistor type power router.

[0021] Based on the fault descriptions in the structured diagnostic report, an automatic recovery strategy is matched. This strategy includes selecting an appropriate restart method, such as a soft restart or a hard restart; and adopting different repair methods or restart procedures for different types of faults, such as short circuits, overloads, and equipment failures. After the recovery strategy is determined, the power router undergoes a self-healing restart according to the strategy. Self-healing restart means that the device can automatically return to normal operation without manual intervention. This automated process improves system reliability and recovery speed, reducing the need for manual intervention and the time of service interruption.

[0022] Furthermore, A110: The hardware protection circuit includes a detection unit, a comparison and decision unit, and a blocking execution unit based on a three-level cascaded architecture; A120: The detection unit collects multiple branch current signals and multiple IGBT on-state voltage drop signals from multiple power transmission branches through a current sensor and a desaturation detection circuit, respectively; A130: The comparison and decision unit maps and compares the multiple branch current signals and multiple IGBT on-state voltage drop signals against multiple hardware thresholds, and outputs a fault indication signal for the faulty branch; A140: The blocking execution unit blocks the IGBT drive pulses corresponding to the faulty branch based on the fault indication signal, and summarizes and generates the fault shutdown signal, which is sent to the main controller.

[0023] The hardware protection circuit adopts a three-level cascaded architecture, including a detection unit, a comparison and decision unit, and a blocking execution unit. Each unit plays a different role in the fault protection of the power router.

[0024] The detection unit collects current signals from the power transmission branch and IGBT (Insulated Gate Bipolar Transistor) on-state voltage drop signals through a current sensor and a desaturation detection circuit, respectively, providing real-time data for subsequent fault detection and protection. The current sensor monitors the current in the power transmission branch in real time; the current signal reflects current fluctuations, overload conditions, and other issues in the circuit, allowing for timely detection of potential faults. The desaturation detection circuit monitors the operating status of the IGBT. The IGBT is a core component for regulating power transmission; its on-state voltage drop reflects whether it is operating normally. When the IGBT's on-state voltage drop is too high, it indicates faults such as overload or short circuit.

[0025] The comparison and decision unit compares the current signal and IGBT on-state voltage drop signal collected by the detection unit based on multiple hardware thresholds, and outputs a fault indication signal. Specifically, the collected current signal and IGBT on-state voltage drop signal are compared with hardware-set thresholds. When the current or voltage drop exceeds the set threshold, the comparison and decision unit will identify the fault and output a fault indication signal, indicating the specific faulty branch.

[0026] The blocking execution unit blocks the IGBT drive pulses of the corresponding faulty branch based on the fault indication signal and generates a fault shutdown signal to notify the main controller for further operation. Specifically, when the comparison and decision unit issues a fault indication signal, the blocking execution unit immediately blocks the IGBT drive pulses of the corresponding faulty branch, cutting off the power transmission of the faulty branch and preventing the fault from spreading. The blocking execution unit transmits the summarized fault information to the main controller, generates a fault shutdown signal, and instructs the entire system to enter fault protection mode, awaiting further fault analysis and repair.

[0027] Furthermore, when the hardware protection circuit of the insulated gate bipolar transistor (IGBT) power router triggers a fault shutdown signal, the main controller synchronously initiates a deterministic data acquisition window to collect data across electrical measurement nodes, obtaining a multi-dimensional snapshot of the fault characteristics. The method includes: A150: After the external interrupt pin of the main controller receives the fault shutdown signal transition, it enters the interrupt service routine in response to the fault shutdown signal; A160: After the interrupt service routine responds, the write pointer of the circular buffer is frozen, and the initial instruction execution time of the interrupt service routine is used as the zero-time reference of the deterministic data capture window; A170: Using the zero-time reference as the cutoff time boundary and the deterministic data capture window as the acquisition duration reference, the pre-fault sampling data segment and the post-fault sampling data segment are retrieved in dual threads in the circular buffer and multiple power transmission branches; A180: The pre-fault sampling data segment and the post-fault sampling data segment are sequentially spliced ​​to obtain the multi-dimensional snapshot of the fault characteristics.

[0028] When the hardware protection circuit detects a fault and issues a fault shutdown signal, the external interrupt pin of the main controller detects a transition in this signal. This transition indicates that a fault has occurred and an immediate response is required. After detecting the transition of the fault shutdown signal, the main controller enters the interrupt service routine. The interrupt service routine is responsible for quickly responding to the fault signal, ensuring that critical data can be captured and subsequent processing can be initiated the instant the fault occurs.

[0029] A circular buffer is used to store real-time acquired data, ensuring that critical data is not lost during data acquisition. When a fault shutdown signal is triggered, the main controller freezes the write pointer of the circular buffer through an interrupt service routine to prevent data from being overwritten or lost after a fault occurs. Freezing the pointer ensures that data segments before and after the fault are completely preserved. After the interrupt service routine responds, the main controller records the initial instruction execution time of the interrupt service routine and uses this time as the zero-time reference. The zero-time reference marks the starting point of data acquisition, and all subsequent data acquisition will be synchronized and aligned based on this time.

[0030] Once the zero-time reference is determined, the time when the fault shutdown signal occurs is set as the cutoff time boundary for data acquisition, and all data acquisition will be performed based on this boundary. The duration reference of the data acquisition window starts from the zero-time reference, and subsequent sampling is performed according to this reference to ensure that data segments before and after the fault are accurately captured. Through a dual-thread mechanism, data segments sampled before and after the fault are retrieved simultaneously from the circular buffer and multiple power transmission branches. The data segments before the fault record the network state before the fault occurred, and the data segments after the fault record the network response after the fault occurred.

[0031] The pre-fault and post-fault sampled data segments are concatenated chronologically to form a complete time series, encompassing all key signal changes before and after the fault. This concatenated time series constitutes a multi-dimensional snapshot of the fault characteristics. This snapshot contains data from multiple electrical measurement nodes, such as current, voltage, and temperature, representing the overall electrical state at the moment of the fault. This snapshot serves as the basis for subsequent fault analysis, diagnosis, and reasoning, helping to accurately identify fault characteristics and causes.

[0032] Furthermore, after aligning the multi-channel timing synchronization with the multi-dimensional snapshots of the fault features, a multi-branch fault timing relationship diagram is constructed. The method includes: A210: Read the channel mapping relationship from the header information of the fault feature multidimensional snapshot, and group the electrical quantity time-series data groups corresponding to the multiple power transmission branches; A220: Using the zero-time reference as the unified time axis origin, perform time axis alignment fault feature point consistency verification on the multiple branch electrical quantity time-series data groups to obtain multiple discrete time grid aligned data groups; A230: Extract time-series features based on fault event marking from the multiple discrete time grid aligned data groups to obtain multiple fault-marked time-series data groups; A240: Compare the fault propagation trend between single-index branches based on the multiple fault-marked time-series data groups to generate the multi-branch fault time-series relationship diagram.

[0033] The fault characteristic multidimensional snapshot contains data collected from multiple electrical measurement nodes. The snapshot header includes channel mapping relationships, indicating the correspondence between each electrical measurement node and the power transmission branch. By reading this mapping relationship, different time-series data can be accurately associated with the corresponding branch electrical quantities. Based on the channel mapping relationship, the electrical quantity time-series data of multiple power transmission branches are grouped, and the time-series data of each branch are combined into a data group for subsequent analysis.

[0034] The zero-time reference serves as the time reference point for the entire data acquisition process. Based on the zero-time reference, the electrical quantity time-series data of all branches are synchronized to the same time axis. In this way, time-series data from different branches can be compared and analyzed within the same time frame. During the time alignment process, consistency checks are performed to ensure that the fault characteristic points of each branch are accurately aligned on a unified time axis, such as the instant of fault occurrence or fluctuations in current and voltage. If any time inconsistencies exist between the data, adjustments are made to ensure the synchronization of fault characteristic points.

[0035] For the aligned discrete-time grid, time-series features are extracted based on fault event markers. These features include: time-domain features, such as the changing trends of current or voltage waveforms; frequency-domain features, such as spectral analysis of electrical signals, detected high-frequency noise, or frequency variations; and IGBT state features, such as IGBT switching state changes and conduction time. Fault event markers refer to the fault-related feature points marked at the time of fault occurrence, such as current abrupt changes or overvoltage points. Relevant time-series data is extracted based on these markers, providing a foundation for subsequent fault propagation analysis.

[0036] Based on multiple fault-marked timing data sets, the trend of fault propagation between different branches is analyzed. The process of fault propagation from one branch to another can be analyzed and compared through changes in timing data, such as fluctuations in current and voltage, and changes in IGBT states. By comparing the fault propagation trends of different branches, a fault timing relationship diagram is drawn. This diagram vividly illustrates the interrelationships between branches during the fault occurrence process, including the order and path of fault propagation. The fault timing relationship diagram provides a reference for subsequent fault diagnosis and location, helping to analyze the specific circumstances of the fault source and fault propagation.

[0037] Furthermore, the branch electrical quantity timing data group includes current timing waveforms, voltage timing waveforms, and IGBT state timing sequences, and the multi-branch fault timing relationship diagram includes current fault timing trace diagrams, voltage fault timing trace diagrams, and IGBT state fault timing trace diagrams for the current timing waveforms, voltage timing waveforms, and IGBT state timing sequences.

[0038] Current timing waveforms record the current fluctuations in each branch. The current signal reflects load changes in the power system, current surges during faults, and potential overload conditions. By analyzing current timing waveforms, abnormal current changes can be identified, thus determining possible fault causes. Voltage timing waveforms record voltage signal changes over time. Voltage fluctuations or drops are key indicators of electrical faults (such as short circuits or overloads). Analyzing voltage timing waveforms can help infer whether the system is in an abnormal operating state. IGBT state timing sequences record the switching states of the IGBTs. IGBTs control power transmission, so their operating state directly affects the normal operation of the power router. IGBT state changes, such as on and off, can help analyze whether there are switching faults or control system problems in the system.

[0039] Based on current timing waveforms, a fault timing trace diagram is generated, displaying the trend of current fluctuations when a fault occurs. This diagram can identify drastic current changes and the fault propagation process during a fault. A voltage fault timing trace diagram is generated from voltage timing waveforms, showing the timing data of abnormal voltage fluctuations. Voltage fluctuations can help identify short circuits, overvoltages, or undervoltages in the circuit. An IGBT state fault timing trace diagram is generated from IGBT state timing sequences, analyzing whether there are abnormalities in the IGBT's switching actions. For example, it can identify IGBTs turning on or off at inappropriate times, leading to power transmission problems. These timing trace diagrams collectively constitute a multi-branch fault timing relationship diagram, used to describe fault propagation and the correlation between branches. Through these diagrams, the propagation path and timing relationship of the fault across different branches can be clearly defined, providing important clues for fault analysis.

[0040] Furthermore, feature extraction and fusion are performed on the multi-dimensional snapshot of the fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branch and preliminary fault type, fault reasoning based on multi-source data fusion is performed in the fault diagnosis model to output a structured diagnostic report. The method includes: A410: Encode the preliminary fault branch and preliminary fault type into an auxiliary diagnostic coding vector; A420: Extract time-domain feature parameter sets, frequency-domain feature parameter sets, and IGBT operation timing feature sets from the current fault timing trace diagram, voltage fault timing trace diagram, and IGBT state fault timing trace diagram, respectively; A430: Perform feature dimensionality reduction and fusion based on steady-state operation baseline on the time-domain feature parameter set, frequency-domain feature parameter set, and IGBT operation timing feature set to obtain the dimensionality-reduced fault feature vector; A440: Use the dimensionality-reduced fault feature vector as the fault waveform feature input, use the auxiliary diagnostic coding vector as the preliminary conclusion input, perform forward inference calculation in the fault diagnosis model, and output the structured diagnostic report.

[0041] The initial fault branch and fault type are encoded into a vector, which will become auxiliary information for subsequent fault reasoning. The resulting auxiliary diagnostic encoding vector provides key fault background information for the fault reasoning model, helping to improve the accuracy and efficiency of reasoning.

[0042] Time-domain features are extracted from the timing waveforms of current, power, and voltage. These features reflect the signal's variation over time, including amplitude, maximum rate of change, peaks, and troughs. Frequency-domain features, such as frequency components, amplitude spectrum, and phase spectrum, are extracted through spectral analysis of the timing signals. These features help identify frequency-related faults in electrical systems, such as harmonic distortion. Action timing features, i.e., the switching timing and behavior patterns of the IGBTs, are extracted from IGBT condition fault timing diagrams. By analyzing the IGBT timing data, it is possible to identify problems such as switching delays, abnormal switching, or abnormal conduction times.

[0043] A steady-state operating baseline is defined, which represents the characteristic parameters under normal equipment operation. Dimensionality reduction methods such as principal component analysis and linear discriminant analysis are used to reduce the dimensionality of the extracted time-domain features, frequency-domain features, and IGBT action time-series features. Dimensionality reduction removes redundant information, extracts the most representative features, and reduces computational complexity. The dimensionality-reduced time-domain features, frequency-domain features, and IGBT action features are then fused to obtain a comprehensive dimensionality-reduced fault feature vector. This vector represents the key characteristic information at the time of fault occurrence, providing more refined and effective data for subsequent fault reasoning.

[0044] The dimensionality-reduced fault feature vector is used as the fault waveform feature input, and the auxiliary diagnostic encoding vector is used as the preliminary conclusion input. Through forward inference calculation in the fault diagnosis model, based on the input feature data, information such as fault type, location, and severity is inferred. The forward inference process is carried out by a deep learning model, which can automatically extract and integrate information from the data to finally draw conclusions. The structured diagnostic report output by the model provides detailed basis for subsequent recovery strategies and can be used for equipment maintenance and fault repair decisions.

[0045] Furthermore, the method involves using the reduced-dimensional fault feature vector as the fault waveform feature input, using the auxiliary diagnostic encoding vector as the preliminary conclusion input, performing forward inference calculations in the fault diagnosis model, and outputting the structured diagnostic report. The method includes: A441: Construct a standard diagnostic model based on a multi-source fusion architecture. The fault diagnosis model includes a waveform feature encoding layer, a conclusion semantic encoding layer, and a cross-attention fusion layer. The cross-attention fusion layer includes a fault discrimination head, a fault location head, a fault level assessment head, and a cause inference head. A442: Retrieve similar sample data based on the power router model code to obtain multiple historical fault case samples. Each historical fault case sample consists of a sample dimensionality reduction feature vector, a sample auxiliary diagnostic vector, and a sample diagnostic report. A443: Use the multiple historical fault case samples to perform multi-task supervised training of the standard diagnostic model to obtain the fault diagnosis model. A444: Utilize the dimensionality reduction fault features... The vector is used as the input of fault waveform features and is nonlinearly mapped in the waveform feature encoding layer to obtain the deep feature representation of the waveform; A445: The auxiliary diagnostic encoding vector is used as the input of the preliminary conclusion and is nonlinearly mapped in the conclusion semantic encoding layer to obtain the conclusion semantic feature representation; A446: The deep feature representation of the waveform and the conclusion semantic feature representation are adaptively weighted and fused in the cross-attention fusion layer to obtain the multi-source fusion hidden layer representation. Based on the fault discrimination head, fault location head, fault level assessment head and cause inference head, the multi-source fusion hidden layer representation is subjected to multi-output branch parallel discrimination to output the fault type, fault location, fault severity level and potential cause inference, which constitute the structured diagnostic report.

[0046] The standard diagnostic model employs multi-source data fusion, integrating information from different data sources. This fusion architecture can synthesize information from different dimensions, thereby improving the accuracy of fault diagnosis. The waveform feature encoding layer processes the input electrical waveform data, such as current and voltage waveforms, encoding these time-series data into feature vectors, enabling the model to understand the waveform's changing patterns. The conclusion semantic encoding layer encodes the auxiliary diagnostic encoding vectors, transforming preliminary conclusions in fault reasoning into a processable vector form. The cross-attention fusion layer fuses waveform features and conclusion semantic features through adaptive weighting. The core of this layer is to effectively combine different types of data, ensuring the model can integrate the advantages of various data sources to make more accurate diagnostic judgments. Specifically, the fault discrimination head determines the fault type based on the fused information; the fault location head identifies the location of the fault, such as which branch is faulty; the fault level assessment head assesses the severity of the fault, helping to determine the scope of its impact; and the cause inference head infers the potential causes of the fault based on existing information, such as overload or short circuit.

[0047] Based on the model code of the power router, the type of historical fault case samples to be retrieved is determined. Each power router model has different fault modes, so relevant data can be accurately retrieved through the model code. By retrieving historical fault cases related to a specific power router model, multiple historical fault case samples containing sample dimensionality reduction feature vectors, sample auxiliary diagnostic vectors, and sample diagnostic reports are obtained. This provides the model with a large amount of real-world fault data, which helps improve the model's diagnostic accuracy and generalization ability.

[0048] Multi-task supervised learning is performed using historical fault case samples. Within this framework, the model can simultaneously handle multiple tasks, such as fault type classification, fault location, and fault severity assessment. By sharing learning weights, the model can optimize across multiple tasks, improving overall performance. During training, sample dimensionality-reduced feature vectors, sample auxiliary diagnostic vectors, and sample diagnostic reports are used as inputs and labels. Training with this data allows the model to learn the characteristic patterns and diagnostic methods for different faults. Through multi-task supervised training, a standard fault diagnosis model is obtained, capable of accurately analyzing and inferring from new fault data.

[0049] The waveform feature encoding layer uses nonlinear mapping, such as activation functions in neural networks like ReLU and Sigmoid, to transform dimensionality-reduced feature vectors into deep feature representations of the waveform. The role of nonlinear mapping is to help the model learn complex, nonlinear signal features, enabling better capture and representation of various patterns and features of the fault waveform. The deep feature representation of the waveform generated by this mapping can better capture hidden patterns in the fault waveform, such as waveform abrupt changes and frequency variations, providing valuable information for subsequent diagnostic reasoning.

[0050] The auxiliary diagnostic encoding vector provides initial clues for fault reasoning and is fed as input into the conclusion semantic encoding layer. This layer employs a non-linear mapping to transform the initial diagnostic conclusion into a more abstract semantic feature representation. This mapping captures higher-level semantic information, such as the relationship between fault type and possible causes. Through this process, a more refined conclusion semantic feature representation is generated for subsequent fault reasoning.

[0051] The cross-attention fusion layer employs a cross-attention mechanism, dynamically adjusting the weights of deep waveform features and semantic features of the conclusions based on their relationship. This weighted fusion ensures optimal combination of information from different data sources. The fused information generates a multi-source fusion hidden layer representation, which contains comprehensive information from waveform features and conclusion features, used for subsequent fault inference calculations. Based on the fused hidden layer representation, discrimination is performed in parallel through multiple output branches: the fault discrimination head determines the fault type based on the fused information; the fault location head identifies the location of the fault, such as which branch failed; the fault level assessment head assesses the severity of the fault, helping to determine the scope of its impact; and the cause inference head infers potential causes of the fault based on existing information, such as overload or short circuit. Finally, a structured diagnostic report is generated, providing maintenance personnel with detailed fault analysis.

[0052] Furthermore, a cross-channel current-voltage causal correlation analysis is performed on the multi-branch fault timing relationship diagram to output the preliminary fault branch and preliminary fault type. The method includes: A310: Perform two-dimensional collaborative anomaly localization on the current fault time-series trace map and the voltage fault time-series trace map to obtain K candidate fault origin branches; A320: Extract K sets of current-voltage timing correlation features of the K candidate fault origin branches from the current fault time-series trace map and the voltage fault time-series trace map, distinguish between active faults and passive disturbances, and output the preliminary fault branch; A330: Extract the IGBT conduction state reversal time of the preliminary fault branch from the IGBT state fault time-series trace map, combine it with the current waveform change time of the preliminary fault branch in the current fault time-series trace map, perform fault type discrimination, and output the preliminary fault type.

[0053] Current and voltage fault time-series trace plots record the changes in current and voltage during the fault occurrence process. By analyzing these two types of plots, the timing and location of abnormal signals can be identified. A two-dimensional collaborative localization method is employed when analyzing current and voltage fault time-series plots. This method not only analyzes anomalies in a single dimension but also considers their interrelationships during the fault occurrence process. This approach allows for more precise localization of potential fault origins. Analysis of the current and voltage time-series plots outputs K candidate fault origin branches, which are potential fault sources inferred based on abnormal signal fluctuations and the correlation between current and voltage.

[0054] By analyzing the data in the current and voltage time-series waveforms, the current-voltage time-series correlation characteristics of each candidate fault branch are extracted. These characteristics reflect the co-changes of current and voltage over time, revealing the relationship between current and voltage fluctuations. These characteristics help analyze whether the fault is caused by the equipment itself (active fault) or by external factors (passive disturbance). By analyzing the current-voltage time-series correlation characteristics, active faults and passive disturbances can be distinguished. Active faults are caused by internal equipment problems, such as drastic fluctuations in current or voltage; passive disturbances are caused by external factors, such as load fluctuations or equipment damage. Based on the above analysis, the preliminary fault branches are output.

[0055] In the IGBT state fault timing diagram, the timing of the IGBT's conduction state transition is identified. This transition signifies a change in the equipment's operating state or the occurrence of a fault. Simultaneously, the timing of current waveform abrupt changes is extracted from the current timing waveform. These current abrupt changes are typically indicators of current changes during fault occurrences, such as short circuits and overloads. By combining the IGBT conduction state transition timing and the current waveform abrupt changes, the fault type can be inferred. For example, a sudden change in the IGBT conduction state combined with abnormal current fluctuations can indicate a short circuit, overload, or open circuit fault. Analyzing these two timing characteristics outputs a preliminary fault type, providing a basis for subsequent fault location and repair.

[0056] Furthermore, by performing two-dimensional collaborative anomaly localization on the current fault time-series trace map and the voltage fault time-series trace map to obtain K candidate fault origin branches, the method includes: A311: Locate the branch with a sudden change in current waveform in the current fault time-series trace diagram to obtain a set of candidate branches for current anomalies; A312: Locate the branch with the starting point of voltage drop trend in the voltage fault time-series trace diagram to obtain a set of candidate branches for voltage anomalies; A313: Solve the intersection of the set of candidate branches for current anomalies and the set of candidate branches for voltage anomalies to locate the K candidate branches for fault origin.

[0057] By analyzing the current timing waveform, the moment when the current waveform changes abruptly can be located. This abrupt change may be caused by equipment failure, load overload, or external impact. Based on the abrupt change in the current waveform, potentially affected branches are identified. The candidate branch set for current anomalies consists of these abruptly changed branches, which are key branches for fault propagation or potential sources of faults.

[0058] By analyzing the voltage timing waveform, the voltage drop trend is detected. Voltage drops usually indicate circuit problems, such as short circuits, overloads, or power equipment failures. Based on the voltage drop trend, the affected branches are located. These branches are the origins of the faults, and the candidate branch set for voltage anomalies is composed of these branches for subsequent fault source localization.

[0059] By solving the intersection problem, branches exhibiting anomalies in both current and voltage time-series data are identified. These branches are most likely the source of the fault. Through intersection analysis, candidate fault origin branches are obtained, which help determine the most probable fault source. This process further improves the accuracy of fault location by comparing the simultaneous occurrence of abrupt changes in current waveforms and voltage drop trends.

[0060] Example 2, based on the same inventive concept as the fault current limiting protection method for the insulated gate bipolar transistor type power router in the foregoing examples, such as... Figure 2 As shown in the figure, this application provides a fault current limiting protection system for an insulated gate bipolar transistor type power router, the system comprising: The data acquisition module 10 is used to acquire data across electrical measurement nodes by synchronously starting a deterministic data capture window through the main controller when the hardware protection circuit of the insulated gate bipolar transistor (IGBT) power router triggers a fault shutdown signal, thereby obtaining a multi-dimensional snapshot of fault features. The relationship graph construction module 20 is used to construct a multi-branch fault time sequence relationship graph after aligning the multi-channel fault feature multi-dimensional snapshots with multi-channel time sequence synchronization. The causal correlation analysis module 30 is used to perform cross-channel current and voltage causal correlation analysis on the multi-branch fault time sequence relationship graph, and output preliminary fault branches and preliminary fault types. The fault reasoning module 40 is used to extract and fuse features from the multi-dimensional snapshots of fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branches and preliminary fault types, fault reasoning based on multi-source data fusion is performed in the fault diagnosis model, and a structured diagnostic report is output. The structured diagnostic report includes fault type, fault location, fault severity level, and potential cause inference. The self-healing restart module 50 is used to perform self-healing restart of the IGBT power router based on the structured diagnostic report and matching recovery strategies.

[0061] Furthermore, the hardware protection circuit includes a detection unit, a comparison and decision unit, and a blocking execution unit based on a three-level cascaded architecture. The detection unit collects multiple branch current signals and multiple IGBT on-state voltage drop signals from multiple power transmission branches through current sensors and desaturation detection circuits, respectively. The comparison and decision unit maps and compares the multiple branch current signals and multiple IGBT on-state voltage drop signals against multiple hardware thresholds and outputs a fault indication signal for the faulty branch. The blocking execution unit blocks the IGBT drive pulses corresponding to the faulty branch based on the fault indication signal and summarizes them to generate a fault shutdown signal, which is then sent to the main controller.

[0062] Furthermore, the data acquisition module 10 is used to perform the following operation steps: After the external interrupt pin of the main controller receives the fault shutdown signal transition, it enters the interrupt service routine in response to the fault shutdown signal. After the interrupt service routine responds, the write pointer of the circular buffer is frozen, and the initial instruction execution time of the interrupt service routine is used as the zero time reference of the deterministic data acquisition window. The zero time reference is used as the cutoff time boundary, and the deterministic data acquisition window is used as the acquisition duration reference. The pre-fault sampled data segment and the post-fault sampled data segment are retrieved in dual threads in the circular buffer and multiple power transmission branches. The pre-fault sampled data segment and the post-fault sampled data segment are sequentially spliced ​​to obtain the multi-dimensional snapshot of the fault characteristics.

[0063] Furthermore, the relationship graph construction module 20 is used to perform the following operation steps: The channel mapping relationship is read from the header information of the multidimensional snapshot of the fault features, and the electrical quantity time series data groups corresponding to the multiple power transmission branches are grouped. Taking the zero time reference as the unified time axis origin, the time axis alignment of the multiple branch electrical quantity time series data groups is checked for the consistency of fault feature points, resulting in multiple discrete time grid aligned data groups. The time series features based on fault event marking are extracted from the multiple discrete time grid aligned data groups, resulting in multiple fault-marked time series data groups. Based on the multiple fault-marked time series data groups, the fault propagation trend between single index branches is compared to generate the fault time series relationship diagram of the multiple branches.

[0064] Furthermore, the branch electrical quantity timing data group includes current timing waveforms, voltage timing waveforms, and IGBT state timing sequences, and the multi-branch fault timing relationship diagram includes current fault timing trace diagrams, voltage fault timing trace diagrams, and IGBT state fault timing trace diagrams for the current timing waveforms, voltage timing waveforms, and IGBT state timing sequences.

[0065] Furthermore, the fault reasoning module 40 is used to perform the following operation steps: The preliminary fault branch and preliminary fault type are encoded into an auxiliary diagnostic coding vector; time-domain feature parameter sets, frequency-domain feature parameter sets, and IGBT operation timing feature sets are extracted from the current fault timing trace diagram, voltage fault timing trace diagram, and IGBT state fault timing trace diagram, respectively; the time-domain feature parameter sets, frequency-domain feature parameter sets, and IGBT operation timing feature sets are fused based on steady-state operating baseline to obtain the dimensionality-reduced fault feature vector; the dimensionality-reduced fault feature vector is used as the fault waveform feature input, and the auxiliary diagnostic coding vector is used as the preliminary conclusion input, and forward inference calculation is performed in the fault diagnosis model to output the structured diagnostic report.

[0066] Furthermore, the fault reasoning module 40 is used to perform the following operation steps: A standard diagnostic model is constructed based on a multi-source fusion architecture. The fault diagnosis model includes a waveform feature encoding layer, a conclusion semantic encoding layer, and a cross-attention fusion layer. The cross-attention fusion layer includes a fault discrimination head, a fault location head, a fault level assessment head, and a cause inference head. Based on the power router model code, similar sample data is retrieved to obtain multiple historical fault case samples. Each historical fault case sample consists of a sample dimensionality reduction feature vector, a sample auxiliary diagnostic vector, and a sample diagnostic report. The standard diagnostic model is then trained using these multiple historical fault case samples through multi-task supervised training to obtain the fault diagnosis model. The dimensionality reduction fault feature vector is used as the fault... The waveform features are input and nonlinearly mapped in the waveform feature encoding layer to obtain a deep feature representation of the waveform. The auxiliary diagnostic encoding vector is used as the initial conclusion input and nonlinearly mapped in the conclusion semantic encoding layer to obtain a conclusion semantic feature representation. The deep feature representation of the waveform and the conclusion semantic feature representation are adaptively weighted and fused in the cross-attention fusion layer to obtain a multi-source fusion hidden layer representation. Based on the fault discrimination head, fault location head, fault level assessment head, and cause inference head, the multi-source fusion hidden layer representation is subjected to parallel discrimination with multiple output branches to output the fault type, fault location, fault severity level, and potential cause inference, thus constituting the structured diagnostic report.

[0067] Furthermore, the causal correlation analysis module 30 is used to perform the following operation steps: Two-dimensional collaborative anomaly localization is performed on the current fault time-series trace and the voltage fault time-series trace to obtain K candidate fault origin branches. K sets of current-voltage timing correlation features are extracted from the current fault time-series trace and the voltage fault time-series trace to distinguish between active faults and passive disturbances, and the preliminary fault branch is output. The IGBT conduction state reversal time of the preliminary fault branch is extracted from the IGBT state fault time-series trace, and combined with the sudden change time of the current waveform in the current fault time-series trace of the preliminary fault branch, the fault type is determined, and the preliminary fault type is output.

[0068] Furthermore, the causal correlation analysis module 30 is used to perform the following operation steps: The current waveform abrupt change branch is located in the current fault time-series trace diagram to obtain a set of candidate branches for current anomalies; the voltage drop trend initiation branch is located in the voltage fault time-series trace diagram to obtain a set of candidate branches for voltage anomalies; the intersection of the candidate branches for current anomalies and the candidate branches for voltage anomalies is solved to locate the K candidate branches for fault origin.

[0069] Through the foregoing detailed description of the fault current limiting protection method for an insulated gate bipolar transistor (IGBT) power router, those skilled in the art can clearly understand the fault current limiting protection system for an IGBT power router in this embodiment. Since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and relevant parts can be referred to in the method section.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A fault current limiting protection method for an insulated-gate bipolar transistor type power router, characterized in that, The method includes: When the hardware protection circuit of the insulated gate bipolar transistor power router triggers the fault shutdown signal, the main controller synchronously starts the deterministic data acquisition window to collect data across electrical measurement nodes and obtain a multi-dimensional snapshot of the fault characteristics. After aligning the multi-channel timing synchronization with the multi-dimensional snapshots of the fault features, a multi-branch fault timing relationship diagram is constructed; Perform cross-channel current-voltage causal correlation analysis on the multi-branch fault timing relationship diagram to output the preliminary fault branch and preliminary fault type; Feature extraction and fusion are performed on the multidimensional snapshot of the fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branch and preliminary fault type, fault reasoning based on multi-source data fusion is performed in the fault diagnosis model to output a structured diagnosis report. The structured diagnosis report includes fault type, fault location, fault severity level and potential cause inference. Based on the structured diagnostic report matching recovery strategy, the insulated gate bipolar transistor type power router performs a self-healing reboot.

2. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 1, characterized in that, The hardware protection circuit includes a detection unit, a comparison and decision unit, and a blocking execution unit based on a three-level cascaded architecture; The detection unit acquires multiple branch current signals and multiple IGBT on-state voltage drop signals of multiple power transmission branches through current sensors and desaturation detection circuits, respectively. The comparison and decision unit maps and compares the multiple branch current signals and multiple IGBT on-state voltage drop signals against multiple hardware thresholds, and outputs a fault indication signal for the faulty branch. The blocking execution unit blocks the IGBT drive pulses corresponding to the faulty branch based on the fault indication signal, and generates the fault shutdown signal and sends it to the main controller.

3. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 1, characterized in that, When the hardware protection circuit of an insulated-gate bipolar transistor (IGBT) power router triggers a fault shutdown signal, a deterministic data acquisition window is synchronously activated by the main controller to collect data across electrical measurement nodes, obtaining a multi-dimensional snapshot of fault characteristics. The method includes: After the external interrupt pin of the main controller receives the fault shutdown signal transition, it enters the interrupt service routine in response to the fault shutdown signal. After the interrupt service routine responds, the write pointer of the circular buffer is frozen, and the initial instruction execution time of the interrupt service routine is used as the zero-time reference of the deterministic data capture window. Using the zero-time reference as the cutoff time boundary and the deterministic data capture window as the acquisition duration reference, the pre-fault sampled data segment and the post-fault sampled data segment are retrieved in a dual-thread manner in the circular buffer and multiple power transmission branches. The pre-fault sampled data segment and the post-fault sampled data segment are sequentially spliced ​​together to obtain a multi-dimensional snapshot of the fault characteristics.

4. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 3, characterized in that, After aligning the multi-channel timing synchronization with the multi-dimensional snapshots of the fault features, a multi-branch fault timing relationship diagram is constructed. The method includes: Read the channel mapping relationship from the header information of the fault feature multidimensional snapshot, and group the multiple branch electrical quantity timing data groups corresponding to the multiple power transmission branches; Using the zero-time reference as the unified time axis origin, the time axis alignment of the multiple branch electrical quantity time series data groups is checked for the consistency of fault feature points, resulting in multiple discrete time grid aligned data groups; The time-series features based on fault event markers are extracted from the multiple discrete-time grid aligned data groups to obtain multiple fault-marked time-series data groups; Based on the multiple fault-marked time-series data groups, the fault propagation trend between single-index branches is compared to generate the fault time-series relationship diagram of the multiple branches.

5. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 4, characterized in that, The branch electrical quantity timing data group includes current timing waveforms, voltage timing waveforms, and IGBT state timing sequences. The multi-branch fault timing relationship diagram includes current fault timing trace diagrams, voltage fault timing trace diagrams, and IGBT state fault timing trace diagrams for the current timing waveforms, voltage timing waveforms, and IGBT state timing sequences.

6. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 5, characterized in that, The method involves extracting and fusing features from the multi-dimensional snapshots of the fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branches and preliminary fault types, fault reasoning based on multi-source data fusion is performed in the fault diagnosis model to output a structured diagnostic report. The method includes: The preliminary fault branch and preliminary fault type are encoded into an auxiliary diagnostic coding vector; The time-domain feature parameter set, frequency-domain feature parameter set, and IGBT action timing feature set are extracted from the current fault timing trace diagram, voltage fault timing trace diagram, and IGBT state fault timing trace diagram, respectively. The time-domain feature parameter set, frequency-domain feature parameter set, and IGBT action timing feature set are fused by feature dimensionality reduction based on steady-state operation baseline to obtain the dimensionality-reduced fault feature vector. The reduced-dimensional fault feature vector is used as the fault waveform feature input, and the auxiliary diagnostic encoding vector is used as the preliminary conclusion input. Forward reasoning calculation is performed in the fault diagnosis model to output the structured diagnostic report.

7. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 6, characterized in that, The method includes: using the reduced-dimensional fault feature vector as the fault waveform feature input, using the auxiliary diagnostic encoding vector as the preliminary conclusion input, performing forward inference calculations in the fault diagnosis model, and outputting the structured diagnostic report. A standard diagnostic model is constructed based on a multi-source fusion architecture. The fault diagnosis model includes a waveform feature encoding layer, a conclusion semantic encoding layer, and a cross-attention fusion layer. The cross-attention fusion layer includes a fault discrimination head, a fault location head, a fault level assessment head, and a cause inference head. Based on the model code of the power router, sample data of the same type is retrieved to obtain multiple historical fault case samples. The historical fault case samples are composed of sample dimensionality reduction feature vectors, sample auxiliary diagnostic vectors and sample diagnostic reports. The fault diagnosis model is obtained by using the multiple historical fault case samples for multi-task supervised training of the standard diagnostic model. The reduced-dimensional fault feature vector is used as the fault waveform feature input, and nonlinear mapping is performed in the waveform feature encoding layer to obtain the deep feature representation of the waveform. The auxiliary diagnostic encoding vector is used as the initial conclusion input, and a nonlinear mapping is performed on the conclusion semantic encoding layer to obtain the conclusion semantic feature representation. After adaptively weighting and fusing the deep feature representation of the waveform and the semantic feature representation of the conclusion in the cross-attention fusion layer to obtain the multi-source fusion hidden layer representation, the multi-output branch parallel discrimination is performed on the multi-source fusion hidden layer representation based on the fault discrimination head, fault location head, fault level assessment head and cause inference head, and the fault type, fault location, fault severity level and potential cause inference are output to form the structured diagnostic report.

8. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 5, characterized in that, The method involves performing cross-channel current-voltage causal correlation analysis on the multi-branch fault timing diagram to output the preliminary fault branch and preliminary fault type. Two-dimensional collaborative anomaly localization is performed on the current fault time sequence trace map and the voltage fault time sequence trace map to obtain K candidate branches for fault origin; K sets of current-voltage timing correlation features of the K fault origin candidate branches are extracted from the current fault timing trace map and the voltage fault timing trace map, active faults and passive disturbances are distinguished, and the preliminary fault branches are output. The IGBT conduction state reversal time of the preliminary fault branch is extracted from the IGBT state fault timing trace diagram. Combined with the sudden change time of the current waveform of the preliminary fault branch in the current fault timing trace diagram, the fault type is determined and the preliminary fault type is output.

9. The fault current limiting protection method for an insulated gate bipolar transistor type power router as described in claim 8, characterized in that, The method involves performing two-dimensional collaborative anomaly localization on the current fault time-series trace map and the voltage fault time-series trace map to obtain K candidate fault origin branches. The current waveform abrupt change branch is located in the current fault timing trace diagram to obtain a set of candidate current anomaly branches; The starting branch of the voltage drop trend is located in the voltage fault timing trace diagram to obtain a set of candidate branches for voltage anomalies. The intersection of the current anomaly candidate branch set and the voltage anomaly candidate branch set is solved to locate the K fault origin candidate branches.

10. A fault current limiting protection system for an insulated gate bipolar transistor type power router, characterized in that, For implementing the fault current limiting protection method for an insulated gate bipolar transistor type power router according to any one of claims 1-9, the system comprises: The data acquisition module is used to acquire data across electrical measurement nodes by synchronously starting a deterministic data acquisition window through the main controller when the hardware protection circuit of the insulated gate bipolar transistor type power router triggers a fault shutdown signal, so as to obtain a multi-dimensional snapshot of the fault characteristics. The relationship graph construction module is used to construct a multi-branch fault time sequence relationship graph after aligning the multi-dimensional snapshots of the fault features with the multi-channel time sequence synchronization. The causal correlation analysis module is used to perform cross-channel current-voltage causal correlation analysis on the multi-branch fault timing relationship diagram and output the preliminary fault branch and preliminary fault type. The fault reasoning module is used to extract and fuse features from the multi-dimensional snapshot of the fault features to obtain a dimensionality-reduced fault feature vector. Combined with the preliminary fault branch and preliminary fault type, it performs fault reasoning based on multi-source data fusion in the fault diagnosis model and outputs a structured diagnostic report. The structured diagnostic report includes fault type, fault location, fault severity level and potential cause inference. The self-healing restart module is used to perform self-healing restart of the insulated gate bipolar transistor type power router based on the structured diagnostic report matching recovery strategy.

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