Charge-discharge control circuit, charge-discharge control device, battery device, and battery system

Abstract

The present application provides a kind of charge-discharge control circuit, charge-discharge control device, battery device and battery system, in the case where using two or more batteries and protection IC, preferably, the battery can be protected.Charge-discharge control circuit (100) includes control circuit (120), the control circuit (120) is transferred to the control state corresponding to the detection result of abnormal state, according to control state, the charge-discharge path of one or more secondary batteries (VBAT) of control object is controlled to open and close, and is connected in parallel with the external terminal (EB+) and external terminal (EB-) arranged in the charge-discharge path, and other charge-discharge control circuit with different secondary battery (VBAT) as control object is transmitted detection result signal containing detection result, so that the control state of the present circuit and the control state of other charge-discharge control circuit are shared.

Description

Technical Field

[0001] This invention relates to a charge / discharge control circuit, a charge / discharge control device, a battery device, and a battery system. Background Technology

[0002] Previously, there were known integrated circuits (ICs) that protected batteries by controlling the charging and discharging of the batteries (see Patent Document 1, Japanese Patent Application Publication No. 2012-257407).

[0003] [Existing Technical Documents]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2012-257407 Summary of the Invention

[0006] [The problem the invention aims to solve]

[0007] In constructing a battery management system that includes two batteries connected in parallel with external terminals and two protection ICs that control each battery, various challenges arise with the protection ICs. For example, when using conventional protection ICs, it can be difficult to maintain a discharge-prohibited state if only one of the protection ICs detects a discharge overcurrent.

[0008] Conventional protection ICs, upon detecting an overcurrent discharge, would disable discharge by turning off the discharge control transistor. When the discharge current is cut off by disabling discharge, the voltage at the VM terminal, which detects whether a charger or abnormal load is connected to the external terminal, rises to maintain the overcurrent discharge detection state.

[0009] However, when two protection ICs are connected in parallel with external terminals, and one protection IC detects a discharge overcurrent while the other does not, the discharge of the other protection IC is not prohibited, thus the voltage at the VM terminal cannot rise. Therefore, after one protection IC is prohibited from discharging, it repeatedly reverts to being able to discharge and then becomes prohibited from discharging again, making it difficult to properly protect the battery.

[0010] In addition, if only one of the protection ICs detects an abnormal state and disables discharge or charging, the voltage balance of the two batteries will be disrupted, which may lead to malfunction.

[0011] Therefore, the present invention is made in view of the aspects described above, and the object of the present invention is to provide a technology that can preferably protect the battery when using two or more batteries and a protection IC.

[0012] [Technical means to solve the problem]

[0013] One embodiment of the present invention is a charge / discharge control circuit, including a control circuit that switches to a control state corresponding to the detection result of an abnormal state, controls the opening and closing of the charge / discharge path of one or more secondary batteries to be controlled according to the control state, is connected in parallel with external terminals provided on the charge / discharge path, and transmits and receives detection result signals containing the detection result with other charge / discharge control circuits that control secondary batteries different from this circuit, thereby sharing the control state of this circuit with the control states of other charge / discharge control circuits.

[0014] [The effects of the invention]

[0015] The present invention can preferably protect the battery when using two or more batteries and a protection IC. Attached Figure Description

[0016] Figure 1 This is a diagram used to illustrate an example of the battery system of the first embodiment.

[0017] Figure 2 This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the first embodiment.

[0018] Figure 3 This is a diagram used to illustrate an example of the structure of the transmitting circuit in the first embodiment.

[0019] Figure 4 This is a diagram used to illustrate an example of the structure of the receiving circuit in the first embodiment.

[0020] Figure 5 This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the second embodiment.

[0021] Figure 6 This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the third embodiment.

[0022] Figure 7 This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the fourth embodiment.

[0023] Figure 8 This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the fifth embodiment.

[0024] Figure 9 This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the sixth embodiment.

[0025] Figure 10This is a diagram used to illustrate a structural example of the charge / discharge control circuit of the seventh embodiment.

[0026] Explanation of icon numbers

[0027] 1: Battery System

[0028] 10: Battery device

[0029] 20: Charge / discharge control device

[0030] 100: Charge / discharge control circuit

[0031] 101, 103, 142: Resistors

[0032] 102: Capacitor

[0033] 104: External FET

[0034] 110: Anomaly Detection Circuit

[0035] 120: Control Circuit

[0036] 130: Transmitting circuit

[0037] 131, 132: Variable resistors

[0038] 133, 134: Switch

[0039] 140: Receiving circuit

[0040] 141: Comparator

[0041] 143: Threshold Voltage Detector

[0042] 144: Smoothing Circuit

[0043] 150: Constant voltage source

[0044] CFET: Charge control transistor

[0045] DFET: Transistor for discharge control

[0046] RL: Load resistance

[0047] VBAT: Secondary battery Detailed Implementation

[0048] [First Implementation Method]

[0049] Preferred embodiments of the charge / discharge control circuit, charge / discharge control device, battery device, and battery system of this embodiment are listed and described in detail below with reference to the accompanying drawings. In the drawings, the same or similar parts are labeled with the same or similar symbols.

[0050] Furthermore, in all the drawings used to describe the embodiments, figures with the same function use the same symbols, and repeated descriptions are omitted. Additionally, the term "based on XX" as used in this application means "at least based on XX," and also includes cases where it is based on other elements besides XX. Furthermore, "based on XX" is not limited to directly using XX, but also includes cases where calculations or processing have been performed on XX. "XX" can be any element (e.g., any information). Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0051] [Example of a battery system structure]

[0052] Figure 1 This is a diagram illustrating an example of the battery system 1 according to the first embodiment. The battery system 1 includes a plurality of battery devices 10 and a load resistor RL. First battery device 10-1 and second battery device 10-2 illustrate the plurality of battery devices 10. The battery system 1 is not limited to an example including two battery devices 10. The plurality of battery devices 10 are connected in parallel with external positive terminals EB+ and external negative terminals EB-. In the following description, the external positive terminals EB+ and external negative terminals EB- are sometimes collectively referred to as external terminals.

[0053] The battery device 10 includes a charge / discharge control circuit 100, a secondary battery VBAT, a resistor 101, a capacitor 102, a resistor 103, and an external field-effect transistor (FET) 104. Sometimes, the charge / discharge control circuit 100 included in the first battery device 10-1 is referred to as the first charge / discharge control circuit 100-1, and the charge / discharge control circuit 100 included in the second battery device 10-2 is referred to as the second charge / discharge control circuit 100-2. The first charge / discharge control circuit 100-1 and the second charge / discharge control circuit 100-2 have the same structure. Without distinguishing between them, they are simply referred to as charge / discharge control circuit 100, and will be described below. In the following description, when explaining the relationship between multiple charge / discharge control circuits 100, the first charge / discharge control circuit 100-1 will be referred to as this circuit, and the second charge / discharge control circuit 100-2 will be described as other circuits.

[0054] The charge / discharge control circuit 100 is an example of a circuit that protects the secondary battery VBAT from abnormal conditions such as overcurrent by controlling the charging and discharging of the secondary battery VBAT under specified conditions. The charge / discharge control circuit 100 includes, for example, a VDD terminal, a VSS terminal, a DO terminal, a CO terminal, a VM terminal, and a CNT terminal. The charge / discharge control circuit 100 may also be referred to as a protection IC. Although an example showing a single secondary battery VBAT controlled by the charge / discharge control circuit 100 is provided, the charge / discharge control circuit 100 can also control multiple secondary battery VBATs. The secondary battery VBATs controlled by each charge / discharge control circuit 100 are different from each other.

[0055] The VDD terminal is a terminal connected to the external power supply of the charge / discharge control circuit 100 (also called the "positive power supply terminal"). For example, the VDD terminal is connected to the positive terminal of the secondary battery VBAT. The VSS terminal is, for example, a terminal connected to the negative terminal of the secondary battery VBAT (also called the "negative power supply terminal"). From the VDD terminal, the DO and CO terminals, which are supplied with voltage during the operation of the charge / discharge control circuit 100, are connected to the external FET 104. The CO terminal can also be called the charging control terminal. The DO terminal can also be called the discharging control terminal. The VM terminal is an external negative voltage input terminal used to detect whether a charger (not shown) is connected to an external terminal. The CNT terminal is connected to the CNT terminals of other charge / discharge control circuits 100 via signal lines.

[0056] The positive terminal of the secondary battery VBAT is connected to one end of resistor 101, one end of load resistor RL, and the external positive terminal EB+. The negative terminal is connected to one end of capacitor 102, the VSS terminal, and the source of the discharge control transistor DFET. Specific examples of secondary batteries VBAT include lithium-ion batteries and lead-acid batteries. The secondary battery VBAT can also be referred to as a battery.

[0057] The other end of resistor 101 is connected to the VDD terminal and the other end of capacitor 102. One end of capacitor 102 is connected to the VDD terminal, and the other end is connected to the VSS terminal. One end of resistor 103 is connected to the VM terminal, and the other end is connected to the source of the charging control transistor CFET, the other end of the load resistor RL, and the external negative terminal EB-.

[0058] The external FET 104 includes a discharge control transistor (DFET) and a charge control transistor (CFET). Hereinafter, the charge / discharge control circuit 100 and the external FET 104 are sometimes referred to together as the charge / discharge control device 20. The gate of the discharge control transistor (DFET) is connected to the DO terminal of the charge / discharge control circuit 100, and its source and drain are connected to the charge / discharge path of the secondary battery VBAT. For example, when a control signal is input to the gate, the discharge control transistor (DFET) is turned off, thereby cutting off the discharge current of the secondary battery VBAT. Similarly, the gate of the charge control transistor (CFET) is connected to the CO terminal of the charge / discharge control circuit 100 and is input with a control signal. The source and drain of the charge control transistor (CFET) are connected to the charge / discharge path of the secondary battery VBAT. For example, by turning off the charge control transistor (CFET), the charging current of the secondary battery VBAT is cut off. As described above, the external FET 104 controls the charge / discharge path of the secondary battery VBAT through the charge control transistor (CFET) and the discharge control transistor (DFET) provided in the charge / discharge path.

[0059] [Example of a charge / discharge control circuit structure]

[0060] Figure 2 This diagram illustrates an example of the structure of the charge / discharge control circuit 100 according to the first embodiment. The charge / discharge control circuit 100 includes an abnormality detection circuit 110, a control circuit 120, a transmitting circuit 130, and a receiving circuit 140. The VSS terminal is connected to a reference voltage, for example. The reference voltage can be 0 V, a small voltage close to 0 V, or any voltage. Figure 2 An example is shown with a charger BC connected to an external terminal.

[0061] Anomaly detection circuit 110 detects abnormal states associated with the secondary battery VBAT, such as overcharging, over-discharging, and overcurrent discharge. The diagram summarizes the circuitry used to detect various abnormal states, including overcharge detection, over-discharge detection, and overcurrent discharge detection circuits. The anomaly detection circuit 110 can detect one or more abnormal states. For example, the first input terminal of the anomaly detection circuit 110 is connected to the VM terminal, and the second input terminal is connected to the VDD terminal; the abnormal state is determined by the voltage supplied from these terminals. The output terminal of the anomaly detection circuit 110 is connected to the control circuit 120. The anomaly detection circuit 110 detects whether an abnormal state has occurred and outputs a signal containing the detection result to the control circuit 120. The detection result includes whether an abnormal state was detected and the type of abnormal state detected. The anomaly detection circuit 110 may or may not aggregate the outputs of the various detection circuits shown in the diagram. When the anomaly detection circuit 110 does not aggregate the outputs, sometimes the signals output from each detection circuit are aggregated and referred to as the detection result signal. In addition, sometimes the signal in the detection result signal that contains the result of detecting the detected object (e.g., a high-level signal) is called the detection signal, and the signal that contains the result of not detecting the object (e.g., a low-level signal) is called the release signal.

[0062] The first terminal of the control circuit 120 is connected to the output terminal of the abnormal detection circuit 110, the second terminal is connected to the DO terminal, the third terminal is connected to the CO terminal, the fourth terminal is connected to the transmitting circuit 130, and the fifth terminal is connected to the receiving circuit 140.

[0063] An anomaly detection circuit 110 supplies a detection result signal to the first terminal of the control circuit 120. The control circuit 120 maintains or switches control states based on the detection result. The control states include a normal state and a protection state. The normal state is the state where no anomaly is detected. The protection state is the state where an anomaly is detected. The control circuit 120 supplies control signals corresponding to the control state to the external FET 104 via the second and third terminals to control the opening and closing of the charging and discharging path of the secondary battery VBAT, thereby responding to the detected anomaly. Additionally, the control circuit 120 controls the transmitting circuit 130 by outputting a control signal from the fourth terminal.

[0064] A detection result signal is supplied from the receiving circuit 140 to the fifth terminal of the control circuit 120. The control circuit 120 maintains or transfers its control state similarly to when a detection result signal is supplied from the anomaly detection circuit 110. If the detection signal supplied from the anomaly detection circuit 110 and the detection signal supplied from the receiving circuit 140 indicate the detection of different types of anomalies, the control state of the control circuit 120 may be unstable. Therefore, the charge / discharge control circuit 100 may also include a structure that does not supply a detection signal from the receiving circuit 140 when an anomaly is detected by the anomaly detection circuit 110. "Not supplying a detection signal from the receiving circuit 140" can mean, for example, not supplying a detection result signal, or supplying a release signal regardless of the detection result received by the receiving circuit 140. Furthermore, the control circuit 120 may maintain or transfer its control state based on the detection signal from either (e.g., the anomaly detection circuit 110), while ignoring the detection signal from the other.

[0065] The transmitting circuit 130 receives a control signal from the control circuit 120 and operates according to the control signal. The transmitting circuit 130 transmits a detection result signal, containing the detection result of the abnormal state obtained by the abnormality detection circuit 110, to other circuits (the second charge / discharge control circuit 100-2) via the CNT terminal. Thus, the charge / discharge control circuit 100 shares the detection result signal of its own circuit (the first charge / discharge control circuit 100-1) with other circuits. The detection result signal can be an analog signal or a digital signal. Furthermore, the detection result signal output by the abnormality detection circuit 110 and the received / transmitted detection result signals only need to contain the detection result; they can be represented in different forms and contain different information.

[0066] Figure 3 This is a diagram illustrating an example of the structure of the transmitting circuit 130 in the first embodiment. The transmitting circuit 130 includes, for example, a variable resistor 131, a variable resistor 132, a switch 133, and a switch 134.

[0067] One end of variable resistor 131 is connected to the VDD terminal via switch 133, and the other end is connected to one end of variable resistor 132 and the CNT terminal. The other end of variable resistor 132 is connected to the VSS terminal via switch 134, and one end is connected to one end of variable resistor 131 and the CNT terminal. The voltage at the connection point of variable resistors 131 and 132 is determined by the ratio of the resistance values ​​of variable resistors 131 and 132. Furthermore, the resistance values ​​of variable resistors 131 and 132 are determined by the control signal supplied from control circuit 120. That is, the voltage supplied by transmitting circuit 130 is determined by the resistance ratio of variable resistors 131 and 132, and further by the voltage ratio of the VDD terminal to the VSS terminal. Therefore, the detection result contained in the detection result signal is represented by the voltage ratio of the VDD terminal to the VSS terminal. The voltage ratio between the VDD terminal and the VSS terminal is the voltage ratio of the detection result signal relative to the voltage between the VDD and VSS terminals. The detection result signal transmitted from the transmitting circuit 130 is received by the receiving circuit 140 of other circuits.

[0068] The receiving circuit 140 receives a detection result signal from the transmitting circuit 130 of other circuits, which includes the detection result of the anomaly detection circuit 110 of those other circuits. The receiving circuit 140 then supplies the received detection result signal to the control circuit 120. Thus, the charge / discharge control circuit 100 shares the detection result signal of the other circuits with this circuit.

[0069] Figure 4 This diagram illustrates an example of the structure of the receiving circuit 140 according to the first embodiment. The receiving circuit 140 includes, for example, a plurality of comparators 141, a plurality of resistors 142, and a threshold voltage detector 143. Comparators 141-1 to 141-3 illustrate a plurality of comparators 141. Resistors 142-1 to 142-4 illustrate a plurality of resistors 142. The plurality of resistors 142 are trapezoidal resistors.

[0070] A comparator 141 supplies a detection result signal from other circuits to its first input terminal via a CNT terminal, and is connected to a trapezoidal resistor at its second input terminal. Based on the relationship between the voltage supplied to the first input terminal and the voltage supplied to the second input terminal, the comparator 141 outputs a digital signal to the control circuit 120. For example, the comparator 141 outputs a high-level signal (hereinafter sometimes referred to as "H" level) when the voltage ratio of the detection result signals is above a predetermined threshold, and outputs a low-level signal (hereinafter sometimes referred to as "L" level) when it is below the threshold. Specifically, the voltage between the VDD and VSS terminals supplied to the second input terminal of comparator 141-1 is obtained by dividing the voltage between resistors 142-1 and resistors 142-2 and beyond by resistance ratio. The voltage between the VDD and VSS terminals supplied to the second input terminal of comparator 141-2 is obtained by dividing the voltage between resistors 142-1 and 142-2 and resistors 142-3 and beyond by resistance ratio. The same applies to comparators 141-3 and later.

[0071] Therefore, the receiving circuit 140 can determine the voltage ratio between the voltage at the VDD terminal and the voltage at the VSS terminal based on the voltage supplied from the transmitting circuit 130 of other circuits, and obtain the detection results from other circuits. By using the voltage ratio to represent the detection results contained in the detection result signal, the detection results can be shared regardless of the voltage value of the secondary battery VBAT, which varies due to usage conditions.

[0072] Furthermore, the voltages at the VDD and VSS terminals are examples of transmission and reception using a common reference in the first charge / discharge control circuit 100-1 and the second charge / discharge control circuit 100-2, and do not necessarily need to be the voltages at the VDD and VSS terminals. Hereinafter, the voltage on the higher potential side, such as the voltage at the VDD terminal, will sometimes be referred to as the first voltage, and the voltage on the lower potential side, such as the voltage at the VSS terminal, will sometimes be referred to as the second voltage.

[0073] The threshold voltage detector 143 supplies the detection result signal from other circuits to the input terminal via the CNT terminal, and its output terminal is connected to the control circuit 120. The threshold voltage detector 143 outputs a high-level signal when the voltage of the detection result signal is above a predetermined threshold, and an low-level signal when it is below the threshold. Depending on the circuit structure, the range of voltage ratios that the comparator 141 can determine may be limited. The threshold voltage detector 143 allows for the determination of magnitude relationships even for voltages based on voltage ratios that are difficult for the comparator 141 to determine, thus increasing the information that can be included in the detection result signal.

[0074] The number of comparators 141 and threshold voltage detectors 143 can be determined according to the number of types of abnormal states of the detected object. For example, the number of comparators 141 and threshold voltage detectors 143 can be the same as the number of types of abnormal states of the detected object.

[0075] In this circuit, the charge / discharge control circuit 100 transmits and receives detection result signals between itself and other circuits via the transmitting circuit 130 and the receiving circuit 140. This allows it to determine whether an abnormal state is detected in other circuits and the type of abnormal state detected, thus enabling the control state of this circuit to be the same as the control states of other circuits. Hereinafter, the situation where the control states are the same will be referred to as a "shared control state." According to this structure, a situation where one circuit is in a protected state while the other is in a normal state can be prevented. Therefore, the situation where the protection of the secondary battery VBAT is hindered due to one circuit being in a protected state and the other in a normal state can be avoided. Furthermore, by sharing the control state, each charge / discharge control circuit 100 performs the same control, preventing the cell balance of the secondary battery VBAT controlled by each charge / discharge control circuit 100 from being disrupted. Therefore, when using two or more secondary batteries VBAT and the charge / discharge control circuit 100, the charge / discharge control circuit 100 can preferably protect the secondary battery VBAT.

[0076] In this description, an example of the control circuit 120 outputting a control signal to the transmitting circuit 130 was given. This embodiment is not limited to this example; the control circuit 120 may also output a detection result signal from a fourth terminal. In this case, the transmitting circuit 130 operates according to the detection result signal.

[0077] Furthermore, the description provided an example of the detection result obtained by the anomaly detection circuit 110 being transmitted to the transmitting circuit 130 via the control circuit 120. This embodiment is not limited to this example; the detection result signal, including the detection result obtained by the anomaly detection circuit 110, can also be directly supplied to the transmitting circuit 130. Moreover, since the control circuit 120 originally has a structure that outputs control signals to the DO or CO terminal for each control state, it is easy to implement a structure that outputs control signals to the transmitting circuit 130. Additionally, controlling the transmitting circuit 130 via the control circuit 120 simplifies the structure of the transmitting circuit 130.

[0078] [Second Implementation]

[0079] Figure 5This diagram illustrates a structural example of the charge / discharge control circuit 100A according to the second embodiment. The charge / discharge control circuit 100A of the second embodiment differs from that of the first embodiment in that it further includes a constant voltage source 150. In the following description, details described in the first embodiment may sometimes be omitted.

[0080] The constant voltage source 150 is a power supply circuit that provides a stable output voltage independent of fluctuations in the voltage value of the secondary battery VBAT. The constant voltage source 150 can also be, for example, a low dropout (LDO) regulator. The voltage output from the constant voltage source 150 replaces the voltage between the VDD and VSS terminals and is supplied to the transmitting circuit 130 and the receiving circuit 140. Accordingly, the transmitting circuit 130 and the receiving circuit 140 can transmit and receive detection result signals that represent the detection result through voltage values. Since the receiving side has high impedance, a detection result with a large output current value is not required when the detection result is represented by a voltage value. Therefore, by using small-area components in the constant voltage source 150, the charge / discharge control circuit 100A can be miniaturized.

[0081] [Third Implementation Method]

[0082] Figure 6 This diagram illustrates a structural example of the charge / discharge control circuit 100B according to the third embodiment. The difference between the charge / discharge control circuit 100B of the third embodiment and the charge / discharge control circuit 100 of the first embodiment is that the detection result is expressed by the duty cycle of the pulse.

[0083] The charging / discharging control circuit 100B includes a transmitting circuit 130B that generates a waveform with a duty cycle corresponding to the detection result and supplies it to other circuits. The transmitting circuit 130B is implemented, for example, by pulse width modulation (PWM) or pulse frequency modulation (PFM).

[0084] The receiving circuit 140B included in the charge / discharge control circuit 100B includes a smoothing circuit 144. The receiving circuit 140B receives a detection result signal from other circuits and supplies it to the smoothing circuit 144. The smoothing circuit 144 converts the supplied voltage waveform to DC by smoothing it. The smoothed voltage becomes a value corresponding to the duty cycle of the waveform before conversion. The receiving circuit 140B determines the detection result contained in the detection result signal based on the smoothed voltage value. By representing the detection result in terms of duty cycle, the impact of noise during transmission and reception can be reduced compared to representing the detection result in terms of voltage value. Therefore, the charge / discharge control circuit 100B can appropriately share control states.

[0085] [Fourth Implementation Method]

[0086] Figure 7 This diagram illustrates a structural example of the charge / discharge control circuit 100C according to the fourth embodiment. The difference between the charge / discharge control circuit 100C of the fourth embodiment and the charge / discharge control circuit 100 of the first embodiment is that the detection result is represented by the pulse width. Furthermore, the difference between the charge / discharge control circuit 100C and the charge / discharge control circuit 100B of the third embodiment is that the supplied detection result signal is not returned to the analog signal.

[0087] The transmitting circuit 130C included in the charge / discharge control circuit 100C generates a waveform with a pulse width corresponding to the detection result and supplies it to other circuits. The transmitting circuit 130C is implemented, for example, by a PFM (Power Flow Meter). The receiving circuit 140C included in the charge / discharge control circuit 100C can also be a pulse width (PW) determination circuit that determines the pulse width of the waveform of the voltage supplied from the transmitting circuit 130C of other circuits. By eliminating the use of a smoothing circuit 144, the time required for smoothing can be reduced, and the detection result signal can be transmitted and received more quickly.

[0088] Furthermore, if the transmitting circuit 130C is a PFM, the receiving circuit 140C may not include the smoothing circuit 144. For example, the receiving circuit 140C may include a bandpass filter passing through a specific frequency band for each abnormal state of the detected object, and determine the detection result based on which bandpass filter the voltage passes through. By adjusting the included frequency band, the presence or absence of detection of various abnormal states can be included in the detection result signal and transmitted and received.

[0089] The charge / discharge control circuits of the first to fourth embodiments described herein can all be implemented using a single terminal. Specifically, the transmission performed by the transmitting circuit 130 and the reception performed by the receiving circuit 140 are performed via the same signal line (the signal line connecting the CNT terminals to each other). The CNT terminals are terminals that are conventionally included in the charge / discharge control circuit 100 for controlling external circuits, etc. By implementing a charge / discharge control circuit 100 that can share the control state without adding terminals from the CNT terminals, the area of ​​the charge / discharge control circuit 100 can be reduced. In addition, since the number of terminals remains unchanged, there is no need to readjust the pattern, which reduces the effort required to install the battery device 10, etc., in the embodiments. Furthermore, when the transmission performed by the transmitting circuit 130 and the reception performed by the receiving circuit 140 are performed via the same signal line, the receiving circuit 140 may malfunction by receiving the detection result signal transmitted by the transmitting circuit 130. Therefore, it is ideal for the receiving circuit 140 not to receive the signal when the transmitting circuit 130 is transmitting. The phrase "not received by receiving circuit 140" can mean cutting off the power supply to receiving circuit 140 during transmission, not outputting the detection result received by receiving circuit 140 to control circuit 120, or not switching control circuit 120 to a control state corresponding to the detection result output from receiving circuit 140. Alternatively, interference can be avoided by pre-scheduling the transmission and reception timings.

[0090] [Fifth Implementation]

[0091] Figure 8 This is a diagram illustrating a structural example of the charge / discharge control circuit 100D according to the fifth embodiment. The difference between the charge / discharge control circuit 100D of the fifth embodiment and the charge / discharge control circuit 100 of the first embodiment is that the transmission of the detection result signal by the transmitting circuit 130 and the reception of the detection result signal by the receiving circuit 140 are performed through different signal lines.

[0092] The charge / discharge control circuit 100D replaces the CNT terminal with a CNT_Send terminal and a CNT_Receive terminal. The CNT_Send terminal is connected to the transmitting circuit 130, and the CNT_Receive terminal is connected to the receiving circuit 140. The transmitting circuit 130 transmits the detection result signal from its own CNT_Send terminal using the signal line of the CNT_Receive terminal connected to other circuits. Similarly, the receiving circuit 140 receives the detection result signal from its own CNT_Receive terminal using the signal line of the CNT_Send terminal connected to other circuits. By using separate, independent signal lines for transmission and reception, interference between the transmitted and received detection result signals can be avoided. Furthermore, since scheduling for interference prevention is not required, the detection result signal can be shared more quickly.

[0093] [Sixth Implementation Method]

[0094] Figure 9 This diagram illustrates a structural example of the charge / discharge control circuit 100E according to the sixth embodiment. The difference between the charge / discharge control circuit 100E of the sixth embodiment and the charge / discharge control circuit 100D of the fifth embodiment is that the sixth embodiment uses binary signals to transmit and receive detection result signals.

[0095] The charge / discharge control circuit 100E includes CNT_Send1 and CNT_Send2 terminals instead of the CNT_Send terminal. Additionally, the charge / discharge control circuit 100E includes CNT_Receive1 and CNT_Receive2 terminals instead of the CNT_Receive terminal. The transmitting circuit 130E included in the charge / discharge control circuit 100E converts the detection result into a binary signal and transmits it to other circuits via the CNT_Send1 and CNT_Send2 terminals. Furthermore, the receiving circuit 140E included in the charge / discharge control circuit 100E receives the binary signal transmitted from other circuits via the CNT_Receive1 and CNT_Receive2 terminals and determines the detection result of the other circuits based on the binary signal. When the detection result is represented by an analog signal, time is spent before the current flows in the signal line and the voltage switches. By using a charge / discharge control circuit 100E that transmits and receives detection result signals using binary signals (digital signals), the detection result signal can be shared more quickly. Furthermore, compared to using analog signals for transmission and reception, the detection result signals can be appropriately shared due to its stronger noise immunity. Moreover, the number of terminals included in the charge / discharge control circuit 100E is only one example, as long as it corresponds to the number of types of abnormal states of the detected object. For example, the charge / discharge control circuit 100E can transmit or receive via a 1-bit (1-terminal) serial signal, or via a multi-bit (multi-terminal) parallel signal. Furthermore, by setting the number of terminals used in transmission or reception to a number corresponding to the number of types of abnormal states, or half of that number, all detection results can be shared at once.

[0096] [Seventh Implementation Method]

[0097] Figure 10 This is a diagram illustrating the structure of the charge / discharge control circuit 100F according to the seventh embodiment. The difference between the charge / discharge control circuit 100F of the seventh embodiment and the charge / discharge control circuit 100 of the first embodiment is that the detection result signal is transmitted and received using the I2C (Inter-Integrated Circuit) communication standard.

[0098] The charge / discharge control circuit 100F does not include the transmitting circuit 130 and the receiving circuit 140. Furthermore, the charge / discharge control circuit 100F includes an SCL terminal and an SDA terminal instead of the CNT_Send terminal and the CNT_Receive terminal. The control circuit 120 is connected to the SCL terminal and the SDA terminal. The SCL terminal is connected to the signal line providing the clock signal. The SDA terminal is connected to the signal line for transmitting and receiving detection result signals. In the I2C communication standard, since the host controls the communication timing, interference between the transmission and reception of detection result signals in the charge / discharge control circuits 100F can be avoided. Based on the charge / discharge control circuit 100F using the I2C communication standard, interference can be easily avoided, thus a battery system 1 including three or more charge / discharge control circuits 100F can be easily implemented even without constructing a complex system. Furthermore, in Figure 10 The diagram shows an example where the charge / discharge control circuit 100F is installed externally, with the slave device (equivalent to the master device) mounted outside the charge / discharge control circuit 100F. This embodiment is not limited to this example; a circuit operating as a master device may also be installed inside any charge / discharge control circuit 100F or control circuit 120 included in the battery system 1.

[0099] The invention has been described in detail above with reference to the accompanying drawings. However, the specific structure is not limited to the described structure, and various design changes can be made without departing from the spirit of the invention. This embodiment is not limited to these embodiments, and also includes embodiments with various modifications or improvements. That is, the constituent elements described below include constituent elements that can be easily conceived by those skilled in the art, substantially the same constituent elements, and the constituent elements described in the various embodiments and examples can be appropriately combined. In addition, various omissions, substitutions, or changes to constituent elements can be made in this embodiment without departing from the spirit of the invention.

[0100] Furthermore, in the above description, the resistor 103 and the external FET 104 are configured to be located on the low side (the negative side of the battery), but this is not a limitation and they may also be configured to be located on the high side (the positive side of the battery).

Claims

1. A charge / discharge control circuit, comprising a control circuit, The control circuit switches to a control state corresponding to the detection result of the abnormal state, and controls the opening and closing of the charging and discharging paths of one or more secondary batteries of the controlled object according to the control state. It is connected in parallel with the external terminal provided in the charging and discharging path, and transmits and receives detection result signals containing the detection results with other charging and discharging control circuits that control a secondary battery different from this circuit, thereby making the control state of this circuit the same as the control state of other charging and discharging control circuits.

2. The charge / discharge control circuit according to claim 1, wherein, The charge / discharge control circuit further includes: The transmitting circuit transmits the detection result signal to the other charge / discharge control circuits; and The receiving circuit receives a detection result signal from the other charge / discharge control circuits, which includes the detection results from the other charge / discharge control circuits. The transmission performed by the transmitting circuit and the reception performed by the receiving circuit are carried out through the same signal line. The receiving circuit does not receive data when the transmitting circuit transmits data.

3. The charge / discharge control circuit according to claim 2, wherein, The detection result contained in the detection result signal is represented by the voltage ratio of the first voltage to the second voltage.

4. The charge / discharge control circuit according to claim 2, wherein, The transmitting circuit supplies a voltage with a duty cycle corresponding to the detection result. The receiving circuit also includes a smoothing circuit for smoothing the supplied voltage, and the detection result is determined based on the smoothed voltage value.

5. The charge / discharge control circuit according to claim 2, wherein, The transmitting circuit supplies a voltage with a pulse width corresponding to the detection result. The receiving circuit determines the detection result based on the pulse width of the supplied voltage.

6. The charge / discharge control circuit according to claim 1, wherein, The charge / discharge control circuit further includes: The transmitting circuit transmits the detection result signal to the other charge / discharge control circuits; and The receiving circuit receives a detection result signal from the other charge / discharge control circuits, which includes the detection results from the other charge / discharge control circuits. The transmission performed by the transmitting circuit and the reception performed by the receiving circuit are carried out through different signal lines.

7. The charge / discharge control circuit according to claim 6, wherein, The transmitting circuit converts the detection result into a binary signal and transmits it. The receiving circuit determines the detection result based on the received binary signal.

8. The charge / discharge control circuit according to claim 1, wherein, The I2C communication standard is used in the transmission and reception of the detection result signal.

9. A charge / discharge control device, comprising: The charge / discharge control circuit as described in any one of claims 1 to 8; A charging control transistor includes a gate connected to a charging control terminal of the control circuit and is disposed in the charging / discharging path; as well as A discharge control transistor includes a gate connected to a discharge control terminal of the control circuit and is disposed in the charge / discharge path.

10. A battery device, comprising: The charge / discharge control device as described in claim 9; as well as The secondary battery.

11. A battery system, wherein, The external terminals include a plurality of charge / discharge control circuits as described in any one of claims 1 to 8.

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