Wide-range adjustable AC test power supply based on input parallel and output cascade

Abstract

The application discloses a wide-range adjustable AC test power supply based on input parallel and output cascade, relates to the technical field of power electronic conversion, and comprises an input parallel rectifying unit, a common DC bus, a plurality of isolation conversion modules and a plurality of cascaded output inverter modules. Each output inverter module is cascaded and superposed to provide a test voltage to a capacitive test object, and each is provided with a local controller and a current sampling unit. Each local controller determines the breakdown of the test object and enters a bypass voltage reduction when the common current collected by the module meets preset surge conditions. The plurality of output inverter modules are bypassed one by one in a preset staggered sequence, only one module is switched at any moment, and the output port voltage falls to a preset protection voltage at a controlled slope. The application solves the problem that the power supply continuously feeds energy to an arc when the capacitive test object breaks down, and the central unified lock is not synchronized with the actions of each module due to communication time delay.

Description

Technical Field

[0001] This application relates to the field of power electronic conversion technology, and in particular to a wide-range adjustable AC test power supply based on input parallel connection and output cascade. Background Technology

[0002] AC test power supplies are used to apply AC voltages of specified waveforms and amplitudes to high-voltage equipment such as cables, bushings, insulators, capacitors, and gas-insulated switchgear to assess their insulation withstand capability. These test objects are mostly electrically capacitive, requiring continuous adjustment over a wide voltage range during testing, with a smooth voltage rise and low harmonic content. Understanding this application relies on two points: first, the current flowing through a capacitive test object is related to the time rate of change of its terminal voltage; a steep voltage jump will induce a steep charging current; second, once gas is broken down by an electric arc, the gas within the arc is in a state of thermal ionization, requiring a recovery time to dissipate ionization and rebuild insulation strength. A converter power supply based on parallel input and cascaded output provides a pathway for wide-range voltage regulation: low-voltage AC is rectified in parallel on the input side to form a common DC bus, then converted by multiple isolated converter modules and sent to each output inverter module. The outputs of each output inverter module are series-superimposed to obtain a high-voltage adjustable AC test voltage. CN112421966A discloses a conversion device that uses cascaded power conversion units and isolated DC-DC modules to achieve power conversion and electrical isolation. CN105490552A discloses a conversion device in which high-voltage AC is rectified by a converter to form a high-voltage DC bus, and then converted into low-voltage AC output by the final stage after isolated DC-DC conversion. Both of these conversion devices are used for power distribution and energy conversion with high-voltage AC input and low-voltage output. The AC test power supply to which this application belongs applies this type of structure in reverse, using low-voltage AC input, which is isolated and converted and then cascaded with the output to obtain a high-voltage adjustable AC output.

[0003] In this type of power supply, breakdown or flashover of the test object is an inherent part of the test process. Once the insulation breaks down, the output port changes from high resistance to near short circuit in a very short time, and the current in the series circuit rises sharply. To address this condition, existing technologies typically insert a current-limiting reactor or current-limiting resistor in series in the output circuit, and use a mechanical circuit breaker or vacuum switch to cut off the power supply; other solutions involve a central controller detecting an output overcurrent and uniformly commanding each output inverter module to be blocked or bypassed. CN107147305A discloses a submodule bypass circuit, in which an internal bypass switch automatically closes when a fault occurs within the submodule, bypassing the faulty submodule to avoid affecting the normal operation of the remaining cascaded submodules.

[0004] The aforementioned solutions present unavoidable difficulties in the testing scenarios of capacitive test objects. The action time of mechanical switches and current-limiting components is on the order of milliseconds. Before their action is complete, the power supply continues to feed energy into the arc. The test object, in addition to its own stored energy, bears this continuously fed energy, thus amplifying what could have been self-extinguishing or only requiring repair into irreversible damage, making retesting difficult. While a unified blocking method by a central controller is faster than mechanical switches, the command must be sent to each output inverter module via a communication link. Communication delays cause the modules to act at different times. After the module that is blocked first exits the series connection, the modules that are not blocked instantaneously bear the entire drop-off voltage, resulting in overvoltage. Even if all modules act sufficiently uniformly, simultaneous exit causes a sudden collapse in output voltage, creating a large reverse voltage change rate on the test object. Although the aforementioned sub-module self-triggered bypass does not rely on central communication, it targets internal faults within the sub-module itself, aiming to maintain the normal operation of other modules, rather than addressing the coordinated and controlled reduction of the overall output voltage by multiple modules under external breakdown conditions of the test object. Furthermore, after the flashover arc is extinguished, the gas inside the arc channel is still in a state of ionization due to heat. If the voltage is immediately restored to the original setting, the arc channel, which has not yet recovered its insulation strength, will break down again in the original position, forcing the test to be interrupted and repeatedly triggering the protection.

[0005] These approaches collectively overlook the following technical problem: the breakdown event itself, with its fault current being equal and simultaneously surging along the cascaded series circuit of the output, is a natural event that can be observed simultaneously by all modules without any timing or communication. However, existing processes treat it merely as an anomaly requiring rapid disconnection, rather than utilizing it as a time reference for coordinated action by all modules. For example, a test power supply consisting of dozens of output inverter modules connected in series experiences a flashover while pressurizing a section of cable: with a unified blocking approach, communication delays cause individual modules to lag behind in exiting the circuit and bear the entire drop-off voltage alone; with current limiting and mechanical switching, the millisecond-level disconnection time allows the arc to absorb a continuous influx of energy far exceeding the energy stored in the test object itself. Both approaches treat a simultaneous event that could have been utilized collaboratively as a mere anomaly requiring suppression.

[0006] Therefore, how to utilize the inherent simultaneity of breakdown fault current to achieve communication-free coordination and controlled voltage reduction of each output inverter module without adding communication and timing hardware, and to smoothly continue the test after the arc is restored, has become an unsolved problem for this type of wide-range adjustable AC test power supply. Summary of the Invention

[0007] The technical problem to be solved by this application is to provide a wide-range adjustable AC test power supply based on parallel input and cascaded output, which utilizes the natural simultaneity of breakdown fault current to achieve non-communication coordination and controlled voltage reduction of each output inverter module without adding communication and timing hardware, and smoothly resumes the test after the arc is restored.

[0008] To achieve the above objectives, this application adopts the following technical solution: A wide-range adjustable AC test power supply based on parallel input and cascaded output includes a parallel input rectifier unit, a common DC bus, multiple isolated conversion modules, multiple cascaded output inverter modules, and a main controller. The input parallel rectifier unit rectifies the low-voltage AC input into the bus voltage of the common DC bus. Each of the isolation conversion modules is connected between the common DC bus and the corresponding output inverter module through a high-frequency isolation link. After multiple output inverter modules are cascaded and superimposed, they provide AC test voltage to the capacitive test object through the output port. Each of the output inverter modules is also provided with a local controller and a current sampling unit, and each of the current sampling units collects the common current flowing through the series circuit of multiple output inverter modules; Each of the local controllers is configured to: based on the common current collected by the current sampling unit of the output inverter module, when the common current meets a preset surge condition, determine that the output inverter module is in the test item breakdown condition and enter the bypass step-down process. During the bypass step-down process, multiple output inverter modules are bypassed one by one from the cascaded stack according to a preset staggered sequence, so that the voltage at the output port drops back to the preset protection voltage with a controlled slope. The staggered sequence ensures that only one output inverter module is bypassed at any given time.

[0009] Optionally, each output inverter module includes an H-bridge circuit and a bypass branch. The DC side of the H-bridge circuit is the DC link of the module, and the AC side is connected in series with the series circuit. The bypass step-down process includes: the local controller turns on the bypass branch of the output inverter module, making the AC output voltage of the output inverter module zero and removing it from the cascaded superposition, while the corresponding isolation converter module maintains the voltage of the DC link of the module.

[0010] Optionally, each local controller determines the bypass time slot of the output inverter module in the staggered sequence based on the fixed sequence number of the output inverter module in the cascaded stack, and the interval between two adjacent bypass time slots is a preset staggered interval; the controlled slope is determined by the ratio of the voltage drop at the output port when a single output inverter module is bypassed to the staggered interval.

[0011] Optionally, the preset surge condition includes the rise rate of the common current exceeding a preset rise rate threshold, or the amplitude of the common current exceeding a preset amplitude threshold; each current sampling unit collects the common current and calculates the rise rate of the common current, so that the corresponding local controller can determine whether the preset surge condition is met.

[0012] Optionally, after the voltage at the output port of each local controller drops back to the preset protection voltage, the local controller keeps the output inverter module in a bypass state for a preset protection holding time. During the preset protection holding time, each current sampling unit continues to collect the common current, and the main controller determines that the breakdown arc of the test object has been extinguished when the common current drops below the preset arc extinguishing current.

[0013] Optionally, the main controller has a built-in controlled slope template library. The controlled slope template library is indexed by the test voltage before breakdown, and each template contains a controlled slope level corresponding to the test voltage. The controlled slope template library is constructed as follows: during the calibration test, the energy fed into the breakdown arc by the output inverter module during the bypass step-down process is recorded for different controlled slope levels. The minimum controlled slope level that ensures the fed energy does not exceed the preset upper limit of fed energy is associated with the corresponding test voltage and stored in the controlled slope template library. The main controller retrieves the controlled slope level from the controlled slope template library according to the test voltage before breakdown and sets the time-off interval based on the controlled slope level.

[0014] Optionally, the main controller is configured to, during normal operation when the bypass step-down process does not occur, set the voltage of the DC link of the multiple output inverter modules to unequal graded voltages through each of the isolation conversion modules, and arrange the switching time of each output inverter module with the zero-crossing point of the common current as the phase reference; the level jump occurring within the voltage zero-crossing interval of the output port is handled by the output inverter module with the smaller value among the graded voltages, and the level jump occurring within the voltage peak interval of the output port is handled by the output inverter module with the larger value among the graded voltages.

[0015] Optionally, the main controller has a built-in step size template library. The step size template library is indexed by the target output voltage amplitude. Each template contains the step voltage of each output inverter module corresponding to the target output voltage amplitude and the switching phase sequence of each output inverter module. The step size template library is constructed as follows: for each target output voltage amplitude, a set of step voltages is selected such that the step size of the level transition occurring within the voltage zero-crossing interval does not exceed a preset step size upper limit. The selected step voltages and the corresponding switching phase sequence are associated with the target output voltage amplitude and stored in the step size template library. The main controller retrieves the step voltage and the switching phase sequence from the step size template library according to the current target output voltage amplitude.

[0016] Optionally, after determining that the breakdown arc has been extinguished and before re-pressurizing the capacitive test sample, the main controller collects the residual voltage at the output port, controls multiple output inverter modules to start the voltage at the output port from a voltage equal to the residual voltage, and then, after the preset arc recovery holding time ends, restores the voltage at the output port to the test operating point before breakdown with a controlled rising slope. The test operating point includes the test voltage, phase, and frequency before breakdown.

[0017] Optionally, the main controller has a built-in arc recovery template library. The arc recovery template library is indexed by the test voltage and frequency before breakdown. Each template contains the arc recovery holding time corresponding to the test voltage and frequency. The arc recovery template library is constructed as follows: in the calibration test, for different combinations of test voltage and frequency before breakdown, the shortest holding time that prevents the breakdown arc from reigniting in the original arc when the voltage is reapplied is recorded. The shortest holding time is associated with the corresponding combination of test voltage and frequency and stored in the arc recovery template library. The main controller retrieves the arc recovery holding time from the arc recovery template library according to the test voltage and frequency before breakdown.

[0018] The beneficial effects of this application are as follows: This application limits the additional energy continuously fed into the power supply during a capacitive test object's own breakdown to a set upper limit. This is achieved because each output inverter module has a current sampling unit that collects the common current of the series circuit. This common current is equal everywhere in the series circuit and surges simultaneously during breakdown. Each local controller determines the breakdown and initiates bypass voltage reduction based on this information, without waiting for a central command. The start-up time is determined by the fault current itself, thus eliminating communication delay. Therefore, the interval from the occurrence of breakdown to the cessation of the current driving the arc is compressed to the level of the switching device's action, limiting the continuous feed into the arc and maintaining the flashover at a self-extinguishing and retestable level. For example, for a cable experiencing a flashover, the power supply completes the voltage reduction within a few switching cycles, and the test object absorbs almost no more energy from the power supply side besides its own stored energy.

[0019] Regarding the voltage reduction method, this application does not allow all modules to exit simultaneously. Instead, it arranges them in a staggered sequence according to their fixed serial numbers, with only one output inverter module bypassing at any given time. This arrangement serves two purposes: simultaneous exit would cause the output voltage to collapse abruptly, resulting in a large reverse voltage change rate on the test object; sequential exit, on the other hand, divides the total voltage drop into several equally spaced small steps, allowing the output voltage to decrease smoothly with a controlled slope. Simultaneously, since only one module changes state at any given moment, the remaining modules continue to share the loop voltage as before, preventing any individual module from lagging behind and bearing the entire voltage drop alone. The staggered interval and the voltage drop amount at each step jointly determine the controlled slope. This controlled slope is then matched with the upper limit of the input energy by a controlled slope template library, ensuring that the voltage reduction is both fast enough and without overshoot.

[0020] This application also reduces the rate of voltage change applied to the test object during normal wide-range voltage application, decreasing false breakdowns that should not occur during the voltage application phase. This is because the current of a capacitive test object leads its voltage by approximately one-quarter of a cycle, with the current peak falling near the zero-crossing of the output voltage. The dense level jumps of conventional equal-step cascaded circuits also concentrate at this point, and the current spike injected by the hard switch is largest when the load current is at its maximum. This application uses an isolation converter module to set unequal, graded DC-link voltages for each module. The output inverter module with the smaller value handles the small-step level during the zero-crossing voltage range, while the output inverter module with the larger value handles the large-step level during the voltage peak range. The switching timing is arranged with the common current zero-crossing point as the phase reference, thus ensuring that only the smallest step level jump occurs at the point of maximum load current. In this way, the current spikes and voltage change rate during the voltage application process are suppressed below the set upper limit, correspondingly reducing the possibility of false protection triggering due to occasional steep voltage changes.

[0021] After the breakdown treatment, this application enables the test to continue smoothly rather than restarting from zero. Capacitive test samples retain residual charge after the arc is extinguished, and this charge cannot change abruptly. If the original voltage is applied directly again, the difference between the residual charge and the reconstruction voltage will create an inrush current, and the arc, whose insulation strength has not yet recovered, will reignite in situ. Therefore, this application, during repressurization, first aligns the output voltage with the acquired residual voltage, starting from an equal voltage. Then, after the arc recovery holding time, determined by the test voltage and frequency before breakdown, is completed, the test returns to the pre-breakdown test operating point with a controlled upward slope. The arc recovery holding time is set because after the arc is extinguished, the gas inside the arc needs time to dissipate ionization before the insulation strength can be rebuilt; without applying pressure during the recovery period, reignition will not occur. Thus, there is no inrush current during the connection, the arc has recovery time without reignition, and the amplitude, phase, and frequency of the test are maintained.

[0022] Overall, the above design revolves around the same series common current: during normal voltage application, it serves as the phase reference for arranging low-impact switching, and during breakdown, it acts as the triggering basis for the lack of communication and coordination among modules; combined with staggered controlled voltage reduction and residual charge recovery, this type of test power supply protects both the test object and itself when capacitive test objects frequently break down, while maintaining the continuity and reproducibility of the test. Attached Figure Description

[0023] Figure 1 A schematic diagram of the system structure of a wide-range adjustable AC test power supply based on parallel input and cascaded output provided for embodiments of this application; Figure 2 A schematic diagram of the circuit principle of a wide-range adjustable AC test power supply based on parallel input and cascaded output provided for embodiments of this application; Figure 3 This is a schematic diagram of the structure of a single output inverter module provided in an embodiment of this application; Figure 4 A timing diagram illustrating the staggered bypass voltage reduction of multiple output inverter modules when the test sample breaks down, as provided in an embodiment of this application. Figure 5 A schematic diagram of the output waveform of a wide-range voltage gradient applied according to an embodiment of this application; Figure 6 A timing diagram illustrating the connection of residual charge and controlled repressurization after the breakdown arc is extinguished, as provided in an embodiment of this application. Figure 7 This is a flowchart illustrating the output inverter module breakdown protection control method provided in an embodiment of this application.

[0024] In the diagram: 10 - Input parallel rectifier unit; 20 - Common DC bus; 30 - Isolation converter module; 31 - High-frequency transformer; 40 - Output inverter module; 41 - H-bridge circuit; 42 - Bypass branch; 43 - Local controller; 44 - Current sampling unit; 45 - Module DC link; 50 - Main controller; 60 - Output port; 61 - Common current; 62 - Output port voltage; 63 - Preset protection voltage; 64 - Preset amplitude threshold; 65 - Preset arc extinction current; 66 - Residual voltage; 67 - Test voltage before breakdown; 70 - Capacitive test object. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The AC test power supply provided in this application embodiment is used to apply an AC voltage of specified waveform and amplitude to high-voltage equipment such as cables, bushings, insulators, and gas-insulated switchgear to assess their insulation withstand capability. These devices are mostly electricalally capacitive, requiring continuous adjustment over a wide voltage range during testing, and demanding a smooth voltage rise and low harmonic content. In such tests, breakdown or flashover of the capacitive test specimen 70 is an inherent part of the test process; once the capacitive test specimen 70 breaks down, the output terminal changes from high resistance to near short circuit in a very short time, and the series circuit current rises sharply. Understanding the following requires two foundations: first, the current flowing through the capacitive test specimen 70 is related to the rate of change of its terminal voltage over time; a steep voltage jump will induce a steep charging current; second, once the gas is broken down by an electric arc, the gas within the arc is in a heated ionized state, requiring a period of time to dissipate the ionization and rebuild insulation strength.

[0027] like Figure 1 As shown, the wide-range adjustable AC test power supply based on parallel input and cascaded output provided in this application includes an input parallel rectifier unit 10, a common DC bus 20, multiple isolated conversion modules 30, and multiple cascaded output inverter modules 40. The power supply also includes a main controller 50, the structure and connection relationship of which will be discussed later. Figure 3As shown. The input parallel rectifier unit 10 rectifies the low-voltage AC input to the bus voltage of the common DC bus 20; each isolation converter module 30 is connected between the common DC bus 20 and the corresponding output inverter module 40 through the high-frequency isolation link formed by its internal high-frequency transformer 31; the AC sides of multiple output inverter modules 40 are connected in series, cascaded and superimposed, and then provide AC test voltage to the capacitive test specimen 70 through the output port 60. Figure 1 In this circuit, the low-voltage AC input enters the input parallel rectifier unit 10 from terminals a, b, and c. The bus voltage is then led out in parallel to each branch along the common DC bus 20. Each branch consists of a DC-to-AC converter, a high-frequency transformer 31, and an AC-to-DC converter, which together form an isolation converter module 30. Following the isolation converter module 30 is an output inverter module 40. The outputs of all output inverter modules 40 are superimposed to obtain a high-voltage adjustable AC test voltage. This structure, which uses a low-voltage AC input, undergoes isolation conversion, and cascades the outputs to obtain a high-voltage adjustable AC output, provides a pathway for wide-range voltage regulation. The connection relationships at the architectural level are part of the embodiments of this application, and specific innovative features are described later. Figures 3 to 7 Expand.

[0028] It should be noted that, in this embodiment, the low-voltage AC input connected to the parallel rectifier unit 10 is power frequency AC, and its voltage level belongs to the low-voltage category, that is, the effective value of the AC line voltage is not higher than 1000 volts, and its standard voltage value conforms to the provisions of GB / T 156 "Standard Voltage", for example, three-phase 380 volts or single-phase 220 volts; the output port 60 provides a high-voltage adjustable AC test voltage to the capacitive test specimen 70, and its voltage level belongs to the high-voltage category specified in GB / T 156 "Standard Voltage". It can be continuously adjusted in the range of several kilovolts to several hundred kilovolts. Its upper limit can reach the test voltage required for test specimens with voltage levels of 10 kV, 35 kV, 110 kV, 220 kV or even higher as specified in the standard. It can also be continuously adjusted downward to a lower voltage as needed for withstand voltage or partial discharge tests, thereby obtaining a wide range of adjustable high-voltage AC test voltage with low-voltage AC input, covering test specimens of different voltage levels such as cables, bushings, insulators and gas-insulated switchgear.

[0029] Figure 2 This is a schematic diagram of the power supply circuit. (For example...) Figure 2As shown, low-voltage AC inputs a, b, and c each enter a bridge arm composed of power switching devices via input inductors, forming an input parallel rectifier unit 10. Its output is a common DC bus 20 with upper and lower buses. Within the isolation converter module 30, the bus voltage is first converted to high-frequency AC by a set of switching devices, then fed into a high-frequency transformer 31, and finally converted to DC by a diode rectifier bridge, establishing a module DC link voltage on the capacitor of the module DC link 45. Following the module DC link 45 is the H-bridge circuit 41 in the output inverter module 40. The AC side of the H-bridge circuit 41 is connected in series with a series loop, and then connected to the capacitive test specimen 70 via the output port 60. (For clarity, please refer to the diagram.) Figure 2 Draw a representative module chain, and then cascade and stack the remaining modules in series with it. The cascading and stacking relationship on the output side is the same.

[0030] In the aforementioned power supply, each output inverter module 40, in addition to the H-bridge circuit 41, is equipped with a local controller 43 and a current sampling unit 44. Each current sampling unit 44 is connected in series in a series loop, collecting the common current 61 flowing through the series loop of multiple output inverter modules 40. Since the AC sides of multiple output inverter modules 40 are connected end-to-end to form the same series loop, this common current 61 is equal at all points in the loop and is the same quantity that can be observed locally by each output inverter module 40. The main controller 50 is connected to each local controller 43, responsible for issuing operating commands such as target test voltage, frequency, and phase, and undertaking global responsibilities such as arc extinction judgment and re-voltage organization during the protection process; while the immediate protection judgment under breakdown conditions is completed by each local controller 43 based on the common current 61 collected by its own module's current sampling unit 44, without relying on the real-time commands of the main controller 50.

[0031] This application also provides a protection and control method for the power supply under breakdown conditions. For example... Figure 7As shown, the method unfolds sequentially from step S1 to step S8, constituting a complete breakdown protection and test connection process. In step S1, the current sampling unit 44 of each output inverter module 40 collects the common current 61 flowing through the series circuit, which serves as the sole input for subsequent determination. In step S2, it is determined whether the common current 61 meets the preset surge condition; if not, it returns to step S1 to continue sampling; if it does, it proceeds to step S3. In step S3, the local controller 43 determines that the output inverter module 40 is in the test item breakdown condition and enters the bypass voltage reduction process. In step S4, multiple output inverter modules 40 bypass one by one from the cascaded stack according to a preset staggered sequence, with only one output inverter module 40 switching bypass at any given time, causing the voltage at the output port 60 to drop back to the preset protection voltage 63 with a controlled slope. In step S5, each output inverter module 40 is kept in the bypass state for a preset protection hold time. In step S6, it is determined whether the common current 61 has dropped below the preset arc-extinguishing current 65; if it has not dropped, the process returns to step S5 to continue holding; if it has dropped, the process proceeds to step S7. In step S7, the residual voltage 66 of the output port 60 is acquired, and the voltage of the output port 60 starts from a voltage equal to the residual voltage. In step S8, after a preset arc recovery holding time, the process returns to the test operating point before breakdown with a controlled rising slope. In the above steps, steps S1 to S6 are completed by the local controllers 43 and the main controller 50 in collaboration to detect breakdown, staggered voltage reduction, and arc extinguishing confirmation. Steps S7 and S8 are organized by the main controller 50 to connect residual charge and apply controlled re-voltage, which will be discussed in detail below. Figures 3 to 6 The mechanisms underlying each step are explained one by one.

[0032] like Figure 3 As shown, a single output inverter module 40 includes a module DC link 45, an H-bridge circuit 41, and a bypass branch 42, as well as a current sampling unit 44 and a local controller 43. The module DC link 45 is powered and its voltage is maintained by the corresponding isolation converter module 30; the DC side of the H-bridge circuit 41 is connected to the module DC link 45, and the AC side is connected in series, then connected to the output port 60 via the current sampling unit 44, and the output port 60 is then connected to the capacitive test sample 70; the bypass branch 42 is connected in parallel with the AC side of the H-bridge circuit 41; the local controller 43 receives the common current 61 collected by the current sampling unit 44 and controls the on / off state of the H-bridge circuit 41 and the bypass branch 42 respectively via control lines; the main controller 50 is connected to the local controller 43 to issue operating commands. The above structure enables each output inverter module 40 to independently complete voltage synthesis of its own module, as well as to independently complete the acquisition of the common current 61 and the bypass operation of its own module.

[0033] During the bypass voltage reduction process, the local controller 43 activates the bypass branch 42 of the output inverter module 40, short-circuiting the AC side of this module and reducing its output voltage to zero, thus removing it from the cascade stack. Simultaneously, the corresponding isolation converter module 30 continues to supply power to the module DC link 45, maintaining its voltage constant. The reason for using the bypass branch 42 to exit the cascade stack instead of blocking the H-bridge circuit 41 and discharging the module DC link 45 is twofold. Firstly, keeping the module DC link 45 energized allows each output inverter module 40 to quickly re-enter the cascade stack after the arc recovers, eliminating the need to re-establish the voltage from the bus side to the module DC link 45, thus shortening the preparation time for re-energizing. Secondly, discharging the module DC link 45 would allow its stored energy to be injected into the still-burning arc via the freewheeling path of the H-bridge circuit 41, increasing the feed into the arc and contradicting the purpose of voltage reduction.

[0034] Each local controller 43 performs a breakdown determination based on the common current 61 collected by the current sampling unit 44 of its output inverter module 40. The determination is based on whether the common current 61 meets a preset surge condition. This preset surge condition includes two criteria, and meeting either one is considered sufficient: one is that the rise rate of the common current 61 exceeds a preset rise rate threshold, and the other is that the amplitude of the common current 61 exceeds a preset amplitude threshold 64. While collecting the common current 61, the current sampling unit 44 calculates the rise rate of the common current 61 based on the difference between adjacent sampling points, providing the corresponding local controller 43 with the information to determine whether the preset surge condition is met. In some embodiments, the preset rise rate threshold can be 3 to 10 times the rise rate of the common current 61 during normal operation, typically 5 times; the preset amplitude threshold 64 can be 1.5 to 5 times the peak value of the rated test current, typically 2 times. When the threshold is set too low, normal ripple is easily misjudged as breakdown and the protection is falsely triggered. When the threshold is set too high, the breakdown detection is delayed. Therefore, a compromise is made between sensitivity and interference immunity according to the above range. The purpose of setting two types of criteria, rise rate and amplitude, is that when the capacitive test object 70 breaks down, the common current 61 has both a steep rise edge and a significant amplitude increase. The two criteria complement each other, and the rise rate criterion can respond quickly before the amplitude accumulates to the threshold.

[0035] The current sampling unit 44 can locally complete the acquisition of the common current 61 and the calculation of its rise rate. In one embodiment, the current sampling unit 44 samples the common current 61 at a fixed sampling period and approximates the rise rate of the common current 61 by dividing the difference between two adjacent sampled values ​​by the sampling period. This sampling period can be from 1 microsecond to 20 microseconds, typically several microseconds. If the sampling period is too large, the estimate of the rise rate will be too sluggish; if it is too small, it will be easily affected by sampling noise. In other embodiments, the current sampling unit 44 can also take a moving average of several adjacent rise rate estimates to suppress noise, and then compare them with a preset rise rate threshold by the local controller 43. The above acquisition and calculation are all completed within this module, and the local controller 43 makes independent decisions based on this, without exchanging the sampling results of the common current 61 with other output inverter modules 40. This is also the basis for the implementation of each output inverter module 40 making its own decisions without relying on lateral communication.

[0036] The detection of the sudden surge in the common current 61 by each local controller 43 is not strictly simultaneous; each has its own detection dispersion. This dispersion arises from the sampling phase difference of each current sampling unit 44, the propagation delay of the comparison decision, and the dispersion of device parameters. In conventional digital sampling and comparison circuits, it is on the order of microseconds, typically between 0.5 and 5 microseconds. In contrast, the timing interval used in the staggered voltage reduction described later is on the order of tens to hundreds of microseconds, typically between 20 and 200 microseconds, and typically between 50 and 100 microseconds in embodiments without communication coordination. When the detection dispersion is on the order of microseconds and the timing interval is typically between 50 and 100 microseconds, the detection dispersion does not exceed a fraction of the timing interval. Therefore, although each local controller 43 starts up very briefly and sequentially, they all fall within the same detection window of the same surge and can be considered to have detected the breakdown at the same instant. Therefore, the time base for each output inverter module 40 to enter the bypass step-down process is consistent, and the subsequent staggered timing sequence arranged according to a fixed number will not be disordered due to the microsecond difference in the start-up time of individual modules, and the staggered timing sequence remains stable. This order of magnitude relationship is the premise for the non-communication coordination of the embodiments of this application: because the common current 61 is equal and increases simultaneously at all points in the series circuit, each module can independently determine its own situation within the same detection window without exchanging information, and the detection dispersion is negligible relative to the staggered timing interval, so the independent determination of each module is equivalent to a synchronous determination.

[0037] Figure 4 The timing diagram shows the staggered bypass step-down of multiple output inverter modules 40 when the capacitive test sample 70 breaks down. For example... Figure 4As shown in the figure, the upper half uses current as the vertical axis and time as the horizontal axis, with the common current 61 represented by a solid line indicating its change over time; the lower half uses voltage as the vertical axis, with the output port voltage 62 represented by a dashed line indicating the voltage at output port 60, the preset protection voltage 63 and the preset amplitude threshold 64 represented by dashed lines, and the preset arc-extinguishing current 65 represented by a dotted line. Before the test object breaks down, the common current 61 exhibits normal ripple, and the output port voltage 62 remains at the test set value. From the moment the test object breaks down, the common current 61 surges and exceeds the preset amplitude threshold 64, and each local controller 43 determines the breakdown based on this and enters the bypass voltage reduction process.

[0038] Multiple output inverter modules 40 do not exit simultaneously, but are bypassed one by one from the cascaded stack according to a preset staggered sequence. Each output inverter module 40 determines its bypass time slot in the staggered sequence based on its fixed sequence number in the cascaded stack. The interval between two adjacent bypass time slots is a preset staggered interval, and only one output inverter module 40 bypasses at any given time. Each time a module is bypassed, the voltage at the output port 60 drops by a single-step voltage drop until it falls back to the preset protection voltage 63. In embodiments where the DC link 45 voltages of all output inverter modules 40 are equal, the single-step voltage drop is equal, and the output port voltage 62 exhibits an equally spaced step drop. The controlled slope is determined by the ratio of the single-step voltage drop at the output port 60 when a single output inverter module 40 is bypassed to the staggered interval. In embodiments where each output inverter module 40 employs unequal graded voltages, the voltage levels undertaken by each output inverter module 40 are not equal, and the single-step voltage drop during bypass is correspondingly unequal. In this case, the controlled slope is defined by the ratio of the maximum single-step voltage drop during a single bypass voltage reduction process to the time-shift interval, ensuring that the time-shift interval satisfies the condition that the reverse voltage change rate of the output port voltage 62 does not exceed a set upper limit even with the maximum single-step voltage drop. In some embodiments, the time-shift interval is typically 50 microseconds to 100 microseconds within the aforementioned range, and the controlled slope is typically 2% to 10% of the rated peak value of the output port voltage 62 dropped per time-shift interval. The single-step voltage drop depends on the voltage level undertaken by the module and is typically between 2% and 10% of the rated peak value of the output port voltage 62. The preset protection voltage 63 can be 5% to 20% of the test voltage before breakdown, typically 10%; a voltage that is too high will result in insufficient suppression of arc feeding, while a voltage that is too low will result in a large voltage span before re-energization.

[0039] The bypass time slot of each output inverter module 40 in the staggered timing sequence is uniquely determined by its fixed sequence number, rather than being negotiated temporarily when a breakdown occurs. The reason for using pre-agreed fixed sequence numbers is that breakdown is a sudden event. If the modules were to negotiate their exit from the sequence after a breakdown, it would inevitably introduce information exchange and waiting, contradicting the premise of no communication coordination. The fixed sequence numbers are written into each local controller 43 during the device commissioning phase. After detecting a breakdown, each module can calculate its own bypass time slot without exchanging information. At any given time, only one output inverter module 40 falls into its time slot and performs a bypass switch. Therefore, the staggered timing sequence is both deterministic and requires no real-time communication. The actions of each module are naturally staggered under the same time base, without overlap or omission.

[0040] Conventional breakdown fault handling aims to simultaneously shut down all output inverter modules 40 as quickly as possible for the fastest possible disconnection. This application's embodiment bypasses only one output inverter module 40 at any given time, with fixed sequence numbers and staggered timing. The motivation for this is twofold. First, the current on the capacitive test object 70 is related to the time-varying rate of change of its terminal voltage. If all modules exit simultaneously, the output port voltage 62 will collapse in one step, creating a large reverse voltage change rate on the capacitive test object 70, which in turn induces a steep reverse charging current and impacts the test object. Staggered bypassing divides a large jump into several equally spaced small steps, allowing the output port voltage 62 to decrease smoothly with a controlled slope, limiting the reverse voltage change rate within a set range. Second, if the modules, which should operate simultaneously, are not synchronized due to component dispersion, the modules that exit first will be de-series stacked, and the modules that have not yet exited will momentarily share a portion of the fallback voltage. In extreme cases, individual modules that exit later may bear the entire fallback voltage that should be shared by multiple modules, resulting in overvoltage. The staggered sequence ensures that only one module changes state at any given time, while the remaining modules continue to share the circuit voltage in their original states. This fundamentally avoids the situation where individual modules are delayed in exiting the circuit and bear the entire drop voltage alone.

[0041] From a quantitative perspective, if there are a certain number of output inverter modules 40 participating in the voltage reduction in the cascaded superposition, then the number of steps is correspondingly similar, generally ranging from 8 to 40. In embodiments where the voltage levels of each module are equal, the total voltage span is evenly distributed across each step, and the voltage drop per step is the quotient of the total span and the number of steps. The reverse voltage change rate on the output port voltage 62 is equal to the ratio of the voltage drop per step to the time-off interval. Therefore, given a given total span, the more steps and the larger the time-off interval, the smaller the reverse voltage change rate. The withstand voltage margin of each module determines the upper limit of the voltage drop per step: to ensure that any module does not experience overvoltage even in the worst-case scenario where other modules lag behind, the voltage drop per step should have a withstand voltage margin, which is typically a margin corresponding to 1.2 to 2 times the rated withstand voltage of the module. For example, when the number of steps is 20, the time interval is 50 microseconds, and the voltage drop of a single step is 5% of the rated peak value, the reverse voltage change rate on the output port voltage 62 is correspondingly reduced to one-tenth of the rate when all modules exit simultaneously.

[0042] It should be noted that the energy limited in this application embodiment has a clear boundary. The time-controlled buck converter clamps the energy continuously fed into the breakdown arc through each output inverter module 40 on the converter side; from the occurrence of breakdown to the completion of bypassing of each module and the voltage of the output port 60 falling back to the preset protection voltage 63, this continuously fed energy is compressed to a very small extent. The energy stored in the capacitive test object 70 before breakdown is approximately proportional to the product of its equivalent capacitance and the square of the voltage before breakdown, and will still be released through the arc at the moment of breakdown. This part of the energy is not within the clamping range of this application embodiment. The purpose of this application embodiment is to enable the capacitive test object 70 to absorb energy fed into the power supply side only briefly during the switching stage time from the breakdown to the completion of bypassing of each output inverter module 40, in addition to the release of its own stored energy; this part of transient fed energy is limited to a set preset upper limit of fed energy, which is equivalent to or lower than the energy stored in the test object itself, so that the flashover can be maintained at a level that is self-extinguishing and the test object is retestable.

[0043] Reference Figure 4After the voltage at the output port 60 of each output inverter module 40 drops to the preset protection voltage 63, the module remains in bypass mode for a preset protection holding time. During the preset protection holding time, each current sampling unit 44 continues to sample the common current 61. The main controller 50 determines whether the breakdown arc has been extinguished based on whether the common current 61 drops below the preset arc extinguishing current 65. When the common current 61 is lower than the preset arc extinguishing current 65 for several consecutive sampling periods, the main controller 50 determines that the breakdown arc of the test object has been extinguished. In some embodiments, the preset protection holding time can be from 1 millisecond to 50 milliseconds, typically 10 milliseconds. If it is too short, the arc path will not be sufficiently deionized; if it is too long, the test cycle will decrease. The preset arc extinguishing current 65 can be from 1% to 10% of the rated test current, typically 5%. The basis for using the common current 61 dropping below the preset arc-extinguishing current 65 as the arc-extinguishing criterion is that once the arc is extinguished, the arc path changes from conductive to high resistance, and the current in the series circuit drops to a very small value. The value of the common current 61 can directly reflect the on / off state of the arc, without the need for an additional arc sensor.

[0044] In some embodiments, this application implements degradation processing for abnormal acquisition and judgment situations. If the current sampling unit 44 of a certain output inverter module 40 has no effective output for multiple consecutive sampling cycles, the local controller 43 determines that the acquisition of this module has failed and directly puts this module into bypass state. The remaining output inverter modules 40 then complete the voltage reduction in a staggered order, so that the protection capability is not lost even when individual acquisition channels are abnormal. If the common current 61 does not drop below the preset arc extinguishing current 65 within the preset protection holding time, the main controller 50 determines that the arc has not been extinguished, extends the holding time, and keeps each output inverter module 40 in bypass state until the common current 61 drops below the preset arc extinguishing current 65 before re-energizing, avoiding premature voltage boosting before the arc is extinguished. The above degradation processing ensures that the protection function is not interrupted under abnormal conditions, and only loses test cycle time in individual cases.

[0045] In some embodiments, the main controller 50 has a built-in controlled slope template library, which is used to quickly provide the value of the controlled slope based on the test voltage 67 before breakdown. The controlled slope template library is indexed by the test voltage 67 before breakdown, and each template contains the controlled slope level corresponding to the test voltage. The controlled slope template library is constructed through calibration tests: using different test voltages 67 before breakdown as index features, a simulated breakdown voltage reduction is performed at each test voltage with different controlled slope levels, and the energy fed into the breakdown arc by each output inverter module 40 during the bypass voltage reduction process at that level is recorded, thereby obtaining a set of samples; for each test voltage, the minimum controlled slope level that ensures the fed-in energy does not exceed the preset upper limit of fed-in energy is taken as the tag value corresponding to the test voltage, and stored in the controlled slope template library after being associated with the test voltage. The preset upper limit of the feed energy can be set to 0.1 to 1 times the energy stored in the capacitive test sample 70, or 0.5 to 50 joules in absolute terms, typically 0.5 times the energy stored in the test sample itself. If the preset upper limit of the feed energy is set too high, the energy suppression of the arc will be insufficient; if it is set too low, the controlled slope will be forced to be smaller, and the voltage drop will be slower. The purpose of setting the minimum acceptable level is that the smaller the controlled slope, the slower the voltage drop and the more feed into the arc; the larger the slope, the higher the reverse voltage change rate. Setting the minimum acceptable level of the energy limit can slow down the voltage drop as much as possible under the premise of energy constraints. The calibrated indexes cover a wide frequency range from power frequency to ultra-low frequency (0.1 Hz to power frequency) and the corresponding wide voltage range. The test voltage range between adjacent index points is obtained by linear interpolation. When equipment aging or changes in the type of test sample cause the measured input energy to deviate from the existing sample, the corresponding index points are recalibrated to update the controlled slope template library. In the cold start phase when there are no calibrated samples, the controlled slope template library outputs a conservative, smaller controlled slope range as the default value. The main controller 50 retrieves the controlled slope range from the controlled slope template library based on the test voltage 67 before breakdown and sets the time interval according to the controlled slope range.

[0046] During the normal operation phase without bypass voltage reduction, the embodiments of this application employ unequal graded voltages to achieve a wide range of voltage application, thereby reducing the rate of voltage change applied to the capacitive test sample 70 during the voltage application phase. Figure 5 The output waveform of output port 60 during this normal operation phase is shown. For example... Figure 5As shown, the horizontal axis represents time, and the vertical axis represents amplitude. The output port voltage 62 exhibits a stepped approximation sine wave. The common current 61 is superimposed on the same coordinate to indicate the phase relationship. The voltage peak range and voltage zero-crossing range are marked in the figure. The current of the capacitive test object 70 leads its terminal voltage by about a quarter cycle. The peak value of the common current 61 falls precisely near the zero-crossing of the output port voltage 62. The dense level jumps of conventional equal-step cascaded circuits are also concentrated near the zero-crossing. The current spike injected by the hard switch at the point of maximum load current is the largest. To reduce the voltage change rate and current spike during the voltage application phase, the main controller 50 sets the module DC link 45 voltages of multiple output inverter modules 40 to unequal graded voltages through each isolation conversion module 30, and arranges the switching time of each output inverter module 40 using the zero-crossing point of the common current 61 as the phase reference. Level transitions occurring within the voltage zero-crossing range are handled by the output inverter module 40 with the smaller value among the graded voltages, taking the smallest step size; level transitions occurring within the voltage peak range are handled by the output inverter module 40 with the larger value among the graded voltages, taking the larger step size. In some embodiments, the ratio of the graded voltages of two adjacent output inverter modules 40 can be between 1.2 and 3, typically 2; a larger ratio of graded voltages results in a coarser step size in the zero-crossing range, while a smaller ratio results in fewer voltage regulation ranges. Thus, only level transitions with the smallest step size occur in the zero-crossing range where the load current is the largest, and the current spikes and voltage change rates during the voltage application process are suppressed below the set upper limit, thereby reducing the likelihood of false protection triggering due to occasional steep voltage changes.

[0047] In some embodiments, the main controller 50 has a built-in step size template library, which is used to quickly provide the step voltage and switching phase sequence of each output inverter module 40 based on the target output voltage amplitude. The step size template library is indexed by the target output voltage amplitude, and each template contains the step voltage of each output inverter module 40 corresponding to the target output voltage amplitude and the switching phase sequence of each output inverter module 40. The step size template library is constructed as follows: using the target output voltage amplitude as the index feature, several sets of candidate step voltages and switching phase sequences are scanned for each target output voltage amplitude, and the level transition step amplitude occurring in each set within the voltage zero-crossing interval is calculated to obtain a set of samples; the set of step voltages and their switching phase sequence that ensure that the level transition step amplitude in the zero-crossing interval does not exceed the preset step size upper limit are taken as the label of the target output voltage amplitude, associated and stored in the step size template library. The preset step size upper limit can be set to 1% to 5% of the rated peak value of the output port voltage 62, typically 2%. If the preset step size upper limit is set too high, the current spike suppression in the zero-crossing interval will be insufficient; if it is set too low, the number of modules required to achieve the same target amplitude will be too large. The calibration index covers a wide target voltage amplitude range from ultra-low frequency 0.1 Hz to power frequency. Adjacent amplitude indices are selected from the nearest index and supplemented by linear interpolation to obtain a classification scheme. When the number of modules or device parameters change, the step size classification template library is rescanned to update it. In the cold start phase when there are no calibration samples, the step size classification template library reverts to the default classification scheme of equal step size. The main controller 50 retrieves the classification voltage and switching phase sequence from the step size classification template library according to the current target output voltage amplitude.

[0048] Figure 6 The timing of residual charge contact and controlled re-pressurization after the breakdown arc is extinguished is shown. For example... Figure 6As shown, the horizontal axis represents time, and the vertical axis represents voltage. The output port voltage 62 starts from the residual voltage 66. The residual voltage 66 and the test voltage 67 before breakdown are both indicated by dashed lines. After the main controller 50 determines that the breakdown arc has been extinguished and before re-pressurizing the capacitive test object 70, the main controller 50 measures the voltage of the output port 60 through a voltage sampling branch located at the output port 60, such as a high-voltage divider and a subsequent sampling circuit, and obtains the residual voltage 66 accordingly. Then, it controls multiple output inverter modules 40 to make the voltage of the output port 60 start from a voltage equal to the residual voltage. The reason for starting from a voltage equal to the residual voltage 66 is that the capacitive test object 70 still retains residual charge after the arc is extinguished, and the charge cannot change abruptly. If the original voltage is directly re-pressurized, the difference between the residual charge and the reconstruction voltage will form an inrush current, and the arc that has not yet recovered its insulation strength will reignite in situ. In some embodiments, the residual voltage 66 can be 10% to 60% of the test voltage before breakdown, typically 30%; when the residual voltage 66 is too high, the starting voltage is higher and the reconnection stroke with controlled ramp can be shortened; when it is too low, the starting voltage is close to zero. Its value depends on the arc extinction time and the self-discharge rate of the test sample.

[0049] Subsequently, the output port voltage 62 remains at a low level equal to the residual voltage for a preset arc recovery holding time, such as... Figure 6 The reason for setting the arc recovery holding time is that after the arc is extinguished, the gas in the arc is still in a heated ionized state, and it takes a period of time to dissipate the ionization before the insulation strength can be rebuilt. If the voltage is not increased during the recovery period, the arc will not reignite in the original arc. After the arc recovery holding time ends, the main controller 50 linearly increases the output port voltage 62 with a controlled rising slope and returns it to the test operating point before breakdown. The test operating point includes the test voltage 67 before breakdown, phase, and frequency. In some embodiments, the arc recovery holding time can be 1 millisecond to 50 milliseconds at power frequency and can be increased to several hundred milliseconds at ultra-low frequency, typically 20 milliseconds at power frequency; the controlled rising slope can be 0.1% to 2% of the test voltage 67 before breakdown per millisecond, typically 0.5% per millisecond. If the slope is too large, the return process itself may induce a charging current spike, and if it is too small, the test connection will be too slow. Therefore, there is no inrush flow during repressurization, the arc channel has recovery time and does not reignite, the amplitude, phase and frequency of the test can be continued, and the test can be smoothly continued instead of restarting from zero.

[0050] In some embodiments, the main controller 50 has a built-in arc recovery template library, which is used to quickly provide the arc recovery holding time based on the test voltage 67 and frequency before breakdown. The arc recovery template library is indexed by the test voltage 67 and frequency before breakdown, and each template contains the arc recovery holding time corresponding to the test voltage and frequency. The arc recovery template library is constructed through calibration tests: using the combination of test voltage 67 and frequency before breakdown as the index feature, different combinations are subjected to a re-pressurization test after arc extinction, and the holding time is shortened successively until the original arc reignites. The shortest holding time that just does not cause reignition is taken as the tag sample of the combination; the shortest arc recovery holding time is associated with the corresponding combination of test voltage and frequency and then stored in the arc recovery template library. The calibrated indexes cover a wide frequency and voltage range from power frequency to ultra-low frequency (0.1 Hz to power frequency). The arc recovery hold time between adjacent index combinations is obtained by bilinear interpolation. When changes in the test sample medium or environmental conditions cause the measured recovery time to deviate from existing samples, the corresponding combinations are recalibrated to update the arc recovery template library. During the cold start phase when there are no calibrated samples, the arc recovery template library outputs a conservative hold time that is slightly longer than the default value. The main controller 50 retrieves the arc recovery hold time from the arc recovery template library based on the test voltage 67 and frequency before breakdown.

[0051] The aforementioned protection and control methods are implemented at the device level by the aforementioned components. (Refer to...) Figure 3 The current sampling unit 44 in the output inverter module 40 corresponds to the acquisition of the common current 61 in the method, and executes step S1; the local controller 43 corresponds to the determination of the preset surge condition and the initiation of the bypass voltage reduction of this module, and executes the actions of this module in steps S2 to S4; the bypass branch 42 is turned on under the control of the local controller 43, and is the execution component for the exit of this module from cascade superposition in step S4; the H-bridge circuit 41 and the module DC link 45 undertake the voltage synthesis and graded voltage establishment of this module during normal operation; the main controller 50 corresponds to the global organization in steps S5 to S8, including making arc extinction determination based on the preset arc extinction current 65, organizing docking start based on the residual voltage 66, and organizing parallel return based on the controlled rise slope. Each component corresponds to a step in the method, and the information transmitted between them is only the operation command issued by the main controller 50 and the common current 61 acquired locally by each local controller 43. Normal operation and breakdown protection do not depend on the horizontal communication between modules. In other embodiments, the input parallel rectifier unit 10, the common DC bus 20, and the isolation converter module 30 may be adopted as follows: Figure 1 and Figure 2 Any equivalent topology other than that shown can be implemented as long as the bus voltage of the common DC bus 20 can be established and maintained on the DC link 45 of the module after isolation by the high-frequency transformer 31. This application embodiment does not limit this.

[0052] A communication link is established between the main controller 50 and each local controller 43. However, this link is only used for non-real-time operation organization, such as issuing target test voltage, frequency, and phase, and organizing re-voltage after arc extinction. The immediate judgment and bypass action that determine success or failure under breakdown conditions are completed locally by each local controller 43 based on the common current 61 collected by the current sampling unit 44 of its module, without going through the communication link. Therefore, even if there is a delay of several milliseconds in the communication link, it does not affect the immediacy of breakdown detection and staggered voltage reduction; the communication delay only involves the organization of re-voltage after arc extinction, and the re-voltage itself is after the arc recovery holding time, so it is not sensitive to this delay. This division of responsibilities allows the embodiments of this application to retain the unified organization of the test process by the main controller 50, while avoiding the inconsistent actions and overvoltage caused by placing the immediate protection on the communication link.

[0053] In summary, the above components revolve around the same series common current 61: under normal voltage application, the common current 61 serves as the phase reference for arranging low-impact switching; during breakdown, the common current 61 also acts as the triggering basis for the lack of communication and coordination among the output inverter modules 40. Combined with staggered controlled voltage reduction and residual charge recovery, this wide-range adjustable AC test power supply, when the capacitive test object 70 experiences frequent breakdowns, not only limits the energy continuously fed into the arc by the power supply and the rate of change of the reverse voltage borne by the test object within a set range, but also ensures that the amplitude, phase, and frequency of the test are maintained after the breakdown process.

[0054] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features, and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A wide-range adjustable AC test power supply based on parallel input and cascaded output, characterized in that, It includes an input parallel rectifier unit, a common DC bus, multiple isolated converter modules, multiple cascaded output inverter modules, and a main controller; The input parallel rectifier unit rectifies the low-voltage AC input into the bus voltage of the common DC bus. Each of the isolation conversion modules is connected between the common DC bus and the corresponding output inverter module through a high-frequency isolation link. After multiple output inverter modules are cascaded and superimposed, they provide AC test voltage to the capacitive test object through the output port. Each of the output inverter modules is also provided with a local controller and a current sampling unit, and each of the current sampling units collects the common current flowing through the series circuit of multiple output inverter modules; Each of the local controllers is configured to: based on the common current collected by the current sampling unit of the output inverter module, when the common current meets a preset surge condition, determine that the output inverter module is in the test item breakdown condition and enter the bypass step-down process. During the bypass step-down process, multiple output inverter modules are bypassed one by one from the cascaded stack according to a preset staggered sequence, so that the voltage at the output port drops back to the preset protection voltage with a controlled slope. The staggered sequence ensures that only one output inverter module is bypassed at any given time.

2. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 1, characterized in that, Each output inverter module includes an H-bridge circuit and a bypass branch, wherein the DC side of the H-bridge circuit is the DC link of the module, and the AC side is connected in series with the series circuit; The bypass voltage reduction process includes: the local controller turning on the bypass branch of the output inverter module, making the AC side output voltage of the output inverter module zero and removing it from the cascade superposition, while the corresponding isolation conversion module maintains the voltage of the DC link of the module.

3. The wide-range adjustable AC test power supply based on parallel input and cascaded output as described in claim 1, characterized in that, Each local controller determines the bypass time slot of its output inverter module in the staggered timing sequence using the fixed sequence number of the output inverter module in the cascaded stack, and the interval between two adjacent bypass time slots is a preset staggered timing interval; The controlled slope is determined by the ratio of the voltage drop at the output port when a single output inverter module is bypassed to the time-off interval.

4. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 1, characterized in that, The preset surge condition includes the rise rate of the common current exceeding a preset rise rate threshold, or the amplitude of the common current exceeding a preset amplitude threshold. Each current sampling unit collects the common current and calculates the rise rate of the common current, which is then used by the corresponding local controller to determine whether the preset surge condition is met.

5. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 1, characterized in that, After the voltage at the output port of each local controller drops back to the preset protection voltage, it keeps the output inverter module in bypass state for a preset protection holding time. During the preset protection holding time, each of the current sampling units continues to collect the common current, and the main controller determines that the breakdown arc of the test object has been extinguished when the common current drops below the preset arc extinguishing current.

6. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 3, characterized in that, The main controller has a built-in controlled slope template library. The controlled slope template library is indexed by the test voltage before breakdown, and each template contains a controlled slope level corresponding to the test voltage. The controlled slope template library is constructed in the following manner: During the calibration test, the energy fed into the breakdown arc by the output inverter module during the bypass step-down process is recorded for different controlled slope levels. The minimum controlled slope level that ensures the fed-in energy does not exceed the preset upper limit of fed-in energy is associated with the corresponding test voltage and stored in the controlled slope template library. The main controller retrieves the controlled slope level from the controlled slope template library based on the test voltage before breakdown, and sets the time interval according to the controlled slope level.

7. The wide-range adjustable AC test power supply based on parallel input and cascaded output as described in claim 1, characterized in that, The main controller is configured to, during normal operation when the bypass step-down process does not occur, set the voltage of the DC link of the multiple output inverter modules to unequal graded voltages through each of the isolation conversion modules, and arrange the switching time of each output inverter module with the zero crossing point of the common current as the phase reference. The level transitions occurring within the zero-crossing voltage range of the output port are handled by the output inverter module with the smaller value among the graded voltages, while the level transitions occurring within the peak voltage range of the output port are handled by the output inverter module with the larger value among the graded voltages.

8. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 7, characterized in that, The main controller has a built-in stride grading template library. The stride grading template library is indexed by the target output voltage amplitude. Each template contains the graded voltage of each output inverter module corresponding to the target output voltage amplitude and the switching phase order of each output inverter module. The step size template library is constructed as follows: For each target output voltage amplitude, a set of graded voltages is selected such that the step size of the level transition occurring within the voltage zero-crossing interval does not exceed the preset step size upper limit. The selected graded voltages and the corresponding switching phase sequence are associated with the target output voltage amplitude and then stored in the step size template library. The main controller retrieves the graded voltage and the switching phase sequence from the step graded template library according to the current target output voltage amplitude.

9. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 5, characterized in that, After determining that the breakdown arc has been extinguished, and before re-pressurizing the capacitive test sample, the main controller collects the residual voltage at the output port, controls multiple output inverter modules to start the voltage at the output port from a voltage equal to the residual voltage, and then, after the preset arc recovery holding time ends, restores the voltage at the output port to the test operating point before breakdown with a controlled rising slope. The test operating point includes the test voltage, phase, and frequency before breakdown.

10. The wide-range adjustable AC test power supply based on input parallel connection and output cascade as described in claim 9, characterized in that, The main controller has a built-in arc recovery template library. The arc recovery template library is indexed by the test voltage and frequency before breakdown. Each template contains the arc recovery holding time corresponding to the test voltage and frequency. The arc recovery template library is constructed as follows: In the calibration test, for different combinations of pre-breakdown test voltage and frequency, the shortest holding time that prevents the breakdown arc from reigniting in the original arc when the voltage is reapplied is recorded, and the shortest holding time is associated with the corresponding combination of test voltage and frequency and then stored in the arc recovery template library. The main controller retrieves the arc recovery holding time from the arc recovery template library based on the test voltage and frequency before breakdown.

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