Layered decoupling and ripple feed-forward suppression control method for solid-state transformer

Abstract

This disclosure relates to a hierarchical decoupling and ripple feedforward suppression control method for solid-state transformers. The method includes: a system controller generating a three-phase total modulation wave, normalizing the three-phase total modulation wave into individual module modulation waves, and broadcasting the individual module modulation waves to the DSPs of each power module; the DSPs driving the cascaded H-bridges of the power modules to perform AC-DC conversion based on the individual module modulation waves to establish a high-voltage DC voltage; the DSPs generating a base shift ratio, extracting the output second harmonic fluctuation component, performing phase compensation on the second harmonic fluctuation component to obtain a phase-compensated fluctuation signal, generating a ripple compensation shift ratio, and superimposing the base shift ratio and the ripple compensation shift ratio to obtain a target shift ratio; the DSPs sending the target shift ratio to the high-voltage side FPGA of the power module, generating a square wave signal based on the target shift ratio, and using the square wave signal to drive the switching transistors of the high-voltage side H-bridge of the DAB. This disclosure achieves effective suppression of battery current ripple without degrading the system's dynamic response.

Description

Technical Field

[0001] This disclosure relates to the field of solid-state transformer technology, and in particular to a method for hierarchical decoupling and ripple feedforward suppression control of solid-state transformers. Background Technology

[0002] In related technologies, solid-state transformers are key equipment for constructing AC / DC hybrid distribution networks and achieving efficient access to energy storage systems. In medium- and high-voltage, high-capacity applications, a cascaded H-bridge topology is often used as the front-end AC-DC conversion stage, with the subsequent stage connected to battery clusters via dual active bridge (DAB) isolation converters to achieve electrical isolation and voltage matching. The entire system consists of dozens of power modules connected in series and parallel, resulting in high control complexity.

[0003] In existing control schemes for cascaded H-bridge solid-state transformers, the system controller typically needs to centrally collect the DC voltage and current of all modules, uniformly perform voltage equalization loop and voltage-current loop calculations, and directly generate modulation waves or ratio shift commands for each H-bridge and DAB. This results in the need for real-time transmission of large amounts of data between controllers, placing extremely stringent requirements on communication bandwidth and latency, and making system expansion difficult. Furthermore, the instantaneous power of a single-phase H-bridge AC / DC converter pulsates at twice the grid frequency, causing second-harmonic voltage fluctuations on the H-bridge DC bus. These fluctuations are transmitted to the battery side through the DAB, resulting in significant second-harmonic ripple components in the battery current, leading to battery heating, decreased cycle efficiency, and reduced battery life. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a hierarchical decoupling and ripple feedforward suppression control method for solid-state transformers.

[0005] According to an embodiment of this disclosure, a hierarchical decoupling and ripple feedforward suppression control method for a solid-state transformer is provided. The solid-state transformer includes a system controller and multiple power modules. Each power module includes a cascaded H-bridge and a multi-channel dual active bridge converter (DAB). The AC sides of the cascaded H-bridges of each power module are connected in series. The method includes: The system controller generates a three-phase total modulation wave based on the three-phase voltage and three-phase current of the power grid, normalizes the three-phase total modulation wave into a single module modulation wave, and broadcasts the single module modulation wave to the module controller DSP of each power module. For each power module, the DSP of the power module drives the cascaded H-bridge of the power module to perform AC-DC conversion based on the modulation wave of the single module, so as to establish a high voltage DC voltage; The DSP generates a base shift ratio based on the output voltage, input voltage, and input current of each DAB within the power module; The DSP extracts the second harmonic fluctuation component from the output voltage, performs phase compensation on the second harmonic fluctuation component to obtain a phase-compensated fluctuation signal, uses the phase-compensated fluctuation signal to generate a ripple compensation shift ratio, and superimposes the base shift ratio with the ripple compensation shift ratio to obtain the target shift ratio. The DSP sends the target shift ratio to the high-voltage side FPGA of the power module. The high-voltage side FPGA generates a square wave signal based on the target shift ratio and uses the square wave signal to drive the switching transistor of the high-voltage side H-bridge of the DAB in the power module to adjust the transmission power of the DAB.

[0006] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: The system controller generates and broadcasts only the normalized single-module modulation wave of the three-phase total modulation wave. The DSPs of each power module independently drive the cascaded H-bridge for AC / DC conversion based on this modulation wave, achieving decoupling between system-level control and module-level drive. This avoids the system controller issuing control commands to each module individually, significantly reducing the amount of ring network communication data and bandwidth requirements. When expanding the system, only power modules need to be added without modifying the upper-level control architecture. Simultaneously, the DSPs of each power module use high-voltage DC voltage as the output voltage of each DAB, and autonomously generate the basic... The ripple compensation shift ratio is generated by extracting the second harmonic fluctuation component from the output voltage, multiplying it by a gain coefficient after phase compensation, and superimposing it onto the base shift ratio to obtain the target shift ratio. The high-voltage side FPGA generates a square wave signal based on the target shift ratio to drive the switching transistors of the high-voltage side H-bridge of the DAB, so that the input current regulation effect generated by the ripple compensation shift ratio is out of phase with the second harmonic fluctuation component in the input current, achieving active cancellation rather than passive filtering. This eliminates the need to increase the DC bus capacitance, introduce a notch filter, and does not affect the dynamic response of the current inner loop. The DSP in each power module independently executes the generation of the base shift ratio and the generation of the ripple compensation shift ratio. The underlying control does not depend on the system controller, and the control between modules is independent of each other.

[0007] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] Figure 1 This is a flowchart illustrating a hierarchical decoupling and ripple feedforward suppression control method for a solid-state transformer according to an exemplary embodiment.

[0010] Figure 2This is a topology diagram of a solid-state transformer system according to an exemplary embodiment.

[0011] Figure 3 This is a flowchart illustrating the system controller modulation wave generation and broadcasting process according to an exemplary embodiment.

[0012] Figure 4 This is a flowchart of the DAB module controller control and second harmonic ripple feedforward suppression. Detailed Implementation

[0013] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure.

[0014] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of embodiments of this disclosure, and similarly, second information may also be referred to as first information. Depending on the context, the words “if” and “suppose” as used herein may be interpreted as “when”, “when”, or “in response to a determination”.

[0016] Furthermore, various forms of processes shown in the embodiments of this disclosure can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0017] It should be noted that the collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0018] The present disclosure will now be described in further detail with reference to the accompanying drawings. In some embodiments of the present disclosure, a method for hierarchical decoupling and ripple feedforward suppression control of a solid-state transformer is provided.

[0019] The control method proposed in this disclosure can be applied to a 35kV cascaded H-bridge dual active bridge (DAB) solid-state transformer (SST). In some embodiments, such as Figure 2 As shown, the solid-state transformer consists of 36 identical power modules, divided into three phases (A, B, and C). The H-bridge AC outputs of 12 power modules in each phase are connected in series and then connected to the grid via a grid-connected reactor. Each power module is internally divided into two symmetrical planes, A and B, each containing two DAB isolation converters and two H-bridges. The high-voltage side DC ports of the two DABs are connected in parallel to the DC bus of the H-bridge on that plane. The two DABs on the low-voltage side are connected in series to the same battery cluster. The entire system has 24 battery clusters, each connected across one side of a power module. In other words, the 36 power modules have a total of 72 planes, with each battery connected to 3 planes, resulting in 24 battery clusters. Each power module's controller is based on a single Digital Signal Processor (DSP) and paired with two Field Programmable Gate Arrays (FPGAs): the low-voltage side FPGA generates pulse width modulation (PWM) pulses for the DAB low-voltage side switches, while the high-voltage side FPGA generates PWM pulses for the DAB high-voltage side and all H-bridge switches. The system controller is independent of the power modules and communicates point-to-multipoint with all power module controllers via a high-speed FPGA ring network. The communication cycle can be 50 microseconds, ensuring control synchronization.

[0020] Figure 1 This is a flowchart illustrating a hierarchical decoupling and ripple feedforward suppression control method for a solid-state transformer according to an exemplary embodiment, such as... Figure 1 As shown, it should be noted that the solid-state transformer described in this disclosure includes a system controller and multiple power modules. Each power module includes a cascaded H-bridge and a multi-channel dual active bridge converter (DAB). The AC sides of the cascaded H-bridges of each power module are connected in series. Figure 1 As shown, the method may include the following steps: Step 101: The system controller generates a three-phase total modulation wave based on the three-phase voltage and three-phase current of the power grid, normalizes the three-phase total modulation wave into a single module modulation wave, and broadcasts the single module modulation wave to the module controller DSP of each power module.

[0021] In some embodiments of this disclosure, such as Figure 3 As shown, step 101 may specifically include the following sub-steps: Step a1: The system DSP in the system controller performs dq coordinate transformation and current closed-loop regulation on the three-phase voltage and three-phase current of the power grid to generate the three-phase total modulation wave (i.e., the original modulation wave) in the three-phase stationary coordinate system.

[0022] Step a2: The system DSP obtains the sum of the output voltages (i.e., the high-voltage side bus voltages) of each power module in each phase.

[0023] In step a3, the system DSP divides the total three-phase modulation wave of each phase by the sum of the output voltages of the corresponding phases to obtain the modulation wave of a single module. The modulation wave of a single module is marked as dutyA, dutyB, and dutyC in the FPGA communication link, i.e., dutyA / B / C, which correspond to the duty cycle commands of a single power module in phases A, B, and C, respectively. After receiving dutyA / B / C, the high-voltage side FPGA uses it as the modulation wave to generate the PWM drive signal for the cascaded H-bridge.

[0024] In this disclosure, the system DSP refers to the core computing chip inside the system controller, which is independent of the power module and focuses on global grid-side control; the DSP in each power module specifically refers to the core computing chip on the module controller inside each power module. Each power module has its own independent module DSP, whose responsibility focuses on autonomous control within the power module.

[0025] In some embodiments of this disclosure, step a1 may specifically include the following sub-steps: Step a11: The system DSP obtains the grid voltage phase angle θ based on the three-phase grid voltage.

[0026] Specifically, the system controller can use a digital phase-locked loop to monitor the three-phase voltage U of the power grid. ga U gb U gc Phase-locked loop (PLL) is performed to obtain the phase angle θ of the grid voltage. This phase angle θ is used for subsequent coordinate transformations and serves as the angular reference for conversion between the dq rotating coordinate system and the three-phase stationary coordinate system.

[0027] Step a12: The system DSP performs dq coordinate transformation on the three-phase currents of the power grid to obtain the active current I. d and reactive current I q .

[0028] Specifically, the system controller samples the three-phase grid current I. ga I gb I gc Using the phase angle θ obtained in step a11, the three-phase currents are transformed into abc / dq coordinates to convert the current components in the three-phase stationary coordinate system into active current I in the two-phase rotating coordinate system. d (d-axis current) and reactive current Iq (q-axis current). This coordinate transformation can decouple the active and reactive components of the grid current, facilitating independent control.

[0029] Step a13, the system DSP will generate the active current I d With active current given value I dref After comparison, the PI controller is adjusted to obtain the d-axis proportional-integral output. This d-axis proportional-integral output is then compared with the output based on the reactive current I... q The WL decoupling compensation amount is superimposed and then combined with the d-axis grid voltage feedforward amount V. gd Superimposed, the d-axis voltage command V is obtained. d .

[0030] Specifically, in the d-axis control branch, the active current feedback value I... d With active current given value I dref The difference is calculated to obtain the deviation signal, which is then fed into a proportional-integral (PI) controller. After PI regulation, the d-axis proportional-integral output is generated. Simultaneously, based on the reactive current I... q The d-axis decoupling compensation is generated using the WL module, where W is the grid angular frequency and L is the AC-side equivalent inductance. The WL decoupling term is used to eliminate current cross-coupling between the d-axis and q-axis. The d-axis proportional-integral output is then compared with the I-based... q After the WL decoupling compensation is superimposed, it is then combined with the d-axis grid voltage feedforward quantity V. gd Superimposed, the d-axis voltage command V is obtained. d .

[0031] Furthermore, in the d-axis control branch, the active current feedback value Id is compared with the active current setpoint I... dref The difference is calculated to obtain the current deviation signal, which is then fed into a proportional-integral (PI) controller. The PI controller is the core component that converts the current deviation into a voltage command: the proportional (P) element amplifies the current deviation proportionally for a fast response; the integral (I) element accumulates the deviation to eliminate steady-state error, enabling the active current to accurately track the given value. Its regulation process is as follows: when I... d dref When the PI output is positive, it makes V d Increase, forcing I d Rise; when I d >I dref When the PI output is negative, V d Decrease, forcing I d Decrease; when I d = I dref ​At this time, the PI output remains stable, and Id remains constant. Through the synergistic effect of P and I, I is ultimately made... d Stable at I dref Meanwhile, based on reactive current I q The d-axis decoupling compensation is generated using the WL module, where W is the grid angular frequency and L is the AC-side equivalent inductance. The WL decoupling term is used to eliminate current cross-coupling between the d-axis and q-axis. The d-axis proportional-integral output is then compared with the I-based... q After the WL decoupling compensation is superimposed, it is then combined with the d-axis grid voltage feedforward quantity V. gd Superimposed, the d-axis voltage command V is obtained. d .

[0032] Among them, V gd The grid voltage is the d-axis component. Introducing grid voltage feedforward can improve the system's dynamic response to grid voltage disturbances.

[0033] Step a14, the system DSP will convert the reactive current I... q With reactive current given value I qref After comparison and proportional-integral adjustment, the q-axis proportional-integral output is obtained. This q-axis proportional-integral output is then compared with the output based on the active current I. d The WL decoupling compensation is superimposed and then combined with the q-axis grid voltage feedforward quantity V. gq Superimposed, the q-axis voltage command V is obtained. q .

[0034] Specifically, in the q-axis control branch, the reactive current feedback value I... q With reactive current given value I qref The difference is calculated to obtain the deviation signal, which is then sent to a PI controller. After PI regulation, the output is the q-axis proportional-integral output (the regulation principle is the same as in step a13, and will not be repeated here). Simultaneously, based on the active current I... d The q-axis decoupling compensation quantity is generated through the WL module, and the q-axis proportional-integral output quantity is combined with the I-based... d After the WL decoupling compensation is superimposed, it is then combined with the q-axis grid voltage feedforward quantity V. gq Superimposed, the q-axis voltage command V is obtained. q V gq This represents the q-axis component of the grid voltage. Through d- and q-axis decoupling compensation and grid voltage feedforward, independent decoupling control of the d- and q-axis currents is achieved, allowing active and reactive power to be adjusted independently.

[0035] Step a15, the system DSP sends the d-axis voltage command V d and q-axis voltage command V q By performing an inverse dq / abc transformation using the grid voltage phase angle θ, the three-phase total modulation wave in the three-phase stationary coordinate system is obtained, i.e., V.pwm .

[0036] Specifically, the system controller will send the d-axis voltage command V d and q-axis voltage command V q Combining the grid voltage phase angle θ obtained in step a11, an inverse dq / abc transformation is performed (i.e., transforming from a two-phase rotating coordinate system back to a three-phase stationary coordinate system) to generate the three-phase total modulation wave V in the three-phase stationary coordinate system. mod_a V mod_b V mod_c This three-phase total modulation waveform represents the total voltage command required by all power modules in that phase. V pwm That is, the three-phase total modulation wave V mod_a V mod_b V mod_c The term "dq / abc" is a general term referring to the three-phase PWM modulated wave signal generated after the inverse dq / abc transformation.

[0037] In some embodiments of this disclosure, step a2 may specifically include: the system DSP receiving the output voltage sample value V of each power module from the high-voltage side FPGA via ring network communication. Hbus The voltages are then summed phase by phase to obtain the sum of the output voltages V of all power modules in each phase. Hbus_a_sum V Hbus_b_sum V Hbus_c_sum .

[0038] In some embodiments of this disclosure, step a3 may specifically include: the system DSP converting the three-phase total modulation wave V generated in step a15 into a signal. mod_a V mod_b V mod_c Divide by the sum of the output voltages of the corresponding phases, V Hbus_a_sum V Hbus_b_sum V Hbus_c_sum The normalized modulation wave V of a single module is obtained. mod_module Taking phase A as an example, V mod_a_j = V mod_a / V Hbus_a_sum V mod_a_j This represents the modulated waveform of the j-th power module in phase A. Phases B and C are processed in the same way. The system controller will... mod_module The signal is broadcast to each power module via the ring network. In the FPGA communication link, this signal is marked as dutyA, dutyB, and dutyC (i.e., dutyA / B / C), which correspond to the duty cycle command of a single power module in the three phases A, B, and C, respectively. After receiving dutyA / B / C, the high-voltage side FPGA uses it as a modulation wave to generate the PWM drive signal for the H-bridge.

[0039] It should be noted that by normalizing the three-phase total modulation waveform by dividing it by the sum of the output voltages of all power modules in that phase, the system-level total voltage command can be reasonably distributed to each series-connected power module. This ensures that the voltage ratio borne by each power module matches its actual bus voltage, preventing overmodulation and guaranteeing a balanced distribution of the AC side voltage of the H-bridge in each module. The system controller packages the modulation waveform of each individual module in each phase into a data frame and synchronously broadcasts it to the module controller of the corresponding power module through the FPGA ring network.

[0040] During this process, the system controller does not perform any internal voltage control of the power modules, thereby effectively simplifying the amount of communication data and control coupling. After receiving the modulated wave, the high-voltage side FPGA of each power module uses a carrier phase-shift modulation strategy to generate the PWM switching signal of the H-bridge, controlling the on / off state of the H-bridge switching transistors to achieve AC current waveform control.

[0041] Step 102: For each power module, the DSP of the power module drives the cascaded H-bridge of the power module to perform AC-DC conversion based on the modulation wave of the single module to establish a high voltage DC voltage.

[0042] In the embodiments disclosed herein, such as Figure 3 As shown, the high-voltage side FPGA of each power module receives the modulated wave V of a single module broadcast through the ring network from the main control FPGA in the system controller. mod_module (Labeled as dutyA / B / C in the main control FPGA), a carrier phase-shift modulation strategy is adopted to compare the modulated wave with the high-frequency carrier, generating PWM drive signals for the four switches of the H-bridge (labeled as PWM H1~H4). These signals drive the cascaded H-bridge switches to turn on and off in a certain timing sequence, rectifying the AC power from the grid side into DC power, and establishing a high-voltage DC voltage V on the DC bus of the power module. Hbus The high-voltage DC voltage V Hbus It is the source of input voltage for each DAB within this power module, and also the controlled variable for subsequent DAB closed-loop control.

[0043] Furthermore, such as Figure 3 As shown, the system DSP in the system controller generates a three-phase raw total modulation wave through closed-loop operation, and the main control FPGA receives the DC bus voltage V from the cascaded H-bridge of each module. Hbus The total modulated wave is normalized into single-module modulated waves dutyA / B / C and broadcast; dutyA / B / C are simultaneously sent to the low-voltage side DSP (i.e., module controller DSP) and the low-voltage side FPGA of each power module, wherein the low-voltage side DSP also acquires the local V HbusThe target shift ratio D1 / D2 is calculated through an internal closed-loop and ripple compensation algorithm and sent to the low-voltage side FPGA of the module. The low-voltage side FPGA generates PWM H1~H4 based on the received dutyA / B / C to drive the low-voltage side H bridge. On the other hand, it transmits the received D1 / D2 and dutyA / B / C to the high-voltage side FPGA of the module to generate square wave signals PWM H1~H4 with phase difference determined by the shift ratio to drive the switching transistors of the high-voltage side H bridge of the DAB, thereby adjusting the DAB transmission power and driving the cascaded H bridge using PWM H1~H4.

[0044] It should be noted that the cascaded H-bridge performs the function of AC-DC conversion, establishing a stable high-voltage DC voltage V on the DC bus. Hbus This provides a stable DC input for the subsequent DAB isolation converter.

[0045] Step 103: The DSP generates a base shift ratio based on the output voltage, input voltage, and input current of each DAB inside the power module.

[0046] In some embodiments of this disclosure, such as Figure 2 As shown, each power module includes two surfaces, and each surface includes two DABs. Figure 4 As shown, step 103 may specifically include the following sub-steps: Step b1: For each surface, the DSP calculates the difference between the sum of the output voltages of the two DABs and the reference value of the output voltage, and then uses proportional-integral adjustment to generate the initial value I of the total current reference. ref_total .

[0047] Specifically, each power module contains two symmetrical planes, A and B, with two DABs per plane. The high-voltage sides of the two DABs on the same plane are connected in parallel to the H-bridge DC bus of that plane, while the low-voltage sides are connected in series to the same battery cluster. The DSP samples the output voltage V of the two DABs on the same plane. Hbus1 and V Hbus2 (i.e., output voltage), the sum of the two output voltages V Hbus1 +V Hbus2 With the output voltage given reference value V outallref The difference is calculated to obtain the voltage deviation signal, which is then fed into a PI controller. After PI regulation, the output total current setpoint I is obtained. ref_total This stage is the outer voltage loop, and its function is to stabilize the total output voltage of the DAB so that it tracks the given reference value.

[0048] Step b2: For each of the two DABs, the DSP calculates the difference between the input voltage of the DAB and the average input voltage of the two DABs, and then uses proportional-integral regulation to generate the voltage equalization regulation amount ΔI. bal And adjust the equalization pressure adjustment amount ΔIbal Superimposed to the initial value I of the total current ref_total Generate the inner loop current given value I in_ref .

[0049] Specifically, since the two DABs on the same plane are connected in series on their low-voltage sides and then connected to the same battery cluster, a voltage equalization loop control is needed to ensure that the input voltages of the two DABs are balanced. The DSP samples the input voltage V of each DAB. Lbus1 and V Lbus2 (i.e., the low-voltage side bus voltage, closer to the battery side), calculate the average value V of the two input voltages. Lbus_avg = (V Lbus1 + V Lbus2 ) / 2. For the first DAB, set its input voltage V Lbus1 With average value V Lbus_avg The difference is calculated to obtain the voltage deviation signal, which is then fed into a PI controller. After PI regulation, the output voltage equalization adjustment amount ΔI is obtained. bal1 Adjust the equalization pressure by ΔI. bal1 The total current given initial value I generated in step b1 is superimposed on it. ref_total The current inner loop setpoint I of the first DAB is obtained. in_ref1 = I ref_total +ΔI bal1 The second DAB is handled in the same way, I in_ref2 = I ref_total +ΔI bal2 Among them, the current DAB's equalization pressure adjustment amount ΔI bal1 and ΔI bal2 In the block diagram, these are labeled as ΔI. bus1 and ΔI bus2 ΔI bus1 The equalization adjustment amount for the first DAB channel, ΔI bus2 This is the equalization adjustment amount for the second DAB channel.

[0050] Step b3, the DSP sets the current inner loop setpoint I. in_ref The input current I of the current path DAB in After difference and proportional-integral adjustment, the basic shift ratio d is generated. base .

[0051] Specifically, the DSP samples the input current I of the current DAB. in (i.e., the low-voltage side current, closer to the battery side), the current inner loop given value I generated in step b2. in_ref With input current feedback value I in The difference is calculated to obtain the current deviation signal, which is then fed into a PI controller. After PI regulation, the output base shift ratio is d. baseThis stage is the inner current loop, whose function is to enable the DAB's input current to quickly track the inner current loop's setpoint, thereby achieving precise control of the transmitted power. The inner current loop features fast response and strong disturbance rejection capabilities, making it the core component for achieving precise power control in the DAB.

[0052] It should be noted that steps b1 to b3 constitute a three-loop cascade control structure of "outer voltage loop, equalizing loop, and inner current loop": the output of the outer voltage loop serves as the initial value of the total current setpoint, the output of the equalizing loop serves as the equalizing adjustment amount superimposed on the initial value of the total current setpoint to form the setpoint of the inner current loop, and the output of the inner current loop is based on the shift ratio d. base The three control loops each perform their respective functions and work in a progressive manner to jointly achieve stable control of the DAB output voltage, balanced control of multiple DAB input voltages, and rapid tracking control of the input current.

[0053] Step 104: The DSP extracts the second harmonic fluctuation component from the output voltage, performs phase compensation on the second harmonic fluctuation component to obtain the phase-compensated fluctuation signal, uses the phase-compensated fluctuation signal to generate a ripple compensation shift ratio, and superimposes the base shift ratio and the ripple compensation shift ratio to obtain the target shift ratio.

[0054] In some embodiments of this disclosure, such as Figure 4 As shown, step 104 may specifically include the following sub-steps: Step c1: The DSP filters the output voltage using a bandpass filter to extract the second harmonic ripple component V. Hbus_ac .

[0055] Specifically, the DSP acquires the output voltage V of the current DAB through an analog-to-digital converter. Hbus (i.e., output voltage). Because the instantaneous power of the front-end single-phase H-bridge AC / DC converter system pulsates at twice the grid frequency (100Hz), the H-bridge DC bus generates a 100Hz voltage fluctuation, which is transmitted to the battery side through the DAB's closed-loop control.

[0056] To actively suppress this second harmonic ripple, the DSP will acquire the V... Hbus The signal is fed into a digital bandpass filter to extract the 100Hz AC ripple component V. Hbus_ac The center frequency f0 of this bandpass filter is twice the mains frequency (100Hz), and the quality factor Q is chosen to be 2 to ensure selectivity while also considering response speed. This bandpass filter can be implemented using a direct form second-order infinite impulse response (IIR) structure with a sampling frequency of 10kHz.

[0057] In step c2, the DSP performs phase lag processing on the second harmonic fluctuation component through a first-order low-pass filter to obtain the phase-compensated fluctuation signal.

[0058] Specifically, the DSP extracts the second harmonic fluctuation component V from step c1. Hbus_ac The signal is fed into a first-order low-pass filter for phase compensation. The transfer function of this first-order low-pass filter is: H(z) = K f / [1 (1 K f )·z - ¹] The corresponding difference equation is: y lpf [n]=K f ·V Hbus_ac [n]+(1 Kf)· y lpf [n 1] Where H(z) is the transfer function of a first-order low-pass filter, K f These are the filter coefficients, and their values ​​range from 0 to 1. <K f <1, the specific value can be determined based on the system sampling frequency and the target phase lag, and the corresponding phase lag compensates for the accumulated phase deviation of the system at 100Hz; z - ¹ represents the delay of one sampling period; y lpf [n] represents the filtered output at the current time, V Hbus_ac [n] represents the second harmonic alternating current fluctuation component at the current moment, y lpf [n [1] is the filtered output of the previous moment. Through this first-order low-pass filter, a precise phase lag can be applied to the extracted second harmonic fluctuation component without introducing a notch filter, so that the feedforward action on the current loop is out of phase with the original disturbance.

[0059] It should be noted that the physical basis for this phase compensation is as follows: The instantaneous power of a single-phase H-bridge contains a pulsating component with an amplitude equal to the apparent power S, causing voltage fluctuations at the same frequency to occur on the H-bridge DC bus. When the DAB uses PI control with an outer voltage loop and an inner current loop, due to the sampling low-pass filter and the phase characteristics of the controller itself, the phase difference between the input current fluctuation component and the output voltage fluctuation component is a fixed angle. Therefore, using the output voltage as a stable reference to extract the fluctuation amount as feedforward, it is necessary to compensate for this fixed phase difference. This disclosure introduces phase lag by inserting a first-order low-pass filter in series after extracting the output voltage fluctuation, and adjusting the filter coefficient K... f The phase lag can be precisely set.

[0060] In step c3, the DSP multiplies the phase-compensated ripple signal by a gain coefficient to generate a ripple compensation shift ratio.

[0061] Specifically, the DSP will output the first-order low-pass filter y in step c2. lpf Multiply by an adjustable gain coefficient K d The ripple compensation shift is obtained compared to Δd. rip = K d ·y lpf Gain coefficient K d It can adaptively adjust according to the load power to achieve the best ripple suppression effect under different power conditions.

[0062] In step c4, the DSP superimposes the base shift ratio with the ripple compensation shift ratio to obtain the target shift ratio.

[0063] In some embodiments of this disclosure, step c4 may specifically include: the DSP shifting the base generated in step b3 compared to d. base (Route 1 is d) base1 The second path is d base2 Compared to the ripple compensation shift generated in step c3, Δdr ip (The first path is Δd) rip1 The second path is Δd rip2 Adding them together, we get the synthetic shift ratio d. syn = d base + Δd rip Then, the synthetic shift ratio d syn A amplitude limiting process is applied, restricting it to the range of [-0.5, 0.5], resulting in a target displacement ratio d = saturate(d syn (, -0.5, 0.5). The target shift ratio of the first DAB is d1, and the target shift ratio of the second DAB is d2. The target shift ratios output by the DSP to the high-voltage side FPGA are d1 and d2, which are marked as D1 and D2 at the FPGA level, corresponding to the phase shift control commands of the first and second DABs, respectively. The high-voltage side FPGA generates square wave drive signals for the corresponding DABs based on D1 and D2.

[0064] It should be noted that the second harmonic ripple feedforward suppression in steps c1 to c4 can shift the ripple compensation ratio by Δd. rip The resulting input current regulation effect is exactly out of phase (180° phase difference) with the second harmonic fluctuation component in the input current, thereby achieving destructive interference and actively canceling the 100Hz component in the input current to suppress battery current ripple. It does not require a complex adaptive algorithm and only uses the output voltage as the feedforward source, which has the outstanding advantages of stable extraction, determined amplitude and phase, and simple implementation.

[0065] Step 105: The DSP sends the target shift ratio to the high-voltage side FPGA of the power module. The high-voltage side FPGA generates a square wave signal based on the target shift ratio and uses the square wave signal to drive the switching transistors of the high-voltage side H-bridge of the DAB in the power module to adjust the transmission power of the DAB.

[0066] In some embodiments of this disclosure, step 105 may specifically include the following sub-steps: Step d1: The high-voltage side FPGA generates two sets of square wave signals based on the target shift ratio.

[0067] In step d2, the phase difference between the two sets of square wave signals is determined by the target shift ratio.

[0068] In step d3, the high-voltage side FPGA uses two sets of square wave signals to drive the corresponding switching transistors of the DAB high-voltage side H-bridge in the power module.

[0069] Specifically, the DSP sends the target phase shift ratio d generated in step 104 (d1 for the first path and d2 for the second path, labeled D1 and D2 in the FPGA) to the high-voltage side FPGA of this power module via on-chip communication. The high-voltage side FPGA generates two sets of square wave signals with a phase difference of d×360° based on the target phase shift ratio d, driving the switches of the two arms of the DAB high-voltage side H-bridge respectively. By changing the phase difference between the two sets of square wave signals, the phase shift angle between the DAB high-voltage side H-bridge and the low-voltage side H-bridge can be controlled, thereby adjusting the magnitude and direction of the current flowing through the transformer leakage inductance, achieving precise control of the DAB power transmission. Simultaneously, the low-voltage side FPGA generates a complementary square wave signal with a fixed duty cycle of 50%, driving the switches of the DAB low-voltage side H-bridge, causing the low-voltage side H-bridge to operate in a fixed 50% duty cycle mode.

[0070] It should be noted that the target shift ratio d is limited to the range of [-0.5, 0.5]. When d is positive, power is transmitted in the forward direction (from the high-voltage side to the low-voltage side); when d is negative, power is transmitted in the reverse direction (from the low-voltage side to the high-voltage side).

[0071] In some embodiments of this disclosure, in steps 101 to 105, the DSP of each power module independently generates the base shift ratio and ripple compensation shift ratio for each DAB within its power module. The system controller does not participate in the voltage equalization control or closed-loop control of each DAB within each power module. Through this hierarchical decoupled control architecture, the system controller only needs to generate and broadcast a unified modulation waveform, and the power module controller independently completes the dual-loop control of DAB voltage and current and second-harmonic ripple feedforward suppression. The amount of ring network communication data is significantly reduced, and the real-time requirements for communication are greatly reduced. When expanding the system, only power modules need to be added and their addresses configured, without modifying the upper-level control architecture, which facilitates standardized module production and plug-and-play functionality.

[0072] In some embodiments of this disclosure, the center frequency of the bandpass filter is twice the grid frequency.

[0073] Specifically, for a system with a grid frequency of 50Hz, twice the grid frequency is 100Hz, therefore the center frequency of the bandpass filter is f0 = 100Hz. When the grid frequency experiences normal fluctuations of ±0.5Hz, since the feedforward suppression method used in this disclosure does not rely on the precise notch frequency of the notch filter, but instead uses the output voltage fluctuation as a feedforward source to achieve active cancellation through phase compensation, the problem of a sharp decrease in ripple suppression effect due to frequency mismatch, as seen in traditional notch filter solutions, will not occur.

[0074] In some embodiments of this disclosure, the power module further includes a low-voltage side FPGA, which generates a complementary square wave signal with a fixed duty cycle to drive the low-voltage side switching transistor of the DAB in the power module.

[0075] Specifically, in the module controller of each power module, the low-voltage side FPGA is responsible for generating the PWM pulses for the DAB low-voltage side H-bridge. The four switches of the low-voltage side H-bridge operate with a fixed 50% duty cycle, with two switches in the same bridge arm using complementary square wave drive (i.e., one is on while the other is off) to avoid shoot-through in the bridge arm. This complementary square wave signal with a fixed duty cycle does not change with the target phase shift d, ensuring that the DAB low-voltage side H-bridge always operates in a 50% duty cycle square wave inverter mode, providing a stable reference for phase shift control.

[0076] In some embodiments of this disclosure, the phase compensation parameters are determined as follows: Frequency sweep tests are performed using offline simulation and an actual power platform, maintaining the DAB in steady-state operation at 0.5 times the rated power load, and the filter coefficient K of the first-order low-pass filter is gradually changed. f Record the effective value of the 100Hz component of the battery current, and take the K value corresponding to the minimum value of the 100Hz component of the battery current. f The value is used as the optimal filtering coefficient. Repeated testing at different power levels showed that this optimal coefficient remained unchanged, proving its robustness. Therefore, this coefficient can be permanently written as a constant value into the DSP program of each power module, eliminating the need for online adjustment.

[0077] In some embodiments of this disclosure, the gain coefficient K of the second harmonic ripple feedforward suppression branch is... d It can adaptively adjust according to the load power to achieve optimal ripple suppression under different power conditions. Gain coefficient K d The adjustment can be achieved by using a lookup table method or a fitting method, and the specific value can be obtained through experimental calibration or theoretical calculation.

[0078] According to the hierarchical decoupling and ripple feedforward suppression control method for solid-state transformers proposed in this disclosure, the system controller generates and broadcasts only the normalized single-module modulation wave of the three-phase total modulation wave. Each power module's DSP independently drives the cascaded H-bridge for AC-DC conversion based on this modulation wave, achieving decoupling between system-level control and module-level drive. This avoids the system controller issuing control commands to each module individually, significantly reducing the data volume and bandwidth requirements of the ring network communication. System expansion only requires adding power modules without modifying the upper-level control architecture. Simultaneously, each power module's DSP uses high-voltage DC voltage as the output voltage of each DAB, autonomously controlling the output voltage, input voltage, and input current of each DAB. The base shift ratio is generated, and the second harmonic fluctuation component in the output voltage is extracted. After phase compensation, it is multiplied by a gain coefficient to generate a ripple compensation shift ratio, which is then superimposed on the base shift ratio to obtain the target shift ratio. The high-voltage side FPGA generates a square wave signal based on the target shift ratio to drive the switching transistors of the high-voltage side H-bridge of the DAB. This makes the input current regulation effect generated by the ripple compensation shift ratio out of phase with the second harmonic fluctuation component in the input current, achieving active cancellation rather than passive filtering. This eliminates the need to increase the DC bus capacitance, introduce a notch filter, and does not affect the dynamic response of the current inner loop. The DSP in each power module independently executes the generation of the base shift ratio and the generation of the ripple compensation shift ratio. The underlying control does not depend on the system controller, and the control between modules is independent of each other.

[0079] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein.

[0080] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A method for hierarchical decoupling and ripple feedforward suppression control of a solid-state transformer, characterized in that, The solid-state transformer includes a system controller and multiple power modules. Each power module includes a cascaded H-bridge and a multi-channel dual active bridge converter (DAB). The AC sides of the cascaded H-bridges of each power module are connected in series. The method includes: The system controller generates a three-phase total modulation wave based on the three-phase voltage and three-phase current of the power grid, normalizes the three-phase total modulation wave into a single module modulation wave, and broadcasts the single module modulation wave to the module controller DSP of each power module. For each power module, the DSP of the power module drives the cascaded H-bridge of the power module to perform AC-DC conversion based on the modulation wave of the single module, so as to establish a high voltage DC voltage; The DSP generates a base shift ratio based on the output voltage, input voltage, and input current of each DAB within the power module; The DSP extracts the second harmonic fluctuation component from the output voltage, performs phase compensation on the second harmonic fluctuation component to obtain a phase-compensated fluctuation signal, uses the phase-compensated fluctuation signal to generate a ripple compensation shift ratio, and superimposes the base shift ratio with the ripple compensation shift ratio to obtain the target shift ratio. The DSP sends the target shift ratio to the high-voltage side FPGA of the power module. The high-voltage side FPGA generates a square wave signal based on the target shift ratio and uses the square wave signal to drive the switching transistor of the high-voltage side H-bridge of the DAB in the power module to adjust the transmission power of the DAB.

2. The method according to claim 1, characterized in that, The system controller generates a three-phase total modulation wave based on the three-phase voltage and three-phase current of the power grid, and normalizes the three-phase total modulation wave into a single module modulation wave, including: The system controller performs dq coordinate transformation and current closed-loop regulation on the three-phase voltage and three-phase current of the power grid to generate a three-phase total modulation wave in the three-phase stationary coordinate system. The system controller obtains the sum of the output voltages of each power module in each phase; The system controller divides the total three-phase modulation wave of each phase by the sum of the output voltages of the corresponding phases to obtain the modulation wave of the individual module.

3. The method according to claim 2, characterized in that, The system controller performs dq coordinate transformation and current closed-loop regulation on the three-phase voltage and current of the power grid to generate a three-phase total modulation wave in a three-phase stationary coordinate system, including: The system controller obtains the grid voltage phase angle θ based on the three-phase grid voltage; The system controller performs dq coordinate transformation on the three-phase currents of the power grid to obtain the active current I. d and reactive current I q ; The system controller will control the active current I. d With active current given value I dref After comparison and proportional-integral adjustment, the d-axis proportional-integral output is obtained. This d-axis proportional-integral output is then compared with the output based on the reactive current I. q The WL decoupling compensation amount is superimposed and then combined with the d-axis grid voltage feedforward amount V. gd Superimposed, the d-axis voltage command V is obtained. d ; The system controller will control the reactive current. I q With reactive current setpoint I qref After comparison and proportional-integral adjustment, the q-axis proportional-integral output is obtained. This q-axis proportional-integral output is then compared with the output based on active current. I d The WL decoupling compensation is superimposed and then combined with the q-axis grid voltage feedforward quantity V. gq Superimposed, the q-axis voltage command V is obtained. q ; The system controller will transmit the d-axis voltage command V. d and the q-axis voltage command V q By performing an inverse dq / abc transformation based on the grid voltage phase angle θ, the three-phase total modulation wave in the three-phase stationary coordinate system is obtained.

4. The method according to claim 1, characterized in that, Each power module includes two sides, and each side includes two DABs; The DSP generates a base shift ratio based on the output voltage, input voltage, and input current of each DAB within the power module, including: For each surface, the DSP calculates the difference between the sum of the output voltages of the two DABs and the given reference value of the output voltage, and then uses proportional-integral adjustment to generate an initial value for the total current. I ref_total ; For each of the two DABs, the DSP calculates the difference between the input voltage of the DAB and the average input voltage of the two DABs, and then uses proportional-integral regulation to generate the voltage equalization regulation amount Δ. I bal and the equalization adjustment amount Δ I bal Superimposed on the given initial value of the total current I ref_total Generate the inner loop current setpoint I in_ref ; The DSP sets the current inner loop value. I in_ref Input current of the current path DAB I in After difference and proportional-integral adjustment, the basic shift ratio d is generated. base .

5. The method according to claim 1, characterized in that, The DSP extracts the second harmonic fluctuation component from the output voltage, performs phase compensation on the second harmonic fluctuation component to obtain a phase-compensated fluctuation signal, and uses the phase-compensated fluctuation signal to generate a ripple compensation shift ratio, including: The DSP filters the output voltage using a bandpass filter to extract the second harmonic fluctuation component; The DSP performs phase lag processing on the second harmonic fluctuation component through a first-order low-pass filter to obtain a phase-compensated fluctuation signal. The DSP multiplies the phase-compensated ripple signal by a gain coefficient to generate a ripple compensation shift ratio.

6. The method according to claim 5, characterized in that, The center frequency of the bandpass filter is twice the grid frequency.

7. The method according to claim 1, characterized in that, The DSP superimposes the base shift ratio and the ripple compensation shift ratio to obtain the target shift ratio, including: The DSP adds the base shift ratio to the ripple compensation shift ratio to obtain the composite shift ratio; The DSP performs amplitude limiting processing on the synthesized shift ratio to obtain the target shift ratio.

8. The method according to claim 1, characterized in that, The high-voltage side FPGA generates a square wave signal based on the target shift ratio, including: The high-voltage side FPGA generates two sets of square wave signals based on the target shift ratio; the phase difference between the two sets of square wave signals is determined by the target shift ratio. The high-voltage side FPGA uses two sets of square wave signals to drive the corresponding switching transistors of the DAB high-voltage side H-bridge in the power module.

9. The method according to claim 1, characterized in that, The power module also includes a low-voltage side FPGA, which generates a complementary square wave signal with a fixed duty cycle to drive the low-voltage side switching transistor of the DAB in the power module.

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