An ultra-low voltage input boost converter and a control method thereof

Abstract

The application discloses an ultra-low voltage input boost converter and a control method thereof. The converter comprises a power taking unit, a multi-phase boost module, a controller, a driving unit, a power supply module and an energy storage capacitor. The power taking unit is connected to a power taking section of a DC transmission line. The multi-phase boost module comprises a plurality of parallel boost branches. Each boost branch boosts the ultra-low voltage input from the power taking unit through an inductor, a main switch tube, a synchronous rectifier tube and a Schottky diode. The controller is used to select a target parameter combination according to a candidate parameter combination, power supply and load parameters, semiconductor parasitic and driving parameters and hardware delay tolerance parameters, generate a PWM signal to control the staggered operation of each boost branch, and output a voltage to an external load from the energy storage capacitor. The embodiment of the application can improve the output stability and working condition adaptability in the ultra-low voltage power taking scene of the DC transmission line. The application can be widely applied to the technical field of boost converters.

Description

Technical Field

[0001] This application relates to the field of boost converter technology, and in particular to an ultra-low voltage input boost converter and its control method. Background Technology

[0002] With the rapid development of smart grids and ultra-high voltage direct current (UHVDC) transmission technology, online safety monitoring, condition assessment, and fault early warning systems for transmission lines have become increasingly important. These distributed online monitoring devices (such as microprocessors and various environmental and electrical sensors) are typically installed thousands of kilometers away on transmission lines in harsh environments, and their power supply has always been a major bottleneck restricting the intelligent development of smart grids. In traditional power supply methods, chemical batteries have limited lifespans and extremely high replacement and maintenance costs; while external micro-energy harvesting technologies such as solar and wind power are heavily dependent on weather conditions, resulting in significant power supply instability. Therefore, directly extracting energy from the UHVDC transmission lines themselves—"on-site"—has become an ideal micro-energy power supply solution with high reliability and all-weather operation.

[0003] Currently, a practical and effective approach to extracting energy from ultra-high voltage direct current (UHVDC) transmission lines is to utilize the inherently small distributed resistance of the transmission lines themselves, generating a potential difference through bypass current shunting. However, this approach faces extreme challenges in practical engineering and circuit physics. To minimize line losses, UHVDC transmission lines have enormous cross-sectional areas and extremely low internal resistance per unit length. This means that within a limited parallel span, the usable potential difference that can be extracted is negligible, typically only a few hundred millivolts or even as low as 0.1V. According to the maximum power transfer theorem and the impedance voltage division principle, in order to obtain more voltage and extract sufficient power from these extremely low-resistance transmission lines, the equivalent impedance presented by the energy extraction converter on the input side must be designed to be sufficiently small. This requires the converter to possess the physical basis for efficient operation under extremely low input voltage and high current input conditions.

[0004] Existing conventional DC-DC boost converters exhibit severe performance degradation or even complete failure under such "ultra-low input" conditions. Firstly, pumping a weak voltage of approximately 0.1V to a standard DC bus voltage directly usable by a microprocessor or sensor requires extremely high conversion gain. In conventional continuous conduction mode (CCM) or simple boost topologies, such extreme gain leads to severe switching losses. In particular, the high-frequency capacitive polarization trapping effect from the output junction capacitance of MOSFETs and the nonlinear ohmic heat loss from the DC resistance (DCR) of passive components such as multiphase inductors are drastically amplified at the extremely low input reference of 0.1V, causing a precipitous drop in the overall system conversion efficiency.

[0005] Furthermore, the actual operating conditions of UHV lines are not static. Due to inter-regional grid dispatching and load changes, the main bus current in UHV lines fluctuates drastically, causing the available micro-voltage at the input of the energy harvesting device to change dynamically. When deploying the same set of fixed-parameter energy harvesting devices on lines of different specifications or with different load rates, existing converters often fail to match the input characteristics of the current line due to the lack of underlying parameter optimization and adaptive adjustment mechanisms. Existing technologies generally lack a control architecture capable of global dynamic matching based on weak input energy boundaries, and cannot automatically sense operating conditions and adjust the number of operating phases, switching frequency, and duty cycle of multi-phase interleaved parallel topologies in real time.

[0006] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0007] The main objective of this application is to propose an ultra-low voltage input boost converter and its control method, which efficiently and stably converts the extremely low voltage power in the DC transmission line energy harvesting section into the DC voltage required by the external load through a multi-phase boost structure, parameter optimization and adaptive PWM control.

[0008] To achieve the above objectives, one aspect of this application proposes an ultra-low voltage input boost converter, comprising: an energy harvesting unit, a multi-phase boost module, a controller, a drive unit, an energy supply module, and an energy storage capacitor. The multi-phase boost module includes several boost branches connected in parallel, each boost branch including an inductor, a main switch, a synchronous rectifier, a first Schottky diode, and a second Schottky diode. The controller is used to acquire candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters, and to determine each candidate parameter based on the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters. The system combines the achievable output voltage and conversion efficiency. Based on the achievable output voltage and conversion efficiency, a target parameter combination is determined from each of the candidate parameter combinations. Based on the target parameter combination, the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, the phase difference of each phase, the soft-switching timing compensation parameters, and the duty cycle of the main switch are determined. A PWM signal is generated based on the target parameter combination, the phase difference of each phase, the soft-switching timing compensation parameters, and the duty cycle of the main switch. The drive unit is used to control the on and off of each of the main switches and each of the synchronous rectifiers in the multiphase boost module according to the PWM signal.

[0009] Preferably, the ultra-low voltage input boost converter further includes a power supply module. The controller and the drive unit are both electrically connected to the power supply module. The power supply module provides operating voltage to the controller and the drive unit. The power harvesting unit includes a first power harvesting terminal and a second power harvesting terminal, which are respectively connected to the two ends of the power harvesting section of the DC transmission line. The first end of the inductor is connected to the positive output terminal of the power harvesting unit. The first end of the main switch and the first end of the synchronous rectifier are both connected to the second end of the inductor. The first Schottky diode is connected in parallel with the main switch, and the second Schottky diode is connected in parallel with the synchronous rectifier. The second terminal of the main switching transistor is connected to the negative output terminal of the energy harvesting unit. The second terminal of the synchronous rectifier is connected to the upper plate of the energy storage capacitor. The lower plate of the energy storage capacitor is connected to the negative output terminal of the energy harvesting unit. The control terminals of the main switching transistor and the synchronous rectifier are both connected to the drive unit. The controller is signal-connected to the drive unit. The controller and the drive unit are both electrically connected to the power supply module. The energy storage capacitor is electrically connected to the external load. The energy storage capacitor is used to output voltage to the external load. The controller is also used to adjust the PWM signal according to the working conditions of the DC transmission line energy harvesting section and the external load.

[0010] Preferably, the power supply module includes an energy harvesting chip and a power supply switching unit. The energy harvesting chip is used to accumulate startup energy from the DC transmission line energy harvesting section and provide startup voltage to the controller and the drive unit. The power supply switching unit is used to determine whether the energy storage capacitor meets the preset power supply conditions. When the energy storage capacitor meets the power supply conditions, the power supply source of the controller and the drive unit is switched to the energy storage capacitor, and the operating voltage is provided to the controller and the drive unit through the energy storage capacitor.

[0011] To achieve the above objectives, another aspect of this application proposes a control method for an ultra-low voltage input boost converter, which is implemented using the aforementioned ultra-low voltage input boost converter. The method includes the following steps: The power supply module is used to provide operating voltage to the controller and the drive unit; The controller acquires candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. Based on the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, it determines the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination. Based on the achievable output voltage and the conversion efficiency, it determines the target parameter combination among each candidate parameter combination. The controller determines the phase difference of each phase, soft-switching timing compensation parameters, and main switch duty cycle of the multiphase boost module based on the target parameter combination, the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, and generates a PWM signal based on the target parameter combination, the phase difference of each phase, the soft-switching timing compensation parameters, and the main switch duty cycle. The driving unit controls the on / off state of each main switch and each synchronous rectifier in the multiphase boost module according to the PWM signal. The energy storage capacitor outputs voltage to the external load. The controller adjusts the PWM signal according to the operating conditions of the DC transmission line energy harvesting section and the external load. The power supply and load parameters include DC input source voltage, load equivalent resistance, and target steady-state output voltage. The candidate parameter combination includes candidate number of phases, candidate inductance value, and candidate switching frequency. The target parameter combination includes target number of phases, target inductance value, and target switching frequency. The soft-switching timing compensation parameters include leading-edge dead time and synchronous rectifier early cutoff time.

[0012] Preferably, the power supply and load parameters include DC input source voltage, load equivalent resistance, and target steady-state output voltage; the candidate parameter combinations include candidate number of phases, candidate inductance value, and candidate switching frequency; and the target parameter combination includes target number of phases, target inductance value, and target switching frequency. The step of determining the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination based on the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, and determining the target parameter combination from each candidate parameter combination based on the achievable output voltage and the conversion efficiency, includes: Based on the power supply and load parameters, determine the single-phase inductor peak current, discharge duration, and load charge requirement corresponding to each candidate parameter combination. The capacitive charge cut-off amount corresponding to each candidate parameter combination is determined based on the semiconductor parasitic and driving parameters, and the net output charge amount corresponding to each candidate parameter combination is determined based on the capacitive charge cut-off amount and the load charge requirement. The duty cycle of the candidate main switch used to maintain the target steady-state output voltage is determined based on the net charge at the output terminal and the equivalent resistance of the load. Based on the single-phase inductor peak current, the discharge duration, and the hardware delay tolerance parameter, the feasibility of the candidate main switch duty cycle for each candidate parameter combination is verified. Based on the feasibility verification results, the achievable output voltage and achievable main switch duty cycle corresponding to each candidate parameter combination are determined. The conversion efficiency corresponding to each of the candidate parameter combinations is determined based on the power supply and load parameters, the semiconductor parasitic and driving parameters, the peak current of the single-phase inductor, the achievable output voltage, and the duty cycle of the achievable main switch. The target parameter combination is determined from each of the candidate parameter combinations based on the achievable output voltage and the conversion efficiency.

[0013] Preferably, the hardware delay tolerance parameters include the inductor saturation current limit, the maximum hardware duty cycle, and the minimum safe dead time of the system. The step of performing feasibility verification on the duty cycle of the candidate main switch for each candidate parameter combination based on the single-phase inductor peak current, the discharge duration, and the hardware delay tolerance parameters, and determining the achievable output voltage and achievable main switch duty cycle corresponding to each candidate parameter combination based on the feasibility verification results, includes: Determine whether the peak current of the single-phase inductor is not greater than the inductor saturation current limit; The on-time of the main switch is determined based on the duty cycle of the candidate main switch and the candidate switching frequency, and it is determined whether the sum of the on-time of the main switch, the discharge duration, and the minimum safe dead time of the system is not greater than the switching cycle corresponding to the candidate switching frequency. Determine whether the duty cycle of the candidate main switch is not greater than the maximum duty cycle of the hardware; The actual input power corresponding to the candidate parameter combination is determined based on the power supply and load parameters, the peak current of the single-phase inductor, and the discharge duration, and it is determined whether the actual input power is not less than the output power required by the external load under the target steady-state output voltage. When the peak current of the single-phase inductor is not greater than the inductor saturation current limit, and the sum of the main switch conduction time, the discharge duration, and the system minimum safe dead time is not greater than the switching cycle corresponding to the candidate switch frequency, and the duty cycle of the candidate main switch is not greater than the maximum duty cycle of the hardware, and the actual input power is not less than the output power required by the external load under the target steady-state output voltage, the duty cycle of the candidate main switch passes the feasibility check, and the duty cycle of the candidate main switch is taken as the main switch duty cycle corresponding to the candidate parameter combination, and the target steady-state output voltage is taken as the achievable output voltage corresponding to the candidate parameter combination; When the peak current of the single-phase inductor is greater than the inductor saturation current limit, or the sum of the main switch conduction time, the discharge duration, and the system minimum safe dead time is greater than the switching cycle corresponding to the candidate switch frequency, or the duty cycle of the candidate main switch is greater than the maximum duty cycle of the hardware, or the actual input power is less than the output power required by the external load under the target steady-state output voltage, it is determined that the duty cycle of the candidate main switch does not pass the feasibility check. The maximum duty cycle and the corresponding maximum output voltage of the corresponding candidate parameter combination under the feasibility check conditions are calculated. The maximum duty cycle is taken as the main switch duty cycle of the corresponding candidate parameter combination, and the maximum output voltage is taken as the achievable output voltage of the corresponding candidate parameter combination.

[0014] Preferably, determining the target parameter combination from each of the candidate parameter combinations based on the achievable output voltage and the conversion efficiency includes: Determine whether there exists an achievable output voltage that satisfies the target steady-state output voltage; When there exists an achievable output voltage that satisfies the target steady-state output voltage, among the candidate parameter combinations corresponding to the achievable output voltage that satisfies the target steady-state output voltage, the candidate parameter combination with the highest conversion efficiency is selected as the target parameter combination; If there is no achievable output voltage that satisfies the target steady-state output voltage, the candidate parameter combination with the highest achievable output voltage is selected as the target parameter combination.

[0015] Preferably, the hardware delay tolerance parameters further include Miller delay dead-time compensation and reverse backflow prevention shutdown margin, and the soft-switching timing compensation parameters are determined through the following steps: Determine the single-phase inductor peak current and discharge duration corresponding to the target parameter combination based on the power supply and load parameters; The capacitive charge cut-off amount corresponding to the target parameter combination is determined based on the semiconductor parasitic and driving parameters. The leading-edge dead-time parameters are determined based on the single-phase inductor peak current, the capacitive charge retention amount, and the Miller delay dead-time compensation amount. The conduction time of the synchronous rectifier tube is determined based on the discharge duration and the anti-reverse backflow shutdown margin. The soft-switching timing compensation parameters are determined based on the leading-edge dead time parameter and the conduction time of the synchronous rectifier.

[0016] Preferably, the duty cycle of the main switch is determined through the following steps: Based on the power supply and load parameters, determine the single-phase inductor peak current, discharge duration, and load charge requirement corresponding to the target parameter combination. The capacitive charge cut-off amount corresponding to each candidate parameter combination is determined based on the semiconductor parasitic and driving parameters, and the net output charge amount corresponding to the target parameter combination is determined based on the capacitive charge cut-off amount and the load charge requirement. The initial main switch duty cycle for maintaining the target steady-state output voltage is determined based on the net charge at the output terminal and the equivalent resistance of the load. The feasibility of the initial main switch duty cycle is verified. When the initial main switch duty cycle passes the feasibility check, the initial main switch duty cycle is determined as the main switch duty cycle; If the initial main switch duty cycle fails the feasibility check, the main switch duty cycle is determined based on the maximum duty cycle of the target parameter combination under the feasibility check conditions.

[0017] Preferably, the ultra-low voltage input boost converter further includes a power supply module, which includes an energy harvesting chip and a power supply switching unit. The control method further includes: The energy harvesting chip is used to accumulate startup energy from the DC transmission line energy harvesting section and to provide startup voltage for the controller and the drive unit; The power supply switching unit determines whether the energy storage capacitor meets the preset power supply conditions. When the energy storage capacitor meets the power supply conditions, the power supply source for the controller and the drive unit is switched to the energy storage capacitor, and the energy storage capacitor provides the operating voltage for the controller and the drive unit. The energy storage capacitor outputs voltage to an external load. The controller adjusts the PWM signal according to the operating conditions of the DC transmission line energy harvesting section and the external load.

[0018] The embodiments of this application include at least the following beneficial effects: This application provides an ultra-low voltage input boost converter and its control method. This scheme can optimize parameters according to the ultra-low voltage input and load changes in the DC transmission line energy harvesting scenario, and automatically select appropriate phase number, inductance value, switching frequency and duty cycle; it can determine the achievable output voltage and conversion efficiency based on hardware safety boundaries; it can prioritize the high-efficiency scheme when the target output voltage is achievable, and maintain the maximum safe output when the target output voltage is not achievable; it can realize soft switching and deep conduction mode through soft switching timing compensation, and reduce losses and ripple by combining multi-phase interleaving control, thereby improving system stability and providing long-term and stable power supply for online monitoring equipment on DC transmission lines. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the system framework of an ultra-low voltage input boost converter using an external power supply, as provided in an embodiment of this application. Figure 2 This is a schematic diagram of the system framework of an ultra-low voltage input boost converter using an energy harvesting chip for self-starting, as provided in an embodiment of this application. Figure 3 This is a schematic diagram illustrating the steps of a control method for an ultra-low voltage input boost converter provided in an embodiment of this application; Figure 4 This is a schematic diagram of the workflow of a control method for an ultra-low voltage input boost converter provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the working principle of a control method for an ultra-low voltage input boost converter provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] The concept of the present invention will now be explained in conjunction with the background art.

[0023] In UHV power line energy extraction applications, due to the extremely low bus resistance, the effective voltage drop is typically in the hundreds of millivolts or even as low as 0.1V. Under these extremely low voltage and high-gain conditions, traditional power electronic systems and conventional continuous conduction mode (CCM) or fixed-parameter boost converters experience nonlinear amplification of high-frequency polarization cutoff losses from the semiconductor switching transistor output junction capacitance and ohmic heat losses from the inductor's DC resistance (DCR). This leads to a sharp increase in the system's equivalent input impedance, and may even result in system crashes or power extraction failures due to the inability to achieve effective impedance matching with the transmission line's internal resistance. When UHV line load fluctuations cause drastic changes in input potential and energy boundaries, systems with fixed parameters cannot automatically adjust phase switching, frequency modulation, and duty cycle. Furthermore, they lack underlying physical defenses and adaptive degradation protection mechanisms under extreme heavy loads or voltage dips, making them highly susceptible to magnetic saturation and system collapse. Simultaneously, traditional systems heavily rely on external stable auxiliary power supplies and cannot achieve energy extraction and long-term fully automated independent operation in passive extreme environments.

[0024] In summary, there is an urgent need in this field for a high-gain adaptive converter technology capable of adapting to ultra-low voltage input. This technology requires achieving lossless soft switching in deep discontinuous conduction mode (DCM) to significantly reduce internal parasitic losses and equivalent internal resistance. Simultaneously, it needs to introduce an automatic dynamic adaptive control algorithm, enabling the converter to automatically adjust phase switching, frequency, and duty cycle according to the varying actual power transmission conditions of ultra-high voltage lines. This will allow for adaptive, efficient, and stable long-term self-operating power supply for monitoring equipment.

[0025] Addressing the challenges of extremely low input potential and extremely high boost ratio in the energy extraction requirements of equipment in ultra-high voltage direct current (UHVDC) transmission lines, as well as the fundamental technical difficulties of traditional DC converters such as sharp efficiency drops under extreme physical boundaries, inability to adaptively optimize, and difficulty in independent cold start-up, this application provides an ultra-low voltage input boost converter and its control method for power extraction from DC transmission lines. This converter can efficiently boost extremely low and weak environmental potentials to a universal standard DC bus voltage that meets the needs of various equipment. Through a global parameter optimization method based on a non-approximate closed-loop algebraic solution and a nonlinear dynamic impedance penalty model, it achieves optimal parameter design for the number of phases, inductance, and switching frequency in a three-dimensional parameter space. Its dynamic adaptive frequency and phase modulation control technology based on the global charge conservation equation, implemented through microcontroller numerical control... Iterative automatic phase switching and duty cycle adjustment prioritize the target output voltage and track the system's global peak efficiency. A dynamic protection mechanism with multiple physical boundary verifications and adaptive degradation operation automatically triggers degradation when faced with unreasonable demand parameters or extreme heavy load conditions, ensuring the system outputs the maximum steady-state voltage within safe physical boundaries. Through lossless soft-switching precise timing self-correction technology for deep discontinuous mode (DCM), and by calculating the natural zero-crossing point of the current, it precisely configures appropriate dead zones and cutoff pulse widths, ensuring low-loss soft-switching operation of the multi-phase circuit during microcontroller automatic adjustment. A handover operation mechanism that meets the initial drive energy and internal closed-loop power supply requirements through energy harvesting enables the converter to achieve long-term independent bootstrapping cold start and self-operation in extreme environments without external main power.

[0026] Figure 1 This is a schematic diagram of the overall structural framework of an ultra-low voltage input boost converter provided in an embodiment of this application, with reference to... Figure 1This invention provides an ultra-low voltage input boost converter, including an energy harvesting unit, a multi-phase boost module, a controller, a drive unit, a power supply module, and an energy storage capacitor. The multi-phase boost module includes several boost branches connected in parallel. Each boost branch includes an inductor, a main switch, a synchronous rectifier, a first Schottky diode, and a second Schottky diode. The power supply module provides operating voltage to the controller and drive unit. The controller acquires candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. The system determines the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination. Based on the achievable output voltage and conversion efficiency, it determines the target parameter combination from among the candidate parameter combinations. Based on the target parameter combination, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters, it determines the phase difference of each phase of the multiphase boost module, soft-switching timing compensation parameters, and main switch duty cycle. Based on the target parameter combination, phase difference of each phase, soft-switching timing compensation parameters, and main switch duty cycle, it generates a PWM signal. The drive unit is used to control the conduction and cutoff of each main switch and each synchronous rectifier in the multiphase boost module according to the PWM signal.

[0027] In some embodiments, the energy harvesting unit includes a first energy harvesting terminal and a second energy harvesting terminal, which are respectively connected to the two ends of the DC transmission line energy harvesting section. The first end of the inductor is connected to the positive output terminal of the energy harvesting unit. The first end of the main switch and the first end of the synchronous rectifier are both connected to the second end of the inductor. The first Schottky diode is connected in parallel with the main switch, and the second Schottky diode is connected in parallel with the synchronous rectifier. The second end of the main switch is connected to the negative output terminal of the energy harvesting unit. The second end of the synchronous rectifier is connected to the upper plate of the energy storage capacitor. The lower plate of the energy storage capacitor is connected to the negative output terminal of the energy harvesting unit. The control terminals of the main switch and the synchronous rectifier are both connected to the drive unit. The controller is signal-connected to the drive unit. The controller and the drive unit are both electrically connected to the power supply module. The energy storage capacitor is electrically connected to the external load. The energy storage capacitor is used to output voltage to the external load. The controller is also used to adjust the PWM signal according to the working conditions of the DC transmission line energy harvesting section and the external load.

[0028] In some embodiments, the power supply module includes an energy harvesting chip and a power supply switching unit. The energy harvesting chip is used to accumulate startup energy from the DC transmission line energy harvesting section and provide startup voltage to the controller and drive unit. The power supply switching unit is used to determine whether the energy storage capacitor meets the preset power supply conditions. When the energy storage capacitor meets the power supply conditions, the power supply source of the controller and drive unit is switched to the energy storage capacitor, and the energy storage capacitor provides the operating voltage to the controller and drive unit.

[0029] Specifically, in this embodiment, when the power supply module operates using an external power supply, the overall structure of the ultra-low voltage input boost converter can be as follows: Figure 1 As shown. (Refer to...) Figure 1 The converter includes an energy harvesting unit, a multi-phase boost module, a controller MCU, a drive unit (Drive), and a power supply module (…). Figure 1 (Not shown in the image) and energy storage capacitor C0. The energy harvesting unit includes positive and negative output terminals. Figure 1 The symbol in the middle represents the power supply. The two input terminals of the energy harvesting unit are connected to the two ends of the energy harvesting section of the DC transmission line. It is used to utilize the small distributed resistance of the DC transmission line itself to generate a potential difference through bypass shunting to obtain energy and provide the DC input source voltage for the converter. The multiphase boost module is connected between the energy harvesting unit and the energy storage capacitor. It is used to boost the DC input source voltage output by the energy harvesting unit and store it in the energy storage capacitor. The energy storage capacitor then supplies power to the external load R. load Power supply; the controller outputs multiple PWM (Pulse Width Modulation) control signals (i.e., PWM1-PWM) through the drive unit. n This controls the on and off states of each switch in the multiphase boost module to achieve boost conversion of weak input voltages.

[0030] Reference Figure 1 In this embodiment, the multiphase boost module adopts a multiphase (N-phase) interleaved Boost topology. This topology enables the converter's front-end to efficiently pump up and convert the weak ultra-low voltage input (as low as 0.1V) collected from the ultra-high voltage line operating environment into standard DC voltages (such as 3.3V and 5V) used by the back-end standard microprocessor (or sensor). To achieve extremely high conversion efficiency (over 90%) under extremely low input voltage and weak energy, the converter, after being configured using this design method, can operate strictly in discontinuous conduction mode (DCM mode), and the switching transistors can be strictly in soft-switching conditions. The optimal matching between the system input impedance and the internal resistance of the energy harvesting front-end can be achieved in the microcontroller system through precise parameter optimization methods, thereby realizing the optimal circuit design.

[0031] Specifically, refer to Figure 1 A multiphase boost module may include N phases connected in parallel as boost branches, and each phase boost branch includes an inductor (i.e., inductors L1-L). n ), main switch transistor (i.e. Figure 1 The MOSFET device located at the bottom (hereinafter referred to as the lower transistor in some simplified descriptions), and the synchronous rectifier diode (i.e. Figure 1The MOSFET device located at the top (hereinafter referred to as the upper MOSFET in some simplified descriptions), the first Schottky diode, and the second Schottky diode are all connected to the positive output terminal of the energy harvesting unit in each phase boost branch. The output side of each phase inductor is connected to the corresponding main switch and synchronous rectifier. The main switch is used to allow the corresponding inductor to absorb and store energy from the energy harvesting unit when it is turned on, and the synchronous rectifier is used to release the inductor energy to the energy storage capacitor and the external load when the main switch is turned off. (Refer to...) Figure 1 In this embodiment, both the main switch and the synchronous rectifier can be implemented using MOSFET devices (Metal-Oxide-Semiconductor Field-Effect Transistors), which specifically include a first input terminal, a second input terminal, and a control terminal. To clarify its circuit characteristics, Figure 1 The diagram also shows the body diodes and parasitic output capacitors of the main switch and synchronous rectifier. The body diode is a diode connected to both the first and second terminals, and the parasitic output capacitor is a capacitor connected in parallel with the body diode. The body diode and parasitic output capacitor are not additional, independently installed components, but rather inherent parasitic structures of the MOSFET device itself. It is particularly important to note that due to the low equivalent internal resistance of DC transmission lines, the input voltage obtainable within a limited energy extraction distance is typically low, possibly even as low as approximately 0.1V. To achieve synchronous rectification using MOSFETs under ultra-low voltage conditions, the body diodes of typical MOSFET switches often fail to conduct due to excessively high forward voltage. To prevent the body diode from failing due to excessive forward voltage drop caused by an excessively low input voltage, this embodiment connects Schottky diodes (i.e., the first Schottky diode and the second Schottky diode) in parallel at both the upper and lower switches of the single-phase boost branch. Figure 1 (The diodes shown are solid black). Therefore, at the switching node of a single branch, the output capacitance of two MOSFETs and the nonlinear junction capacitance of two Schottky diodes are actually connected in parallel. Based on the above multi-phase interleaved parallel structure, this embodiment, on the one hand, prevents excessive current in a single-phase branch by sharing the large input current through multi-phase parallel connection; on the other hand, it can reduce the input current ripple by driving the PWM signals of each phase in a staggered manner.

[0032] In order to control the operation of the multiphase boost module under ultra-low voltage input scenarios, this embodiment sets up a controller and a drive unit. The controller and the drive unit are connected by signals, and the drive unit is connected to the main switch tube and synchronous rectifier tube in each phase boost branch. The controller determines the target parameter combination suitable for the current operating conditions based on candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. It further determines the phase difference between each phase, soft-switching timing compensation parameters, and the duty cycle of the main switching transistors. Subsequently, the controller generates a PWM signal, and the drive unit controls the on / off state of each main switching transistor and synchronous rectifier transistor according to this PWM signal. This allows the multiphase boost module to operate according to the target number of phases, target inductance value, target switching frequency, and corresponding duty cycle. In the candidate parameter combinations, the target number of phases is controlled by inputting signals to different circuits. In some conventional cases, the designer usually directly selects or predetermines the value of inductor L. In this case, the target inductance value in the candidate parameter combinations is a fixed value. This embodiment can calculate the optimal solution for the remaining parameters, allowing the microcontroller to directly set the circuit to its maximum value when the circuit parameters are completely fixed. If the designer does not select the value of inductor L, the entire circuit can approach the theoretical optimal value. To minimize input current ripple and achieve current sharing across phases, the PWM drive signals for each phase are sequentially delayed by 360° / N phases on the time axis (i.e., the time delay is...). ,in , The time of a single switching cycle is N, which is the number of phases of the currently parallel boost branch. (This refers to the current switching frequency). Furthermore, under this parameter adjustment, the entire circuit will automatically enter a deep DCM mode with soft switching. It can be understood that this control process allows the converter to operate without relying on fixed parameters, instead selecting optimal phase number, frequency, duty cycle, and switching sequence based on current operating conditions. It can also dynamically adjust the PWM signal according to the power extraction section of the DC transmission line and the operating conditions of the external load, thereby ensuring that the current operating phase number, switching frequency, duty cycle, and other parameters are in an optimal state to adapt to changes in input voltage and load requirements.

[0033] In this embodiment, the energy storage capacitor is used to receive the boosted electrical energy and output voltage to an external load. This external load can be a microprocessor, various environmental and electrical sensors, monitoring equipment, or other low-power electrical devices installed on the DC transmission line. The power supply module provides operating voltage to the controller and drive unit, enabling them to operate continuously, and provides gate drive voltage to the control terminal of the multiphase boost module, thereby controlling the switching of each phase branch.

[0034] For example, when the power supply module is a power source such as a battery, it can directly provide energy to the MOSFET drive of the multiphase boost module. If there is no external power source such as a battery, the power supply module can be designed to include an energy harvesting chip and a power supply switching unit, as shown in the reference. Figure 2 The energy harvesting chip is used to accumulate startup energy from the DC transmission line energy harvesting section during the initial stage of the system (i.e., Figure 2 Energy Harvesting in the middle), and for the controller (i.e. Figure 2 MCU and drive unit (i.e. Figure 2 The Drive module provides the starting operating voltage. After the multiphase boost module starts working, the energy storage capacitor gradually builds up the output voltage. At this time, the power supply switching unit determines whether the energy storage capacitor meets the power supply conditions for driving the controller and drive unit. If it does, the power supply source for the controller and drive unit is switched to the energy storage capacitor. Thus, the system can transition from initial energy accumulation to a state where the controller and drive unit are maintained by its own output, reducing the dependence on external auxiliary power supply. This is suitable for monitoring scenarios of remote, harsh, and difficult-to-maintain DC transmission lines.

[0035] It can be recognized that this embodiment reduces conduction losses in low-voltage scenarios by using Schottky diodes, thereby enabling boost conversion and ultra-low voltage energy harvesting even when the voltage of the DC transmission line energy harvesting section is extremely low; it reduces single-phase current pressure by using multi-phase parallel connection and reduces input ripple by designing phase differences between phases; it improves the low efficiency and poor adaptability of traditional fixed-parameter converters in ultra-low voltage energy harvesting scenarios by adaptively adjusting the number of phases, switching frequency, duty cycle and soft-switching timing through parameter optimization, thereby improving the system operating efficiency; and it achieves startup and long-term self-powered operation under conditions without external power supply through the design of energy harvesting chip and power supply switching unit.

[0036] Please see Figure 3 This application also provides a control method for an ultra-low voltage input boost converter, which is implemented using the aforementioned ultra-low voltage input boost converter. The method includes the following steps: S101. Obtain candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters through the controller. Determine the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination based on the power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. Determine the target parameter combination among each candidate parameter combination based on the achievable output voltage and conversion efficiency. In some embodiments, the power supply and load parameters include DC input source voltage, load equivalent resistance, and target steady-state output voltage; candidate parameter combinations include candidate number of phases, candidate inductance value, and candidate switching frequency; and the target parameter combination includes target number of phases, target inductance value, and target switching frequency. The achievable output voltage and conversion efficiency corresponding to each candidate parameter combination are determined based on the power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. The target parameter combination is then determined from the candidate parameter combinations based on the achievable output voltage and conversion efficiency, including: S1011. Determine the single-phase inductor peak current, discharge duration and load charge requirement corresponding to each candidate parameter combination based on the power supply and load parameters. S1012. Determine the capacitive charge cut-off amount corresponding to each candidate parameter combination based on the semiconductor parasitic and driving parameters, and determine the net output charge amount corresponding to each candidate parameter combination based on the capacitive charge cut-off amount and the load charge requirement. S1013. Determine the duty cycle of the candidate main switch for maintaining the target steady-state output voltage based on the net charge at the output terminal and the equivalent resistance of the load. S1014. Based on the peak current of the single-phase inductor, the discharge duration, and the hardware delay tolerance parameters, perform a feasibility check on the duty cycle of the candidate main switch for each candidate parameter combination. Based on the feasibility check results, determine the achievable output voltage and achievable main switch duty cycle corresponding to each candidate parameter combination. In some embodiments, hardware delay tolerance parameters include inductor saturation current limits, maximum hardware duty cycle, and minimum system dead time. Feasibility is verified for the duty cycle of the candidate main switch for each candidate parameter combination based on the single-phase inductor peak current, discharge duration, and hardware delay tolerance parameters. Based on the feasibility verification results, the achievable output voltage and achievable main switch duty cycle corresponding to each candidate parameter combination are determined, including: S10141. Determine whether the peak current of a single-phase inductor is not greater than the inductor saturation current limit. S10142. Determine the on-time of the main switch based on the duty cycle and frequency of the candidate main switch, and determine whether the sum of the on-time of the main switch, the discharge duration, and the minimum safe dead time of the system is not greater than the switching cycle corresponding to the candidate switching frequency. S10143. Determine whether the duty cycle of the candidate main switch is not greater than the maximum duty cycle of the hardware; S10144. Determine the actual input power corresponding to the candidate parameter combination based on the power supply and load parameters, the peak current of the single-phase inductor, and the discharge duration, and determine whether the actual input power is not less than the output power required by the external load under the target steady-state output voltage. S10145. When the peak current of a single-phase inductor is not greater than the inductor saturation current limit, and the sum of the main switch conduction time, discharge duration, and minimum safe dead time of the system is not greater than the switching cycle corresponding to the candidate switching frequency, and the duty cycle of the candidate main switch is not greater than the maximum duty cycle of the hardware, and the actual input power is not less than the output power required by the external load under the target steady-state output voltage, the duty cycle of the candidate main switch passes the feasibility verification, and the duty cycle of the candidate main switch is taken as the main switch duty cycle of the corresponding candidate parameter combination, and the target steady-state output voltage is taken as the achievable output voltage of the corresponding candidate parameter combination. S10146. When the peak current of a single-phase inductor is greater than the inductor saturation current limit, or the sum of the main switch conduction time, discharge duration, and minimum safe dead time of the system is greater than the switching cycle corresponding to the candidate switch frequency, or the duty cycle of the candidate main switch is greater than the maximum duty cycle of the hardware, or the actual input power is less than the output power required by the external load under the target steady-state output voltage, the duty cycle of the candidate main switch fails the feasibility check. Calculate the maximum duty cycle and the corresponding maximum output voltage of the corresponding candidate parameter combination under the condition of satisfying the feasibility check. Use the maximum duty cycle as the main switch duty cycle of the corresponding candidate parameter combination, and use the maximum output voltage as the achievable output voltage of the corresponding candidate parameter combination.

[0037] S1015. Determine the conversion efficiency corresponding to each candidate parameter combination based on power supply and load parameters, semiconductor parasitic and drive parameters, single-phase inductor peak current, achievable output voltage, and achievable main switch duty cycle. S1016. Determine the target parameter combination from among the candidate parameter combinations based on the achievable output voltage and conversion efficiency.

[0038] In some embodiments, determining a target parameter combination from among the candidate parameter combinations based on the achievable output voltage and conversion efficiency includes: S10161. Determine whether there exists an achievable output voltage that satisfies the target steady-state output voltage; S10162. When there is an achievable output voltage that satisfies the target steady-state output voltage, among the candidate parameter combinations corresponding to the achievable output voltage that satisfies the target steady-state output voltage, the candidate parameter combination with the highest conversion efficiency is selected as the target parameter combination. S10163. When there is no achievable output voltage that satisfies the target steady-state output voltage, select the candidate parameter combination with the highest achievable output voltage as the target parameter combination.

[0039] S102. The controller determines the phase difference of each phase of the multiphase boost module, the soft-switching timing compensation parameters, and the duty cycle of the main switch tube according to the target parameter combination, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. It also generates a PWM signal according to the target parameter combination, phase difference of each phase, soft-switching timing compensation parameters, and the duty cycle of the main switch tube. In some embodiments, the hardware delay tolerance parameters also include Miller delay dead-time compensation and reverse backflow prevention turn-off margin. The soft-switching timing compensation parameters are determined through the following steps: S301. Determine the single-phase inductor peak current and discharge duration corresponding to the target parameter combination based on the power supply and load parameters. S302. Determine the capacitive charge cut-off amount corresponding to the target parameter combination based on the semiconductor parasitic and driving parameters; S303. Determine the leading edge dead time parameters based on the peak current of the single-phase inductor, the amount of capacitive charge retention, and the amount of Miller delay dead time compensation. S304. Determine the conduction time of the synchronous rectifier tube based on the discharge duration and the reverse backflow prevention shutdown margin. S305. Determine the soft-switching timing compensation parameters based on the leading-edge dead time parameter and the conduction time of the synchronous rectifier.

[0040] In some embodiments, the power supply and load parameters include the DC input source voltage, the load equivalent resistance, and the target steady-state output voltage. The duty cycle of the main switch is determined through the following steps: S401. Determine the single-phase inductor peak current, discharge duration and load charge requirement corresponding to the target parameter combination based on the power supply and load parameters. S402. Determine the capacitive charge cut-off amount corresponding to each candidate parameter combination based on the semiconductor parasitic and driving parameters, and determine the net output charge amount corresponding to the target parameter combination based on the capacitive charge cut-off amount and the load charge requirement. S403. Determine the target parameter combination based on the net charge at the output terminal and the equivalent resistance of the load to maintain the initial duty cycle of the main switch for the target steady-state output voltage; S404. Perform a feasibility check on the initial main switch duty cycle; S405. When the initial main switch duty cycle passes the feasibility verification, the initial main switch duty cycle is determined as the main switch duty cycle. S406. If the initial main switch duty cycle fails the feasibility check, the main switch duty cycle shall be determined based on the maximum duty cycle of the target parameter combination under the condition of satisfying the feasibility check.

[0041] S103. The drive unit controls the on and off of each main switch and each synchronous rectifier in the multiphase boost module according to the PWM signal.

[0042] In some embodiments, the power supply module includes an energy harvesting chip and a power supply switching unit, and the control method further includes: S501 uses an energy harvesting chip to accumulate startup energy from the DC transmission line energy harvesting section and provides startup voltage for the controller and drive unit; S502. Determine whether the energy storage capacitor meets the preset power supply conditions through the power supply switching unit. S503. When the energy storage capacitor meets the power supply conditions, the power supply source of the controller and drive unit is switched to the energy storage capacitor, and the energy storage capacitor provides the working voltage to the controller and drive unit. S504: Outputs voltage to an external load through an energy storage capacitor; S505: The controller adjusts the PWM signal according to the operating conditions of the DC transmission line energy extraction section and the external load.

[0043] Specifically, the following section will first introduce the "known parameters" that need to be obtained based on existing components and design requirements in this embodiment. The parameters described below all have the same meaning in the formulas below.

[0044] In this embodiment, the power supply and load parameters specifically include: (DC input source voltage): The extremely low DC source voltage equivalent to the input terminal of the converter from the ultra-high voltage energy extraction line.

[0045] (Equivalent load resistance): The equivalent load resistance of the sensors or batteries connected to the back end of the converter.

[0046] (Target steady-state output voltage): The constant DC voltage that the converter expects and prioritizes to maintain in order to drive the back-end microprocessor or sensor. Current required to be drawn from the front end. It is entirely adaptively adjusted by the system based on the global charge conservation.

[0047] The above parameters can be determined according to the actual design requirements of the work scenario and can be updated according to the actual working conditions.

[0048] Semiconductor parasitic and driving parameters specifically include: (Total Gate Charge): The total gate charge required for the MOSFET to turn on, used to accurately assess multi-path drive losses. .

[0049] (Drive voltage): The actual high-level voltage applied to the gate of the semiconductor switch.

[0050] (Nominal nonlinear output charge): MOSFET in The equivalent output charge under the test voltage is used to... Perform full voltage domain integration to calculate the cut-off charge.

[0051] (Nominal reference output capacitance): Semiconductor manufacturers typically provide the junction capacitance value measured at a specific test voltage (most commonly 12V, but 25V for some special transistors). It serves as the mathematical anchor point for determining the entire nonlinear curve.

[0052] (Zero-bias junction capacitance) and (PN junction built-in potential): A nonlinear constant used to construct the junction capacitance polarization equation, which together determine the lower limit of energy dissipation during soft switching.

[0053] and The reference inductance value of the power inductor for the selected specific package size ( ) and their corresponding nominal DC resistance ( ).

[0054] The lower limit of the inductor's basic package and physical contact resistance is used to prevent the mathematical divergence that the resistance becomes zero when the inductance value approaches zero.

[0055] (Winding process nonlinearity index): An empirical constant determined by the device packaging structure, winding fill factor, and core material. Its value is typically within... The value between these values ​​can be obtained by fitting the data from the device datasheet. In this embodiment, the index is defined as follows: .

[0056] (Total parasitic impedance of charging circuit): Includes the DC resistance (DCR) of the single-phase filter inductor and the on-resistance of the main switch (lower transistor). The sum of . Since DCR is a variable with respect to inductance L, The nonlinear function of inductance L is:

[0057] (Total parasitic impedance of the discharge circuit): including the DC resistance (DCR) of the single-phase filter inductor and the on-resistance of the synchronous rectifier diode (upper diode). The sum of . Since DCR is a variable about L, The nonlinear function of L is:

[0058] in, , , Isolinear parasitic parameters are determined based on the official datasheet of the selected semiconductor device at a specific driving voltage. Direct extraction under constraints; and , and For nonlinear constants, the information can be obtained from the device datasheet. and Characteristic curves are obtained by directly reading characteristic curve parameters or by extracting them using mathematical fitting techniques such as least squares. This is the drain-source voltage of the MOSFET. This refers to the junction capacitance of a Schottky diode. This is the reverse voltage of the Schottky diode.

[0059] Boundary conditions and hardware delay tolerance parameters are mainly used to prevent extreme cases from occurring. In this embodiment, they specifically include: (Miller Delay Dead Zone Compensation): A time margin added on top of the theoretical dead zone calculation value to counteract the linear current tailing caused by the Miller Plateau when the actual MOSFET is turned off.

[0060] (Anti-reverse backflow turn-off margin): This is the time compensation amount for the signal transmission and turn-off delay inherent in the immune gate driver, which forces the upper transistor to turn off in advance to prevent reverse backflow of charge from the output capacitor.

[0061] (Inductor Saturation Current Limit): The absolute upper limit of the physical saturation current of the selected filter inductor. Used to prevent core saturation failure during extremely low voltage and high current extraction.

[0062] (Maximum duty cycle of controller hardware): The maximum duty cycle limit that the microprocessor or driver chip is allowed to output (usually 0.9 or 0.95, to allow time for bootstrap capacitor charging or signal dead time).

[0063] (System minimum safe dead time): The absolute physical time limit to prevent shoot-through between upstream and downstream pipes.

[0064] In this embodiment, at the start of the control process, the power supply module first provides operating voltage to the controller and drive unit, enabling the controller to perform subsequent calculations and control operations. The drive unit can drive the main switching transistors and synchronous rectifier transistors in each phase boost branch to turn on and off according to the PWM signal output by the controller. For application scenarios without external auxiliary power supply, the power supply module can accumulate startup energy from the DC transmission line energy harvesting section through the energy harvesting chip. After the energy storage capacitor reaches the preset power supply conditions, the power supply switching unit switches the power source of the controller and drive unit to the energy storage capacitor, thereby realizing the system's self-starting and self-powered operation.

[0065] After the controller obtains the operating voltage and begins operation, it first acquires candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. The candidate parameter combinations include candidate number of phases, candidate inductance values, and candidate switching frequencies. In some cases, the candidate inductance values ​​can be fixed values ​​pre-specified by the designer. Power supply and load parameters include the DC input source voltage, the equivalent load resistance, and the target steady-state output voltage; their specific values ​​can be determined by the specific operating conditions of the DC transmission line's energy extraction terminal and the external load. Semiconductor parasitic and drive parameters characterize the parasitic losses introduced by actual devices such as switches, inductors, and diodes. Hardware delay tolerance parameters characterize physical constraints such as inductor saturation current limits, maximum hardware duty cycle, and minimum system dead time. These parameters can be used to verify the feasibility of the duty cycle of the candidate main switch obtained through parameter optimization and provide a reference for the soft-switching timing control in this embodiment.

[0066] For each candidate parameter combination, the controller calculates its achievable output voltage and conversion efficiency under the current input and load conditions, and selects the target parameter combination accordingly. When calculating each candidate parameter combination, the controller first determines the peak current of the single-phase inductor, the discharge duration, and the load charge demand based on the power supply and load parameters, thereby determining the energy storage and release capacity of each phase boost branch in one switching cycle.

[0067] For example, refer to Figure 4 and Figure 5 The workflow of this embodiment will be described below. To ensure the logical coherence of the description of the process, the order in which some parameters are solved in this parameter optimization process may be different from the order described in the aforementioned scheme.

[0068] Firstly, in this embodiment, the peak current of a single-phase inductor can be determined by modeling the circuit voltage and current and analyzing the peak current. The specific process is as follows: A first-order ordinary differential equation is established for the circuit operating under ultra-low voltage conditions. Let the DC input source voltage be... The single-phase filter inductor value is (i.e., candidate inductance value), the total parasitic impedance of the charging circuit is ( For the DC resistance of the inductor and the on-resistance of the lower transistor The sum of ( ). When the current tube is conducting ( ) When ), the circuit is only affected and Constraints, establish state equation (1): (1) The entire circuit is in DCM, which means it meets the discontinuous state condition, where t is the time variable. The total equivalent on-resistance of the charging circuit corresponding to the candidate inductance value L, and the inductor input current. By performing an absolute definite integral on the above differential equation, we can obtain an exact exponential model of the current changing with time, as shown in equation (2): (2) Switching time t = D / f sw e is a natural constant, where D is the duty cycle of the candidate main switch, which is still an unknown parameter at this point, and f SW Given the candidate switching frequency, substituting it into equation (2) yields the single-phase inductor peak current I, which eliminates the linear approximation error. pk : (3) Secondly, this embodiment intercepts parasitic capacitive charges in the circuit. Modeling is used to determine the amount of capacitive charge retention.

[0069] The system energy is transferred to the back-end voltage output V. out Previously, parasitic capacitance in the circuit would consume some of the electrical energy. In this circuit, capacitive capacitance is used to retain the charge. The power consumption mainly comes from the output capacitance of the MOSFET. junction capacitance of Schottky diode The consumption on the surface, where the nominal charge is known. Back-calculate the nominal reference output capacitor The consumption of this part is related to the voltage in a strongly nonlinear physical model as shown in equation (4): (4) In equation (4), It is a voltage variable, with a value range of 0 to V. out， The junction capacitance of a Schottky diode varies with... A changing function, That is, the aforementioned zero-bias junction capacitance. The aforementioned built-in potential of the PN junction belongs to the semiconductor parasitic and driving parameters. For the nonlinear capacitor in equation (4) in the full voltage domain ( By performing an absolute definite integral, the capacitive cut-off charge shown in equation (5) can be obtained. : (5) Integrating equations (4) and (5) simultaneously, in order to directly call the nominal charge given in the datasheet in the microprocessor calculation. ,because: (6) The total amount of charge consumed by the MOSFET switching section for: (7)

[0070] If the device datasheet provides the energy equivalent capacitance or charge equivalent capacitance Then directly substitute If not provided, the nonlinear integral model in this embodiment will be used.

[0071] It is important to note that, in order to achieve synchronous rectification using MOSFETs under ultra-low voltage conditions, the body diodes of ordinary MOSFET switches typically fail to conduct due to excessive forward voltage. To prevent the body diodes from failing due to excessive forward voltage drop caused by insufficient input voltage, this patented solution connects Schottky diodes in parallel at both the upper and lower switching transistors in the single-phase boost branch. Therefore, at a single switching node, the parasitic output capacitance of two MOSFETs and the nonlinear junction capacitance of two Schottky diodes are actually connected in parallel. The coefficients 2 and 4 in the first and second terms of the formula (single-electrode integral coefficient 2 multiplied by the number of devices 2) are derived from this actual hardware topology, thus revealing the capacitive charge that will inevitably be lost in the system. : (8) Subsequently, this embodiment achieves optimal design by matching the optimal input impedance based on charge conservation.

[0072] When powering a backend microprocessor or sensor, the circuit needs to maintain a steady-state target output voltage at all times. Maintain at the target operating voltage At this time, the load current is , The load is the equivalent resistance. To maintain global charge conservation at the output node, the microprocessor needs to dynamically adjust the duty cycle D (i.e., the duty cycle of the candidate master switch) through a closed-loop algorithm so that the net charge rate input in the multiphase circuit is exactly equal to the load consumption rate.

[0073] Since electrical energy flows to the load resistor during the discharge phase, the net discharge charge is calculated as shown in equation (16) (see below). (i.e., the amount of charge required) The absolute time point at which the inductor current naturally crosses zero (i.e., the duration of discharge), minus the capacitively trapped charge. The net charge at the output terminal can then be obtained, and the true equivalent resistance flowing to the load, as shown in equation (9), can then be established. Voltage transcendence equation: (9) Because the circuit equipment needs to maintain the target steady-state operating voltage ,so As a known constant, the duty cycle D is the only control variable in the charge calculation equation (15) during the charging period (see below). The rest are known quantities among candidate parameter combinations, power supply and load parameters, and semiconductor parasitic and drive parameters. Based on the above equation, the MCU microcontroller can approximate the value of the duty cycle D required by the converter to maintain the output voltage at the standard voltage by solving Newton's method in mathematical tools (such as Matlab, Mathematica, etc.), thereby determining the value of the duty cycle of the candidate main switch (this process is to determine the duty cycle of the candidate main switch used to maintain the target steady-state output voltage based on the net charge at the output terminal and the equivalent resistance of the load).

[0074] In practice, such as the required load R in the design load Excessive weight causes the power required for output to unreasonably exceed the input power at the front end. In this case, the calculated D value is unreasonable, and forcibly calculating an unreasonable D value will lead to system crashes. Therefore, this embodiment needs to add the following three safety boundary conditions to prevent extreme situations: (1) Boundary against saturation peak current: This ensures that the inductor never enters the magnetic saturation region.

[0075] (2) DCM and soft switching boundary: Sufficient physical time must be reserved within a single cycle for the natural zero crossing of discharge (i.e., discharge duration) and dead zone, and at least 5% blank discontinuity time must be forcibly reserved after the discharge is completed within a single cycle, i.e., satisfying .in, This is the absolute time point at which the inductor current naturally crosses zero, i.e., the discharge duration. The solution process for this parameter will be given in subsequent steps. The switching cycle.

[0076] (3) Maximum duty cycle limit of hardware:

[0077] In addition to the three safety boundary conditions mentioned above, it is also necessary to determine whether D satisfies the law of conservation of energy based on the actual input power of the energy harvesting unit and the output power required by the external load under the target steady-state output voltage. The detailed steps of this energy conservation judgment process will be given in the subsequent discussion.

[0078] If the calculated D does not satisfy any of the above physical safety boundaries, the system determines that the target is a constant voltage. This is not feasible in practice. In this case, the algorithm immediately triggers an adaptive degradation mechanism, proactively abandoning the constant voltage objective and resetting the duty cycle to the maximum critical safe duty cycle that satisfies all the above inequality constraints. (i.e., maximum duty cycle) enables the system to output the maximum safe steady-state voltage that the current hardware can support. At this time, the output voltage is allowed to drop to a certain extent, but it can ensure that the system is in a soft-switching state in deep DCM mode.

[0079] Subsequently, this embodiment seeks the optimal soft-switching timing design of the circuit by avoiding parasitic delays in system hardware.

[0080] To ensure the soft switching of the MOSFETs despite variations in device configurations and phase switching parameters, the MCU controller must incorporate precise timing compensation when generating the PWM wave. This involves introducing soft-switching timing compensation parameters, which specifically include: Front Dead Zone Time : After the lower pipe is shut off, the upper pipe should be shut off with a delay of t. dt Dead time is enabled. To ensure normal node voltage ramp-up and reduce the Miller plateau tail of the MOSFET in real-world conditions, the dead time should be set to the sum of the node constant current charging time and the Miller delay dead time compensation. sum: (10) Preemptive pulse width cutoff : To enable soft switching of the upper transistor in DCM mode, a discharge differential equation is established during the conduction period of the upper transistor, i.e., the synchronous rectifier. Let the total parasitic impedance of the discharge circuit be... (Including inductor DCR and upper MOSFET on-resistance) ), candidate inductance value Input power Voltage at the output load terminal and total parasitic resistance of the circuit To form a closed loop, the following equations can be established according to Kirchhoff's voltage law: (11) Inductor output current under initial conditions Solving equation (11) yields the precise time function of the inductor current during discharge, as shown in equation (12): (12) Solving for the natural zero-crossing point of equation (12) yields the absolute time point at which the inductor current naturally crosses zero. (i.e., discharge duration): (13) To mitigate the inherent signal transmission delay between the microprocessor and the gate driver, the PWM generator is forced to prematurely cut off the upper transistor's turn-on pulse width. A reverse backflow prevention turn-off margin is introduced here. This parameter is obtained by fine-tuning the actual circuit parameters. This ensures that the actual conduction time of the upper transistor is... The upper transistor conducts under zero-voltage switching, achieving soft switching: (14) Based on the above actual conduction time of the upper pipe and leading edge dead zone time parameters This allows for the determination of precise soft-switching timing compensation parameters for the PWM signal, ensuring that the turn-on and turn-off of the upper and lower transistors occur within the appropriate switching time range when both the switching node voltage and inductor current are within the appropriate switching time interval. Specifically, after the lower transistor turns off, the controller does not immediately control the upper transistor to turn on, but instead determines the turn-on time based on the leading-edge dead time parameters. A dead time is reserved to allow the switching node voltage to change naturally and to prevent a shoot-through short circuit caused by simultaneous conduction of the upper and lower transistors; after the upper transistor turns on, the controller then adjusts the voltage based on the actual conduction time of the upper transistor. By turning off the upper transistor early, the upper transistor ends its conduction before the inductor current naturally crosses zero, preventing output charge from flowing back to the input side via the synchronous rectifier. Thus, both the upper and lower transistors can avoid the hard-switching region where high voltage and high current coexist, reducing losses caused by voltage and current overlap during switching and achieving soft-switching operation.

[0081] The process of making the energy conservation judgment in this embodiment is explained below.

[0082] In order to ensure the energy conservation of the entire system, the system must calculate the actual average input power provided by the front-end power supply. In a Boost topology, the input current is the current flowing through the inductor; therefore, the total charge drawn from the power supply in a single phase and single cycle is... Charge during charging period With discharge period charge sum.

[0083] (1) Charge during the charging period Calculation: During conduction The differential equation of the loop is:

[0084] For this equation during conduction time Integrate both sides simultaneously. Given that the current increases from 0 to... and charge amount We can obtain:

[0085] By rearranging and simplifying, we can obtain the charge solution during the charging period: (15) 2) Charge during discharge period Calculation: During freewheeling discharge ( The differential equation of the loop is:

[0086] For this equation during discharge time Integrate both sides simultaneously. Given that the current flows from... Descending to and charge amount We can obtain:

[0087] By rearranging and simplifying, we obtain the charge solution during the discharge period: (16) Based on the above and The solution is needed to determine the actual input power of this system. for: (17) In solving for the duty cycle, the constraint condition of equation (18) needs to be added to ensure energy conservation. The algorithm should discard solutions that do not satisfy equation (18): (18) After the above process is completed, this embodiment needs to calculate the losses related to the number of phases, thereby providing a reference for the conversion efficiency corresponding to the candidate parameter combination. In deep DCM mode, the current exhibits large ripple characteristics, and the traditional average current method will lead to serious ohmic heat prediction errors, resulting in inaccurate loss calculations. This embodiment is based on the charge and discharge equation and uses a high-precision numerical integral substitution rule to extract the square of the effective current value during the single-phase charging and discharging periods, and then mathematically describes it as follows: Current equation for single-phase charging period exist By performing a definite integral over the interval, we can derive the following:

[0088] in The current equation during the charging phase is the square of the effective value of the inductor current. Similarly, for the single-phase discharge phase current equation... In the natural zero-crossing interval Perform a square definite integral within the given boundary conditions. After rigorous algebraic elimination and simplification, a closed analytic solution with no approximation can be obtained:

[0089] in The conduction loss during the entire charging and discharging process is calculated using the following formula, which is the square of the effective value of the inductor current during the charging phase. : (19) The multi-drive loss is calculated using the following formula. : (20) in, The aforementioned total gate charge, The aforementioned driving voltage, both belong to semiconductor parasitic and driving parameters.

[0090] The high-frequency capacitive polarization loss is calculated using the following formula. : (twenty one) The conversion efficiency of the system can be obtained. As shown in equation (22): (twenty two) In the global three-dimensional parameter space In the process, if there exists a voltage that can successfully maintain the target steady-state voltage (i.e., the voltage actually calculated) Therefore, among all these schemes that can meet the voltage target, the one with the highest physical conversion efficiency should be selected first. The highest-performing set is taken as the global optimal solution.

[0091] If the physical limits of extremely low input voltage and heavy load cause the entire system to reach its physical boundary, and all parameters fail to maintain the target voltage (i.e., triggering adaptive degradation, all possible solutions...), then... At this point, the system prioritizes selecting the actual maximum output voltage that meets the above conditions. For parameter design that minimizes voltage drop, if combinations with the same voltage output capability exist, then efficiency should be further selected. Those who are of higher caliber.

[0092] The following is the mathematical expression: To express this priority mathematically, a segmented evaluation model is established as shown below: (twenty three) in, That is, the objective piecewise evaluation function. (Boundary barrier constant) is a given maximal positive real number, and satisfies (That is, far greater than the highest efficiency that the system's physical capabilities can achieve). In this embodiment, it is set to 900. (Voltage sag gradient penalty weight) is a positive real number coefficient. When the system encounters extreme physical bottlenecks (such as under ultra-low voltage heavy load) and is forced to enter adaptive degradation mode, efficiency... No longer used as the primary evaluation criterion, at this time by The penalty term guides the optimization direction. In this embodiment, it is set to 100.

[0093] Under degraded working conditions, due to ,so It's a positive number; adding a negative sign means that the greater the voltage drop, the more negative the function becomes, thus allowing the algorithm optimizer to find... The largest critical point.

[0094] While converting ultra-low voltage input to standard voltage, the system losses are minimized. In practical applications, because this scheme is designed with optimal values, it can be compatible with design objectives that are even lower than the optimal design requirements.

[0095] Therefore, this embodiment forms a control logic that prioritizes ensuring the target output voltage and then pursuing conversion efficiency; when the target output voltage cannot be achieved, it prioritizes ensuring the maximum safe output capability.

[0096] After determining the target parameter combination, the controller determines the phase difference of each phase in the multiphase boost module based on the target number of phases. For example, when the target number of phases is N, the phase difference of each phase drive signal can be set in a way that is uniformly staggered within one switching cycle, thereby reducing input current ripple and improving current sharing among phases. The controller also determines the soft-switching timing compensation parameters and the duty cycle of the main switch transistor based on the target parameter combination, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters.

[0097] Subsequently, the controller generates a PWM signal based on the target parameter combination, phase difference between each phase, soft-switching timing compensation parameters, and the duty cycle of the main switch. The drive unit controls the main switch and synchronous rectifier in each phase boost branch to turn on or off according to the PWM signal, causing the inductors of each phase to store and release energy sequentially, and output voltage to the external load through the energy storage capacitor. During system operation, the controller can also continue to adjust the PWM signal according to the operating conditions of the DC transmission line energy extraction section and the external load, enabling the converter to adapt to changes in input voltage and external load.

[0098] It can be recognized that this embodiment breaks through the limitation of traditional converters that can only operate under fixed and favorable conditions. It can adaptively and efficiently boost the variable and weak potential in the line to the universal standard voltage required by the monitoring equipment, thus broadening the applicable environment and working range of the micro-energy harvesting device. Secondly, this embodiment establishes a set of underlying parameter optimization algorithms. The system can automatically and comprehensively calculate the inductor heating and the micro-losses inside the switching devices, and quickly find the most matching combination among the number of phases, inductance value, and switching frequency. This ensures the highest overall energy conversion efficiency, avoiding energy waste caused by unreasonable hardware parameter configuration. Furthermore, the dynamic adaptive control and protection mechanism of this embodiment significantly improves the system's resilience and reliability. The microcontroller automatically determines the number of phases to activate and dynamically adjusts the duty cycle based on changes in external input energy and load size, ensuring the circuit is always in a low-loss soft-switching state under DCM mode. Especially in extreme conditions such as severe input energy shortages or excessive downstream loads, the system will not crash like conventional equipment, but will automatically trigger an "adaptive degradation" protection mechanism. Under the premise of hardware safety, the system will output the highest voltage it can currently maintain, maximizing the continuous online operation of the monitoring equipment on the UHVDC transmission line. Finally, the switching power supply mechanism of this embodiment solves the cold start problem of passive equipment in the field. The system uses an external energy acquisition module to provide power for the initial operation of the switching transistor drive, and then switches to its own output power supply after establishing a stable output. This completely frees the system from dependence on chemical batteries or external main power sources, truly enabling long-term, maintenance-free, and fully automatic independent operation of UHVDC transmission lines in remote and harsh environments.

[0099] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0100] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0101] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0102] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0103] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0104] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0105] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. An ultra-low voltage input boost converter, characterized in that, include: The system comprises an energy harvesting unit, a multiphase boost module, a controller, a drive unit, and an energy storage capacitor. The multiphase boost module includes several boost branches connected in parallel. Each boost branch includes an inductor, a main switch, a synchronous rectifier, a first Schottky diode, and a second Schottky diode. The controller acquires candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. Based on the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, it determines the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination. The voltage and the conversion efficiency are used to determine the target parameter combination from the candidate parameter combinations. Based on the target parameter combination, the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, the phase difference of each phase, the soft switching timing compensation parameters, and the duty cycle of the main switch are determined. A PWM signal is generated based on the target parameter combination, the phase difference of each phase, the soft switching timing compensation parameters, and the duty cycle of the main switch. The drive unit is used to control the conduction and cutoff of each main switch and each synchronous rectifier in the multiphase boost module according to the PWM signal. The power supply and load parameters include DC input source voltage, load equivalent resistance, and target steady-state output voltage. The candidate parameter combinations include candidate number of phases, candidate inductance value, and candidate switching frequency. The target parameter combination includes target number of phases, target inductance value, and target switching frequency. The process of determining the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination based on the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, and determining the target parameter combination from each candidate parameter combination based on the achievable output voltage and the conversion efficiency, includes: Based on the power supply and load parameters, determine the single-phase inductor peak current, discharge duration, and load charge requirement corresponding to each candidate parameter combination; The capacitive charge cut-off amount corresponding to each candidate parameter combination is determined based on the semiconductor parasitic and driving parameters, and the net output charge amount corresponding to each candidate parameter combination is determined based on the capacitive charge cut-off amount and the load charge requirement. The duty cycle of the candidate main switch used to maintain the target steady-state output voltage is determined based on the net charge at the output terminal and the equivalent resistance of the load. Based on the single-phase inductor peak current, the discharge duration, and the hardware delay tolerance parameter, the feasibility of the candidate main switch duty cycle for each candidate parameter combination is verified. Based on the feasibility verification results, the achievable output voltage and achievable main switch duty cycle corresponding to each candidate parameter combination are determined. The conversion efficiency corresponding to each of the candidate parameter combinations is determined based on the power supply and load parameters, the semiconductor parasitic and driving parameters, the peak current of the single-phase inductor, the achievable output voltage, and the duty cycle of the achievable main switch. Determine whether there exists an achievable output voltage that satisfies the target steady-state output voltage; When there exists an achievable output voltage that satisfies the target steady-state output voltage, among the candidate parameter combinations corresponding to the achievable output voltage that satisfies the target steady-state output voltage, the candidate parameter combination with the highest conversion efficiency is selected as the target parameter combination; If there is no achievable output voltage that satisfies the target steady-state output voltage, the candidate parameter combination with the highest achievable output voltage is selected as the target parameter combination.

2. The ultra-low voltage input boost converter according to claim 1, characterized in that, The energy harvesting unit includes a first energy harvesting terminal and a second energy harvesting terminal, which are respectively connected to the two ends of the DC transmission line energy harvesting section. The first end of the inductor is connected to the positive output terminal of the energy harvesting unit. The first end of the main switch and the first end of the synchronous rectifier are both connected to the second end of the inductor. The first Schottky diode is connected in parallel with the main switch, and the second Schottky diode is connected in parallel with the synchronous rectifier. The second end of the main switch is connected to the negative output terminal of the energy harvesting unit. The second end of the synchronous rectifier is connected to the upper plate of the energy storage capacitor, and the lower plate of the energy storage capacitor is connected to the negative output terminal of the energy harvesting unit. The control terminals of the main switch and the synchronous rectifier are both connected to the drive unit. The controller is signal-connected to the drive unit. The energy storage capacitor is electrically connected to an external load and is used to output voltage to the external load. The controller is also used to adjust the PWM signal according to the operating conditions of the DC transmission line energy harvesting section and the external load.

3. The ultra-low voltage input boost converter according to claim 1, characterized in that, The ultra-low voltage input boost converter also includes a power supply module. The controller and the drive unit are both electrically connected to the power supply module. The power supply module is used to provide operating voltage to the controller and the drive unit. The power supply module includes an energy harvesting chip and a power supply switching unit. The energy harvesting chip is used to accumulate startup energy from the DC transmission line energy harvesting section and provide startup voltage to the controller and the drive unit. The power supply switching unit is used to determine whether the energy storage capacitor meets the preset power supply conditions. When the energy storage capacitor meets the power supply conditions, the power source of the controller and the drive unit is switched to the energy storage capacitor, and the operating voltage is provided to the controller and the drive unit through the energy storage capacitor.

4. A control method for an ultra-low voltage input boost converter as described in any one of claims 1 to 3, characterized in that, include: The controller acquires candidate parameter combinations, power supply and load parameters, semiconductor parasitic and drive parameters, and hardware delay tolerance parameters. Based on the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, it determines the achievable output voltage and conversion efficiency corresponding to each candidate parameter combination. Based on the achievable output voltage and the conversion efficiency, it determines the target parameter combination among each candidate parameter combination. The controller determines the phase difference of each phase, soft-switching timing compensation parameters, and main switch duty cycle of the multiphase boost module based on the target parameter combination, the power supply and load parameters, the semiconductor parasitic and drive parameters, and the hardware delay tolerance parameters, and generates a PWM signal based on the target parameter combination, the phase difference of each phase, the soft-switching timing compensation parameters, and the main switch duty cycle. The driving unit controls the on / off state of each main switch and each synchronous rectifier in the multiphase boost module according to the PWM signal.

5. The control method for an ultra-low voltage input boost converter according to claim 4, characterized in that, The hardware delay tolerance parameters include the inductor saturation current limit, the maximum hardware duty cycle, and the system minimum safe dead time. The feasibility verification of the candidate main switch duty cycle for each candidate parameter combination is performed based on the single-phase inductor peak current, the discharge duration, and the hardware delay tolerance parameters. Based on the feasibility verification results, the achievable output voltage and achievable main switch duty cycle corresponding to each candidate parameter combination are determined, including: Determine whether the peak current of the single-phase inductor is not greater than the inductor saturation current limit; The on-time of the main switch is determined based on the duty cycle of the candidate main switch and the candidate switching frequency, and it is determined whether the sum of the on-time of the main switch, the discharge duration, and the minimum safe dead time of the system is not greater than the switching cycle corresponding to the candidate switching frequency. Determine whether the duty cycle of the candidate main switch is not greater than the maximum duty cycle of the hardware; The actual input power corresponding to the candidate parameter combination is determined based on the power supply and load parameters, the peak current of the single-phase inductor, and the discharge duration, and it is determined whether the actual input power is not less than the output power required by the external load under the target steady-state output voltage. When the peak current of the single-phase inductor is not greater than the inductor saturation current limit, and the sum of the main switch conduction time, the discharge duration, and the system minimum safe dead time is not greater than the switching cycle corresponding to the candidate switch frequency, and the duty cycle of the candidate main switch is not greater than the maximum duty cycle of the hardware, and the actual input power is not less than the output power required by the external load under the target steady-state output voltage, the duty cycle of the candidate main switch passes the feasibility check, and the duty cycle of the candidate main switch is taken as the main switch duty cycle corresponding to the candidate parameter combination, and the target steady-state output voltage is taken as the achievable output voltage corresponding to the candidate parameter combination; When the peak current of the single-phase inductor is greater than the inductor saturation current limit, or the sum of the main switch conduction time, the discharge duration, and the system minimum safe dead time is greater than the switching cycle corresponding to the candidate switch frequency, or the duty cycle of the candidate main switch is greater than the maximum duty cycle of the hardware, or the actual input power is less than the output power required by the external load under the target steady-state output voltage, it is determined that the duty cycle of the candidate main switch does not pass the feasibility check. The maximum duty cycle and the corresponding maximum output voltage of the corresponding candidate parameter combination under the feasibility check conditions are calculated. The maximum duty cycle is taken as the main switch duty cycle of the corresponding candidate parameter combination, and the maximum output voltage is taken as the achievable output voltage of the corresponding candidate parameter combination.

6. The control method for an ultra-low voltage input boost converter according to claim 4, characterized in that, The hardware delay tolerance parameters also include Miller delay dead-time compensation and reverse backflow prevention shutdown margin. The soft-switching timing compensation parameters are determined through the following steps: Determine the single-phase inductor peak current and discharge duration corresponding to the target parameter combination based on the power supply and load parameters; The capacitive charge cut-off amount corresponding to the target parameter combination is determined based on the semiconductor parasitic and driving parameters. The leading-edge dead-time parameters are determined based on the single-phase inductor peak current, the capacitive charge retention amount, and the Miller delay dead-time compensation amount. The conduction time of the synchronous rectifier tube is determined based on the discharge duration and the anti-reverse backflow shutdown margin. The soft-switching timing compensation parameters are determined based on the leading-edge dead time parameter and the conduction time of the synchronous rectifier.

7. The control method for an ultra-low voltage input boost converter according to claim 4, characterized in that, The power supply and load parameters include the DC input source voltage, the load equivalent resistance, and the target steady-state output voltage. The duty cycle of the main switch is determined through the following steps: Based on the power supply and load parameters, determine the single-phase inductor peak current, discharge duration, and load charge requirement corresponding to the target parameter combination. The capacitive charge cut-off amount corresponding to each candidate parameter combination is determined based on the semiconductor parasitic and driving parameters, and the net output charge amount corresponding to the target parameter combination is determined based on the capacitive charge cut-off amount and the load charge requirement. The initial main switch duty cycle for maintaining the target steady-state output voltage is determined based on the net charge at the output terminal and the equivalent resistance of the load. The feasibility of the initial main switch duty cycle is verified. When the initial main switch duty cycle passes the feasibility check, the initial main switch duty cycle is determined as the main switch duty cycle; If the initial main switch duty cycle fails the feasibility check, the main switch duty cycle is determined based on the maximum duty cycle of the target parameter combination under the feasibility check conditions.

8. The control method for an ultra-low voltage input boost converter according to claim 4, characterized in that, The ultra-low voltage input boost converter also includes a power supply module, which includes an energy harvesting chip and a power supply switching unit. The control method further includes: The energy harvesting chip accumulates startup energy from the DC transmission line energy harvesting section and provides startup voltage for the controller and the drive unit; The power supply switching unit determines whether the energy storage capacitor meets the preset power supply conditions. When the energy storage capacitor meets the power supply conditions, the power supply source for the controller and the drive unit is switched to the energy storage capacitor, and the energy storage capacitor provides the operating voltage for the controller and the drive unit. The energy storage capacitor outputs voltage to an external load. The controller adjusts the PWM signal according to the operating conditions of the DC transmission line energy harvesting section and the external load.

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