Conduction time control circuit, step-down control circuit, chip and converter

Abstract

The application provides a conduction time control circuit, a step-down control circuit, a chip and a step-down converter. The conduction time control circuit comprises a controllable integration module, a capacitor multiplication module, a self-calibration module, a first switch unit and a second switch unit which are electrically connected; two input ends of the controllable integration module receive a reference voltage and a sampling voltage, and an output end of the controllable integration module is connected to the capacitor multiplication module, the self-calibration module, the first switch unit and the second switch unit; the conduction time control circuit is configured to work in a self-calibration stage when the first switch unit is turned on and the second switch unit is turned off, and work in a current integration stage when the first switch unit is turned off and the second switch unit is turned on, so as to output a voltage signal for controlling the conduction time of a switch in the step-down converter. The application can realize constant conduction time control by using a smaller capacitor, can significantly reduce the cost, and can effectively inhibit the negative influence of process mismatch and high-temperature leakage on the control loop precision.

Description

Technical Field

[0001] This invention relates to the field of buck converter technology, and particularly to a conduction time control circuit, a buck control circuit, a chip, and a buck converter. Background Technology

[0002] Floating-ground buck converters employing constant on-time (COT) control and critical conduction mode (CrM) can achieve higher power factors. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the topology of a buck converter and its control circuit in the prior art. (Example:) Figure 1 As shown, in order to ensure the effectiveness of COT, the voltage signal V in control loop 1 is required to... CTRL It maintains an approximately constant input line voltage while also allowing for slow variations based on the average output current of load 2 (e.g., an LED). This is achieved by obtaining the average output current and slowing down the voltage signal V. CTRL The rate of change usually requires the use of large-area filter capacitors, compensation circuits, or analog-to-digital converters (ADCs).

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to address one or more of the problems in existing technologies, such as the need for large capacitors to achieve constant on-time control of buck converters, leading to difficulties in integration and high costs. This invention provides an on-time control circuit, a buck control circuit, a chip, and a buck converter. The capacitor multiplication module of this invention achieves constant on-time control using smaller capacitors, making integration easier and significantly reducing costs. Simultaneously, the self-calibration module has a self-calibration function, effectively suppressing the negative impact of process mismatch and high-temperature leakage on the accuracy of the control loop, significantly improving the stability, reliability, and applicability of the system.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a conduction time control circuit for a buck converter, the conduction time control circuit comprising a controllable integrator module, a capacitor multiplication module, a self-calibration module for generating a self-calibration current, a first switching unit, and a second switching unit; the first and second input terminals of the controllable integrator module respectively receive a reference voltage and a sampled voltage from the output terminal of the buck converter, and its output terminal is connected to a first node via the first terminal of the capacitor multiplication module, the first terminal of the self-calibration module, the first terminal of the first switching unit, and the first terminal of the second switching unit; the second terminal of the self-calibration module is connected to the second terminal of the first switching unit, and its third terminal is connected to the second terminal of the capacitor multiplication module via a second node; the third terminal of the capacitor multiplication module is connected to the second terminal of the second switching unit.

[0006] The on-time control circuit is configured to generate a voltage signal at the second node based on the sampled voltage and the reference voltage, and control the on-time of the switches in the buck converter based on the voltage signal; wherein, the on-time control circuit switches its operating phase according to a control signal, and operates in the self-calibration phase when the control signal indicates that the first switch unit is on and the second switch unit is off, and operates in the current integration phase when the control signal indicates that the first switch unit is off and the second switch unit is on.

[0007] Optionally, the self-calibration phase and the current integration phase are performed alternately, and the frequency at which the conduction time control circuit switches the operating phase is greater than the frequency of the line voltage of the buck converter.

[0008] Optionally, the controllable integration module includes a first transconductance amplifier, a third switching unit, and a fourth switching unit; the first input terminal of the first transconductance amplifier is connected to the first terminal of the third switching unit and receives the reference voltage, the second input terminal of the first transconductance amplifier is connected to the second terminal of the third switching unit and the first terminal of the fourth switching unit, and its output terminal is connected to the first node; the second terminal of the fourth switching unit receives the sampled voltage.

[0009] The controllable integration module is configured such that when the conduction time control circuit operates in the self-calibration phase, the third switch unit is turned on and the fourth switch unit is turned off, and when it operates in the current integration phase, the third switch unit is turned off and the fourth switch unit is turned on.

[0010] Optionally, the capacitance multiplication module includes a second transconductance amplifier, a fifth switching unit, a differential input resistor, and a first capacitor; the output terminal of the second transconductance amplifier is connected to the first node, its first input terminal is connected to the second terminal of the second switching unit, its second input terminal and the first terminal of the first capacitor are connected to the second node, and the fifth switching unit and the differential input resistor are connected in parallel between the first input terminal and the second input terminal of the second transconductance amplifier, and the second terminal of the first capacitor is grounded;

[0011] The capacitance multiplication module is configured such that the fifth switching unit is turned on when the conduction time control circuit is operating in the self-calibration phase, and the fifth switching unit is turned off when the circuit is operating in the current integration phase.

[0012] Optionally, the self-calibration module includes a third transconductance amplifier and a second capacitor. The output terminal of the third transconductance amplifier is connected to the first node, its first input terminal and the first terminal of the second capacitor are connected to the second terminal of the first switching unit, and its second input terminal is connected to the second node. The second terminal of the second capacitor is grounded.

[0013] Optionally, when operating in the self-calibration phase, the controllable integrator generates a first offset current, and the capacitance multiplier generates a second offset current; when operating in the current integration phase, the controllable integrator outputs a first current containing the first offset current based on the reference voltage and the sampled voltage, and the capacitance multiplier outputs a second current containing the second offset current; the self-calibration current can cancel out the first offset current and the second offset current in the self-calibration phase and the current integration phase.

[0014] Optionally, the conduction time control circuit is further configured to operate in a delay phase before switching from the self-calibration phase to the current integration phase and before switching back from the current integration phase to the self-calibration phase; when operating in the delay phase, the third switching unit is turned on, and the first switching unit, the second switching unit, the fourth switching unit, and the fifth switching unit are all turned off.

[0015] Optionally, at least one of the first switching unit, the second switching unit, and / or the fifth switching unit of the capacitor multiplication module includes an NMOS transistor using a deep N-well process, and a clamping circuit is connected between the base and source of the NMOS transistor.

[0016] Optionally, the clamping circuit includes an operational amplifier, one input terminal of which is connected to the base of the NMOS transistor and the output terminal of the operational amplifier, and the other input terminal is connected to the source of the NMOS transistor.

[0017] Optionally, the source of the NMOS transistor is the second terminal of the first switching unit, the second terminal of the second switching unit, and / or the terminal of the fifth switching unit connected to the second node.

[0018] To achieve the above-mentioned ideas, the present invention also provides a buck control circuit, which includes the conduction time control circuit described in any of the above-mentioned claims.

[0019] To achieve the above-mentioned ideas, the present invention also provides a chip, wherein the chip integrates the conduction time control circuit or the buck control circuit described above.

[0020] To achieve the above-mentioned ideas, the present invention also provides a buck converter, which includes a buck converter circuit, and the conduction time control circuit described in any of the above-mentioned embodiments, or the buck control circuit described in the above-mentioned embodiments, or the chip described in the above-mentioned embodiments.

[0021] Compared with the prior art, the conduction time control circuit, buck control circuit, chip, and buck converter provided by the present invention have the following beneficial effects:

[0022] (1) The capacitance multiplication module of the present invention can achieve constant conduction time control by using a smaller capacitor, which is easier to integrate and can significantly reduce costs. At the same time, the self-calibration module has a self-calibration function, which can effectively suppress the negative impact of process mismatch and high temperature leakage on the accuracy of the control loop, and can significantly improve the stability, reliability and applicability of the system.

[0023] (2) By adopting the alternation of the self-calibration stage and the current integration stage, and the frequency of the self-calibration stage being greater than the frequency of the line voltage of the buck converter, the reliability and stability of the present invention can be further improved.

[0024] (3) By using NMOS transistors with deep N-well technology in conjunction with clamping circuits to realize the first switching unit, the second switching unit and / or the fifth switching unit, high-temperature leakage current can be effectively suppressed, thereby further improving the stability and reliability of the present invention.

[0025] Since the buck control circuit, chip, and buck converter provided by this invention belong to the same inventive concept as the conduction time control circuit provided by this invention, the buck control circuit, chip, and buck converter provided by this invention have at least all the above-mentioned advantages of the conduction time control circuit provided by this invention. To avoid redundancy, they will not be described in detail here. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the topology of a buck converter and its control circuit in the prior art.

[0027] Figure 2 This is a structural block diagram of a conduction time control circuit provided in one embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the junction topology of a conduction time control circuit provided in one embodiment of the present invention.

[0029] Figure 4 for Figure 3 The diagram shows the control timing of each switching unit in the conduction time control circuit.

[0030] Figure 5 for Figure 3 The diagram shows the circuit connection of the conduction time control circuit during the self-calibration phase.

[0031] Figure 6 for Figure 3 The circuit connection diagram shown is for the conduction time control circuit when it is operating in the current integration stage.

[0032] Figure 7 for Figure 3 The diagram shows the leakage current during the current integration phase of the conduction time control circuit.

[0033] Figure 8 for Figure 3 The diagram shows the leakage current during the self-calibration phase of the conduction time control circuit.

[0034] Figure 9 This is a schematic diagram of the switching unit in a conduction time control circuit provided in one embodiment of the present invention.

[0035] The reference numerals in the attached figures are explained as follows:

[0036] Control loop-1, load-2; controllable integral module-100, first transconductance amplifier-Gm1, third switching unit-S3, fourth switching unit-S4; capacitor multiplication module-200, second transconductance amplifier-Gm2, fifth switching unit-S5, differential input resistor-R0, first capacitor-C1; self-calibration module-300, third transconductance amplifier-Gm3, first switching unit-S1, second switching unit-S2, second capacitor-C2; clamping circuit-40, operational amplifier-Buffer. Detailed Implementation

[0037] To make the objectives, advantages, and features of the present invention clearer, the on-time control circuit, buck control circuit, chip, and buck converter proposed in this invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the drawings do not necessarily show the specific structure of the invention to scale, and the illustrative features used to illustrate certain principles of the invention in the drawings are also drawn in a slightly simplified manner. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. Where appropriate, these terms used thus can be replaced.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0039] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0040] The core idea of ​​this invention is to provide a conduction time control circuit, a buck control circuit, a chip, and a buck converter. The capacitance multiplication module of this invention can achieve constant conduction time control by using a smaller capacitor, which is not only easier to integrate, but also significantly reduces costs. At the same time, the self-calibration module can realize self-calibration function, which can effectively suppress the negative impact of process mismatch and high temperature leakage on the accuracy of the control loop, thereby significantly improving the stability, reliability and applicability of the system.

[0041] To achieve the above-mentioned goals, one embodiment of the present invention provides an on-time control circuit for a buck converter. For example, please refer to... Figure 2 , Figure 2 This is a structural block diagram of the conduction time control circuit provided in this embodiment. From... Figure 2As can be seen, the conduction time control circuit includes a controllable integrator module 100, a capacitance multiplication module 200, a self-calibration module 300 that generates a self-calibration current Isc, a first switching unit S1, and a second switching unit S2; the first and second input terminals of the controllable integrator module 100 respectively receive a reference voltage V. REF and the sampling voltage V at the output terminal of the buck converter SENSE Its output terminal is connected to the first terminal of the capacitance multiplication module 200, the first terminal of the self-calibration module 300, the first terminal of the first switching unit S1, and the first terminal of the second switching unit S2 at a first node N1; the second terminal of the self-calibration module 300 is connected to the second terminal of the first switching unit S1, and its third terminal is connected to the second terminal of the capacitance multiplication module 200 at a second node N2; the third terminal of the capacitance multiplication module 200 is connected to the second terminal of the second switching unit S2. The conduction time control circuit is configured to control the conduction time based on the sampled voltage V. SENSE and the reference voltage V REF At the second node N2 voltage signal V CTRL And according to the voltage signal V CTRL The on-time of the switches in the buck converter is controlled; wherein the on-time control circuit switches the operating stage according to a control signal. When the control signal indicates that the first switch unit S1 is on and the second switch unit S2 is off, it operates in the self-calibration stage; when the control signal indicates that the first switch unit S1 is off and the second switch unit S2 is on, it operates in the current integration stage.

[0042] Therefore, the conduction time control circuit provided by the present invention, through the controllable integrator module 100, can control the conduction time based on the real-time acquired sampling voltage V. SENSE The integral current I is generated by current integration. INT This avoids the sampling voltage V SENSE An averaging filter operation is performed to produce an output voltage signal V that can follow the changes in the output current of the buck converter. CTRL This lays a solid foundation. Furthermore, the capacitance multiplier module 200 requires only a small capacitor to form a low-speed loop, which can effectively realize the voltage signal V. CTRLThe gradual change in the voltage level provides a solid foundation for controlling the on-time of the buck converter. Simultaneously, the first switching unit S1 and the second switching unit S2 can respond to the on / off indications of the control signal, enabling the on-time control circuit provided by this invention to operate in the self-calibration and current integration phases. This allows the self-calibration module 300 to continuously generate a self-calibration current Isc that effectively suppresses process mismatch and high-temperature leakage, thereby significantly improving the stability and reliability of this invention. In summary, the capacitor multiplication module 200 of this invention achieves constant on-time control using a smaller capacitor, making it easier to integrate and significantly reducing costs. Furthermore, the self-calibration module 300 possesses a self-calibration function, effectively suppressing the negative impact of process mismatch and high-temperature leakage on the accuracy of the control loop, significantly improving the system's stability, reliability, and applicability.

[0043] It should be noted that those skilled in the art should understand that whether the conduction time control circuit provided by the present invention operates in the self-calibration stage or the current integration stage is determined by the control signal it receives. The present invention does not limit the source of the control signal. For example, the control signal may come from the circuit system in which the buck converter is located.

[0044] Exemplary examples, in some of these exemplary embodiments, the self-calibration phase and the current integration phase are performed alternately (see Appendix). Figure 4 Furthermore, the frequency of the switching operation phase of the on-time control circuit is much higher than the frequency of the line voltage of the buck converter. Therefore, by employing an alternating self-calibration phase and a current integration phase, and by ensuring that the frequency of the switching operation phase of the on-time control circuit is higher than the frequency of the line voltage of the buck converter, the reliability and stability of this invention can be further improved.

[0045] For example, please see Figure 3 and Figure 4 ,in, Figure 3 A schematic diagram of the junction topology of a conduction time control circuit provided in one embodiment of the present invention; Figure 4 for Figure 3 The diagram shows the control timing of each switching unit in the conduction time control circuit. Figure 4 In the diagram, t1-t2 and t5-t6 are the self-calibration stages, t3-t4 is the current integration stage, and S1 to S5 are the control signals corresponding to the first switching unit S1 to the fifth switching unit S5, respectively. A high level indicates that the switch is on, and a low level indicates that the switch is off. Figure 3 It can be seen that in some exemplary embodiments, the controllable integrator module 100 ( Figure 3 , Figure 5 and Figure 6 (Illustrated in blue) includes a first transconductance amplifier Gm1, a third switching unit S3, and a fourth switching unit S4; the first input terminal of the first transconductance amplifier Gm1 is connected to the first terminal of the third switching unit S3 and receives the reference voltage V. REF The second input terminal of the first transconductance amplifier Gm1 is connected to the second terminal of the third switching unit S3 and the first terminal of the fourth switching unit S4, and its output terminal is connected to the first node N1; the second terminal of the fourth switching unit S4 receives the sampled voltage V. SENSE .like Figure 4 As shown, the controllable integration module 100 is configured such that when the conduction time control circuit operates in the self-calibration stage, the third switch unit S3 is turned on and the fourth switch unit S4 is turned off, and when it operates in the current integration stage, the third switch unit S3 is turned off and the fourth switch unit S4 is turned on.

[0046] Therefore, by turning off the fourth switching unit S4 and turning on the third switching unit S3 during the self-calibration phase, the sampling voltage V can be cut off. SENSE The impact on self-calibration, thereby improving the stability and reliability of the present invention; by turning on the fourth switching unit S4 and turning off the third switching unit S3 during the current integration phase, the first transconductance amplifier Gm1 can be adjusted according to the sampling voltage V. SENSE and the reference voltage V REF Generate integral current I INT This allows the output to follow the output current (sampling voltage V) of the buck converter. SENSE The voltage signal V obtained from the output current changes. CTRL This lays a good foundation; furthermore, the design of the controllable integrator module 100, which uses the third switching unit S3, the fourth switching unit S4 and the first transconductance amplifier Gm1, also has the advantages of simple structure and easy implementation.

[0047] For example, please continue to see Figure 3 and Figure 4 ,like Figure 3 As shown, in some exemplary embodiments, the capacitance multiplication module 200 ( Figure 3 and Figures 5 to 8(Illustrated by the red area) The system includes a second transconductance amplifier Gm2, a fifth switching unit S5, a differential input resistor R0, and a first capacitor C1. The output of the second transconductance amplifier Gm2 is connected to the first node N1, its first input is connected to the second terminal of the second switching unit S2, its second input and the first terminal of the first capacitor C1 are connected to the second node N2, and the fifth switching unit S5 and the differential input resistor R0 are connected in parallel between the first and second input terminals of the second transconductance amplifier Gm2. The second terminal of the first capacitor C1 is grounded. Figure 4 As shown, the capacitance multiplication module 200 is configured such that the fifth switching unit S5 is turned on when the conduction time control circuit is operating in the self-calibration stage, and the fifth switching unit S5 is turned off when the circuit is operating in the current integration stage.

[0048] Therefore, by turning off the second switching unit S2 and turning on the fifth switching unit S5 during the self-calibration phase, the first capacitor C1 can be prevented from being directly connected to the first node N1. This allows the capacitance of the first capacitor C1 to be multiplied by the second transconductance amplifier Gm2. This configuration achieves the technical effect of constant on-time control using a smaller first capacitor C1, facilitating circuit integration and significantly reducing costs. Furthermore, by turning on the second switching unit S2 and turning off the fifth switching unit S5 during the current integration phase, the linearity of the first transconductance amplifier Gm1 can be improved and harmonic distortion reduced through the differential input resistor R0. Additionally, by appropriately selecting the value of the differential input resistor R0, precise control of the gain of the first transconductance amplifier Gm1 can be achieved, thereby effectively ensuring the output voltage signal V of this invention. CTRL It is more accurate and reliable; furthermore, the design of the capacitor multiplication module 200 using the fifth switching unit S5 and the second transconductance amplifier Gm2 also has the advantages of simple structure and easy implementation.

[0049] For example, please continue to see Figure 3 ,like Figure 3 As shown, in some exemplary embodiments, the self-calibration module 300 ( Figure 3 as well as Figures 5 to 8(Using green area for illustration) This includes a third transconductance amplifier Gm3 and a second capacitor C2. The output terminal of the third transconductance amplifier Gm3 is connected to the first node N1, its first input terminal and the first terminal of the second capacitor C2 are connected to the second terminal of the first switching unit S1, and its second input terminal is connected to the second node N2. The second terminal of the second capacitor C2 is grounded. Thus, the second capacitor C2 ensures that the input voltage of the third transconductance amplifier Gm3 during the current integration stage (when the first switching unit S1 is off) is basically the same as the input voltage during the self-calibration stage, thereby ensuring that the self-calibration current Isc generated by the third transconductance amplifier Gm3 can offset the first offset current I generated by the controllable integration module 100. OS1 (as in the following text) Figure 5 or Figure 6 (as shown) and the second offset current I generated by the capacitor multiplication module 200. OS2 (as in the following text) Figure 5 or Figure 6 As shown), this effectively suppresses the negative impact of process mismatch on the accuracy of the control loop, the first offset current I OS1 This is caused by a process mismatch in the first transconductance amplifier Gm1, which is equivalent to an offset voltage Vos1 at the input of the first transconductance amplifier Gm1, and the second offset current I. OS2 The offset voltage Vos2 is caused by the process mismatch of the second transconductance amplifier Gm2, which is equivalent to the existence of an offset voltage Vos2 at the input terminal of the second transconductance amplifier Gm2. Furthermore, the design of the self-calibration module 300 using the second capacitor C2 and the third transconductance amplifier Gm3 has the advantages of simple structure and easy implementation.

[0050] It should be noted that those skilled in the art should understand that the present invention does not limit the specific implementation of the first transconductance amplifier Gm1, the second transconductance amplifier Gm2, and the third transconductance amplifier Gm3. For example, the first transconductance amplifier Gm1 to the third transconductance amplifier Gm3 can be implemented using combinations including but not limited to amplifiers, switching transistors, resistors, and current mirrors. For more detailed information on transconductance amplifiers, please refer to the relevant technical adaptations known to those skilled in the art; due to space limitations, this will not be elaborated upon herein.

[0051] For example, in some exemplary embodiments, please refer to Figure 5 and Figure 6 , Figure 5 for Figure 3 The diagram shown illustrates the circuit connection of the conduction time control circuit during the self-calibration phase. Figure 6 for Figure 3The diagram shows the circuit connection of the conduction time control circuit during the current integration phase. Figure 5 and Figure 6 As shown, when operating in the self-calibration phase, the controllable integrator 100 generates a first offset current I. OS1 The capacitor multiplier module 200 generates a second offset current I. OS2 The offset voltage Vos3 in the self-calibration module 300 is suppressed by the self-calibration loop and will not generate a corresponding offset current; when operating in the current integration phase, the controllable integration module 100 adjusts the current according to the reference voltage V. REF and the sampling voltage V SENSE The output includes the first offset current I OS1 The first current (exemplary, Figure 6 I in INT +I OS1 (i.e., integral current and offset current), the output of the capacitor multiplication module 200 includes the second offset current I. OS2 The fourth current (exemplary, Figure 6 G in m2 R0I CHARGE,SC +I OS2 (i.e., integral current and offset current); the self-calibration current Isc cancels the first offset current I during the self-calibration phase and the current integration phase. OS1 and the second offset current I OS2 Therefore, by canceling the first offset current I... OS1 and the second offset current I OS2 It can effectively suppress the negative impact of process mismatch on the accuracy of the control loop, thereby effectively improving the voltage signal V. CTRL It not only ensures the accuracy of the conduction time control circuit, but also guarantees the stability and reliability of the conduction time control circuit provided by this invention.

[0052] For example, please continue to see Figure 4 ,like Figure 4 As shown, in some exemplary embodiments, the on-time control circuit, from the self-calibration phase (e.g.) Figure 4 Switching to the current integration stage (e.g., t1-t2, t5-t6) Figure 4 t3-t4, t7-t8 ( Figure 4 (t8 is not shown in the image) before and during the integration phase from the current (e.g.) Figure 4 Switching back to the self-calibration stage (e.g., -t0, t3-t4) is an example of this. Figure 4 Before t1-t2 and t5-t6, the work is in the delayed phase ( Figure 4In the intervals t0-t1, t2-t3, t4-t5, and t6-t7, when operating in the delay phase, the third switching unit S3 is turned on, and the first switching unit S1, the second switching unit S2, the fourth switching unit S4, and the fifth switching unit S5 are all turned off. This ensures that the third switching unit S3 is the first to turn on when entering the self-calibration phase and the last to turn off when exiting the self-calibration phase, effectively preventing the sampling voltage V from being affected. SENSE The impact on the calibration process further enhances the reliability and stability of the present invention.

[0053] For example, please continue to see Figure 4 ,like Figure 4 As shown, when the conduction time control circuit operates in the delay stage, both the second switching unit S2 and the fifth switching unit S5 are turned off. Therefore, the fifth switching unit S5 can only be turned on when the second switching unit S2 is turned off (i.e., when switching from the current integration stage to the self-calibration stage, the second switching unit S2 is turned off first, and then the fifth switching unit S5 is turned on; when switching from the self-calibration stage to the current integration stage, the fifth switching unit S5 is turned off first, and then the second switching unit S2 is turned off). This ensures that the first capacitor C1 is not directly connected to the first node N1, thereby effectively guaranteeing the capacitance multiplication achieved through the second transconductance amplifier Gm2.

[0054] For example, please see Figures 3 to 6 The working principle of this invention will be briefly explained below:

[0055] First, combined Figure 3 , Figure 4 and Figure 5 It can be seen that during the self-calibration phase, the first switching unit S1, the third switching unit S3, and the fifth switching unit S5 are turned on, while the second switching unit S2 and the fourth switching unit S4 are turned off. During this phase, the first offset current I output by the first transconductance amplifier Gm1... OS1 and the second offset current I output by the second transconductance amplifier Gm2 OS2 As the current flows into or out of the first node N1, due to the high impedance of the first node N1, the third transconductance amplifier Gm3 can output a self-calibrating current I. SC To counteract the first offset current I OS1 and the second offset current I OS2 The third transconductance amplifier Gm3 is powered by its own offset voltage V. OS3 The introduced offset current is also suppressed by the self-calibration loop itself.

[0056] Secondly, in the current integration stage, combined with Figure 3 , Figure 4 and Figure 6 It can be seen that: the first switching unit S1, the third switching unit S3, and the fifth switching unit S5 are turned off, while the second switching unit S2 and the fourth switching unit S4 are turned on. During this stage, the second capacitor C2 can maintain the input voltage (relative to the voltage signal V) at the first input terminal of the third transconductance amplifier Gm3 during the self-calibration stage. CTRL Therefore, the third transconductance amplifier Gm3 is still able to provide the same self-calibration current I as in the self-calibration phase. SC Finally, the input offset voltage V of the first transconductance amplifier Gm1 OS1 The input offset voltage V of the second transconductance amplifier Gm2 OS2 and the offset voltage V of the third transconductance amplifier Gm3 itself OS3 The introduced offset current is suppressed and becomes 1 / (1+G) of the original value. m3 R N1 ), where R N1 G represents the impedance at node N1 during the self-calibration phase. m3 The transconductance gain of the third transconductance amplifier Gm3 is given.

[0057] Additionally, it should be noted that, as mentioned earlier, the input voltage at the first input terminal of the third transconductance amplifier Gm3 is relative to the voltage signal V. CTRL And the voltage signal V CTRL Since the input line voltage is not constant under varying conditions, the frequency of the control signal applied to the conduction time control circuit should be much higher than the frequency of the line voltage, so that the conduction time control circuit periodically enters the self-calibration phase to refresh the voltage across the second capacitor C2.

[0058] Furthermore, during the current integration phase, when the integrating current I generated by the first transconductance amplifier Gm1... INT When the first capacitor C1 is charged, a portion of the charging current flows through the differential input resistor R0. The voltage drop across the differential input resistor R0 acts on the two input terminals of the second transconductance amplifier Gm2, causing it to generate an integrating current G. m2 R0I CHARGE，SC From the integral current I INT The charging current I is drawn from the middle, therefore the charging current is... CHARGE，SC Reduce to I INT / (1+G m2 R0); where G m2Rm represents the transconductance gain of the second transconductance amplifier Gm2, and R0 represents the resistance value of the differential input resistor R0. During the self-calibration phase, the discharge process of the first capacitor C1 is similar to the charging process, and will not be elaborated further here.

[0059] The study also found that at high temperatures, the leakage current of the first switching unit S1, the second switching unit S2, and the fifth switching unit S5 may significantly change the charging current of the first capacitor C1. The leakage current suppression during the current integration stage and the self-calibration stage are described below:

[0060] First, in the current integration stage, please refer to... Figure 7 , Figure 7 for Figure 3 The diagram shows the leakage current during the current integration phase of the conduction time control circuit. Specifically, Figure 7 The leakage current of the first switching unit S1 and the fifth switching unit S5 during the current integration phase is shown. Figure 7 In the diagram, leakage current that can be suppressed by the capacitance multiplication loop is indicated in green, while leakage current that cannot be suppressed by the capacitance multiplication loop is indicated in red. This illustrates whether or not leakage current can be suppressed. The leakage current I of the first switching unit S1 near the first node N1... LK1N1 The capacitance multiplication loop formed by the capacitance multiplier module 200 can therefore be factored by 1 / (G m2 R0) suppression; wherein, the leakage current I of the first switching unit S1 near the second capacitor C2 side LK1C This will change the charge on the second capacitor C2, thereby changing the output current of the third transconductance amplifier Gm3 (the change is as follows). Figure 7 ΔI in SC The leakage current I of the fifth switching unit S5 near the first node N1 is difficult to suppress by the capacitance multiplication loop formed by the capacitance multiplication module 200. LK5N1 With leakage current I LK1N1 Similarly, this can be suppressed by the capacitance multiplication loop. In contrast, the leakage current I of the fifth switching unit S5 near the first capacitor C1... LK5C The first capacitor C1 is directly charged and discharged during the entire current integration phase, which cannot be suppressed by the capacitance multiplication loop.

[0061] Secondly, during the self-calibration phase, please refer to... Figure 8 , Figure 8 for Figure 3 The diagram shows the leakage current during the self-calibration phase of the conduction time control circuit. Specifically, Figure 8 The leakage current of the second switching unit S2 during the self-calibration phase is shown. Figure 8In the diagram, leakage currents that can be suppressed by the self-calibration loop are indicated in green, while leakage currents that cannot be suppressed by the self-calibration loop are indicated in red, indicating whether or not they can be suppressed. The leakage current I of the second switching unit S2 near the first node N1... LK2N1 During the self-calibration phase, the third transconductance amplifier Gm3 can be calibrated. However, after the current integration phase, when the second switching unit S2 is turned on, the third transconductance amplifier Gm3 will still output a self-calibration current I. LK2N1,Gm3 However, the self-calibrating current I LK2N1,Gm3 It can still be suppressed by the self-calibration loop. On the other hand, the leakage current I of the second switching unit S2 near the side of the first capacitor C1 LK2C The first capacitor C1 is directly charged and discharged during the entire self-calibration phase, which cannot be suppressed.

[0062] Based on the above analysis, it can be seen that for each of the first switching unit S1, the second switching unit S2, and the fifth switching unit S5, only one side of the leakage current needs to be deliberately suppressed (e.g., Figure 7 and Figure 8 (As shown by the red arrow in the image), while the leakage current on the other side can be naturally suppressed by the loop (such as...). Figure 7 and Figure 8 (As shown by the green arrow in the image).

[0063] Based on the above research, in some exemplary embodiments, at least one of the first switching unit S1, the second switching unit S2, and the fifth switching unit S5 includes an NMOS transistor using a deep N-well process. For example, please refer to... Figure 9 , Figure 9 This is a schematic diagram of the switching unit in a conduction time control circuit provided in one embodiment of the present invention. Figure 9 As shown, a clamping circuit 40 is connected between the base B and source S of the NMOS transistor M0. Therefore, by using a deep N-well NMOS transistor to implement the first switching unit S1, the second switching unit S2, and the fifth switching unit S5, high-temperature leakage current can be effectively suppressed. Furthermore, by using the clamping circuit 40 connected between the source S and the base B, the potential between the base B and the source S of the NMOS transistor M0 can be effectively clamped, thereby effectively suppressing leakage current and improving the stability and reliability of the present invention.

[0064] For example, please continue to see Figure 9 ,like Figure 9As shown, the clamping circuit 40 includes an operational amplifier buffer. One input terminal of the operational amplifier buffer is connected to the base B of the NMOS transistor M0 and the output terminal of the operational amplifier buffer, and the other input terminal is connected to the source S of the NMOS transistor M0. Therefore, using an operational amplifier buffer to implement the clamping circuit 40 has the advantages of high reliability and ease of implementation.

[0065] Exemplary examples, in some exemplary embodiments, the source S of the NMOS transistor M0 is the second terminal of the first switching unit S1, the second terminal of the second switching unit S2, and / or the terminal of the fifth switching unit S5 connected to the second node N2. This allows for more effective suppression of leakage current.

[0066] Specifically, when the NMOS transistor M0 is turned off, the potential difference V between the drain D and the source S... DS Caused leakage current I LKD The leakage current flows out from the drain (D), but almost none from the source (S). When the NMOS transistor M0 is closed, the potentials of its source (S), drain (D), and base (B) are approximately equal, and the leakage current is negligible. When the NMOS transistor M0 is open, the leakage current at the source (S) of the deep N-well NMOS transistor can be absorbed by the clamping circuit 40. Therefore, by... Figure 9 The source S of the structure shown is oriented... Figure 7 and Figure 8 Middle I LK1C I LK2C and I LK5C The direction in which the source S of the first switching unit S1 faces the second capacitor C2, the source S of the second switching unit S2, and the source S of the fifth switching unit S5 face the first capacitor C1 can effectively suppress leakage current.

[0067] It should be noted that those skilled in the art should understand that the use of NMOS transistors with deep N-well technology to implement the first switching unit S1, the second switching unit S2, and the fifth switching unit S5 is merely an illustrative description of preferred embodiments and not a limitation of the present invention. The present invention does not impose too many limitations on the specific implementation of the first switching unit to the fifth switching unit S5. For example, the first switching unit S1 to the fifth switching unit S5 may be implemented using power switching transistors including but not limited to NMOS transistors and PMOS transistors.

[0068] Another embodiment of the present invention provides a buck control circuit, wherein, exemplarily, the buck control circuit includes the conduction time control circuit provided in any embodiment of the present invention.

[0069] Another embodiment of the present invention provides a chip, on which the conduction time control circuit described in any of the embodiments herein or the buck control circuit provided by the present invention is integrated.

[0070] It is understood that the present invention does not limit the manufacturing process of the chip. For example, the chip may be, but is not limited to, a 180nm chip, a 130nm chip, and a 90nm chip.

[0071] Another embodiment of the present invention provides a buck converter, the buck converter including a buck conversion circuit, and the on-time control circuit described in any embodiment, or the buck control circuit provided by the present invention, or the chip provided by the present invention.

[0072] Since the buck control circuit, chip, and buck converter provided by this invention belong to the same inventive concept as the conduction time control circuit provided by this invention, the buck control circuit, chip, and buck converter provided by this invention have at least all the above-mentioned advantages of the conduction time control circuit provided by this invention. To avoid redundancy, they will not be described in detail here.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0074] Therefore, compared with the prior art, the conduction time control circuit, buck control circuit, chip, and buck converter provided by the present invention have the following beneficial effects:

[0075] (1) The capacitance multiplication module of the present invention can achieve constant conduction time control by using a smaller capacitor, which is easier to integrate and can significantly reduce costs. At the same time, the self-calibration module has a self-calibration function, which can effectively suppress the negative impact of process mismatch and high temperature leakage on the accuracy of the control loop, and can significantly improve the stability, reliability and applicability of the system.

[0076] (2) By adopting the alternation of the self-calibration stage and the current integration stage, and the frequency of the self-calibration stage being greater than the frequency of the line voltage of the buck converter, the reliability and stability of the present invention can be further improved.

[0077] (3) By using NMOS transistors with deep N-well technology in conjunction with clamping circuits to realize the first switching unit, the second switching unit and the fifth switching unit, high-temperature leakage can be effectively suppressed, thereby further improving the stability and reliability of the present invention.

[0078] In summary, the above embodiments have provided detailed descriptions of different configurations of the conduction time control circuit, buck control circuit, chip, and buck converter provided by the present invention. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the claims.

Claims

1. A conduction time control circuit for a buck converter, characterized in that, The conduction time control circuit includes a controllable integrator module, a capacitance multiplier module, a self-calibration module that generates a self-calibration current, a first switching unit, and a second switching unit. The first and second input terminals of the controllable integrator module respectively receive a reference voltage and a sampled voltage from the output terminal of the buck converter. Its output terminal is connected to the first terminal of the capacitance multiplier module, the first terminal of the self-calibration module, the first terminal of the first switching unit, and the first terminal of the second switching unit at a first node. The second terminal of the self-calibration module is connected to the second terminal of the first switching unit, and its third terminal is connected to the second terminal of the capacitance multiplier module at a second node. The third terminal of the capacitance multiplier module is connected to the second terminal of the second switching unit. The on-time control circuit is configured to generate a voltage signal at the second node based on the sampled voltage and the reference voltage, and control the on-time of the switches in the buck converter based on the voltage signal; wherein, the on-time control circuit switches its operating phase according to a control signal, and operates in the self-calibration phase when the control signal indicates that the first switch unit is on and the second switch unit is off, and operates in the current integration phase when the control signal indicates that the first switch unit is off and the second switch unit is on.

2. The conduction time control circuit according to claim 1, characterized in that, The self-calibration phase and the current integration phase are performed alternately, and the frequency at which the conduction time control circuit switches between operating phases is greater than the frequency of the line voltage of the buck converter.

3. The conduction time control circuit according to claim 1, characterized in that, The controllable integration module includes a first transconductance amplifier, a third switching unit, and a fourth switching unit; the first input terminal of the first transconductance amplifier is connected to the first terminal of the third switching unit and receives the reference voltage; the second input terminal of the first transconductance amplifier is connected to the second terminal of the third switching unit and the first terminal of the fourth switching unit; its output terminal is connected to the first node; the second terminal of the fourth switching unit receives the sampled voltage. The controllable integration module is configured such that when the conduction time control circuit operates in the self-calibration phase, the third switch unit is turned on and the fourth switch unit is turned off, and when it operates in the current integration phase, the third switch unit is turned off and the fourth switch unit is turned on.

4. The conduction time control circuit according to claim 3, characterized in that, The capacitance multiplication module includes a second transconductance amplifier, a fifth switching unit, a differential input resistor, and a first capacitor; the output terminal of the second transconductance amplifier is connected to the first node, its first input terminal is connected to the second terminal of the second switching unit, its second input terminal and the first terminal of the first capacitor are connected to the second node, and the fifth switching unit and the differential input resistor are connected in parallel between the first input terminal and the second input terminal of the second transconductance amplifier, and the second terminal of the first capacitor is grounded; The capacitance multiplication module is configured such that the fifth switching unit is turned on when the conduction time control circuit is operating in the self-calibration phase, and the fifth switching unit is turned off when the circuit is operating in the current integration phase.

5. The conduction time control circuit according to claim 1, characterized in that, The self-calibration module includes a third transconductance amplifier and a second capacitor. The output terminal of the third transconductance amplifier is connected to the first node, its first input terminal and the first terminal of the second capacitor are connected to the second terminal of the first switching unit, its second input terminal is connected to the second node, and the second terminal of the second capacitor is grounded.

6. The conduction time control circuit according to claim 1, characterized in that, When operating in the self-calibration phase, the controllable integrator generates a first offset current, and the capacitor multiplier generates a second offset current; when operating in the current integration phase, the controllable integrator outputs a first current containing the first offset current based on the reference voltage and the sampling voltage, and the capacitor multiplier outputs a second current containing the second offset current. The self-calibrating current can cancel out the first offset current and the second offset current during the self-calibration phase and the current integration phase.

7. The conduction time control circuit according to claim 4, characterized in that, The on-time control circuit is further configured to operate in a delay phase before switching from the self-calibration phase to the current integration phase and before switching back from the current integration phase to the self-calibration phase; when operating in the delay phase, the third switching unit is turned on, and the first switching unit, the second switching unit, the fourth switching unit, and the fifth switching unit are all turned off.

8. The conduction time control circuit according to claim 1 or 4, characterized in that, At least one of the first switching unit, the second switching unit, and / or the fifth switching unit of the capacitor multiplication module includes an NMOS transistor using a deep N-well process, and a clamping circuit is connected between the base and source of the NMOS transistor.

9. The conduction time control circuit according to claim 8, characterized in that, The clamping circuit includes an operational amplifier, one input terminal of which is connected to the base of the NMOS transistor and the output terminal of the operational amplifier, and the other input terminal is connected to the source of the NMOS transistor.

10. The conduction time control circuit according to claim 8, characterized in that, The source of the NMOS transistor is the second terminal of the first switching unit, the second terminal of the second switching unit, and / or the terminal of the fifth switching unit connected to the second node.

11. A step-down control circuit, characterized in that, Includes the conduction time control circuit as described in any one of claims 1 to 10.

12. A chip, characterized in that, It integrates a conduction time control circuit as described in any one of claims 1 to 10 or a buck control circuit as described in claim 11.

13. A buck converter, characterized in that, The buck converter includes a buck converter circuit, and an on-time control circuit as described in any one of claims 1 to 10, or a buck control circuit as described in claim 11, or a chip as described in claim 12.

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