Dual chip solution for dual / multi-channel power devices

Abstract

A power device and a method of manufacturing the same are disclosed. The device includes a gate controller coupled to a first substrate. A first set of one or more transistor devices is coupled to a second substrate, and a second set of one or more transistor devices is also coupled to the second substrate. The first set of transistor devices and the second set of transistor devices are communicatively coupled to the gate controller.

Description

Technical Field

[0001] Various aspects of the present invention relate to drive MOSFET (DrMOS) devices, and more particularly, various aspects of the present invention relate to wafer-level packaging and drivers in DRMOS devices. Background Technology

[0002] In conventional DRMOS devices, the transistor driver and the transistor are packaged together in a multi-chip package. Popular multi-chip packages include quad flat no-lead (QFN) packages and flip-chip packages, which connect the chip within the package to the lead frame via bonding wires. Flip-chip packages also include the use of clips to connect the back of the chip to the lead frame.

[0003] Figure 1A and Figure 1B A prior art flip-chip design is schematically illustrated. As shown, the flip-chip package includes a transistor driver 101, a high-side metal-oxide-semiconductor field-effect transistor (MOSFET) 103, a low-side MOSFET 102, a lead frame 107, and a back clip 110. The gate of the low-side MOSFET 102 includes a large gate contact pad 104, which needs to have sufficient area to connect to the transistor driver 101. A large solder joint 111 establishes the connection between the gate contact pad 104 and the lead frame 107. Metal bonding wires 106 connect the lead frame to the transistor driver, enabling the transistor to send signals to the gate contact pad 104 of the low-side MOSFET 102 through the large solder joint 111. The high-side MOSFET 103 also includes a large gate contact pad 105; a high-side gate bonding wire 108 connects this gate contact pad 105 to the high-side gate control output node of the transistor driver 101. These large gate contact pads occupy a significant amount of space in the low-side MOSFET 102 and the high-side MOSFET 103. In particular, because there is no active region below the gate pad, the space below the gate contact pad is wasted. The transistor driver 101 also includes pads for other control inputs, which are connected to the lead frame 107 via bonding wires 109.

[0004] like Figure 1BAs shown, the back clip 110 connects the source of the high-side MOSFET 103 and the drain of the low-side MOSFET 102 to the VSWH pin of the lead frame 107. Bonding wires require space within the device package because a sufficiently large gap must be maintained between each wire to prevent arcing, and the pads on each device must be large enough to achieve bonding. Furthermore, bonding wires have a larger inductance compared to thin metal leads. The lead frame and clip also present dimensional disadvantages because the metal clips must be strong enough to maintain contact with the back of the chip. Finally, large individual bonding pads can lead to uneven gate impedance, resulting in uneven switching of the transistor devices.

[0005] It is against this backdrop that various aspects of the present invention have been proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a power device that enables more uniform transistor switching and reduces device area.

[0007] To achieve the above objectives, the present invention provides a power device comprising: a gate controller coupled to a first substrate; a first group of one or more transistor devices coupled to a second substrate; and a second group of one or more transistor devices coupled to the second substrate, wherein the first group of transistor devices is configured for high-side switching in a power conversion device, and the second group of transistor devices is configured for low-side switching in the power conversion device, wherein the first group of transistor devices and the second group of transistor devices are communicatively coupled to the gate controller, and wherein the gate controller is configured to drive the gates of the first group of transistor devices and the second group of transistor devices.

[0008] In some embodiments, the first group of transistor devices and the second group of transistor devices each include one or more gate drivers.

[0009] In some embodiments, the one or more gate drivers of the first group of transistor devices are distributed proportionally among the transistor devices in the first group of transistor devices.

[0010] In some embodiments, the one or more gate drivers of the second group of transistor devices are distributed proportionally among the transistor devices in the second group of transistor devices.

[0011] In some embodiments, the gate controller is communicatively coupled to the first set of transistors and the second set of transistors via conductive traces in a molded interconnect substrate or thin-film substrate.

[0012] In some embodiments, the gate controller is communicatively coupled to the first group of transistor devices and the second group of transistor devices via conductive leads in the lead frame package.

[0013] In some embodiments, the gate controller is connected to the conductive trace or the conductive lead via at least one bonding wire.

[0014] In some embodiments, the first set of transistor devices and the second set of transistor devices are formed of a semiconductor material different from that of the gate controller.

[0015] In some embodiments, the feature size of the gate controller is different from the feature size of the first group of transistor devices and the second group of transistor devices.

[0016] In some embodiments, the feature size of the first group of transistors and the second group of transistors is smaller than the feature size of the gate controller.

[0017] In some embodiments, the power device further includes one or more discrete electronic components mounted on the back side of a die containing the gate controller or a die containing the first set of transistor devices and the second set of transistor devices.

[0018] In some embodiments, the one or more discrete electronic components include one or more surface mount elements or back-to-back mount elements.

[0019] The improved DRMOS device provided by this invention can be manufactured using a distributed contact layout in the transistor device, thereby achieving more uniform transistor switching and reducing device area. Furthermore, employing distributed gate drive in wafer-level or panel-level packaging can reduce parasitic inductance, reduce device area, and improve robustness by distributing failure points among multiple drivers. Finally, employing both distributed contact layout and distributed gate drive simultaneously provides an enhanced DRMOS device that combines all the above advantages. The dual-chip solution also offers the additional advantages of reduced assembly costs, smaller package size, and the ability to achieve advanced packaging styles. Attached Figure Description

[0020] The features and advantages of the present invention will become apparent after reading the following detailed description and referring to the following figures, wherein: Figure 1A This is a top-view diagram illustrating existing flip-chip designs.

[0021] Figure 1B This is a side view of a current flip-chip design.

[0022] Figure 2 A top view showing the redistribution layer (RDL) of a transistor device according to various aspects of the present invention.

[0023] Figure 3 This is an RDL top view of a DRMOS device with distributed gate drive and each MOSFET having a single gate bus, according to various aspects of the present invention.

[0024] Figure 4 The image shows an RDL top view of a DRMOS device having distributed gate drive and each MOSFET having a plurality of proportionally distributed gate buses at its gate, according to various aspects of the invention.

[0025] Figure 5 The image shows an RDL top view of a DRMOS device, according to various aspects of the present invention, having distributed gate drive and with multiple proportionally distributed gate buses on the top gate electrode contact areas on both sides of each FET device.

[0026] Figure 6 The image shows an RDL top view of a DRMOS device, according to various aspects of the present invention, having a distributed gate drive and wherein the gate electrode contact regions on both sides of the top of each FET device containing a sense FET are equipped with a plurality of proportionally distributed gate buses.

[0027] Figure 7 The image shows an RDL top view of a DRMOS device with a distributed gate drive, having a FET device integrated with gate control and a gate electrode contact region at the top edge of the independent FET device equipped with a plurality of proportionally distributed gate buses, according to various aspects of the present invention.

[0028] Figure 8 This is an RDL top view of a DRMOS device with trench capacitors integrated in a semiconductor wafer, according to various aspects of the present invention.

[0029] Figure 9 This is an RDL top view of a DRMOS device with a distributed gate driver according to various aspects of the present invention.

[0030] Figure 10 This is an RDL top view of a DRMOS device including a split FET device, according to various aspects of the present invention.

[0031] Figure 11A According to various aspects of the present invention, along Figure 10 A cross-sectional side view of the shielded gate trench (SGT) MOSFET device in the DRMOS embodiment, taken from the AA line.

[0032] Figure 11B According to various aspects of the present invention, along Figure 10A cross-sectional side view of the shielded gate trench (SGT) MOSFET device in the DRMOS embodiment, taken from the BB line.

[0033] Figure 12A According to various aspects of the present invention, along Figure 10 A cross-sectional side view of the planar gate MOSFET device in the DRMOS embodiment, taken by line AA.

[0034] Figure 12B According to various aspects of the present invention, along Figure 10 A cross-sectional side view of the planar gate MOSFET device in the DRMOS embodiment, taken from the BB line.

[0035] Figure 13 This is a top view schematic diagram illustrating a dual-chip solution according to various aspects of the present invention.

[0036] Figure 14 This is a top view schematic diagram illustrating a dual-chip solution with a distributed transistor driver according to various aspects of the present invention.

[0037] Figure 15A This is a top view schematic diagram illustrating a dual-chip device package having a molded interconnect substrate (MIS) according to various aspects of the present invention.

[0038] Figure 15B This is a side view schematic diagram illustrating a dual-chip device package having a molded interconnect substrate (MIS) according to various aspects of the present invention.

[0039] Figure 16A This is a top view schematic diagram illustrating a dual-chip device package having a flip-chip gate controller and a molded interconnect substrate (MIS) according to various aspects of the present invention.

[0040] Figure 16B This is a side view schematic diagram illustrating a dual-chip device package having a flip-chip gate controller and a molded interconnect substrate (MIS) according to various aspects of the present invention.

[0041] Figure 17A This is a top view schematic diagram illustrating a dual-chip device package with a conventional lead frame according to various aspects of the present invention.

[0042] Figure 17B This is a side view schematic diagram illustrating a dual-chip device package with a conventional lead frame according to various aspects of the present invention.

[0043] Figure 18A This is a top view schematic diagram illustrating a dual-chip device package having a flip-chip gate controller and a conventional lead frame according to various aspects of the present invention.

[0044] Figure 18BThis is a side view schematic diagram illustrating a dual-chip device package having a flip-chip gate controller and a conventional lead frame according to various aspects of the present invention.

[0045] Figure 19 This is a side view schematic diagram illustrating a three-chip device package with a three-dimensional stacked arrangement according to various aspects of the present invention.

[0046] Figure 20 This is a side view schematic diagram illustrating a four-chip device package with a three-dimensional stacked arrangement according to various aspects of the present invention.

[0047] Figure 21 A flowchart illustrating the manufacturing process of a dual-chip solution according to various aspects of the present invention. Detailed Implementation

[0048] While the following detailed description contains many specific details for illustrative purposes, it will be understood by any person skilled in the art that many variations and modifications of these details are within the scope of the invention. Therefore, the examples of embodiments of the invention described below are given without affecting the generality of the claimed invention, nor are they intended to limit it.

[0049] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, illustrating specific embodiments in which the invention may be practiced by way of example. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “front end,” and “rear end” are used with reference to the orientation described in the drawings. Since components of embodiments of the invention can be placed in various different orientations, the directional terms are for illustrative purposes only and are not intended to be limiting. It should be understood that other embodiments may be adopted, and structural or logical changes may be made, without departing from the scope of the invention. Therefore, the following detailed description should not be considered limiting, and the scope of the invention is defined by the appended claims.

[0050] The semiconductor materials (such as silicon) mentioned herein are doped with ions of a first conductivity type or a second conductivity type. The first conductivity type ions may be the opposite of the second conductivity type ions. For example, and not limitingly, in some embodiments, the first conductivity type ions may be n-type, contributing negative charge carriers (such as electrons) when doped into silicon. In such embodiments, the first conductivity type ions may include phosphorus, antimony, bismuth, lithium, and arsenic. In such embodiments, the second conductivity type ions may be p-type, generating holes as charge carriers when doped into silicon, and are therefore referred to as the opposite of n-type. p-type ions include boron, aluminum, gallium, and indium. Although the foregoing description uses n-type as the first conductivity type and p-type as the second conductivity type, the invention is not limited thereto; p-type may be the first conductivity type and n-type may be the second conductivity type. Furthermore, semiconductor materials other than silicon may also be used in MOSFET devices according to the present invention.

[0051] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate specific embodiments in which the invention may be practiced. For convenience, + or - is used after the specification of conductivity type or net impurity carrier type (p or n), generally referring to the relative concentration of the specified type of net impurity carriers in the semiconductor material. Generally, the concentration of n-type net dopant (e.g., electrons) is higher in n+ materials than in n materials, and the carrier concentration is higher in n materials than in n- materials. Similarly, the concentration of p-type net dopant (e.g., holes) is higher in p+ materials than in p materials, and the concentration is higher in p materials than in p- materials. It should be noted that what is relevant is the net carrier concentration, and not necessarily the dopant concentration. For example, if the material is also sufficiently reverse-doped with p-type dopant, the material may be heavily doped with n-type dopant but still have a relatively low net carrier concentration. As used herein, less than about 10 15 / cm -3 The dopant concentration can be considered "lightly doped", greater than about 10. 17 / cm -3 The dopant concentration can be considered "heavily doped".

[0052] According to various aspects of the present invention, improved DRMOS devices can be fabricated by employing a distributed contact layout in the transistor device at the wafer-level or panel-level packaging, thereby achieving more uniform transistor device switching and reducing device area. Furthermore, employing distributed gate drive in the wafer-level or panel-level packaging can also improve DRMOS devices, reducing parasitic inductance, reducing device area, and improving robustness by distributing failure points among multiple drivers. Finally, employing both distributed contact layout and distributed gate drive in the wafer-level or panel-level packaging can provide an enhanced DRMOS device that combines all the above advantages.

[0053] Figure 2This is a top view showing the redistribution layer (RDL) of a transistor device according to various aspects of the present invention. As shown, transistor device 201 includes a gate RDL or gate top metal 205. The transistor device also includes a source RDL or source top metal 204. An isolation region 206 isolates the source RDL or source top metal 204 from the gate RDL or gate top metal 205.

[0054] As shown in the figure, the gate RDL or gate top metal 205 includes plated gate vias 202, which provide conductive paths through the gate insulating layer to the gate electrode. The gate electrode material may be distributed within the substrate structure, forming a gate contact region along the top edge of the substrate structure. It should be noted that the implementation is not limited to providing a gate contact region only along a single top edge; the gate contact region may exist in any region on the top of the substrate structure in the form of one or more horizontal lines, or as... Figure 5 and Figure 6 As shown, it extends along two top edges. Two or more vias through the gate insulating material expose a portion of the gate electrode material in the gate contact region, and the conductive material of the plated gate via 202 forms a conductive contact with a portion of the gate electrode material at the edge of the transistor device. These two or more vias may be proportionally distributed across the gate contact region. A sufficient number of vias of appropriate size may be provided to proportionally distribute the voltage through the gate electrode. In some embodiments, the plated gate via 202 may be filled with the conductive material of the gate RDL or gate metal layer. The gate RDL or gate metal layer may be made of, for example, but not limited to, copper, aluminum, iron, tungsten, lead, or any alloy thereof.

[0055] In discussing RDLs, this article may refer to source RDL, gate RDL, or drain RDL. These terms refer to the RDL material that is electrically coupled to the aforementioned components within the RDL. For example, a gate RDL is an RDL material that is electrically coupled to the gate electrode through vias in the gate insulating layer. Similarly, a source RDL is an RDL material that is electrically coupled to the source region and body region through vias in the source insulating layer, and a drain RDL is an RDL material that is electrically coupled to the drain region through vias in the drain insulating layer. It should be understood that source RDLs and gate RDLs can be different traces on the same RDL layer or traces on different RDL layers.

[0056] As shown, the source RDL or source top metal 204 includes plated source vias 203 that penetrate the source insulating layer to the source contact. The source insulating layer and the gate insulating layer may be made of the same material and may be formed simultaneously. Therefore, in some embodiments, the gate insulating layer and the source insulating layer may be the same layer above the device substrate structure. The source insulating layer and the gate insulating layer may be made of oxides (e.g., silicon dioxide) or other materials (e.g., silicon nitride), which may be formed on top of the gate electrode material (e.g., polysilicon or silicide). Two or more vias through the source insulating material expose the source region in the substrate structure, and the conductive material of the plated source vias 203 forms a conductive contact with a portion of the source region. These two or more plated source vias may be distributed proportionally on the source RDL or source metal.

[0057] A sufficient number of vias can be provided to proportionally distribute the voltage through the gate region. Furthermore, the electroplated source vias 203 can form conductive contacts with the body region of the substrate structure, thereby forming a so-called anti-parallel diode of the MOSFET device. In some embodiments, the electroplated source vias 203 can be filled with conductive material of the source RDL or source metal layer. The source RDL or source metal layer can be made of, for example, but not limited to, copper, aluminum, iron, tungsten, lead, or any alloy thereof.

[0058] Compared to implementations using a single gate pad, distributed vias can improve device switching performance by distributing contacts with the gate electrode more evenly.

[0059] Figure 3This figure illustrates an RDL top view of a DRMOS device with distributed gate drives, where each MOSFET's gate is equipped with a single gate bus, according to various aspects of the invention. As shown, a first FET device 302 and a second FET device 303 are each connected to a gate driver output node of a gate controller 301 via a single bus for each FET device. The gate controller 301 may be, for example, but not limited to, a gate controller integrated circuit. The gate controller 301 may include gate drivers distributed proportionally between gate electrodes. In the illustrated example, three gate drivers correspond to three gate contacts on the first FET device 302, and plated vias 308 connect these gate drivers to an RDL 306 on the gate controller 301. The RDL 306 electrically couples each distributed driver through the plated vias 308. A single bus 304 in the device RDL connects the distributed drivers to the first gate of the first FET device 302 via a gate RDL 305. The first FET device gate plated via 308 connects the first FET device gate RDL 305 to the three gate electrodes of the first FET device 302. The first FET source RDL or source metal layer 307 also includes two or more plated vias that make contact with the source region of the first FET device 302. As shown, multiple plated vias exist in the source RDL or source metal layer of the first FET device. Distributed drivers improve the fault tolerance of the device because the device can continue to operate even if one driver fails.

[0060] Similarly, the second FET device 303 includes two sets of gate vias that penetrate the gate insulating layer, exposing the gate electrode of the FET device. A conductive plating layer of the plated vias 310 connects the gate RDL 311 to the gate electrode. A second bus 312 formed by the RDL connects the gate electrode to the gate controller 301. A second plated via 313 in the second gate RDL 314 connects the gate driver to the second gate RDL 314 and the second bus 312. As shown, the source RDL 309 of the second FET device includes two or more plated vias that form conductive contacts with the gate region of the FET device. Here, the first FET device may be a low-side FET, and the second FET device may be a high-side FET, but aspects of the invention are not limited thereto. In some embodiments, the first FET device may be a high-side FET, and the second FET device may be a low-side FET. For example, the high-side FET and the low-side FET may be part of a voltage regulator. Furthermore, in some embodiments, the illustrated configuration can be extended to a multiphase configuration, where a controller may be connected to multiple low-side and high-side devices. Furthermore, although the illustrated embodiments have two or three gate drivers, aspects of the invention are not limited thereto, and any number of gate drivers sufficient to control the FET device can be provided.

[0061] Figure 4 This figure shows a top view of the RDL of a DRMOS device according to various aspects of the present invention, having distributed gate drives and each MOSFET having a plurality of proportionally distributed gate buses. As shown, three buses 402 are made of RDL material. These three buses can be traces formed from the RDL layer. In an alternative embodiment, these three traces can be wires made of conductive material. These three buses are proportionally distributed between the three gate drivers of the gate controller. Plated vias 401 through the gate controller insulating layer conductively couple the RDL material to the output node of each gate driver of the first FET. In the illustrated embodiment, each output node of the gate driver is conductively coupled to the RDL material through four plated vias 401. These three buses are proportionally distributed with connections to three sets of gate plated vias 403 in the RDL. Here, the gate electrode of the first FET device is connected through three sets of five plated vias 403 each. Similarly, the gate drivers of the second FET device are distributed proportionally and have two buses made of RDL material, which are connected to two sets of five gate vias passing through the gate insulating layer and two sets of five plated gate driver vias passing through the gate controller insulating layer.

[0062] Figure 5 This figure shows a top view of an RDL (Regulator-Derivative Node) device according to various aspects of the present invention, having distributed gate drive and with multiple proportionally distributed gate buses on the top gate electrode contact areas on both sides of each FET device. As shown, the gate contact areas are located on a first top edge 503 and a second top edge 504. Electroplated vias in the RDL material form conductive contacts with the gate electrodes on the first top edge 503 and the second top edge 504. Two buses 502 made of RDL material conductively couple the gate electrodes to the gate driver output nodes through electroplated vias 501 made of RDL material. These two buses 502 are proportionally distributed with the two gate contact areas, and each of the two gate drivers is conductively coupled to the buses through six electroplated vias.

[0063] Figure 6This figure shows a top view of an RDL of a DRMOS device according to various aspects of the present invention, having distributed gate drive and with multiple proportionally distributed gate buses on the top and side gate electrode contact areas of each FET device containing a sense FET. Positioning the gate electrode contact areas at the edges provides new possibilities for the location of the sense FET. Typically, the sense FET is located at the edge of the device for easy connection. However, this leads to unsatisfactory detection performance because the sense FET is separated from the rest of the FET device. As shown, the sense FET source region 603 is located in the middle of the source region, enabling more accurate detection of the operating state. The two edge contact areas avoid interference from the RDL material buses. The sense FET source region is connected to the sense FET RDL material via conductive vias. A dedicated sense gate bus 604 made of RDL material connects the sense FET source region to the sense FET node of the gate controller integrated circuit 601 via conductive via 602. Although the illustrated embodiment includes two edge contact areas for the gate electrode material, various aspects of the invention are not limited thereto. Alternatively, the sense FET located in the middle of the source region can be implemented with a single edge contact area or three or more edge contact areas.

[0064] Figure 7 This figure shows a top view of an RDL of a DRMOS device with a distributed gate drive, comprising a FET device integrated with gate control and a gate electrode contact region at the top edge of each FET device equipped with a plurality of proportionally distributed gate buses, according to various aspects of the present invention. As shown, the gate controller 701 includes an integrated FET 704. The integrated FET may be, for example, but not limited to, a high-side FET. The integrated FET drain RDL 702 may include an RDL having plated vias 705 that form conductive contacts with the drain region of the integrated FET 704. The plated vias 705 may be proportionally distributed on the drain region of the integrated FET. The integrated FET drain RDL 702 may extend to the drain connection node of the DRMOS device. The integrated FET source RDL 703 may form conductive contacts with the source region of the integrated FET 704 via plated vias 706. The integrated FET source RDL 703 may also include plated vias 707 that provide conductive paths through the molding material layer to the source connection node of the DRMOS device. In addition, DRMOS devices may include independent FET devices and distributed drivers similar to those shown in the previous embodiments.

[0065] Figure 8This is a top view of the RDL of a DRMOS device with trench capacitors integrated in a semiconductor substrate structure according to various aspects of the present invention. As shown here, a first FET device 803 includes an on-chip trench capacitor 802 formed in the substrate structure of the first FET device. In some alternative embodiments, the on-chip capacitor may be a planar capacitor. A plated via 801 may form a conductive contact with the gate electrode material in the gate contact region at the top edge of the substrate structure. The trench capacitor may also form a conductive contact with the gate electrode of the FET device gate. A second FET device 804 may also include a trench capacitor 805 similarly coupled to the gate electrode material. The gate electrode material in the contact region forms a conductive contact with the trench capacitor. Here, each distributed gate driver is coupled to a separate trench capacitor via the gate RDL. The aspects of the invention are not limited thereto; for example, but not limited to, a single trench capacitor structure may form a conductive contact with each gate driver, or multiple trench capacitor structures may form a conductive contact with a single gate driver.

[0066] Figure 9 This is a top view of the RDL of a DRMOS device with distributed gate drivers according to various aspects of the present invention. Here, the gate controller 901 includes a gate driver 902 for a first FET device and a gate driver 903 for a second FET device, which are visible. It can also be seen that each gate driver 902 for the first FET device and each gate driver 903 for the second FET device are coupled to their respective FET devices via plated vias 904. The distributed gate drivers provide redundancy in the event of driver failure and, in embodiments including multiple RDL traces connecting the gate electrodes, enable better energy distribution to the gate electrodes.

[0067] Figure 10This diagram shows a top view of an RDL of a DRMOS device comprising a split FET device according to various aspects of the present invention. In the illustrated embodiment, the first FET device 1010 includes two separate gate structures of different sizes. Here, the first gate structure 1001 of the first FET device is a larger gate for normal device operation. Gate size, as used herein, refers to the device area occupied by the gate electrode. The second gate structure 1002 of the first FET device is a smaller gate for use under light load conditions. In some embodiments, the distributed drivers of the first FET may be proportionally distributed between the first gate structure 1001 and the second gate structure 1002. Specifically, the larger FET may have a larger distributed driver than the smaller FET. Here, the first gate driver is connected to the first gate structure RDL 1004 via a plated via, thereby connecting to the first gate structure. The second gate driver is connected to the second gate structure RDL 1005 via a plated via, thereby connecting to the second gate structure.

[0068] Similarly, the second FET device 1011 includes two independent gate structures of different sizes. The first gate structure 1006 of the second FET device is a larger gate for normal device operation. The second gate structure 1007 of the first FET device is a smaller gate for use under light load conditions. The distributed drivers of the first FET can also be evenly distributed between the first gate structure 1006 and the second gate structure 1007. As shown here, the first gate driver is connected to the first gate structure RDL 1009 via a plated via, thus connecting to the first gate structure. The second gate driver is connected to the second gate structure RDL 1008 via a plated via, thus connecting to the second gate structure. Similar to the first FET device 1010, the distributed drivers of the second FET device 1011 can be proportionally distributed between the first gate structure 1006 and the second gate structure 1007. The larger of the two FETs can have a smaller, larger distributed driver.

[0069] Figure 11A and Figure 11B This is a cross-sectional side view of a shielded gate trench (SGT) MOSFET device in a DRMOS embodiment according to various aspects of the present invention. Figure 11A The cross-section of the device region below the source region RDL1101 is shown. Figure 11BThe cross-section of the gate contact region below the gate RDL1106 is shown. As shown, the substrate structure of this device includes a substrate layer 1113 heavily doped with ions of a first conductivity type, a drift region 1118 formed on top of the substrate layer and lightly doped with ions of the first conductivity type, and a body region 1112 formed in the drift region and doped with ions of a second conductivity type. The source region 1111 is formed on top of the body region and is heavily doped with ions of the first conductivity type. Here, the substrate structure can be a semiconductor material, such as, but not limited to, gallium nitride, silicon, or silicon carbide.

[0070] The substrate structure includes trenches, each trench surface lined with a trench insulating layer 1119. In the illustrated embodiment, a shielding electrode 1109 is located on the trench insulating layer 1119 above the bottom surface of the trench. The trench insulating layer 1119 extends above the shielding electrode 1109. A gate electrode 1105 is located on the trench insulating layer 1119 above the shielding electrode 1109. The trench insulating layer 1119 also covers the gate electrode. It should be noted that each source region 1111 is further located near one side of the trench. Furthermore, although an SGT structure is shown, aspects of the invention are not limited thereto, and a trench gate structure can be formed by simply omitting the shielding electrode. The gate electrode 1105 is connected to the gate contact region via a gate extension 1110, as shown. Figure 11B As shown, the gate extension is connected to the gate metal layer 1123 through an electroplated via 1124 in the molding material layer 1126, and forms an electrical contact with the gate RDL 1106 through a conductive via 1108 in the gate contact region insulating layer 1120. The shielding electrode 1109 can be conductively coupled to the source region RDL 1101 (not shown in the figure). The RDL vias can be formed by laser ablation and can have a diameter of 20 micrometers or less.

[0071] like Figure 11B As shown, the gate RDL1106 extends along the top edge of the substrate structure. The gate RDL1106 can be made of the same material as the source region RDL1101, for example, through conventional metal deposition and patterning techniques.

[0072] The source insulating layer 1102 is located on top of the substrate structure, below the top metal 1121 of the source region, and covers the source region 1111 and the body region 1112. Vias 1103 formed in the source insulating layer expose a portion of the source region 1111 and a portion of the body region 1112. In some embodiments, a doped region 1112a of a second conductivity type may exist between the two source regions 1111 of the first conductivity type. This doped region 1112a is more heavily doped than the heavily doped body region 1112. For example, if the body region is p-type and the source region is n-type, then the doped region 1112a may be p-type. + Doping. Alternatively, shallow trenches p can be formed in the bulk region. +Contact plug, making the shallow groove contact plug perpendicular to the n side + and p + / p Body area short circuit.

[0073] As shown, via 1104 may be plated with a conductive material, and this conductive material may fill each via. Here, for example, but not limited to, the top metal may be aluminum, copper, tungsten, nickel, iron, or any alloy thereof. The conductive vias form conductive contacts with both the source region 1111 and the body region 1112, thereby forming an anti-parallel diode. The source top metal 1121 forms conductive contacts with the source RDL layer 1101 through electroplated RDL vias 1122. The RDL vias in the molding material layer 1125 expose the source top metal 1121. RDL material may be plated on the sides of the vias, and in some embodiments (e.g., as shown here), the entire electroplated RDL via 1122 may be filled. The electroplated RDL vias 1122 may be proportionally distributed on the source top metal and conductively coupled to the source and body regions of the substrate structure.

[0074] like Figure 11B As shown, the gate contact region insulating layer 1120 covers the top of the substrate structure above the gate contact region. Vias 1108 through the gate contact region insulating layer 1120 and the trench insulating layer in the gate contact region expose the gate electrode material forming the gate extension 1110. A gate RDL 1106 is located on top of the gate contact region insulating layer 1120. The gate RDL 1106 can be plated on and fill each of the gate RDL plated vias 1124. The conductive gate RDL plated vias 1124 can form conductive contacts with the gate metal layer 1123. The gate metal layer 1123 can be plated on and fill each of the gate contact vias 1108. The conductive gate vias form conductive contacts with the gate extension 1110, which is formed in an insulating trench in a manner similar to that of the gate electrode 1105. A portion of the shielding electrode 1109 can also be formed in the trench along with the gate extension 1110. The RDL vias can be distributed proportionally on the gate contact region 1110. Here, the gate electrode material and the shielding electrode material can be conductive materials, such as polysilicon.

[0075] In the illustrated embodiment, substrate layer 1113 serves as the back drain contact region. Drain insulating layer 1114 is formed below the bottom of the substrate structure. Via 1116 formed through drain insulating layer 1114 exposes substrate 1118. Drain RDL or metal layer 1115 is located below drain insulating layer 1114. Drain RDL is plated on via 1117, as shown here, drain RDL is plated and fills the entire via. Here, drain RDL, source RDL, and gate RDL may be made of conductive materials, such as, but not limited to, copper, aluminum, nickel, tungsten, gold, silver, or any alloy thereof.

[0076] It should be noted that for implementations using trench capacitors (e.g.) Figure 8 The trench capacitor 805 can be formed using any combination of the gate electrode 1105 and the shield electrode 1109, with one end connected to the source terminal or the drain terminal. For example, a trench capacitor can be formed with one end being the top gate electrode 1105 and the other end being the source metal (the shield electrode 1109 is connected to the source terminal).

[0077] Figure 12A and Figure 12B This is a cross-sectional side view of a planar gate MOSFET device in a DRMOS embodiment according to various aspects of the present invention. Figure 12A The cross-section of the device region below the source region RDL1203 is shown. Figure 12B The cross-section of the gate contact region below the gate RDL1213 is shown. In this embodiment, a heavily doped body region 1207 of the second conductivity type is formed in the body region 1208 below the source region RDL1203. A heavily doped source region 1209 of the first conductivity type is formed in the body region. In some embodiments, a doped region 1207a of the second conductivity type may exist between the two source regions 1209. This doped region 1207a is more heavily doped than the heavily doped body region 1207. Alternatively, a shallow trench contact plug of the second conductivity type may be formed in the body region, short-circuiting the source region and the body region on the vertical side of the shallow trench contact plug.

[0078] A planar gate electrode 1202 is located above the substrate structure, on a planar gate insulating layer 1206. In some embodiments, the planar gate insulating layer may enclose the planar gate electrode 1202. In alternative embodiments, a source insulating layer 1215 may isolate the top and sides of the planar gate electrode. A portion of the planar gate electrode overlaps with the source region and the body region.

[0079] like Figure 12B As shown, the planar gate extension 1201 forms an electrical contact between the gate RDL 1213 and the planar gate electrode 1202. The gate RDL may be located at the top edge of the substrate structure, for example... Figure 10As shown. A planar gate electrode contact region insulating layer 1215 is located above the substrate structure in the planar gate electrode contact region. A gate RDL 1213 extends above the planar gate electrode contact region insulating layer 1215. A gate via 1204 passing through the planar gate electrode contact region insulating layer 1215 exposes the gate electrode material forming the planar gate extension 1201. The gate RDL 1213 can be plated on the gate RDL gate via 1204 and can fill the entire via, forming contact with the gate top metal layer 1221. The gate top metal layer 1221 can be plated on the gate via 1204 and can fill the entire via, forming contact with the gate electrode material. RDL vias 1220 can be proportionally distributed on the planar gate electrode contact region.

[0080] Figure 13 This diagram illustrates a top view of a dual-chip solution according to various aspects of the present invention. As shown, a gate controller 1301 is located on a first substrate 1302. Furthermore, in this embodiment, the first substrate includes a first set of drivers 1303 and a second set of drivers 1304 for transistors. The first set of drivers 1303 and the second set of drivers 1304 can be, for example, but not limited to, a high-side transistor driver and a low-side transistor driver, or a low-side driver and a high-side driver. Furthermore, although the first set of drivers 1303 is shown as relatively smaller than the second set of drivers 1304, it should be understood that the size of each set of drivers should be large enough to drive the gate of the transistor connected to it at the desired voltage and current of the device. Typically, the size of the low-side FET is usually larger, for example, 3 to 4 times that of the high-side FET, and the size of the gate driver is scaled accordingly.

[0081] The gate controller 1301 may be an integrated circuit device formed in the first substrate, or it may be made from a discrete device attached to the first substrate, in which case the first substrate can provide structural rigidity and may include trace paths for the gate controller. Similarly, the driver may be made in the first substrate, or it may be made from a discrete component attached to the first substrate.

[0082] In this embodiment, a first group of transistors 1305 and a second group of transistors 1306 are coupled to a second substrate 1307. The first group of transistors 1305 and the second group of transistors 1306 can be fabricated in the second substrate 1307 through a sequential masking, doping, and metallization process, or as discrete transistors attached to the second substrate, in which case the second substrate can provide structural support and may include trace paths for the transistor devices. As shown, each of the first group of transistors 1305 and the second group of transistors 1306 includes two transistors, but aspects of the invention are not limited thereto. Each group of transistors may have at least one transistor, and depending on the embodiment, may have more than two transistors. For example, but not limited to, in a power converter embodiment such as a switch-mode buck-boost converter, the two transistors 1305 in the first group may be high-side transistors, and the two transistors 1306 in the second group may be low-side transistors. In a simpler buck-boost converter embodiment, the high-side transistor group may have a single transistor and / or the low-side transistor group may have a single transistor. While this article discusses implementations integrated into switch-mode power supplies, it should be understood that the application of the dual-chip solution is not limited to this; it can be integrated into any application requiring transistor-controlled switching. Furthermore, the transistors used in the transistor group are not limited to a specific type of transistor (e.g., MOSFETs), and can be any transistor suitable for the application. The types of transistors that can be used in the transistor group include, but are not limited to, bipolar junction transistors (BJTs), field-effect transistors (FETs), metal-oxide-semiconductor (MOS) FETs, junction transistors (JTs), insulated-gate bipolar transistors (IGBTs), unipolar transistors (unipolar transistors), avalanche transistors (APTs), Schottky transistors (SMTs), high electron mobility transistors (HEMTs), and diffused transistors, as well as transistors that can be made from wide-bandgap semiconductor materials, including lateral silicon carbide (SiC) MOSFETs and gallium nitride (GaN) high electron mobility transistors (HEMTs).

[0083] Figure 14 This is a top view schematic diagram illustrating a dual-chip solution with distributed transistor drivers according to various aspects of the present invention. In this embodiment, a gate controller 1401 is coupled to a first substrate 1402. Figure 13In a different embodiment, the drivers are coupled to a second substrate 1407. A first set of gate drivers 1403 and a second set of gate drivers 1404 may each be proportionally distributed between corresponding first sets of transistors 1405 and second sets of transistors 1406. For example, but not limited to, the first set of gate drivers 1403 may be proportionally distributed between transistors in the first set of transistors 1405, and the second set of gate drivers 1404 may be proportionally distributed between transistors in the second set of transistors 1406. As shown, the gate drivers 1403 and 1404 are located inside the second substrate. In some embodiments, vias can connect the gate drivers to interconnects or a horizontal bus that transfers the communication path of the gate drivers to the edge of the second substrate. Alternatively, the gate drivers may be located near the edge of the second substrate. As described above, the distributed gate drivers can be connected to the transistor gates via plated vias in the RDL or conventional metal interconnects.

[0084] Various aspects of this invention include the application of the aforementioned dual-chip solution in single-phase shift (SPS) and dual-phase shift (DPS) applications. In SPS applications, the gate controller has only one switch (SW) output. In contrast, in DPS applications, the gate controller has two SW outputs. Furthermore, for DPS, there are two different sets of high-side FETs and low-side FETs, which are controlled and operated in a specific synchronous manner. For SPS applications, the driver, high-side FET, and low-side FET are arranged in a mirrored configuration (e.g., ...). Figure 14 (As shown) can offer some advantages in terms of metal and package connection.

[0085] Figure 15A This diagram illustrates a top view of a dual-chip device package with a molded interconnect substrate (MIS) according to various aspects of the present invention. The configuration of the MIS substrate is similar to that of a printed circuit board (PCB), but the manufacturing process of the MIS allows for the formation of smaller conductive traces and bonding pads. The MIS substrate is typically fabricated in layers using photolithography and etching processes very similar to those used in semiconductor device manufacturing to form upper metal layer interconnects. Typically, metal (e.g., copper) interconnects are built onto a carrier substrate through a series of electroplating, photolithography, and etching processes. The spaces between the different layers of metal interconnects are filled with a molding compound. The molding compound is ground flat, and the carrier substrate is removed to expose the contact points with the interconnects.

[0086] In this embodiment, the gate controller 1501 on the first substrate 1502 is communicatively coupled to the first group of transistor devices 1505 and the second group of transistor devices 1506 on the second substrate 1507 via conductive traces 1509 in the MIS 1508. As described above, the first substrate 1502 may include a gate driver group for the transistor group, or alternatively, the second substrate 1507 may include a gate driver group; for clarity, the gate drivers are omitted in this figure.

[0087] The conductive traces may include conductive contact pads 1511 that connect conductive posts to the conductive traces in the MIS1508. The conductive posts may connect to conductive plated vias 1510 in the substrate to allow signals to be transmitted from the gate controller (in some embodiments, via a gate driver) through the conductive traces to the transistor on the second substrate. The conductive traces and conductive posts may be made of any suitable conductive material, such as, but not limited to, metals (e.g., copper, iron, nickel, aluminum, lead, or alloys thereof), conductive nonmetals (e.g., graphite), or doped conductive materials (e.g., n-type doped polysilicon). Similarly, the vias 1510 may be plated and / or filled with conductive material as described above.

[0088] The conductive trace 1509 may also include a conductive second chip contact pad 1513. The conductive second chip contact pad 1513 is connected to second chip conductive pillars that can connect the conductive vias 1512 of the second chip 1507 to a first group of transistor devices 1505, a second group of transistor devices 1506, and / or gate drivers (not shown) on the second chip 1507. As shown, conductive traces 1509 and conductive contact pads 1511 and conductive second chip contact pads 1513 may be present for each transistor device in the transistor device group. Alternatively, contact pads and conductive traces may be present for each gate driver. In other alternative embodiments, each conductive pillar may have a corresponding contact pad. Furthermore, it should be understood that any number of conductive traces, pillars, and pads sufficient to control transistors may be provided, depending on the needs of the device. Additionally, the device may include conductive input traces and conductive output traces, which are not shown in the simplified diagram. The conductive input traces can electrically couple the power inputs and power outputs of the first set of transistor devices 1505 and the second set of transistor devices 1506 on the second chip 1507 to device input pads and output pads in the MIS. In some embodiments, these pads are located at the edge of the device package 1520, as shown. The input traces can also communicatively couple the communication pads in the MIS to the communication input of the gate controller. Furthermore, the input traces can electrically couple the power input of the gate controller 1501 to the power input pads in the MIS 1508, which may be located near the edge of the device package 1520, as shown.

[0089] Figure 15B This diagram illustrates a side view of a dual-chip device package having a molded interconnect substrate (MIS) according to various aspects of the present invention. As shown, a set of first substrate conductive pillars 1521 connects a gate controller 1501 on a first substrate 1502 to traces in a MIS 1508. Here, some devices of the gate controller 1501 are formed on top of the first substrate, and some devices are formed inside the first substrate. For example, but not limited to, silicon transistors may be formed in the first substrate, conductive circuitry may be formed on top of the first substrate, and devices such as inductors and capacitors may be attached to the top of the first substrate or alternatively formed inside it. In some embodiments, the circuitry may be part of an RDL below the substrate, rather than on top of the substrate. Furthermore, in some embodiments, devices such as capacitors, diodes, and resistors may also be formed in the substrate. Second substrate conductive pillars 1522 connect a first set of transistor devices 1505, a second set of transistor devices 1506 (and / or gate drivers not shown) on a second substrate 1507 to traces in a MIS 1508. Figure 15B In the illustrated embodiment, the first substrate 1502 is flipped so that the top connection to the gate controller 1501 can be directly connected to the conductive pads on the conductive pillars 1521 of the first substrate. Figure 15B As shown, the second substrate 1507 is also flipped so that the top connections to the first set of transistor devices 1505 and the second set of transistor devices 1506 can be directly connected to the conductive pads (e.g., copper pads) on the conductive pillars 1521 of the first substrate. The first substrate 1502, the second substrate 1507, and any external components attached thereto may optionally be encapsulated in the molding compound 1525, which is conventional practice.

[0090] The transistor and / or gate controller may include a high electron mobility transistor (HEMT) having a heterojunction between two different materials. Therefore, in some embodiments, the transistor and / or gate controller may be formed on and within a substrate by a second material. The substrate and the second material may include, for example, but not limited to: silicon, germanium, gallium, indium, carbon, silicon carbide, silicon nitride, silicon arsenide, gallium arsenide, aluminum gallium arsenide, gallium nitride, indium gallium arsenide, indium gallium nitride, aluminum gallium nitride, silicon germanium, indium phosphide, and aluminum oxide. Furthermore, one advantage of this dual-substrate approach for gate controllers and power transistor devices is that the gate controller can be made of a different material than the first and second sets of transistors. For example, but not limited to, the first substrate may be made of a first material such as silicon, and the second substrate may be made of a different second material such as silicon carbide. One advantage of this technique is the ability to fabricate and use low-cost silicon gate controllers with high breakdown resistance transistors (e.g., silicon carbide transistors). Another advantage of this approach is that relatively simple transistor sets can use larger and less expensive process nodes, while more complex gate controllers can use smaller process nodes. For example, but not limited to, the minimum feature size of the gate controller can be 55 nanometers, and the minimum feature size of the transistor array can be between 0.14 micrometers and 0.2 micrometers. Finally, in some embodiments, the MIS can be replaced with a thin film such as a flexible polyimide film material, and the conductive pillars can be made of a material suitable for the film.

[0091] In an alternative implementation, one of the two substrates 1502 and 1507 may be configured with a flip-chip, while the other may not. The unflipped chip may be placed on top of the MIS, and the connections on top of the unflipped chip may be connected to conductive pads in the MIS via bonding pads and bonding wires. An example of this implementation is shown below. Figures 16A-16B As shown.

[0092] Figure 16A This is a top view schematic diagram illustrating a dual-chip device package having a gate controller and a molded interconnect substrate (MIS) according to various aspects of the present invention. This is consistent with... Figure 15A and 15B The illustrated implementation is similar, except that the gate controller 1601 is not flipped, exposing the contact pads 1634 for the bonding wire 1632. The bonding wire 1632 connects the gate controller contact pads 1634 to the MIS contact pads 1633, enabling electrical signals to be transmitted from the gate controller 1601 (in some embodiments via the gate driver) through conductive traces 1609 in the MIS 1607 to the first set of transistor devices 1505 and the second set of transistor devices 1506 on the second substrate. The bonding wire 1632 can be made of any suitable bonding wire material, such as, but not limited to, gold, silver, copper, aluminum, or any alloy thereof.

[0093] Figure 16B This is a side view schematic diagram illustrating a dual-chip device package having a gate controller and a molded interconnect substrate (MIS) according to various aspects of the present invention. It can be seen that the non-flipped orientation of the first substrate 1602 positions the gate controller 1601 on the surface of the first substrate 1602 away from the MIS 1607, which is consistent with... Figure 15A and 15B The orientation of the second substrate 1507 is different. The flip orientation positions the first group of transistor devices 1505 and the second group of transistor devices 1506 near the MIS 1607. The connection between the first group of transistor devices 1505, the second group of transistor devices 1506 and the MIS 1607 can be achieved via copper pillars 1522 and contact pads (not shown) on the flip surface of the second substrate 1507. The first substrate 1602, the second substrate 1507, and any external components attached thereto can be encapsulated in a molding compound, such as... Figure 15B As shown. For clarity, Figure 16B The molding compound was not shown in the data.

[0094] Figure 17A This is a top view schematic diagram illustrating a dual-chip device package with a conventional lead frame according to various aspects of the present invention. This embodiment is related to... Figure 15A The illustrated implementation is similar, but uses a leadframe package instead of conductive traces in molded material. The leadframe package can use conductive bus 1742 (also referred to as conductive leads) to connect the gate controller 1701 on the first substrate 1702 to a first group of transistor devices 1505 and a second group of transistor devices 1506 on the second substrate 1507. The conductive bus 1742 can be supported by the device frame 1720. The conductive bus 1742 may include first substrate bus contacts 1743, which provide connection points for conductive vias on the first substrate and conductive posts of the gate controller. Furthermore, the conductive bus 1742 may also include second substrate bus contacts 1744, which provide connection points for conductive vias on the second substrate 1507 and conductive posts of the transistor groups.

[0095] Similar to the conductive traces discussed above, this device may include conductive input buses and conductive output buses, which are not shown in the simplified diagram. The conductive input buses electrically couple the power inputs and power outputs of the first group of transistor devices 1505 and the second group of transistor devices 1506 on the second substrate 1507 to the device input pads and output pads on the device frame 1720, as shown. The input buses also communicatively couple the communication pads on the device frame 1720 to the communication input of the gate controller. Furthermore, the input buses electrically couple the power supply input of the gate controller to the power input pads on the device frame 1720, as shown.

[0096] Figure 17B This is a side view schematic diagram of a dual-chip device package with a conventional lead frame according to various aspects of the present invention. From this angle, it can be clearly seen that the first substrate bus contact 1743 connects the conductive bus 1742 to the first substrate 1702 and the gate controller 1701 via conductive posts 1721. Here, the gate controller 1701 is formed inside the first substrate. Furthermore, it can be seen that the second substrate bus contact 1744 connects the conductive bus 1742 to the second substrate 1507 and the first group of transistor devices 1505 and the second group of transistor devices 1506 via conductive posts 1722. Figure 15A and Figure 15B Similarly, both the first substrate 1702 and the second substrate 1507 are configured with a flip-chip design, allowing direct contact between the contact pads on the front side of the second substrate and the conductive pillars 1722. The first substrate 1702, the second substrate 1507, and any external components attached thereto can be encapsulated in a molding compound, such as... Figure 15B As shown. For clarity, Figure 17B The molding compound was not shown in the data.

[0097] Figure 18A This is a top view schematic diagram illustrating a dual-chip device package having a flip-chip gate controller and a conventional lead frame 1831 according to various aspects of the present invention. This embodiment is related to... Figure 17A and 17B The implementation described herein is similar, except that the gate controller 1801 is not flipped, exposing the contact pad 1834 for the bonding wire 1832. The bonding wire 1832 connects the gate controller contact pad 1834 to the bus contact pad 1833, enabling electrical signals to be transmitted from the gate controller 1801 (in some embodiments via a gate driver) through the bus 1842 to the first set of transistor devices 1505 and the second set of transistor devices 1506 on the second substrate. The bonding wire 1832 can be made of any suitable bonding wire material, such as, but not limited to, gold, silver, copper, aluminum, or any alloy thereof. Here, the bus may include second substrate bus contacts 1844, which provide connection points for conductive vias and conductive posts of transistor groups that can be connected to the second substrate 1507.

[0098] In some embodiments, one or more discrete electronic components may optionally be mounted directly on the back side of the die without being connected via a MIS. For example, such discrete electronic components may include capacitors, diodes (e.g., transient voltage suppression (TVS) diodes), heat sinks, etc. In some embodiments, one or more surface-mount electronic components 1846 may be attached to the back side of the gate controller 1801 die (i.e., the first substrate 1502) and connected to the lead frame 1831 via bonding wires. The surface-mount component 1846 may be a capacitor, diode, resistor, or transistor. Alternatively, one or more back-to-back mounted components 1848 may be mounted (e.g., by soldering) to the back metal contact 1849 on the gate controller 1801. For example, the back-to-back mounted component may be a capacitor, inductor, diode, or resistor with two terminals. One terminal forms an electrical contact with the gate controller 1801 via the back metal contact 1849, and the other terminal forms a contact with the lead frame 1831 via a bonding wire. Although Figure 18A The discrete components mounted on the back side of the gate controller 1801 are shown, but aspects of the invention are not limited thereto. In an alternative embodiment, the discrete components may be similarly mounted on the back side of the transistor die (i.e., the second substrate 1507).

[0099] Figure 18B This is a side view schematic diagram illustrating a dual-chip device package having a flip-chip gate controller and a conventional lead frame according to various aspects of the present invention. It can be seen that the non-flip orientation positions the gate controller 1801 on the surface of the first substrate 1802 near the support plate 1850, which is consistent with... Figure 17A and 17B Different. With Figure 16B Similarly, the first substrate 1802 is not flipped for bonding wire connections, while the second substrate 1507 is flipped for connection to the lead frame 1831 via conductive posts 1822. The first substrate 1802, the second substrate 1507, and any external components attached thereto can be encapsulated in a molding compound, such as... Figure 15B As shown. For clarity, Figure 18B The molding compound is not shown.

[0100] Aspects of the invention include embodiments in which an external component (not flipped) is placed on top of a flip chip assembly, and the external component is connected to the MIS via bonding wires and bonding pads. For external components (e.g., capacitors) having terminals on both the top and bottom, terminals on one side can be directly connected to the flip chip via ground (e.g., PGND) contacts on the back of the flip chip, and terminals on the other side can be connected to the MIS via bonding wires and bonding pads.

[0101] Figure 19This is a side view schematic diagram illustrating a three-chip device package with a three-dimensional stacked arrangement according to various aspects of the present invention. In this embodiment, a single gate controller 1901 and four sets of transistors are shown on a first substrate 1902. A first set of transistors 1905 and a second set of transistors 1906 are located on a second substrate 1907, and a third set of transistors 1915 and a fourth set of transistors 1916 are located on a third substrate 1917. Here, the second substrate 1907 and the third substrate 1917 are stacked on top of each other, with a second MIS 1910 inserted between them. All three substrates 1902, 1907, and 1917 are in a flip-chip configuration. As described above, conductive interconnect pillars 1920 connect the second substrate 1907 to conductive traces in the first MIS 1904. Similarly, conductive pillars 1925 connect the third substrate to conductive traces in the second MIS 1910. Furthermore, conductive interconnect pillars 1922 can connect traces in the first MIS 1904 to the second MIS 1910. Furthermore, the bottom post 1923 can connect the traces in the second MIS 1910 to the connection point in the first substrate 1902, which allows the gate controller 1901 to control the transistors in the third substrate 1917.

[0102] Figure 20 This diagram illustrates a side view of a four-chip device package with a three-dimensional stacked arrangement according to various aspects of the present invention. In this example, all four substrates 1902, 1907, 1917, and 2050 are in a flip-chip configuration. In this embodiment, a second gate controller 2010 located on the fourth substrate 2050 is coupled to a second MIS 2011, forming a complete second power stage on the second MIS 2011 stacked above the first substrate 1902, the second substrate 1907, and the first MIS 1904. The second power stage can also be communicatively coupled to the first gate controller 1901 via bottom conductive posts 2023 and / or conductive interconnect posts 2022. As shown, conductive posts 2021 can connect the second gate controller 2010 to traces in the second MIS 2011. The addition of the second gate controller and the connection between the second gate controller and the first gate controller enables operational synchronization, and allows the other power stage to serve as a backup in the event of a failure in one power stage. Alternatively, this configuration can be used for multiphase operation, such as embodiments involving three or more phases.

[0103] Figure 21 This is a flowchart illustrating a dual-chip solution manufacturing process according to various aspects of the present invention. As shown here, a first set of transistors 2101 can be formed using a second substrate. This can be achieved through appropriate photolithography processes, including masking, doping, and metallization steps. Furthermore, a second set of transistors 2103 can be formed in the second substrate simultaneously, after, or before the formation of the first set of transistors, using appropriate photolithography processes (including masking, doping, and metallization steps).

[0104] In another step, the gate controller 2102 may be formed in the first substrate before, after, or during the formation of the transistor. The gate controller may be made from a discrete component attached to and connected to the first substrate via traces on the first substrate, or formed in the first substrate by appropriate photolithography processes, including masking, doping, and metallization steps.

[0105] The busbars in the device frame or the traces in the MIS or thin film can be fabricated using wire bonding or photolithography to form conductive paths. Next, the gate controller on the first substrate can be connected to the conductive path 2104. This can be achieved by soldering or bonding conductive pads on the first substrate to conductive pillars. The conductive pillars may already be bonded to the conductive pads in the conductive path, or the conductive pillars may be attached to the conductive pads on the substrate first, and then to the conductive path. Once the gate controller integrated circuit is attached to the conductive path, the transistor on the second substrate can be attached to the conductive path 2105 in a similar manner. Alternatively, the transistor on the second substrate can be connected to the conductive path before the gate controller on the first substrate.

[0106] As described above, it should be understood that the transistor array on the second substrate may be made of a different material (e.g., a different substrate) than the gate controller. Furthermore, the minimum or minimum feature size of the gate controller may differ from that of the transistor array.

[0107] The improved DRMOS devices of the type described in this article can be fabricated using a distributed contact layout in the transistor device, thereby achieving more uniform transistor switching and reducing device area. Furthermore, employing distributed gate drives in wafer-level or panel-level packaging can reduce parasitic inductance, reduce device area, and improve robustness by distributing failure points among multiple drivers. Finally, employing both a distributed contact layout and a distributed gate drive simultaneously provides an enhanced DRMOS device that combines all of the above advantages. The dual-chip solution also offers the additional benefits of reduced assembly costs, smaller package size, and the ability to achieve advanced packaging styles.

[0108] While the foregoing is a complete description of preferred embodiments of the invention, various alternatives, modifications, and equivalents may be used. Therefore, the scope of the invention should not be determined by reference to the foregoing description, but rather by reference to the appended claims and their full scope of equivalents. Any feature described herein (whether preferred or not) may be combined with any other feature described herein (whether preferred or not). In the following claims, the indefinite article “a” or “an” refers to one or more items immediately following the article, unless expressly stated otherwise. The appended claims should not be construed as including means plus functional limitations, unless such limitations are expressly described in a particular claim using the phrase “means for…”.

Claims

1. A power device, characterized in that, include: A gate controller coupled to the first substrate; A first group of one or more transistor devices coupled to a second substrate; as well as A second set of one or more transistor devices coupled to the second substrate, wherein the first set of transistor devices is configured for high-side switching in a power conversion device, and the second set of transistor devices is configured for low-side switching in the power conversion device, wherein the first set of transistor devices and the second set of transistor devices are communicatively coupled to the gate controller, wherein the gate controller is configured to drive the gates of the first set of transistor devices and the second set of transistor devices.

2. The power device according to claim 1, characterized in that, The first group of transistor devices and the second group of transistor devices each include one or more gate drivers.

3. The power device according to claim 2, characterized in that, The one or more gate drivers of the first group of transistor devices are distributed proportionally among the transistor devices in the first group of transistor devices.

4. The power device according to claim 2, characterized in that, The one or more gate drivers of the second group of transistor devices are distributed proportionally among the transistor devices in the second group of transistor devices.

5. The power device according to claim 1, characterized in that, The gate controller is communicatively coupled to the first group of transistor devices and the second group of transistor devices via conductive traces in a molded interconnect substrate or thin film substrate.

6. The power device according to claim 1, characterized in that, The gate controller is communicatively coupled to the first group of transistors and the second group of transistors via conductive leads in the lead frame package.

7. The power device according to claim 5 or 6, characterized in that, The gate controller is connected to the conductive trace or the conductive lead via at least one bonding wire.

8. The power device according to claim 1, characterized in that, The first group of transistor devices and the second group of transistor devices are formed of semiconductor materials different from those of the gate controller.

9. The power device according to claim 1, characterized in that, The feature size of the gate controller is different from the feature size of the first group of transistors and the second group of transistors.

10. The power device according to claim 9, characterized in that, The feature size of the first group of transistor devices and the second group of transistor devices is smaller than the feature size of the gate controller.

11. The power device according to claim 1, characterized in that, It further includes one or more discrete electronic components mounted on the back side of a die containing the gate controller or a die containing the first set of transistor devices and the second set of transistor devices.

12. The power device according to claim 11, characterized in that, The one or more discrete electronic components include one or more surface mount components or back-to-back mounted components.

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