Pulse current source adaptive overshoot protection control method, system, test power supply equipment and test system

Abstract

This invention discloses an adaptive overshoot control method, system, test power supply equipment, and test system for pulse current sources. The method includes an adaptive iterative phase: extracting the average duty cycle of the tail time window of the previous pulse cycle and using it as the target feedforward value for the current pulse cycle; wherein the tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized; within the current pulse cycle, before the freeze delay time of the integrator arrives, only the target feedforward value is injected into the PWM generator of the subsequent converter; and after the freeze delay time arrives, the integrator begins to operate, and the target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter. This invention helps to avoid deep integral saturation and fatal overshoot, and it helps to adapt to the nonlinearity and discreteness of semiconductor loads, thereby avoiding the failure of traditional feedforward compensation.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to an adaptive overshoot control method, system, test power supply equipment, and test system for pulse current sources. Background Technology

[0002] In high-power semiconductor device testing applications, test power supplies are typically required to output high-power currents with microsecond-level rise times (e.g., 20 µs) and extremely high peak currents (e.g., 500 A).

[0003] In existing technologies, two-stage switching power supply topologies are widely used. At the control strategy level, the downstream converter employs traditional proportional-integral-derivative (PID) closed-loop regulation, or a composite closed-loop control strategy combined with fixed feedforward parameters. For extremely fast, large-step operating conditions of nonlinear loads, the existing two-stage switching power supply topologies using traditional closed-loop control technology have the following significant drawbacks: Firstly, the control loop is prone to deep integral saturation and fatal overshoot: When the system is required to respond to a step input of hundreds of amperes within an extremely short time (e.g., 20µs), the transient error is drastically amplified. The integral control unit in a traditional PI controller will rapidly and blindly accumulate during this phase, leading to deep integral saturation. When the output current approaches the target threshold, the accumulated integral cannot achieve transient desaturation, resulting in an excessively high duty cycle output and severe current overshoot. For sensitive semiconductor loads with extremely low heat capacity, this overshoot can easily cause irreversible thermal breakdown damage to the semiconductor device.

[0004] Secondly, the nonlinearity and discreteness of semiconductor loads cause traditional feedforward compensation to fail: the series components of the semiconductor device under test exhibit exponential nonlinear VI characteristics, accompanied by temperature drift and individual manufacturing differences, and its impedance model has strong time-varying and unpredictable properties. The system cannot predict the steady-state duty cycle corresponding to different target currents by establishing a definite mathematical model, making traditional feedforward compensation mechanisms based on lookup tables or fixed parameters unsuitable.

[0005] Thirdly, topology cascading leads to dynamic response mismatch and steady-state noise interference: when the output limit pulse of the downstream converter is deloaded, the upstream converter is limited by its limited closed-loop bandwidth and cannot achieve transient energy matching compensation, resulting in a severe drop in the intermediate bus voltage and deterioration of the output pulse quality. Summary of the Invention

[0006] This invention provides an adaptive overshoot control method, system, test power supply equipment, and test system for pulse current sources.

[0007] According to one aspect of the present invention, an adaptive overshoot prevention control method for pulse current sources is provided, applied to a two-stage switching power supply topology, the method comprising an adaptive iterative phase: The average duty cycle of the tail time window of the previous pulse cycle is extracted and used as the target feedforward value for the current pulse cycle; wherein, the tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized. During the current pulse cycle, before the freeze delay time of the integrator is reached, only the target feedforward value is injected into the PWM generator of the subsequent converter; and after the freeze delay time is reached, the integrator starts to work, and the target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter.

[0008] Optionally, the step of using only the target feedforward value as the input to the PWM generator of the subsequent converter within the current pulse period, before the freeze delay time of the integrator arrives, specifically includes: Within the current pulse cycle, before the freeze delay time of the integrator is reached, the target feedforward value is divided into multiple stepped proportional segments for equal-time injection within the rising edge time of the pulse current.

[0009] Optionally, the freeze delay time of the integrator is dynamically segmented according to the target pulse current amplitude; wherein the freeze delay time of the integrator is positively correlated with the target pulse current amplitude.

[0010] Optionally, the adaptive iteration phase further includes: During the first pulse cycle, the target feedforward value is forcibly set to 0, and the initial test current is established only after the integrator starts working.

[0011] Optionally, the adaptive iteration phase further includes: If the error of the average tail current of M consecutive pulse cycles meets the standard, then the target feedforward value is locked and the adaptive iteration phase ends.

[0012] Optionally, after the adaptive iteration phase, the following steps are also included: During multiple pulse cycles, before the freeze delay time of the integrator is reached, the locked target feedforward value is injected into the PWM generator of the subsequent converter only; and after the freeze delay time is reached, the integrator starts to work, and the locked target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter.

[0013] Optionally, before the first pulse current output of the subsequent converter, the preceding converter is woken up by a preset time. The preceding converter directly switches in and starts up at a preset switching frequency and operates in a closed loop to replenish energy to the input capacitor.

[0014] Optionally, the front-end converter is an isolated DC-DC converter; And / or, the subsequent converter is a multiphase interleaved buck converter; The input capacitor is located between the pre-stage converter and the post-stage converter. The pre-stage converter replenishes energy to the input capacitor and provides an intermediate bus voltage.

[0015] Optionally, after the pulse current output of the subsequent converter ends, the ripple output of the preceding converter is blocked, causing the preceding converter to enter a standby hiccup mode.

[0016] According to another aspect of the present invention, an adaptive overshoot prevention control system for pulse current sources is provided, applied to a two-stage switching power supply topology, the system comprising: The tail time window sampling module is used to extract the average duty cycle of the tail time window of the previous pulse cycle and use it as the target feedforward value for the current pulse cycle; wherein, the tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized. An integrator is used to inject the target feedforward value into the PWM generator of the subsequent converter only during the current pulse period, before the freeze delay time of the integrator arrives; and after the freeze delay time arrives, the integrator starts to work, and the target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter. The delay configuration module is used to generate the freeze delay time.

[0017] Optionally, the pulse current source adaptive overshoot prevention control system also includes: A stepped feedforward generator is used to divide the target feedforward value into multiple stepped proportional segments for equal-time injection within the rising edge time of the pulse current, before the freeze delay time of the integrator is reached during the current pulse cycle.

[0018] Optionally, the pulse current source adaptive overshoot prevention control system also includes: The pre-stage converter collaborative control module is used to wake up the pre-stage converter in advance at a preset time before the first pulse current output of the subsequent stage converter. The pre-stage converter directly switches in and starts up at a preset switching frequency and operates in a closed loop to replenish energy to the input capacitor. After the pulse current output of the subsequent stage converter ends, the pre-stage converter's waveform is blocked, so that the pre-stage converter enters a standby hiccup mode.

[0019] According to another aspect of the present invention, a test power supply device is provided, comprising a two-stage switching power supply topology and a controller, the controller being configured to execute the pulse current source adaptive overshoot control method as described in any embodiment of the present invention.

[0020] According to another aspect of the present invention, a testing system is provided for testing semiconductor devices, including the test power supply equipment and measuring instruments described in any embodiment of the present invention.

[0021] This invention employs a pure integral + feedforward control method with cross-cycle adaptive learning, enabling the actual current to gradually increase within each pulse cycle. This helps avoid deep integral saturation and fatal overshoot. Furthermore, since the target feedforward value gradually increases with the pulse cycle, it helps adapt to the nonlinearity and discreteness of semiconductor loads, thereby avoiding the failure of traditional feedforward compensation.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart of an adaptive overshoot control method for a pulse current source provided in an embodiment of the present invention; Figure 2 A cross-cycle adaptive current waveform diagram provided in an embodiment of the present invention; Figure 3 A timing waveform diagram of a single pulse period is provided for an embodiment of the present invention; Figure 4 Another cross-cycle adaptive current waveform diagram provided in an embodiment of the present invention; Figure 5 A waveform diagram showing the enable timing coordination between a front-end converter and a back-end converter, provided in an embodiment of the present invention; Figure 6 A flowchart of another pulse current source adaptive overshoot control method provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a pulse current source adaptive overshoot prevention control system provided in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] This invention aims to provide an adaptive overshoot control method for pulse current sources, applied to a two-stage switching power supply topology. An input capacitor connects the front-stage and rear-stage converters, with the front-stage converter supplying energy to the input capacitor to provide an intermediate bus voltage. The front-stage converter can be an isolated DC-DC converter (such as an LLC resonant converter or a phase-shifted full-bridge converter), and the rear-stage converter can be a multiphase interleaved buck converter. This invention utilizes a pure integral + feedforward control architecture with cross-cycle adaptive learning to solve the integral saturation overshoot problem caused by sudden large current changes within a very short time, achieving extremely fast and smooth pulse current drive for unknown nonlinear loads.

[0028] Figure 1 This is a flowchart illustrating an adaptive overshoot control method for a pulse current source, provided in an embodiment of the present invention. See also... Figure 1 The adaptive overshoot control method for this pulse current source includes an adaptive iterative stage. Specifically, the adaptive iterative stage enables a pulse current generation method with no proportional (P) gain and adaptive feedforward dominance. The control process is divided into two parts: cross-cycle adaptive iteration and intra-cycle anti-overshoot execution, including the following steps: S110. Extract the average duty cycle of the tail time window of the previous pulse cycle and use it as the target feedforward value for the current pulse cycle.

[0029] The tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized. This step is a cross-cycle adaptive iterative step.

[0030] S120. During the current pulse cycle, before the freeze delay time of the integrator is reached, only the target feedforward value is injected into the PWM generator of the subsequent converter; and after the freeze delay time is reached, the integrator starts to work, and the target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter.

[0031] This step is the intra-cycle overshoot suppression step. Before the freeze delay time arrives, overshoot within the pulse cycle is suppressed by injecting only the target feedforward value into the PWM generator of the subsequent converter. After the freeze delay time arrives, only the output of the integrator is superimposed with the target feedforward value. This embodiment of the invention abandons proportional (P) regulation and adopts pure integral (I) control. When the current pulse cycle begins, the integrator's initial value is reset to 0 and it is in a frozen state; the output current of the subsequent converter is driven to climb solely by the target feedforward value. This continues until the set freeze delay time has elapsed. Tdelay Afterwards (when the output current driven by the target feedforward value has stabilized), the integrator is unfrozen and begins to integrate and accumulate based on the error between the actual current and the target current to eliminate steady-state error. Therefore, this embodiment of the invention can achieve a proportional (P) gain, which helps to avoid deep integration saturation and fatal overshoot.

[0032] Figure 2 This is a cross-cycle adaptive current waveform diagram provided as an embodiment of the present invention. See also... Figure 2 During the first pulse cycle, the actual current output by the subsequent converter gradually increases, approaching the target current. The average duty cycle of the tail time window of the first pulse cycle is extracted as the target feedforward value for the second pulse cycle. During the second pulse cycle, the actual current output by the subsequent converter gradually increases, even closer to the target current. The average duty cycle of the tail time window of the second pulse cycle is extracted as the target feedforward value for the third pulse cycle. During the third pulse cycle, the actual current output by the subsequent converter gradually increases and eventually stabilizes near the target current. The average duty cycle of the tail time window of the third pulse cycle is extracted as the target feedforward value for the fourth pulse cycle. Since the duty cycle of the tail time window in the third pulse cycle is sufficient to stabilize the actual current near the target current, the average duty cycle of the tail time window in the third pulse cycle is used as the target feedforward value for the fourth pulse cycle, ensuring that the actual current in the fourth pulse cycle and subsequent pulse cycles can quickly stabilize near the target current. It should be noted that... Figure 2The example illustrates how the actual current eventually stabilizes near the target current using three pulse cycles, but this is not intended to limit the invention. In other embodiments, the time required for the actual current to eventually stabilize near the target current can be adjusted by changing the integration parameters of the integrator.

[0033] Therefore, the embodiments of the present invention, through a pure integral + feedforward control method with cross-cycle adaptive learning, enable the actual current to gradually increase within each pulse cycle, which helps to avoid deep integral saturation and fatal overshoot. Furthermore, since the target feedforward value gradually increases with the pulse cycle, it helps to adapt to the nonlinearity and discreteness of semiconductor loads, thereby avoiding the failure of traditional feedforward compensation.

[0034] Figure 3 This is a timing waveform diagram of a single pulse period provided in an embodiment of the present invention. See also... Figure 3 Based on the above embodiments, optionally, within the current pulse period (i.e., a single pulse period), the freeze delay time of the integrator is... Tdelay Before reaching the target feedforward value, the rising edge time of the pulse current is divided into multiple stepped proportional segments for equal-time injection. Figure 3 For example, the target feedforward value is divided into three stepped proportions: 30%, 60%, and 100%. This setting divides the target feedforward value into three equal stages and maps them equally over time, gradually injecting them into the pulse width modulation (PWM) generator. Therefore, this embodiment of the invention employs a dual anti-overshoot mechanism of multi-step feedforward injection and anti-saturation delay integration, which further facilitates the gradual increase of the pulse current.

[0035] Therefore, the embodiments of the present invention aim to provide an adaptive overshoot control method for pulse current sources. By combining cross-cycle adaptive learning with segmented timing coordination within a single cycle, a pure integral + feedforward control architecture is used to improve the integral saturation overshoot problem caused by sudden large current changes in a very short time, thereby achieving extremely fast and smooth pulse current drive for unknown nonlinear loads.

[0036] Based on the above embodiments, optionally, the freeze delay time of the integrator is dynamically segmented according to the target pulse current amplitude; wherein, the freeze delay time of the integrator is positively correlated with the target pulse current amplitude. This setting ensures that the larger the target pulse current amplitude, the longer the freeze delay time is set; and the smaller the target pulse current amplitude, the shorter the freeze delay time is set. Specifically, the larger the target pulse current amplitude, the longer the required rise time, and the longer the set freeze delay time, which helps ensure that the output current driven by the target feedforward value has stabilized when the integrator is unfrozen.

[0037] In practical applications, the freeze delay time of the integrator can be dynamically calculated by looking up a table or by using a formula. Tdelay .

[0038] Figure 4 Another cross-cycle adaptive current waveform diagram provided in an embodiment of the present invention. See also Figure 4 Based on the above embodiments, optionally, the adaptive iteration stage further includes: within the first pulse period (i.e., the first pulse period), the target feedforward value is forcibly set to 0, only when the freeze delay time is reached. Tdelay After the integrator starts working, it establishes an initial test current. During the freeze delay time... Tdelay No internal current output. After the freeze delay time... Tdelay The integrator then slowly accumulates the output safety detection current to ensure that there is absolutely no overshoot during the initial pulse cycle optimization.

[0039] Based on the above embodiments, optionally, the adaptive iteration stage further includes: detecting whether the average error of the tail current over M consecutive pulse cycles meets the standard; if so, locking the target feedforward value and ending the adaptive iteration stage. Here, the average value of the actual output current and the average duty cycle value can be extracted simultaneously within the tail time window. The average error of the tail current is the error between the average tail current and the target current value. If this error is less than the set allowable error threshold for M consecutive times (e.g., preferably 3 times), it is determined that the current target feedforward value has converged and stabilized, the adaptive iteration stops, and the target feedforward value is locked for subsequent pulse cycles.

[0040] Based on the above embodiments, optionally, after the adaptive iteration stage, the method further includes: during multiple pulse cycles, before the freeze delay time of the integrator is reached, injecting only the locked target feedforward value into the PWM generator of the subsequent converter; and after the freeze delay time is reached, the integrator starts to work, and the locked target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter.

[0041] Based on the above embodiments, optionally, a maximum upper limit number of pulse cycles in the adaptive iteration phase can be set. If the number of pulse cycles in the adaptive iteration phase exceeds the set maximum upper limit number and still fails to converge, it indicates that the integration parameters set by the integrator are inappropriate or there are other reasons, and an error will be directly reported and the output will be terminated.

[0042] Based on the above embodiments, optionally, if an open circuit / short circuit of the semiconductor load is detected, an error is directly reported and the output is terminated.

[0043] Figure 5 This is a waveform diagram illustrating the enable timing coordination between a pre-stage converter and a post-stage converter, provided as an embodiment of the present invention. See also... Figure 5Based on the above embodiments, optionally, before the first pulse current output of the subsequent converter, the preceding converter is woken up by a preset time (e.g., 10 µs). The preceding converter directly switches in and starts up at a preset switching frequency and operates in closed loop, replenishing energy to the input capacitor. The start-up time of the preceding and following converters can be controlled by an enable signal. Specifically, the start-up time of the preceding and following converters can be controlled by a timer signal. t 0 Upon receiving the start command "trigger" from the host computer, the pre-amplifier is immediately enabled; wait until the time is up. t 1 Then enable the subsequent converter; after the pulse ends, both the preceding and following converters are in an disabled state. t 0 and t 1 The time difference is the pre-wake-up phase of the preceding converter. This setting helps to avoid the output limit pulse of the following converter from being deloaded, thereby helping to avoid a severe drop in the intermediate bus voltage and improving the output pulse quality.

[0044] Based on the above embodiments, optionally, after the pulse current output of the subsequent converter ends, the ripple output of the preceding converter is blocked, causing the preceding converter to enter a standby burst mode. In the standby burst mode, it only operates briefly when the intermediate bus voltage is below the safety lower limit, ensuring no high-frequency switching noise during the pulse interval measurement period. This helps prevent the continuous high-frequency switching action of the test power supply equipment from injecting conducted and radiated electromagnetic interference (EMI) into the test circuit, affecting the measurement accuracy of the measuring instrument.

[0045] Figure 6 A flowchart of another pulse current source adaptive overshoot prevention control method provided in an embodiment of the present invention. See also... Figure 6 Based on the above embodiments, the method may optionally include an adaptive iteration phase, specifically including the following steps: S210. Receive the target current and look up the table to obtain the integral delay. Tdelay .

[0046] S220. Determine if the current pulse period is the first pulse period; if yes, execute S230; otherwise, execute S240.

[0047] S230, Target feedforward value cleared to zero.

[0048] S240. Update the target feedforward value based on the average duty cycle of the tail time window of the previous pulse cycle.

[0049] S250, execute a single pulse cycle.

[0050] Within a single pulse cycle, the actual current gradually increases.

[0051] S260, tail time window sampling.

[0052] S270: Determine whether the average error of the tail current is less than the allowable error threshold; if yes, execute S280; otherwise, execute S2A0.

[0053] S280, Pulse cycle count +1.

[0054] S290. Determine if the number of consecutive pulse cycles is equal to M; if yes, end the adaptive iteration phase; otherwise, return to S220.

[0055] S2A0, Pulse cycle count reset to zero.

[0056] In summary, compared with the prior art, the embodiments of the present invention can achieve at least the following significant beneficial effects: Firstly, it completely eliminates overshoot caused by integral saturation: by using a multi-segment stepped feedforward dominance at the beginning of the pulse cycle combined with a dynamic delay integration intervention mechanism based on the target current, it avoids the blind accumulation of the integrator in the large error stage, and achieves a rapid ramp-up to 500A within 20us with no current overshoot, which greatly protects the expensive and fragile nonlinear test load.

[0057] Secondly, it perfectly adapts to unknown nonlinear loads: there is no need to know the VI characteristics of the semiconductor device combination under test in advance. Through a cross-cycle learning mechanism based on the average acquisition of the tail time window, it can start from zero (target feedforward value is 0) and automatically approach and lock the most accurate feedforward duty cycle with only a few safe trial pulses.

[0058] Thirdly, the purity and power supply stability of the aging test are improved by introducing a decoupled control for the linkage between the front and rear stages. The pre-wake-up mechanism effectively solves the problem of bus voltage drop caused by transient load withdrawal due to high current pulses; while the measurement silence mechanism ensures that no electromagnetic interference is generated during the pulse shutdown period, significantly improving the sampling accuracy of external instruments for test data.

[0059] Fourthly, the algorithm exhibits strong robustness and engineering feasibility: it decomposes complex nonlinear problems into multi-cycle trial-and-error learning and single-cycle fixed-form execution. The algorithm has low computational resource consumption and possesses an open / short-circuit fault-tolerant exit mechanism, greatly improving the reliability of industrial aging test power supply equipment.

[0060] This invention also provides an adaptive overshoot protection control system for a pulse current source, which is used to execute the adaptive overshoot protection control method for a pulse current source provided in any embodiment of this invention. This adaptive overshoot protection control system can be implemented in hardware and / or software and configured in the controller of the test power supply equipment.

[0061] Figure 7 This is a schematic diagram of a pulse current source adaptive overshoot prevention control system provided in an embodiment of the present invention. See also... Figure 7 The pulse current source adaptive overshoot prevention control system includes: a tail time window sampling module 310, used to extract the average duty cycle value of the tail time window of the previous pulse cycle and use it as the target feedforward value for the current pulse cycle; wherein, the tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized. The tail time window sampling module 310 is input with the actual current. Ifbk .

[0062] The pulse current source adaptive overshoot control system also includes an integrator 320, used to adjust the integrator's freeze delay time within the current pulse period. Tdelay Before arrival, only the target feedforward value is injected into the PWM generator of the subsequent converter; and during the freeze delay time... Tdelay Upon arrival, the integrator begins operation, and the target feedforward value and the integrator's output are superimposed and injected into the PWM generator of the subsequent converter. The integrator 320 receives the target current as input. Iref and actual current Ifbk The integrator is unfrozen and begins operating based on the actual current. Iref With target current Ifbk The error is integrated and accumulated to eliminate the steady-state error.

[0063] The pulse current source adaptive overshoot control system also includes: a delay configuration module 330, used to generate a freeze delay time. Tdelay .

[0064] Optionally, the pulse current source adaptive overshoot prevention control system further includes: a stepped feedforward generator 340, used to divide the target feedforward value into multiple stepped proportional segments with equal-time injection within the current pulse period, before the freeze delay time of the integrator arrives. The stepped feedforward generator 340 outputs the target feedforward value. DFF .

[0065] Optionally, the pulse current source adaptive overshoot control system further includes: a front-stage converter cooperative control module 350, which is used to wake up the front-stage converter in advance at a preset time before the first pulse current output of the rear-stage converter, so that the front-stage converter can directly switch in and start up at a preset switching frequency and run in closed loop to replenish energy to the input capacitor; and, after the pulse current output of the rear-stage converter ends, the front-stage converter is blocked from emitting waves, so that the front-stage converter enters a standby hiccup mode.

[0066] This invention also provides a test power supply device, including a two-stage switching power supply topology and a controller. The controller is used to execute the pulse current source adaptive overshoot control method provided in any embodiment of this invention, and has corresponding beneficial effects.

[0067] This invention also provides a testing system for testing semiconductor devices, including the test power supply equipment and measuring instruments provided in any embodiment of this invention, and has corresponding beneficial effects.

[0068] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An adaptive overshoot prevention control method for a pulse current source, characterized in that, Applied to a two-stage switching power supply topology, the method includes an adaptive iterative phase: The average duty cycle of the tail time window of the previous pulse cycle is extracted and used as the target feedforward value for the current pulse cycle; wherein, the tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized. During the current pulse cycle, before the freeze delay time of the integrator is reached, only the target feedforward value is injected into the PWM generator of the subsequent converter; and after the freeze delay time is reached, the integrator starts to work, and the target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter.

2. The pulse current source adaptive overshoot control method according to claim 1, characterized in that, The provision that, within the current pulse period, before the integrator's freeze delay time arrives, only the target feedforward value is used as the input to the PWM generator of the subsequent converter specifically includes: Within the current pulse cycle, before the freeze delay time of the integrator is reached, the target feedforward value is divided into multiple stepped proportional segments for equal-time injection within the rising edge time of the pulse current.

3. The pulse current source adaptive overshoot control method according to claim 1 or 2, characterized in that, The freeze delay time of the integrator is dynamically segmented according to the target pulse current amplitude; wherein, the freeze delay time of the integrator is positively correlated with the target pulse current amplitude.

4. The pulse current source adaptive overshoot control method according to claim 1, characterized in that, The adaptive iteration phase also includes: During the first pulse cycle, the target feedforward value is forcibly set to 0, and the initial test current is established only after the integrator starts to work.

5. The pulse current source adaptive overshoot control method according to claim 1, characterized in that, The adaptive iteration phase also includes: If the error of the average tail current of M consecutive pulse cycles meets the standard, then the target feedforward value is locked and the adaptive iteration phase ends.

6. The pulse current source adaptive overshoot control method according to claim 5, characterized in that, Following the adaptive iteration phase, the following is also included: During multiple pulse cycles, before the freeze delay time of the integrator is reached, the locked target feedforward value is injected into the PWM generator of the subsequent converter only; and after the freeze delay time is reached, the integrator starts to work, and the locked target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter.

7. The pulse current source adaptive overshoot control method according to claim 1, characterized in that, Before the first pulse current output of the downstream converter, the upstream converter is woken up by a preset time. The upstream converter starts up directly at a preset switching frequency and operates in closed loop to replenish energy to the input capacitor.

8. The pulse current source adaptive overshoot control method according to claim 7, characterized in that, The preceding converter is an isolated DC-DC converter; And / or, the subsequent converter is a multiphase interleaved buck converter; The input capacitor is located between the pre-stage converter and the post-stage converter. The pre-stage converter replenishes energy to the input capacitor and provides an intermediate bus voltage.

9. The pulse current source adaptive overshoot control method according to claim 1, characterized in that, After the pulse current output of the subsequent converter ends, the ripple output of the preceding converter is blocked, causing the preceding converter to enter standby hiccup mode.

10. A pulse current source adaptive overshoot prevention control system, characterized in that, The system, applied to a two-stage switching power supply topology, includes: The tail time window sampling module is used to extract the average duty cycle of the tail time window of the previous pulse cycle and use it as the target feedforward value for the current pulse cycle; wherein, the tail time window is a set time window after the actual output current of the previous pulse cycle has stabilized. An integrator is used to inject the target feedforward value into the PWM generator of the subsequent converter only during the current pulse period, before the freeze delay time of the integrator arrives; and after the freeze delay time arrives, the integrator starts to work, and the target feedforward value and the output of the integrator are superimposed and injected into the PWM generator of the subsequent converter. The delay configuration module is used to generate the freeze delay time.

11. The pulse current source adaptive overshoot control system according to claim 10, characterized in that, Also includes: A stepped feedforward generator is used to divide the target feedforward value into multiple stepped proportional segments for equal-time injection within the rising edge time of the pulse current, before the freeze delay time of the integrator is reached during the current pulse cycle.

12. The pulse current source adaptive overshoot prevention control system according to claim 10, characterized in that, Also includes: The pre-stage converter collaborative control module is used to wake up the pre-stage converter in advance at a preset time before the first pulse current output of the subsequent stage converter. The pre-stage converter directly switches in and starts up at a preset switching frequency and operates in a closed loop to replenish energy to the input capacitor. After the pulse current output of the subsequent stage converter ends, the pre-stage converter's waveform is blocked, so that the pre-stage converter enters a standby hiccup mode.

13. A test power supply device, characterized in that, It includes a two-stage switching power supply topology and a controller, the controller being used to execute the pulse current source adaptive overshoot control method as described in any one of claims 1-9.

14. A testing system, characterized in that, Applications to the testing of semiconductor devices include the test power supply equipment and measuring instruments as described in claim 13.

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