A soft start control method for a single-stage interleaved DAB AC-DC converter

Abstract

This invention relates to the field of power electronics technology, specifically to a soft-start control method for a single-stage interleaved DAB AC-DC converter, comprising: S1: calculating the real-time voltage gain and selecting a three-level modulation strategy and the optimal operating mode; S2: constructing an optimization problem with the goal of maximizing instantaneous power transmission and a peak current constraint of a safe threshold for the phase-shifting inductor current; S3: solving the optimization problem using the Lagrangian function and KKT conditions to obtain the optimal combination of modulation variables; S4: inputting the optimal combination of modulation variables and a preset start-up frequency into a PWM generation unit to generate drive signals for each switch of the converter; S5: when the preset cut-off and stability conditions are not met, returning to step S1 and continuing to execute the soft-start control strategy; otherwise, switching from the soft-start control strategy to the steady-state control strategy. This invention can effectively suppress the dual stress of phase-shifting inductor current and grid-side current over a very wide voltage gain range during startup.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a soft-start control method for a single-stage interleaved DAB AC-DC converter. Background Technology

[0002] Single-stage interleaved DAB AC-DC converters, with their advantages of high power density, bidirectional power flow, and high integration, have broad application prospects in fields such as on-board charging, DC microgrids, and energy storage systems. As the primary stage for system commissioning, the performance during startup directly determines commissioning efficiency, system reliability, and user experience. However, compared to the maturity of steady-state control strategies, research on soft-start strategies for single-stage DAB AC-DC converters is still in the exploratory stage and faces many challenges that urgently need to be addressed.

[0003] Currently, there are few startup strategies specifically for single-stage DAB AC-DC converters; however, startup strategies for DAB DC-DC converters can be referenced. Early startup strategies for DAB AC-DC converters mostly employed open-loop logic, gradually increasing the phase shift angle through a "two-step" or multi-step method to limit input power. While these methods are simple to implement, they are highly dependent on parameters such as the phase shift slope, involve cumbersome parameter tuning, and result in a lengthy startup process because they cannot fully utilize the maximum allowable current stress of the system. Subsequent research shifted to full-process closed-loop soft-start methods, such as Model Predictive Control (MPC) or dynamic boundary control based on SPS modulation. However, MPC strategies are highly sensitive to parameter changes and have a heavy computational load, while SPS-based strategies have limited current limiting capabilities under extremely low voltage gain conditions. Although subsequent research has proposed maximum current stress startup strategies based on extended phase-shift (EPS) modulation, aiming to accelerate startup by maximizing power within a safe threshold, and even introducing frequency conversion control to improve the power-current stress ratio (PPS), these methods mainly focus on DC-DC scenarios with a fixed voltage gain range.

[0004] When applying the above startup strategy to a single-stage interleaved DAB AC-DC converter, the following significant technical challenges still need to be addressed:

[0005] 1) Increased stress coupling complexity: The current stresses experienced by various switching devices in a single-stage structure are different, mainly affected by the combined influence of two types of currents: phase-shifting inductor current and grid-connected current. At the same time, the difficulty of real-time constraint of the two types of current stresses increases significantly.

[0006] 2) Extremely wide operating range: During the startup process of AC-DC converter, both the input and output voltages fluctuate within a large range, and the voltage gain spans the extreme range from zero to infinity, which can easily induce catastrophic inrush currents.

[0007] 3) Strategy switching impact: The startup phase focuses on current stress and startup speed, while the steady-state phase focuses on grid-connected current quality and efficiency. Due to the different objective functions, it is necessary to switch from startup to steady state in a timely manner after the startup target is met in order to avoid continuous impact on the power grid. Furthermore, the switching process is required to be smooth and seamless to avoid current surges.

[0008] The applicant discovered that the prior art lacks a soft-start control strategy for single-stage interleaved DAB AC-DC converters that can constrain multiple current stresses over an extremely wide voltage gain range, significantly improve startup speed, and support a smooth and seamless transition from startup to steady-state control strategies. Summary of the Invention

[0009] To address the shortcomings of the prior art, the technical problem to be solved by this invention is: how to provide a soft-start control method for a single-stage interleaved DAB AC-DC converter, which can effectively suppress the dual stress of phase-shifting inductor current and grid-side current within an extremely wide voltage gain range during startup, while accelerating startup speed by optimizing instantaneous power transmission capability, and ensuring a smooth and seamless transition from startup to steady state after reaching the cut-off stability condition.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0011] A soft-start control method for a single-stage interleaved DAB AC-DC converter includes:

[0012] S1: Calculate the real-time voltage gain based on the instantaneous voltage values ​​of the converter grid side and DC side, and select the three-level modulation strategy and optimal operating mode of the converter according to the real-time voltage gain and the preset phase-shifting inductor current safety threshold.

[0013] S2: Based on the discrete time-domain model corresponding to the optimal operating mode, construct an optimization problem with the goal of maximizing instantaneous transmission power and the peak current constraint of the phase-shifting inductor current safety threshold.

[0014] S3: Solve the optimization problem using the Lagrangian function and KKT conditions to obtain the optimal combination of modulation variables, which includes the optimal external phase shift angle of the converter, the optimal internal phase shift angle of the grid side, and the optimal internal phase shift angle of the DC side.

[0015] S4: Input the optimal combination of modulation variables and the preset start-up frequency into the PWM generation unit to generate drive signals for each switch of the converter and control the working state of the converter.

[0016] S5: Determine whether the preset cut-off stability condition is met by comparing the converter's output voltage error with the grid-side voltage zero-crossing point. If the preset cut-off stability condition is met, return to step S1 and continue executing the soft-start control strategy; otherwise, switch from the soft-start control strategy to the steady-state control strategy.

[0017] Preferably, in step S1, the formula for calculating the voltage gain M is:

[0018] M = nV s / v p ;

[0019] In the formula: n is the transformer turns ratio of the main circuit of the converter, v p V is the instantaneous sampled value of the AC side voltage of the converter. s This is the instantaneous sampled value of the DC-side voltage of the converter.

[0020] Preferably, in step S1, selecting the three-level modulation strategy of the converter includes:

[0021] When the voltage gain M is greater than 1, the DC-side full-bridge uses three-level modulation, and the DC-side full-bridge midpoint voltage v cd It is a three-level waveform, and the grid-side full bridge uses two-level modulation. The DC-side full bridge midpoint voltage v ab It is a square wave;

[0022] When the voltage gain M is less than or equal to 1, the grid-side full-bridge uses three-level modulation, and the DC-side full-bridge midpoint voltage v ab It is a three-level waveform, and the DC-side full-bridge uses two-level modulation. The DC-side full-bridge midpoint voltage v cd It is a square wave.

[0023] Preferably, in step S1, the operating modes of the converter include:

[0024] (1) Pattern A

[0025] DC-side full-bridge midpoint voltage v ab The voltage at the midpoint of the DC-side full-bridge is a square wave. cd It is a three-level waveform, and the high-level range of the three-level waveform is completely contained within the high-level range of the two-level waveform. The phase shift angle constraints are D1 = 0.5, D0 ≥ 0, D2 ≥ 0, D0 + 0.5D2 ≥ 0.25, D0 + D2 ≤ 0.5, which is applicable to the voltage gain M > 1 condition.

[0026] The formula is expressed as:

[0027] ;

[0028] (2) Pattern B

[0029] DC-side full-bridge midpoint voltage v ab The voltage at the midpoint of the DC-side full-bridge is a square wave. cdIt is a three-level waveform, and the high-level range of the three-level waveform extends beyond the high-level range of the two-level waveform. The phase shift angle is constrained as follows: D1 = 0.5, D0 ≥ 0, D2 ≥ 0, D0 + 0.5D2 ≥ 0.25, D0 + D2 > 0.5. It is applicable to the condition where the voltage gain M > 1.

[0030] The formula is expressed as:

[0031] ;

[0032] (3) Pattern C

[0033] DC-side full-bridge midpoint voltage v ab It is a three-level wave, and the DC-side full-bridge midpoint voltage V cd It is a square wave, and the high-level range of the three-level waveform is completely contained within the high-level range of the two-level waveform. The phase shift angle is constrained as follows: D2 = 0.5, D0 ≤ 0, D1 ≥ 0, D0 + 0.25 ≥ 0.5D1, D1 ≤ 0.5 + D0. It is suitable for voltage gain M ≤ 1.

[0034] The formula is expressed as:

[0035] ;

[0036] (4) Pattern D

[0037] DC-side full-bridge midpoint voltage v ab It is a three-level waveform, and the DC-side full-bridge midpoint voltage V cd It is a square wave, and the high-level range of the three-level waveform extends beyond the high-level range of the two-level waveform. The phase shift angle is constrained as follows: D2 = 0.5, D0 ≥ 0, D1 ≥ 0, D0 + 0.25 ≥ 0.5D1, D1 > D0. It is applicable to the voltage gain M ≤ 1 condition.

[0038] The formula is expressed as:

[0039] ;

[0040] In the formula: D0 is the outward phase shift angle between the converter grid-side full bridge and the DC-side full bridge, D1 is the inward phase shift angle of the converter grid-side full bridge, and D2 is the inward phase shift angle of the converter DC-side full bridge.

[0041] Preferably, in step S1, the logic for selecting the optimal working mode is as follows:

[0042] Under the condition that voltage gain M > 1, when the preset safe threshold I of phase-shifting inductor current... lim-Ls Greater than the peak current boundary between Mode A and Mode B, i * bd1Use mode B if necessary, otherwise use mode A.

[0043] Under the condition that voltage gain M ≤ 1, when the preset safe threshold I of phase-shifting inductor current... lim-Ls The peak current boundary between mode C and mode D is greater than i. * bd2 Use mode D if the condition is met, otherwise use mode C.

[0044] Preferably, in step S2, the discrete-time model corresponding to the working mode includes:

[0045] (1) Pattern A

[0046] ;

[0047] ;

[0048] (2) Pattern B

[0049] ;

[0050] ;

[0051] (3) Pattern C

[0052] ;

[0053] ;

[0054] (4) Pattern D

[0055] ;

[0056] ;

[0057] In the formula: i * DAB i represents the average power transfer current of the DAB unit of the converter during one switching cycle. * p This represents the peak value of the phase-shifting inductor current in the DAB unit of the converter during one switching cycle.

[0058] Preferably, in step S2, the optimization problem is to make the average transmission power current i * DAB Maximum, with the peak value of the phase-shifting inductor current i * p At the preset safety threshold I * lim-Ls The internal constraints ensure that the converter operates in the corresponding operating mode.

[0059] The formula for the optimization problem is expressed as:

[0060] ;

[0061] In the formula: , , The conditions for phase-shift angle boundary constraints are expressed.

[0062] Preferably, in step S3, the optimal combination of modulation variables obtained by solving the optimization problem using the Lagrangian function and KKT conditions includes:

[0063] (1) Pattern A

[0064] D1 = 0.5;

[0065] ;

[0066] (2) Pattern B

[0067] D1 = 0.5;

[0068] ;

[0069] (3) Pattern C

[0070] D2 = 0.5;

[0071] ;

[0072] (4) Pattern D

[0073] D2 = 0.5;

[0074] .

[0075] Preferably, in step S4, the preset startup frequency Satisfy the following formula:

[0076] ;

[0077] I lim-g =2I lim-Ls ;

[0078] In the formula: V s L is the input voltage of the converter. s I is the phase-shifting inductance of the converter, n is the transformer turns ratio of the main converter circuit, and I is the phase-shifting inductance of the converter. lim-g I is the safe threshold for grid-side current. lim-Ls This is the safe threshold for the phase-shifting inductor current.

[0079] Preferably, in step S5, the preset stabilization conditions include:

[0080] (1) Determine the output voltage error: Monitor whether the DC-side output voltage error of the converter enters the steady-state tolerance range;

[0081] (2) Input voltage zero-crossing detection: After the converter output voltage reaches the standard, the input voltage is further detected to see if it is at the zero-crossing point;

[0082] The switch from soft-start control strategy to steady-state control strategy is executed only when both conditions are met simultaneously, so as to ensure that the instantaneous transmission power of both soft-start control strategy and steady-state control strategy tends to zero at the time of switching, thus suppressing current or voltage surges.

[0083] Compared with existing technologies, the soft-start control method for a single-stage interleaved DAB AC-DC converter in this invention has the following advantages:

[0084] This invention proposes a dynamic switching mechanism for a three-level modulation port based on multi-mode extended phase-shift (EPS) modulation. It fully utilizes the limiting capability of peak current stress of the phase-shift inductor and effectively solves the problem that current surges are easily triggered in the early and late stages of startup of this type of converter due to the voltage gain approaching zero and infinity, respectively, thereby improving the operational safety of magnetic components and switching devices.

[0085] This invention actively increases the peak current of the phase-shifting inductor to a preset safety threshold (or the maximum peak value achievable under current operating conditions within the safety threshold), and aims to maximize instantaneous power transmission, thereby fully tapping the energy transmission potential of the system and effectively improving the system's startup speed while ensuring that the peak current of the phase-shifting inductor does not exceed the safety threshold.

[0086] This invention indirectly limits the grid-side peak current by setting a preset start-up frequency, cleverly solving the problem of controlling multiple stress couplings in various converters. It ensures that the grid-side current does not exceed the safety threshold and simplifies the logic complexity of the control system.

[0087] This invention proposes a switching strategy based on dual judgment of voltage error and voltage zero crossing point, which can significantly suppress transient overshoot during startup and steady-state switching, protect each device from surge current impact, and reduce harmonic pollution to the grid side, thereby ensuring the stability and reliability of the entire converter system during commissioning.

[0088] The proposed solution is logically rigorous and highly feasible in engineering, providing a key soft-start technology guarantee for the industrial application of high-power single-stage AC-DC converters. Attached Figure Description

[0089] To make the objectives, technical solutions, and advantages of the invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein:

[0090] Figure 1This diagram illustrates the topology of a single-stage interleaved DAB AC-DC converter and its soft-start strategy.

[0091] Figure 2 To modulate the drive signals of each high-frequency switching transistor S1-S3 and Q1-Q4 under various operating modes of the multi-mode EPS, as well as the AC and DC side full-bridge midpoint voltage V... ab and v cd The waveform.

[0092] Figure 3 A mapping diagram showing the relationship between the average transmission power current iDAB and the peak current withstand capacity ip of the phase-shifting inductor under various operating modes of multi-mode EPS modulation.

[0093] Figure 4 Optimization solutions for various operating modes of multi-mode EPS modulation under maximum power constraints with limited peak current. Figure 3 Distribution trajectory in: Figure 4 (a) Figure 4 (b) Figure 4 (c) Figure 4 (d) are the distribution trajectories of patterns A, B, C and D, respectively.

[0094] Figure 5 The average transmission power current i in each mode * DAB Regarding the peak current i * p Distribution characteristics: Figure 5 (a) Figure 5 (b) Distribution characteristics for M=2 and M=1 / 2, respectively.

[0095] Figure 6 To optimize the power transfer trajectory under different current peak constraints: Figure 6 (a) Figure 6 (b) Power transfer trajectories for M=2 and M=1 / 2, respectively.

[0096] Figure 7 This is a diagram showing the overall control structure from system soft start to steady-state operation.

[0097] Figure 8 This is a flowchart illustrating the implementation of the soft-start strategy in the overall system control structure diagram.

[0098] Figure 9 This describes the process for determining the start-up and steady-state strategy cut-off conditions in the overall system control structure diagram.

[0099] Figure 10 For single-stage interleaved DAB AC-DC converters at different reference voltages V sref The following are the waveforms from the soft-start experiment: Figure 10(a) Figure 10 (b) Figure 10 (c) V sref = 350V, V sref = 400V, V sref = 450V soft start test waveform.

[0100] Figure 11 For single-stage interleaved DAB AC-DC converters under different loads R L The following are the waveforms from the soft-start experiment: Figure 11 (a) Figure 11 (b) Figure 11 (c) are R respectively L = 267Ω, R L = 400Ω, R L = 800Ω soft-start experimental waveform.

[0101] Figure 12 For single-stage interleaved DAB AC-DC converters with different output capacitors C o The following are the waveforms from the soft-start experiment: Figure 12 (a) Figure 12 (b) Figure 12 (c) are C respectively o = 1580μF, C o = 1780μF, C o = 1980μF soft-start experimental waveform. Detailed Implementation

[0102] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but only to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0103] The following detailed explanation illustrates the specific implementation methods:

[0104] Example:

[0105] This embodiment discloses a soft-start control method for a single-stage interleaved DAB AC-DC converter.

[0106] like Figure 1 As shown, a soft-start control method (strategy) for a single-stage interleaved DAB AC-DC converter includes:

[0107] S1: Calculate the real-time voltage gain based on the instantaneous voltage values ​​of the converter grid side and DC side, and select the three-level modulation strategy and optimal operating mode of the converter according to the real-time voltage gain and the preset phase-shifting inductor current safety threshold.

[0108] S2: Based on the discrete time-domain model corresponding to the optimal operating mode, construct an optimization problem with the goal of maximizing instantaneous transmission power and the peak current constraint of the phase-shifting inductor current safety threshold.

[0109] S3: Solve the optimization problem using the Lagrangian function and KKT conditions to obtain the optimal combination of modulation variables, which includes the optimal external phase shift angle of the converter, the optimal internal phase shift angle of the grid side, and the optimal internal phase shift angle of the DC side.

[0110] S4: Input the optimal combination of modulation variables and the preset start-up frequency into the PWM generation unit to generate drive signals for each switch of the converter and control the working state of the converter.

[0111] S5: Determine whether the preset cut-off stability condition is met by comparing the converter's output voltage error with the grid-side voltage zero-crossing point. If the preset cut-off stability condition is met, return to step S1 and continue executing the soft-start control strategy; otherwise, switch from the soft-start control strategy to the steady-state control strategy.

[0112] like Figure 1 As shown, the soft-start control strategy of the present invention is applicable to single-stage interleaved DAB AC-DC converter topologies. The core of the startup strategy includes the soft-start regulation process and the strategy switching process. The theoretical support involved covers: system modeling and stress deconstruction of the startup process, time-domain model configuration based on multi-mode EPS modulation, optimization solution of peak current transmission to maximum power, and indirect constraint on grid-side current stress through frequency.

[0113] The core of the soft-start strategy for a single-stage interleaved DAB AC-DC converter is: based on a discrete-time model of multi-mode extended phase-shift (EPS) modulation, the maximum instantaneous power optimization solution under the current peak constraint is obtained by solving the Lagrangian function and KKT conditions, thereby achieving the limitation of peak current stress of the phase-shift inductor and rapid establishment of output voltage. At the same time, the peak current stress on the grid side is limited by a preset start-up frequency, and finally, a smooth transition to the steady-state strategy is achieved through dual triggering criteria.

[0114] The strategy proposed in this invention first analyzes the equivalent model of a single-stage interleaved DAB AC-DC converter during startup, taking into account the grid-side voltage fluctuation range of 0 to 2V. gmThe DC side voltage fluctuation range is 0 to V. s The system faces significant risks of phase-shifting inductor current surges during the initial startup phase (when voltage gain approaches zero) and near the zero-crossing point of the grid-side voltage (when voltage gain approaches infinity). To mitigate these risks, this invention employs a multi-mode EPS modulation strategy, dynamically configuring the three-level waveform positions based on the instantaneous voltage relationship between the grid and DC sides: when voltage gain M ≤ 1, the grid-side full-bridge uses three-level modulation, and the DC-side full-bridge uses two-level modulation; when M > 1, the DC-side full-bridge uses three-level modulation, and the DC-side full-bridge uses two-level modulation. This dynamic configuration mechanism of the multi-mode EPS modulation operating mode ensures that the converter provides optimal phase-shifting inductor current stress suppression capability over an extremely wide voltage gain range.

[0115] Based on the mode division, discrete-time models for various modes can be derived. According to the voltage distribution characteristics across the phase-shifting inductor, the inductor current within one switching cycle is linearly divided into pieces, thereby deriving the average transmitted power current i of the DAB unit within one modulation cycle. DAB and the peak current i of the phase-shifting inductor p Regarding the analytical relationship of modulation variables, the mapping relationship between the average transmitted power current and the peak current of the phase-shifting inductor under various modes can be fully characterized.

[0116] Based on the above mapping relationship, to balance startup speed and safety, this invention proposes an optimization method for limiting peak current to maximize power transmission, thereby simultaneously achieving peak current stress limitation of the phase-shifting inductor and improved startup speed. This method can be modeled as a constrained optimization problem: given a known current safety threshold, firstly, select the operating mode capable of transmitting the maximum instantaneous power; then, strictly constrain the peak current of the phase-shifting inductor to the safety threshold point (or the maximum peak value the system can achieve within the safety threshold); and optimize the modulation variables with the goal of maximizing the instantaneous power transmission of the system, thereby simultaneously ensuring the safety of the phase-shifting inductor current stress and the fastest establishment of the DC-side voltage.

[0117] Building upon the aforementioned limitation of the peak current of the phase-shifting inductor, this invention further proposes a method for limiting the peak current of the grid side based on a preset startup frequency, thereby achieving real-time constraint of two types of current stress. First, based on the principle of instantaneous power conservation, this method ignores the ripple of the grid-side inductor current. According to the relationship that the average current of the grid-side inductor is less than the peak current of the phase-shifting inductor, it proposes to equally distribute the safe current threshold of the switching device to the grid-side inductor current and the phase-shifting inductor current, thus clearly defining the safe thresholds for both the grid-side current and the phase-shifting inductor current. Then, to avoid complex real-time grid-side current closed-loop control and to prevent logical conflicts with the method of limiting peak current to maximum power, this invention uses a preset switching frequency f. s To lock the maximum instantaneous power limit nV that the system can achieve.p V s / (8L s f s This indirectly keeps the grid-side current within a preset safety threshold.

[0118] To verify the effectiveness of this strategy, the following detailed description of each part is provided in conjunction with specific parameters. The main circuit parameters of the converter in this embodiment are shown in Table 1.

[0119] Table 1. Main circuit parameters of the single-stage interleaved DAB AC-DC converter in this embodiment.

[0120]

[0121] I. System Modeling, Stress Deconstruction, and Control Logic of the Startup Process

[0122] 1. System modeling of the startup process

[0123] Before implementing the soft-start strategy described in this invention, it is necessary to analyze the equivalent model of a single-stage interleaved DAB AC-DC converter during the startup process. For example... Figure 2 As shown, the converter faces challenges of an extremely wide voltage gain range and extreme current stress during the startup phase:

[0124] 1) In the initial stage of startup, since the DC side voltage approaches zero and the equivalent voltage gain M approaches zero, the phase-shifting inductor is subjected to a very large volt-second integral, which can easily generate a severe current surge.

[0125] 2) At the end of startup, if the grid-side voltage is close to zero while the DC-side voltage has been established, the voltage gain M tends to infinity, which also presents an extremely high inductor current peak challenge.

[0126] 2. Stress analysis of power switching transistors

[0127] Because single-stage interleaved DAB AC-DC converters employ the principle of switching device function multiplexing, the current stress experienced by each power switch varies significantly, necessitating classified suppression. Based on different current stresses, the switches can be divided into three categories:

[0128] 1) Power frequency tube stress i Jx It depends only on the absolute level of the grid-side current;

[0129] 2) DC-side high-frequency tube stress i Sz It is only directly affected by the phase-shifting inductor current;

[0130] 3) High-frequency tube stress on the mesh side Qy It withstands the dual stress of grid-side inductor current (or grid-side current) and phase-shifting inductor current.

[0131] Therefore, in this embodiment, ignoring the grid-connected inductor current ripple, i Qy The dual-coupling stress is deconstructed into two components: independently limited grid-side current and phase-shifting inductor current. Under the premise of absolute safety, the safety thresholds of both are reasonably allocated and their peak values ​​are limited.

[0132] 3. Control logic of the startup process

[0133] This embodiment, ignoring grid-connected inductor current ripple, proposes a control strategy that balances current stress limitations and rapid start-up by theoretically deconstructing the control requirements. The overall logic is as follows:

[0134] 1) Simplified safety constraints: By taking into account the relationship between the grid-side current and the phase-shifting inductor current, and reasonably allocating the safety thresholds of the two, the complex system stress control is simplified to: real-time limitation of the peak current of the phase-shifting inductor and upper limit constraint of the instantaneous transmission power (i.e., grid-side current).

[0135] 2) Fast optimization solution: Under the premise of satisfying the two types of current safety constraints, in order to shorten the DC side voltage settling time, the system seeks to maximize the instantaneous transmission power by dynamically adjusting the modulation variables.

[0136] II. Time-Domain Model Configuration Based on Multi-Mode EPS Modulation

[0137] To effectively suppress the peak current stress of the phase-shifting inductor under extreme voltage gain conditions, this embodiment proposes a mechanism based on multi-mode EPS modulation where three-level modulation changes synchronously with the high-voltage port. Figure 3 Its typical operating waveforms are shown, based on the grid-side voltage v. p With DC side voltage V s Real-time dynamic configuration of three-level waveform positions:

[0138] 1) When the grid-side voltage is high (M ≤ 1), the grid-side full-bridge uses three-level modulation, and the DC-side full-bridge uses two-level modulation. At this time, v ab It is a three-level waveform, v cd It is a two-level waveform;

[0139] 2) When the DC-side voltage is high (M > 1), the DC-side full-bridge uses three-level modulation, and the grid-side full-bridge uses two-level modulation. At this time, v ab It is a two-level waveform, v cd It is a three-level waveform.

[0140] 2. Classification of Multimode EPS Modulation Modes

[0141] Define the external phase shift angle between switches S1 and Q1 as D0, the grid-side internal phase shift angle between S1 and S2 as D1, and the DC-side internal phase shift angle between Q1 and Q3 as D2. Based on voltage waveform characteristics, multi-mode EPS modulation is divided into four typical modes, such as... Figure 4 As shown in Table 2, operating conditions are configured based on the current suppression characteristics of various modes: Under high voltage gain (M > 1), modes A and B are used, with control achieved by fixing D1=0.5 and adjusting D0 and D2. Mode A is also called the internal mode, where the high-level range of the three-level wave is completely contained within the high-level range of the two-level wave; mode B is called the external mode, where the high-level range of the three-level wave extends beyond the high-level range of the two-level wave. Under low voltage gain (M ≤ 1), modes C and D are used, with optimized control achieved by fixing D2=0.5 and adjusting D0 and D1. Modes C and D are the internal and external modes, respectively. The phase shift angle constraints for each mode are shown in Table 2.

[0142] Table 2. Phase shift angle constraints for various modes of multimodal EPS modulation

[0143]

[0144] 2. Discrete-time model of multi-mode EPS modulation

[0145] Taking mode A as an example, this embodiment utilizes the piecewise linear variation characteristic and half-wave odd symmetry characteristic of the phase-shifting inductor current within one switching cycle to establish a discrete-time analytical model for multi-mode EPS modulation. The voltage gain M and the current reference value i are defined. b for:

[0146] (1)

[0147] Through mathematical derivation, the benchmark value i of the average transmitted power current of the DAB unit within one modulation cycle can be obtained. * DAB for:

[0148] (2)

[0149] Based on the current distribution characteristics of Mode A, the positive peak value can only occur at times t1, t3, or t5. To compare the magnitudes of these three values, we can first analyze the relationship between the following time intervals:

[0150] (3)

[0151] In mode A, power is always transmitted in the forward direction, subject to a phase shift constraint: D0 + 0.5D2 > 0.25. Under this condition, Δt1 > Δt2. Since the absolute values ​​of the current change slopes are equal within Δt1 and Δt2, we can obtain i... Ls(t1) > i Ls (t5). Therefore, the benchmark value for the positive peak value of the inductor current in mode A may be:

[0152] (4)

[0153] Similarly, the expressions for the average transmission power current and peak current of modes B, C and D can be derived, and the results are summarized in Table 3.

[0154] Table 3 Discrete-time models of each mode of multimodal EPS modulation

[0155]

[0156] 3. Mode configuration for multi-mode EPS modulation

[0157] Based on the analytical expressions in Table 3, the average transmission power current i under each mode can be obtained. * DAB Regarding the peak current i * p The distribution characteristics, such as Figure 5 As shown. Among them, Figure 5 (a) represents the case where M > 1 (taking M = 2 as an example), and the blue and green areas represent the feasible regions of modes A and B, respectively; Figure 5 (b) represents the case where M ≤ 1 (taking M = 1 / 2 as an example), and the blue and green areas represent the feasible regions of modes C and D, respectively.

[0158] Depend on Figure 5 As can be seen from the distribution characteristics, the peak value of the phase-shifting inductor current directly determines the physical upper limit of the system's power transmission capability: the larger the peak current, the higher the upper limit of the achievable power transmission capability. Therefore, this characteristic should be fully utilized during the fast start-up phase by actively increasing the peak value of the inductor current within the safety threshold to obtain a greater instantaneous power transmission capability, thereby effectively shortening the start-up time.

[0159] Based on the specific current peak safety threshold and different voltage gain conditions, the selection strategy for each mode is as follows: Under the condition of M > 1, mode B is preferred for larger current peak safety thresholds, and mode A is only used when the safety threshold is smaller; under the condition of M ≤ 1, mode D is preferred when the current peak safety threshold is larger, and mode C is only used when the safety threshold is smaller, so as to make full use of the characteristic of transmitting maximum power at maximum current peak.

[0160] III. Optimization of peak current transfer to maximum power

[0161] To balance startup speed and safety, this embodiment fully utilizes the characteristic that higher peak current leads to stronger power transmission capability, and proposes an optimization method to limit peak current and transmit maximum power: actively increasing the peak current i of the phase-shifting inductor within a safe threshold. * p Strictly control it within the preset safety threshold I * lim-Ls (If the real-time operating condition cannot reach this threshold condition, it should be strictly controlled to the maximum achievable peak point), and under this constraint, the maximum instantaneous power (i.e., let i) be optimized. DAB * (Maximum), to speed up startup. Taking mode A as an example, its mathematical optimization model is as follows:

[0162] (5)

[0163] The optimization problem is solved using the Lagrangian function combined with the KKT conditions. For mode A, when D²M + D₀ - 0.5 > 0, the peak current i is substituted... p * = 0.5D2M + D0 - 0.25, the optimized solution is:

[0164] (6)

[0165] When D2M + D0 - 0.5 ≤ 0, substitute the peak current i p * = 0.25 - 0.5D²M, the optimized solution is:

[0166] (7)

[0167] Following the same steps, the optimized solutions for the other modes can be obtained, and the results are summarized in Table 4:

[0168] Table 4 Optimization solutions for each mode of multimodal EPS modulation

[0169]

[0170] Combining Tables 2 and 4, by substituting the optimized solutions for modes A and B (or modes C and D) under the condition of M > 1 (or M ≤ 1) into the critical constraint condition of the phase shift angle, the current peak boundary between the internal and external modes under the corresponding operating conditions can be determined as follows:

[0171] (8)

[0172] According to Table 4, the power transfer trajectory of the optimization solution under different current peak constraints can be characterized, such as... Figure 6As shown in the figure, the red curve represents the trajectory of the optimized solution under both M > 1 and M ≤ 1 conditions. In each mode, this trajectory always lies within the upper envelope of the feasible region of transmitted power and peak current. This proves the effectiveness of the optimized solution: under any given peak current constraint, this strategy can drive the system to achieve the maximum instantaneous power output, thereby accelerating the startup speed.

[0173] IV. Indirect Constraints and Frequency Setting of Grid-Side Current Stress

[0174] The current stress experienced by each switching device during the startup process of a single-stage interleaved DAB AC-DC converter is complex. To simplify the protection logic under multiple stresses, the overall system stress control can be decoupled to i Ls with i g Independent hierarchical constraints on peak values ​​require further restrictions on grid-side peak current in addition to limiting the peak current of the phase-shifting inductor.

[0175] For the known safe current threshold of grid-side high-frequency switching devices, it is first necessary to clarify the reasonable distribution mechanism of this threshold between the two types of current stress. Given the symmetrical characteristics of the two-phase interleaved inductor current under EPS modulation, and ignoring the ripple during the modulation period, it can be assumed that:

[0176] (9)

[0177] During EPS modulation startup, the relationship of the grid-side voltage multiplier Boost circuit still holds, which can be derived from the principle of instantaneous power conservation:

[0178] (10)

[0179] Therefore i DAB with i Lg Their sizes are roughly the same. Under EPS modulation, i DAB For i Ls The average value over half a switching cycle is always less than or equal to i. Ls peak i p , so i Lg ≤i p This always holds true. Therefore, i can be... Lg The threshold is set to be the same as i. p The same principle applies, ensuring the absolute safety of each component. Therefore, the safety threshold I for the phase-shifting inductor current can be obtained. lim-Ls With grid-side current safety threshold I lim-g The following relationship should be satisfied:

[0180] (11)

[0181] Based on this allocation mechanism, and assuming the known current safety threshold of the switching devices, this threshold can be reasonably allocated to the current stress constraints of the phase-shifting inductor and the grid-side inductor. Since the selected devices are required to have a maximum current stress not exceeding 20A during operation, I is set accordingly. lim-Ls =10A, I lim-g =20A.

[0182] Furthermore, directly applying real-time limiting to the grid-side current presents a logical conflict: if the "limit peak current to maximum power" strategy is simply implemented, the system will tend to approach the maximum power transmission limit. Under instantaneous power balance, this is equivalent to actively increasing grid-side current stress, thus deviating from the original intention of overcurrent protection. Considering that the grid-side current is essentially limited by the converter's instantaneous power transmission, the physical upper limit of power transmission capability can be locked by preset switching frequency. This method eliminates cumbersome current detection and feedback calculations while ensuring that the grid-side current remains within the preset safety packet threshold during startup. The specific expression is as follows:

[0183] (12)

[0184] Among them, nV p V s / (8L s f s ) represents the maximum transmission power that the DAB unit of the converter can achieve.

[0185] Because of v p =2|v g |Constantly holds true if the safety threshold I of the grid-side current is known. lim-g Stress control of the grid-side current can be indirectly achieved by setting the start-up frequency:

[0186] (13)

[0187] To ensure safety under all operating conditions, substituting the specific parameters yields the lower limit of the starting frequency:

[0188] (14)

[0189] Furthermore, considering the time-varying characteristics of the input voltage in a single-stage structure, to simplify control and avoid transient stability imbalances caused by frequency conversion control, this embodiment chooses to keep the startup frequency consistent with the rated steady-state switching frequency, setting it to 100kHz. In other specific application scenarios, the startup frequency can be appropriately selected above the lower limit.

[0190] V. Core Process of Soft Start Strategy

[0191] The soft-start phase prioritizes maximum power transmission, compromising grid-side current quality. The resulting non-sinusoidal current pollution is acceptable during the short startup period. However, continuing this logic after the output voltage reaches the target value will cause sustained grid pollution. Therefore, the system must smoothly transition from soft-start to a steady-state strategy in a timely and efficient manner, ensuring no current or voltage surges during the switching process to guarantee system reliability and safety.

[0192] The overall control architecture of the system is as follows Figure 7 As shown, based on the real-time judgment results of the shedding stability condition, corresponding control strategies are adopted: when the shedding stability condition is not met, a soft-start control strategy is adopted; once the shedding stability condition is met, a steady-state control strategy is quickly and smoothly switched to ensure the stability of system operation.

[0193] 1. Soft start control process

[0194] Figure 8 The implementation process of the startup strategy in the overall control block diagram is shown in detail. Its control logic can be divided into three stages: (1) Initial synchronization and startup triggering: The phase-locked loop is used to accurately capture the zero-crossing point of the grid voltage and trigger the startup command near it, which aims to make the grid side and the voltage of each capacitor tend to match, thereby suppressing the overshoot current in the early stage of startup at the source. Conversely, if the startup is triggered at a non-zero-crossing point, the system prioritizes charging the clamping capacitor, and its energy is entirely provided by the grid side. The higher the grid voltage, the greater the energy required for the clamping capacitor to establish twice the grid voltage, and the greater the grid side current overshoot; (2) Dynamic optimization calculation: Once the startup is triggered, the system enters the dynamic calculation stage. Based on the real-time sampled voltage gain and the preset current safety threshold, the system seeks the accurate working mode and the optimal combination of modulation variables online; (3) State maintenance and strategy switching: After the startup logic is activated, the system switches from the trigger mode to the continuous solution mode. That is, after startup, there is no need to trigger the calculation again based on the zero-crossing logic. Instead, the optimization calculation state is maintained to ensure that the output voltage quickly tracks the reference value until the stabilization condition is reached. The system switches from soft-start control to steady-state control.

[0195] 2. Strategy Switching Process

[0196] Figure 9The judgment process of the start-up and steady-state strategy switching conditions in the overall control block diagram is shown in detail. In order to balance the switching speed and safety, this paper designs a dual triggering condition based on the output voltage error threshold and the input voltage zero-crossing detection, as follows: (1) Output voltage error threshold: When the DC side output voltage error enters the allowable steady-state tolerance range (±5% in this embodiment), the start-up task can be considered to be up to standard. This condition aims to ensure that the switching timing has sufficient advance, thereby shortening the pollution time of the non-sinusoidal current to the power grid during the soft start process; (2) Input voltage zero-crossing detection: On the basis of the output voltage being up to standard, it is also necessary to further monitor the zero-crossing point of the input voltage. If a forced switch is made when the input voltage is large, due to the large deviation between the phase shift angle under the transient and steady-state optimization solutions, it is very easy to cause a sudden change in the phase shift angle, which in turn causes a violent current surge to the system. At the time of the input voltage zero-crossing point, the transmission power of the system under the control of the start-up strategy and the steady-state strategy both tend to be zero. At this time, the phase shift angle can be considered to be close, which is the best time to achieve smooth switching.

[0197] VI. Experimental Instructions

[0198] To better illustrate the advantages of the technical solution of the present invention, the following experiment is disclosed in this embodiment.

[0199] 1. Start-up tests under different reference voltages

[0200] Figure 10 This demonstrates the effect of using the proposed soft-start strategy on output load R. L = 200Ω and output capacitor C o Under the condition of 1180μF, for different reference voltages V sref = Startup waveforms at 350V, 400V, and 450V. The results show that the system triggers a soft-start strategy after detecting the grid-side voltage crossing to zero, and actively increases the peak inductor current based on the real-time operating conditions obtained from voltage sampling. This maximizes instantaneous power transmission while fully utilizing the safety threshold, thereby accelerating the establishment of DC-side voltage.

[0201] Furthermore, when the error between the output voltage and the reference voltage enters the allowable steady-state error range and a zero-crossing is detected, the system control switches to a steady-state strategy to achieve high-performance operation. Throughout the process, there are no significant current surges or voltage drops, and the phase-shifting inductor current and grid-side current remain within safe thresholds, demonstrating excellent safety and stability.

[0202] In summary, under strict safety threshold constraints, the system current stress does not exceed the limit, startup is rapid and stable, and switching is smooth and efficient. Different reference voltages V SrefThe startup times at 350V, 400V and 450V are 180ms, 230ms and 320ms respectively. The overall startup time is short, which verifies the adaptability of the proposed strategy to different reference voltages and proves the theoretical expectation that the startup time increases with the increase of reference voltage.

[0203] 2. Start-up tests under different loads

[0204] Figure 11 This demonstrates the application of the proposed soft-boot strategy in V sref = 400V and C o Under the condition of 1180μF, for different load sizes R L = Startup waveforms at 267Ω, 400Ω, and 800Ω. The results show that the converter can fully utilize the safety threshold of the phase-shifting inductor current under various load conditions, achieving rapid startup while ensuring that neither the phase-shifting inductor current stress nor the grid-side current stress exceeds limits, and the switching process with steady state is smooth and shock-free. In R L The startup times at 267Ω, 400Ω and 800Ω are 180ms, 170ms and 150ms respectively, which verifies the adaptability of the proposed soft-start strategy to different load sizes, and also proves the theoretical expectation that the startup time increases with the increase of the output load.

[0205] 3. Start-up test under different output capacitors

[0206] Figure 12 This demonstrates the application of the proposed soft-boot strategy in R. L = 200Ω and V s = Under 400V conditions, for different output capacitors C o = Startup waveforms at 1580μF, 1780μF, and 1980μF. The results show that, under various output capacitors, i during startup... Ls and i g The current stress is strictly limited within the safe threshold range, and rapid start-up and smooth, shock-free steady-state switching are achieved. In C o The startup times at 1580μF, 1780μF, and 1980μF are 290ms, 320ms, and 360ms, respectively, which verifies the adaptability of the proposed strategy to different output capacitors and proves the theoretical expectation that the startup time increases with the increase of the output capacitor.

[0207] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A soft-start control method for a single-stage interleaved DAB AC-DC converter, characterized in that, include: S1: Calculate the real-time voltage gain based on the instantaneous voltage values ​​of the converter grid side and DC side, and select the three-level modulation strategy and optimal operating mode of the converter according to the real-time voltage gain and the preset phase-shifting inductor current safety threshold. S2: Based on the discrete time-domain model corresponding to the optimal operating mode, construct an optimization problem with the goal of maximizing instantaneous transmission power and the peak current constraint of the phase-shifting inductor current safety threshold. S3: Solve the optimization problem using the Lagrangian function and KKT conditions to obtain the optimal combination of modulation variables, which includes the optimal external phase shift angle of the converter, the optimal internal phase shift angle of the grid side, and the optimal internal phase shift angle of the DC side. S4: Input the optimal combination of modulation variables and the preset start-up frequency into the PWM generation unit to generate drive signals for each switch of the converter and control the working state of the converter. S5: Determine whether the preset cut-off stability condition is met by comparing the converter's output voltage error with the grid-side voltage zero-crossing point. If the preset cut-off stability condition is met, return to step S1 and continue executing the soft-start control strategy; otherwise, switch from the soft-start control strategy to the steady-state control strategy.

2. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 1, characterized in that: In step S1, the formula for calculating the voltage gain M is: M = nV s / in p ; In the formula: n is the transformer turns ratio of the main circuit of the converter, v p V is the instantaneous sampled value of the AC side voltage of the converter. s This is the instantaneous sampled value of the DC-side voltage of the converter.

3. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 1, characterized in that: In step S1, the three-level modulation strategy of the converter is selected as follows: When the voltage gain M is greater than 1, the DC-side full-bridge uses three-level modulation, and the DC-side full-bridge midpoint voltage v cd It is a three-level waveform, and the grid-side full bridge uses two-level modulation. The DC-side full bridge midpoint voltage v ab It is a square wave; When the voltage gain M is less than or equal to 1, the grid-side full-bridge uses three-level modulation, and the DC-side full-bridge midpoint voltage v ab It is a three-level waveform, and the DC-side full-bridge uses two-level modulation. The DC-side full-bridge midpoint voltage v cd It is a square wave.

4. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 3, characterized in that: In step S1, the converter's operating modes include: (1) Pattern A DC-side full-bridge midpoint voltage v ab The voltage at the midpoint of the DC-side full-bridge is a square wave. cd It is a three-level waveform, and the high-level range of the three-level waveform is completely contained within the high-level range of the two-level waveform. The phase shift angle constraints are D1 = 0.5, D0 ≥ 0, D2 ≥ 0, D0 + 0.5D2 ≥ 0.25, D0 + D2 ≤ 0.5, which is applicable to the voltage gain M > 1 condition. The formula is expressed as: ； (2) Pattern B DC-side full-bridge midpoint voltage v ab The voltage at the midpoint of the DC-side full-bridge is a square wave. cd It is a three-level waveform, and the high-level range of the three-level waveform extends beyond the high-level range of the two-level waveform. The phase shift angle is constrained as follows: D1 = 0.5, D0 ≥ 0, D2 ≥ 0, D0 + 0.5D2 ≥ 0.25, D0 + D2 > 0.

5. It is applicable to the condition where the voltage gain M > 1. The formula is expressed as: ； (3) Pattern C DC-side full-bridge midpoint voltage v ab It is a three-level waveform, and the DC-side full-bridge midpoint voltage V cd It is a square wave, and the high-level range of the three-level waveform is completely contained within the high-level range of the two-level waveform. The phase shift angle is constrained as follows: D2 = 0.5, D0 ≤ 0, D1 ≥ 0, D0 + 0.25 ≥ 0.5D1, D1 ≤ 0.5 + D0. It is suitable for voltage gain M ≤ 1. The formula is expressed as: ； (4) Pattern D DC-side full-bridge midpoint voltage v ab It is a three-level waveform, and the DC-side full-bridge midpoint voltage V cd It is a square wave, and the high-level range of the three-level waveform extends beyond the high-level range of the two-level waveform. The phase shift angle is constrained as follows: D2 = 0.5, D0 ≥ 0, D1 ≥ 0, D0 + 0.25 ≥ 0.5D1, D1 > D0. It is applicable to the voltage gain M ≤ 1 condition. The formula is expressed as: ； In the formula: D0 is the outward phase shift angle between the converter grid-side full bridge and the DC-side full bridge, D1 is the inward phase shift angle of the converter grid-side full bridge, and D2 is the inward phase shift angle of the converter DC-side full bridge.

5. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 4, characterized in that: In step S1, the logic for selecting the optimal working mode is as follows: Under the condition that voltage gain M > 1, when the preset safe threshold I of phase-shifting inductor current... lim-Ls Greater than the peak current boundary between Mode A and Mode B, i * bd1 Use mode B if necessary, otherwise use mode A. Under the condition that voltage gain M ≤ 1, when the preset safe threshold I of phase-shifting inductor current... lim-Ls The peak current boundary between mode C and mode D is greater than i. * bd2 Use mode D if the condition is met, otherwise use mode C.

6. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 5, characterized in that: In step S2, the discrete-time model corresponding to the working mode includes: (1) Pattern A ； ； (2) Pattern B ； ； (3) Pattern C ； ； (4) Pattern D ； ； In the formula: i * DAB i represents the average power transfer current of the DAB unit of the converter during one switching cycle. * p This represents the peak value of the phase-shifting inductor current in the DAB unit of the converter during one switching cycle.

7. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 6, characterized in that: In step S2, the optimization problem is to let the average transmission power current i * DAB Maximum, with the peak value of the phase-shifting inductor current i * p At the preset safety threshold I * lim-Ls The internal constraints ensure that the converter operates in the corresponding operating mode. The formula for the optimization problem is expressed as: ； In the formula: , , The conditions for phase-shift angle boundary constraints are expressed.

8. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 7, characterized in that: In step S3, the optimal combination of modulation variables obtained by solving the optimization problem includes: (1) Pattern A D1 = 0.5； ； ； (2) Pattern B D1 = 0.5； ； (3) Pattern C D2 = 0.5； ； (4) Pattern D D2= 0.5； 。 9. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 1, characterized in that: In step S4, the preset startup frequency Satisfy the following formula: ； AND lim-g =2I lim-Ls ; In the formula: V s L is the input voltage of the converter. s I is the phase-shifting inductance of the converter, n is the transformer turns ratio of the main converter circuit, and I is the phase-shifting inductance of the converter. lim-g I is the safe threshold for grid-side current. lim-Ls This is the safe threshold for the phase-shifting inductor current.

10. The soft-start control method for a single-stage interleaved DAB AC-DC converter as described in claim 1, characterized in that: In step S5, the preset stabilization conditions include: (1) Determine the output voltage error: Monitor whether the DC-side output voltage error of the converter enters the steady-state tolerance range; (2) Input voltage zero-crossing detection: After the converter output voltage reaches the standard, the input voltage is further detected to see if it is at the zero-crossing point; The switch from soft-start control strategy to steady-state control strategy is executed only when both shedding and steady-state conditions are met simultaneously.

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