Charge pump circuit and power supply

Abstract

The application discloses a charge pump circuit and a power supply. The charge pump circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, a second capacitor and a third capacitor. The on and off of the switches of the charge pump circuit are controlled by a control circuit, so that the charge pump circuit provides a positive voltage through a positive voltage output end and provides a negative voltage through a negative voltage output end. The application can provide the positive voltage and the negative voltage by using only one charge pump circuit, does not need two independent charge pump circuits, is relatively simple in design, reduces the area and is easy to integrate.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a charge pump circuit and power supply. Background Technology

[0002] In some applications, such as automotive electronics, car audio systems, navigation systems, and screen drivers all require both positive and negative power supplies. Therefore, charge pump circuits that can provide both positive and negative power supplies are becoming increasingly widely used.

[0003] Traditional dual-power charge pumps typically employ two independent charge pump circuits to provide positive and negative voltages respectively. The positive charge pump circuit uses a loop for active control to generate the positive voltage, while the negative charge pump circuit also uses a loop for active control to generate the negative voltage. However, this design is relatively complex and occupies a large area. Summary of the Invention

[0004] The purpose of this application is to provide a charge pump circuit and power supply to solve the technical problem that the prior art requires two independent charge pump circuits to provide positive and negative voltages respectively, which is relatively complex in design and occupies a large area.

[0005] In a first aspect, embodiments of this application provide a charge pump circuit, including: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, a second capacitor, and a third capacitor;

[0006] Both the first terminal of the first switch and the first terminal of the fifth switch are electrically connected to the power supply terminal.

[0007] The second terminal of the first switch, the first terminal of the third switch, the second terminal of the sixth switch, and the first terminal of the first capacitor are all electrically connected to the first node; the second terminal of the third switch is electrically connected to the ground terminal.

[0008] The second terminal of the fifth switch, the first terminal of the sixth switch, the first terminal of the seventh switch, and the first terminal of the second capacitor are all electrically connected to the second node. The second node is electrically connected to the positive voltage output terminal. The second terminal of the second capacitor is electrically connected to the ground terminal.

[0009] The second terminal of the first capacitor, the first terminal of the second switch, the second terminal of the fourth switch, and the second terminal of the seventh switch are all electrically connected to the third node; the second terminal of the second switch is electrically connected to the ground terminal; the first terminal of the fourth switch is electrically connected to the first terminal of the third capacitor and is also electrically connected to the negative voltage output terminal; the second terminal of the third capacitor is electrically connected to the ground terminal.

[0010] The control terminals of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are all electrically connected to the control circuit.

[0011] The control circuit is configured to control the on and off of the first, second, third, fourth, fifth, sixth, and seventh switches of the charge pump circuit, so that the charge pump circuit provides a positive voltage through the positive voltage output terminal and a negative voltage through the negative voltage output terminal.

[0012] Secondly, embodiments of this application provide a power supply, including a charge pump circuit as described in the first aspect, a positive voltage output terminal, a negative voltage output terminal, and a control circuit; the charge pump circuit is electrically connected to the positive voltage output terminal and the negative voltage output terminal respectively.

[0013] The control circuit includes:

[0014] The feedback circuit is electrically connected to the positive voltage output terminal and the negative voltage output terminal respectively. It is used to receive the positive voltage provided from the positive voltage output terminal and the negative voltage provided from the negative voltage output terminal, and output the feedback voltage.

[0015] An operational amplifier, electrically connected to a feedback circuit, is used to receive a reference voltage and a feedback voltage, and output a drive signal.

[0016] A clock circuit is used to output the first set of clock signals and the second set of clock signals.

[0017] The front-end analog drive circuit is electrically connected to the clock circuit, operational amplifier and charge pump circuit respectively. It is used to receive the drive signal and the first set of clock signals, and generate the first adjustment voltage and the second adjustment voltage according to the drive signal and the first set of clock signals and provide them to the charge pump circuit.

[0018] The pre-stage digital drive circuit is electrically connected to the clock circuit and the charge pump circuit, respectively. It is used to receive the second set of clock signals and digitally amplify the second set of clock signals before providing them to the charge pump circuit.

[0019] This application provides a novel charge pump circuit, which includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, a second capacitor, and a third capacitor. A control circuit controls the on / off state of each switch in the charge pump circuit, enabling the circuit to provide a positive voltage through a positive output terminal and a negative voltage through a negative output terminal. This application uses only one charge pump circuit to provide both positive and negative voltages, eliminating the need for two separate charge pump circuits. This simplifies the design, reduces area, and facilitates integration. Attached Figure Description

[0020] Figure 1 A schematic diagram of the circuit principle of a charge pump circuit provided in an embodiment of this application;

[0021] Figure 2A schematic diagram of a charge pump circuit operating in a first high-voltage mode in an open-loop state, provided as an embodiment of this application; wherein, Figure 2 (a) is a schematic diagram of the switching on and off of the charge pump circuit. Figure 2 (b) is a timing diagram of the clock signals of the first phase Φ1 and the second phase Φ2;

[0022] Figure 3 This application provides a schematic diagram of a charge pump circuit operating in a second high-voltage mode in an open-loop state, according to an embodiment of the present application; wherein, Figure 3 (a) is a schematic diagram of the switching on and off of the charge pump circuit. Figure 3 (b) is a timing diagram of the clock signals of the first phase Φ1 and the second phase Φ2;

[0023] Figure 4 This application provides a schematic diagram of a charge pump circuit operating in low-voltage mode in an open-loop state, according to an embodiment of the present application; wherein, Figure 4 (a) is a schematic diagram of the switching on and off of the charge pump circuit. Figure 4 (b) is a timing diagram of the clock signals for the third phase Φ1', the fourth phase Φ2' and the fifth phase Φ3';

[0024] Figure 5 for Figure 4 The diagram shows the capacitor connections of the charge pump circuit under clock signals in the third phase Φ1', fourth phase Φ2', and fifth phase Φ3'; where, Figure 5 (a) is a schematic diagram of the capacitor connection of the charge pump circuit under the clock signal of the third phase Φ1'. Figure 5 (b) is a schematic diagram of the capacitor connection of the charge pump circuit under the clock signal of the fourth phase Φ2'. Figure 5 (c) is a schematic diagram of the capacitor connection of the charge pump circuit under the clock signal of the fifth phase Φ3';

[0025] Figure 6 A schematic diagram of a power supply structure provided in an embodiment of this application;

[0026] Figure 7 A schematic diagram of the circuit principle of a feedback circuit provided in an embodiment of this application;

[0027] Figure 8 A schematic diagram of the circuit connection of the charge pump circuit provided in the embodiment of this application operating in the first high voltage mode in a closed-loop state;

[0028] Figure 9 A schematic diagram of the circuit connection of the charge pump circuit provided in the embodiment of this application operating in the second high voltage mode in a closed-loop state;

[0029] Figure 10afor Figure 8 and Figure 9 A schematic diagram of the circuit principle of the front-end analog drive circuit in the image;

[0030] Figure 10b for Figure 10a A timing diagram of the clock signals of SWN1 and SWN1B in the diagram;

[0031] Figure 11 A schematic diagram of the circuit connection of the charge pump circuit provided in the embodiment of this application operating in low-voltage mode in a closed-loop state;

[0032] Figure 12a for Figure 11 A schematic diagram of the circuit principle of the front-end analog drive circuit in the image;

[0033] Figure 12b for Figure 11 The timing diagram of the clock signals of SWP1B, SWN3, and SWN3B is shown. Detailed Implementation

[0034] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0035] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0036] An embodiment of this application provides a charge pump circuit, such as... Figure 1 As shown, the charge pump circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, a first capacitor Cflying, a second capacitor Cp, and a third capacitor Cn.

[0037] The first terminal of the first switch S1 and the first terminal of the fifth switch S5 are both electrically connected to the power supply terminal Vin.

[0038] The second terminal of the first switch S1, the first terminal of the third switch S3, the second terminal of the sixth switch S6, and the first terminal of the first capacitor Cflying are all electrically connected to the first node N1; the second terminal of the third switch S1 is electrically connected to the ground terminal.

[0039] The second terminal of the fifth switch S5, the first terminal of the sixth switch S6, the first terminal of the seventh switch S7, and the first terminal of the second capacitor Cp are all electrically connected to the second node N2. The second node N2 is electrically connected to the positive voltage output terminal Vp. The second terminal of the second capacitor Cp is electrically connected to the ground terminal.

[0040] The second terminal of the first capacitor Cflying, the first terminal of the second switch S2, the second terminal of the fourth switch S4, and the second terminal of the seventh switch S7 are all electrically connected to the third node N3; the second terminal of the second switch S2 is electrically connected to the ground terminal; the first terminal of the fourth switch S4 is electrically connected to the first terminal of the third capacitor Cn and is also electrically connected to the negative voltage output terminal Vn; the second terminal of the third capacitor Cn is electrically connected to the ground terminal.

[0041] The control terminals of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are all electrically connected to the control circuit.

[0042] The control circuit is configured to control the on and off of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6 and the seventh switch S7 of the charge pump circuit, so that the charge pump circuit provides a positive voltage through the positive voltage output terminal Vp and a negative voltage through the negative voltage output terminal Vn.

[0043] This application provides a novel charge pump circuit, which includes seven switches and three capacitors. The switching on and off of each switch of the charge pump circuit is controlled by a control circuit, so that the charge pump circuit provides a positive voltage through the positive voltage output terminal and a negative voltage through the negative voltage output terminal. This application only uses one charge pump circuit to provide positive and negative voltages, eliminating the need for two independent charge pump circuits. The design is simpler, the area is reduced, and it is easy to integrate.

[0044] In some embodiments, combined with Figure 1 , Figure 8 , Figure 9 and Figure 11 In the charge pump circuit, the first switch S1 includes a first transistor, the second switch S2 includes a second transistor, the third switch S3 includes a third transistor, the fourth switch S4 includes a fourth transistor, the fifth switch S5 includes a fifth transistor, the sixth switch S6 includes a sixth transistor, and the seventh switch S7 includes a seventh transistor. In specific implementations, each transistor can be a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOS), and no limitation is made here. Optionally, the first transistor S1 and the fifth transistor S5 are PMOS transistors; the second transistor S2, the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all NMOS transistors.

[0045] Specifically, the source of the first transistor S1 and the source of the fifth transistor S5 are both electrically connected to the power supply terminal Vin (VBAT).

[0046] The drain of the first transistor S1, the source of the third transistor S3, the drain of the sixth transistor S6, and the first terminal of the first capacitor Cflying are all electrically connected to the first node N1; the drain of the third transistor S3 is electrically connected to the ground terminal; wherein, the first capacitor Cflying is a flying capacitor.

[0047] The drain of the fifth transistor S5, the source of the sixth transistor S6, the source of the seventh transistor S7, and the first terminal of the second capacitor Cp are all electrically connected to the second node N2. The second node N2 is electrically connected to the positive voltage output terminal Vp. The second terminal of the second capacitor Cp is electrically connected to the ground terminal.

[0048] The second terminal of the first capacitor Cflying, the source of the second transistor S2, the drain of the fourth transistor S4, and the drain of the seventh transistor S7 are all electrically connected to the third node N3; the drain of the second transistor S2 is electrically connected to the ground terminal; the source of the fourth transistor S4 is electrically connected to the first terminal of the third capacitor Cn and electrically connected to the negative voltage output terminal Vn; the second terminal of the third capacitor Cn is electrically connected to the ground terminal.

[0049] The gates of the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, and the seventh transistor S7 are all electrically connected to the control circuit.

[0050] The charge pump circuit structure provided in this application uses only one Flying Capacitance and fewer transistors, while avoiding the use of expensive inductors to generate positive and negative voltages, thus reducing costs.

[0051] In some embodiments, combined with Figure 2 As shown, the control circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, causing the charge pump circuit to operate in a first high-voltage mode; wherein,

[0052] The control terminals of both the first switch S1 and the second switch S2 receive a clock signal of the first phase Φ1 from the control circuit. Figure 2 Φ1(S1,S2) in the diagram. Specifically, when both the first switch S1 and the second switch S2 receive a high-level signal, both the first switch S1 and the second switch S2 are turned on; when both the first switch S1 and the second switch S2 receive a low-level signal, both the first switch S1 and the second switch S2 are turned off.

[0053] Both the control terminals of the third switch S3 and the fourth switch S4 receive the clock signal of the second phase Φ2 from the control circuit, i.e. Figure 2 Φ2(S3,S4) in the diagram. Specifically, when both the third switch S3 and the fourth switch S4 receive a high-level signal, both switches S3 and S4 are turned on; when both switches S3 and S4 receive a low-level signal, both switches S3 and S4 are turned off.

[0054] The fifth switch S5 is on; the sixth switch S6 and the seventh switch S7 are both off.

[0055] The clock signal of the first phase Φ1 and the clock signal of the second phase Φ2 are two non-overlapping clock signals;

[0056] The charge pump circuit provides a first positive voltage through the positive voltage output terminal Vp and a first negative voltage through the negative voltage output terminal Vn.

[0057] Figure 2 (b) shows a timing diagram of two non-overlapping clock signals when the seven switches of the charge pump circuit are transistors of the same type, for example, all seven transistors can be NMOS transistors. If the first transistor S1 and the fifth transistor S5 are PMOS transistors, and the second transistor S2, the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all NMOS transistors, then because S1 and S2 are two different types of transistors, the level signals controlling the conduction of S1 and S2 are exactly opposite. Therefore, the timing of the clock signals of S1 and S2 is exactly out of phase, but the clock signals of S1 and S2 are in the same phase Φ1 (the timing diagram of their clock signals is not shown in the figure).

[0058] See Figure 2 As shown, the working principle of the charge pump circuit is as follows:

[0059] The fifth switch S5 is normally on, and the sixth switch S6 and the seventh switch S7 are normally off. Therefore, Vp = Vin.

[0060] When both the first switch S1 and the second switch S2 are on, both the third switch S3 and the fourth switch S4 are off, and the first capacitor Cflying is charging. Cflying =Vin;

[0061] When both the first switch S1 and the second switch S2 are off, both the third switch S3 and the fourth switch S4 are on. The first capacitor Cflying discharges, and charge is transferred from the first capacitor Cflying to the third capacitor Cn. The voltage difference across the first capacitor Cflying remains constant transiently, Vn = -V. Cflying＝ -Vin;

[0062] Through this alternating charging and discharging method, and with the help of the second capacitor Cp and the third capacitor Cn, the output of the charge pump circuit always remains: Vp = Vin, Vn = -Vin.

[0063] The embodiments of this application only provide two-phase non-overlapping clock signals to the first, second, third, and fourth switches of the charge pump circuit, enabling the charge pump circuit to operate in the first high-voltage mode and generate positive and negative voltages, which is simple in design.

[0064] In other embodiments, combined with Figure 3 As shown, the control circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, causing the charge pump circuit to operate in the second high-voltage mode; wherein,

[0065] The control terminals of the sixth switch S6 and the second switch S2 both receive a clock signal of the first phase Φ1 from the control circuit, i.e. Figure 3 Φ1(S6,S2) in the diagram. Specifically, when both the sixth switch S6 and the second switch S2 receive a high-level signal, both the sixth switch S6 and the second switch S2 are turned on; when both the sixth switch S6 and the second switch S2 receive a low-level signal, both the sixth switch S6 and the second switch S2 are turned off.

[0066] Both the control terminals of the third switch S3 and the fourth switch S4 receive the clock signal of the second phase Φ2 from the control circuit, i.e. Figure 3 Φ2(S3,S4) in the diagram. Specifically, when both the third switch S3 and the fourth switch S4 receive a high-level signal, both switches S3 and S4 are turned on; when both switches S3 and S4 receive a low-level signal, both switches S3 and S4 are turned off.

[0067] The fifth switch S5 is on; the first switch S1 and the seventh switch S7 are both off.

[0068] The clock signal of the first phase Φ1 and the clock signal of the second phase Φ2 are two non-overlapping clock signals;

[0069] The charge pump circuit provides a first positive voltage through the positive voltage output terminal Vp and a first negative voltage through the negative voltage output terminal Vn.

[0070] Figure 3(b) shows a timing diagram of two non-overlapping clock signals when the seven switches of the charge pump circuit are transistors of the same type, for example, all seven transistors can be NMOS transistors. If the first transistor S1 and the fifth transistor S5 are PMOS transistors, and the second transistor S2, the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all NMOS transistors, then because S6 and S2 are two different types of transistors, the level signals controlling the conduction of S6 and S2 are exactly opposite. Therefore, the timing of the clock signals of S6 and S2 is exactly out of phase, but the clock signals of S6 and S2 are in the same phase Φ1 (the timing diagram of their clock signals is not shown in the figure).

[0071] See Figure 3 As shown, the working principle of the charge pump circuit is as follows:

[0072] The fifth switch S5 is normally on, and the first switch S1 and the seventh switch S7 are normally off. Therefore, Vp = Vin.

[0073] When both the sixth switch S6 and the second switch S2 are on, the third switch S3 and the fourth switch S4 are both off, the first capacitor Cflying is charging, and V Cflying =Vin;

[0074] When both the sixth switch S6 and the second switch S2 are off, both the third switch S3 and the fourth switch S4 are on. The first capacitor Cflying discharges, and charge is transferred from the first capacitor Cflying to the third capacitor Cn. The voltage difference across the first capacitor Cflying remains constant transiently, Vn = -V. Cflying＝ -Vin;

[0075] Through this alternating charging and discharging method, and with the help of the second capacitor Cp and the third capacitor Cn, the output of the charge pump circuit always remains: Vp = Vin, Vn = -Vin.

[0076] The embodiments of this application only provide two-phase non-overlapping clock signals to the sixth, second, third, and fourth switches of the charge pump circuit, enabling the charge pump circuit to operate in the first high-voltage mode and generate positive and negative voltages, which is simple in design.

[0077] In the two embodiments described above, the charge pump circuit is in an open-loop state. The control circuit provides two-phase non-overlapping clock signals to different switches of the charge pump circuit to control the conduction and cutoff of each switch, so that the charge pump circuit operates in the first high-voltage mode or the second high-voltage mode.

[0078] Furthermore, for ease of explanation, the voltage provided by the positive voltage output terminal Vp in this application is represented by Vp, and the negative voltage provided by the negative voltage output terminal Vn is represented by Vn.

[0079] The charge pump circuit operates in the first high-voltage mode, which is an open-loop circuit. Transistors S1, S2, S3, S4, and S5 all operate in the linear region. The positive output terminal Vp provides the first positive voltage, and the negative output terminal Vn provides the first negative voltage, as follows:

[0080] Vp = Vin - Ip * (ron5 + esr_Cp);

[0081] Vn=-(Vin-In*(ron1+ron2+ron3+ron4+esr_Cflying+esr_Cn)*2).;

[0082] The charge pump circuit operates in the second high-voltage mode, which is an open-loop circuit. Transistors S2, S3, S4, S5, and S6 all operate in the linear region. The positive output terminal Vp provides the first positive voltage, and the negative output terminal Vn provides the first negative voltage, as follows:

[0083] Vp = Vin - Ip * (ron5 + esr_Cp);

[0084] Vn=-(Vp-In*(ron6+ron2+ron3+ron4+esr_Cflying+esr_Cp));

[0085] Where esr_Cn, esr_Cp, and esr_Cflyting are the impedances of capacitors Cn, Cp, and Cflying, respectively; ron1, ron2, ron3, ron4, ron5, and ron6 are the on-resistances of transistors S1 to S6 in the linear region. Ip and In are the currents flowing out of the positive voltage output terminal Vp and the negative voltage output terminal Vn, respectively. Assuming all switches are ideal, in an open-loop charge pump circuit, then in the first or second high-voltage mode, according to the principle of charge conservation, Vn = -Vp, Vp = Vin. The voltage values ​​of Vp and Vn are fixed and cannot be adjusted.

[0086] In some embodiments, combined with Figure 4 As shown, the control circuit is configured to provide a three-phase non-overlapping clock signal to the charge pump circuit, causing the charge pump circuit to operate in low-voltage mode; wherein,

[0087] Both the control terminals of the first switch S1 and the seventh switch S7 receive the clock signal of the third phase Φ1', i.e. Figure 4Φ1'(S1,S7) in the diagram. Specifically, when both the first switch S1 and the seventh switch S7 receive a high-level signal, both the first switch S1 and the seventh switch S7 are turned on; when both the first switch S1 and the seventh switch S7 receive a low-level signal, both the first switch S1 and the seventh switch S7 are turned off.

[0088] Both the control terminals of the second switch S2 and the sixth switch S6 receive the clock signal of the fourth phase Φ2', i.e. Figure 4 Φ2'(S2,S6) in the diagram. Specifically, when both the second switch S2 and the sixth switch S6 receive a high-level signal, both the second switch S2 and the sixth switch S6 are turned on; when both the second switch S2 and the sixth switch S6 receive a low-level signal, both the second switch S2 and the sixth switch S6 are turned off.

[0089] Both the control terminals of the third switch S3 and the fourth switch S4 receive the clock signal of the fifth phase Φ3', i.e. Figure 4 Φ3'(S3,S4) in the diagram. Specifically, when both the third switch S3 and the fourth switch S4 receive a high-level signal, both switches S3 and S4 are turned on; when both switches S3 and S4 receive a low-level signal, both switches S3 and S4 are turned off.

[0090] Fifth switch S5 is off;

[0091] The clock signals of the third phase Φ1', the fourth phase Φ2', and the fifth phase Φ3' are three-phase non-overlapping clock signals;

[0092] The charge pump circuit provides a second positive voltage through the positive voltage output terminal Vp and a second negative voltage through the negative voltage output terminal Vn.

[0093] Figure 4 (b) shows a timing diagram of two non-overlapping clock signals when the seven switches of the charge pump circuit are transistors of the same type, for example, all seven transistors can be NMOS transistors. If the first transistor S1 and the fifth transistor S5 are PMOS transistors, and the second transistor S2, the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all NMOS transistors, then because S1 and S7 are two different types of transistors, the level signals controlling the conduction of S1 and S7 are exactly opposite. Therefore, the timing of the clock signals of S1 and S7 is exactly out of phase, but the clock signals of S1 and S7 are in the same phase Φ1' (the timing diagram of their clock signals is not shown in the figure).

[0094] See Figure 4 and Figure 5In the open-loop state of the charge pump circuit, the control circuit provides a three-phase non-overlapping clock signal to the charge pump circuit, enabling the charge pump circuit to operate in low-voltage mode to achieve the output of the second positive voltage and the second negative voltage. The working principle of the charge pump circuit is described below:

[0095] The fifth switch S5 is normally off.

[0096] Under the control of the clock signal of the third phase Φ1', the charge pump circuit has the first switch S1 and the seventh switch S7 both turned on, while the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all turned off. The first capacitor Cflying and the second capacitor Cp are connected in series (e.g., Figure 5 (a) As shown in the diagram; In the open-loop state of the charge pump circuit, the voltage value of the positive output terminal Vp is determined by the capacitance values ​​of the first capacitor Cflying and the second capacitor Cp. If Cflying = Cp = Cn, that is, the capacitance values ​​of the first capacitor Cflying, the second capacitor Cp, and the third capacitor Cn are all equal, then Vp = 1 / 2Vin, that is, the second positive voltage output by the positive output terminal Vp is equal to 1 / 2Vin.

[0097] Under the control of the clock signal of the fourth phase Φ2', the charge pump circuit has the second switch S2 and the sixth switch S6 both turned on, while the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, and the seventh switch S7 are all turned off. The first capacitor Cflying and the second capacitor Cp are connected in parallel (e.g., Figure 5 (b) As shown; In the open-loop state of the charge pump circuit, the first capacitor Cflying and the second capacitor Cp share the charge.

[0098] Under the control of the clock signal of the fifth phase Φ3', the charge pump circuit has the third switch S3 and the fourth switch S4 both turned on, while the first switch S1, the second switch S2, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are all turned off. The first capacitor Cflying and the third capacitor Cn are connected in series (e.g., Figure 5 (c) As shown, according to the principle of charge conservation, Vn = -1 / 2Vin, that is, the second negative voltage output by the negative voltage output terminal Vn is equal to -1 / 2Vin.

[0099] As can be seen from the above, the charge pump circuit provides a second positive voltage 1 / 2Vin through the positive voltage output terminal Vp, and a second negative voltage -1 / 2Vin through the negative voltage output terminal Vn, that is, Vp = 1 / 2Vin, Vn = -1 / 2Vin (here we assume that all switches are ideal).

[0100] The charge pump circuit in this embodiment is a step-down charge pump circuit. It only provides a three-phase non-overlapping clock signal to the first, seventh, second, sixth, third, and fourth switches of the charge pump circuit, so that the charge pump circuit can operate in a low-voltage mode to achieve "half-voltage" conversion and generate a second positive voltage and a second negative voltage. The design is simple.

[0101] The charge pump circuit provided in this application embodiment can generate both positive and negative voltages simultaneously using only one charge pump circuit structure instead of two independent charge pump circuits, reducing area and facilitating integration. The charge pump circuit structure uses only one Cflying capacitor (Flying Capacitance) and fewer transistors, while avoiding the use of expensive inductors to generate positive and negative voltages, thus reducing costs.

[0102] Furthermore, by providing the charge pump circuit with two-phase or three-phase non-overlapping clock signals, the charge pump circuit can operate in three different voltage modes. This makes it suitable for various operating scenarios when applied to automotive audio Class-G (Class-G power amplifier) ​​amplifiers or LCD (Liquid Crystal Display) / TFT ​​(Thin Film Transistor) screen drivers. The design is simple.

[0103] Based on the same inventive concept, see [link to inventive concept] Figure 6 As shown, this application embodiment provides a power supply, which includes a charge pump circuit, a positive voltage output terminal Vp, a negative voltage output terminal Vn, and a control circuit provided in any of the above embodiments; the charge pump circuit is electrically connected to the positive voltage output terminal Vp and the negative voltage output terminal Vn respectively.

[0104] The control circuit includes a feedback circuit, an operational amplifier, a clock circuit, a pre-amplifier analog drive circuit, and a pre-amplifier digital drive circuit.

[0105] Specifically, the feedback circuit is electrically connected to the positive voltage output terminal Vp and the negative voltage output terminal Vn respectively, and is used to receive the positive voltage provided by the positive voltage output terminal Vp and the negative voltage provided by the negative voltage output terminal Vn, and output the feedback voltage VFB;

[0106] The operational amplifier is electrically connected to the feedback circuit to receive the reference voltage and the feedback voltage VFB, and outputs the drive signal EAOUT.

[0107] The clock circuit is used to output the first set of clock signals and the second set of clock signals;

[0108] The front-end analog drive circuit is electrically connected to the clock circuit, operational amplifier and charge pump circuit respectively. It is used to receive the drive signal EAOUT and the first set of clock signals, and generate the first adjustment voltage Vreg1 and the second adjustment voltage Vreg2 according to the drive signal EAOUT and the first set of clock signals and provide them to the charge pump circuit.

[0109] The pre-stage digital drive circuit is electrically connected to the clock circuit and the charge pump circuit respectively. It is used to receive the second set of clock signals and provide the second set of clock signals to the charge pump circuit after digital amplification.

[0110] The power supply provided in this application includes a charge pump circuit, a positive voltage output terminal, a negative voltage output terminal, and a control circuit. The control circuit automatically modulates the voltages output from the positive and negative voltage output terminals, forming a closed-loop modulation of the active charge pump circuit. The power supply provided in this application can provide high-performance positive and negative voltages, and the values ​​of the positive and negative voltages are adjustable. For example, the charge pump circuit in the power supply can operate in three different voltage modes to suit different application scenarios such as class-G power amplifier circuits and LCD / TFT screen drivers. This eliminates the need for two independent charge pump circuits to generate positive and negative voltages. The charge pump circuit structure of the power supply provided in this application is simple, uses fewer components, is low-cost, and highly efficient. The voltage source Vin of the charge pump circuit can be a general voltage source or the battery voltage VBAT; this application does not limit its use.

[0111] Optionally, the second set of clock signals may include two-phase non-overlapping clock signals and three-phase non-overlapping clock signals.

[0112] Optionally, see Figure 6 As shown, the power supply also includes a logic control circuit. The logic control circuit is electrically connected to the clock circuit and is used to control the clock circuit to output a two-phase non-overlapping clock signal or a three-phase non-overlapping clock signal to the preceding digital drive circuit.

[0113] Optionally, see Figure 6 As shown, the power supply also includes a compensation network. The compensation network is electrically connected to the output of the operational amplifier.

[0114] Optionally, see Figure 7 As shown, the feedback circuit includes a current source Ib, a first resistor R1, and a second resistor R2. The current source Ib is electrically connected to one end of the first resistor R1 and to the positive voltage output terminal Vp. The other end of the first resistor R1 is electrically connected to one end of the second resistor R2 and receives the feedback voltage VFB. The other end of the second resistor R2 is electrically connected to the negative voltage output terminal Vn.

[0115] Combination Figure 6 and Figure 7As shown, the feedback circuit yields: Vp = VFB + Ib*R1, Vn = VFB - Ib*R2. In this embodiment, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 in the feedback circuit, the feedback voltage is adjusted, which in turn adjusts the drive signal output by the operational amplifier. Based on the drive signal, the first regulating voltage Vreg1 and the second regulating voltage Vreg2 generated by the preceding analog drive circuit are controlled, thereby adjusting the positive and negative voltage values ​​output by the charge pump circuit. The reference voltage Vref can be 0 or other non-zero references.

[0116] In some embodiments, the front-end digital drive circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit is configured to provide a first regulating voltage Vreg1 and a second regulating voltage Vreg2 to the charge pump circuit, such that the charge pump circuit operates in a first high-voltage mode; wherein...

[0117] The control terminal of the fifth switch S5 in the charge pump circuit receives the first regulating voltage Vreg1 provided by the preceding analog drive circuit;

[0118] The control terminal of the second switch S2 of the charge pump circuit receives the second regulating voltage Vreg2 provided by the preceding analog drive circuit.

[0119] The control terminal of the first switch S1 of the charge pump circuit receives the clock signal of the first phase Φ1 provided by the preceding digital drive circuit;

[0120] The control terminals of the third switch S3 and the fourth switch S4 of the charge pump circuit both receive the clock signal of the second phase Φ2 provided by the preceding digital drive circuit.

[0121] The control terminals of the sixth switch S6 and the seventh switch S7 of the charge pump circuit both receive the turn-off signal provided by the preceding digital drive circuit.

[0122] The clock signal of the first phase Φ1 and the clock signal of the second phase Φ2 are two non-overlapping clock signals; the second set of clock signals includes the clock signal of the first phase Φ1 and the clock signal of the second phase Φ2.

[0123] In one specific embodiment, see Figure 8 As shown, each switch in the charge pump circuit is a transistor. Specifically, the first transistor S1 and the fifth transistor S5 are both PMOS transistors; the second transistor S2, the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all NMOS transistors.

[0124] The front-end digital drive circuit of the control circuit provides a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit of the control circuit provides a first regulating voltage Vreg1 and a second regulating voltage Vreg2 to the charge pump circuit, performing closed-loop modulation on the charge pump circuit. The charge pump circuit operates in the first high-voltage mode. It should be noted that... Figure 8 Only the fifth transistor S5 and the second transistor S2 of the charge pump circuit are shown, receiving the first regulating voltage Vreg1 and the second regulating voltage Vreg2 provided by the preceding analog drive circuit. Other transistors of the charge pump circuit are not shown, receiving the two-phase non-overlapping clock signal provided by the preceding digital drive circuit.

[0125] Figure 8 In this process, different high and low levels are driven by the transistors. The purpose is to make the transistors conduct more completely, reduce the Rdson (on-resistance), and thus improve efficiency.

[0126] For example, Figure 8 In this configuration, the gate of the first transistor S1 is turned off when it receives the battery voltage VBAT and turned on when it receives the voltage at the negative output terminal Vn; the gate of the third transistor S3 is turned on when it receives the battery voltage VBAT and turned off when it receives the voltage at the negative output terminal Vn; the gate of the second transistor S2 is turned on when it receives the second regulating voltage Vreg2 and turned off when it receives the voltage at the negative output terminal Vn; the gate of the fourth transistor S4 is turned on when it receives the battery voltage VBAT and turned off when it receives the voltage at the negative output terminal Vn.

[0127] Specifically, the gate of the fifth transistor S5 in the charge pump circuit receives the first regulating voltage Vreg1 provided by the preceding analog drive circuit.

[0128] The gate of the second transistor S2 in the charge pump circuit receives the second regulating voltage Vreg2 provided by the preceding analog drive circuit.

[0129] The gate of the first transistor S1 in the charge pump circuit receives the clock signal of the first phase Φ1 provided by the preceding digital drive circuit;

[0130] The gates of the third transistor S3 and the fourth transistor S4 in the charge pump circuit both receive the second phase Φ2 clock signal provided by the preceding digital drive circuit.

[0131] The sixth transistor S6 of the charge pump circuit receives the turn-off signal 0 provided by the preceding digital driving circuit, and the gate of the seventh transistor S7 also receives the turn-off signal Vn provided by the preceding digital driving circuit.

[0132] The clock signal of the first phase Φ1 and the clock signal of the second phase Φ2 are two-phase non-overlapping clock signals. The timing sequence of the clock signals of the first phase Φ1 and the second phase Φ2 can be found in [reference needed]. Figure 2And the related description above.

[0133] Specifically, the charge pump circuit operates in the first high-voltage mode. Under the control of the clock signal of the first phase Φ1, the first transistor S1, the second transistor S2, and the fifth transistor S5 are all turned on, while the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all turned off. One end of the first capacitor Cflying is connected to the power supply terminal Vin (VBAT), and the other end of the first capacitor Cflying is connected to the ground terminal. That is, the voltage of the power supply terminal Vin (VBAT) is connected to the ground through the first capacitor Cflying, Vp = Vin, and the positive voltage provided by the positive voltage output terminal Vp is a fixed maximum positive voltage.

[0134] Under the control of the clock signal of the second phase Φ2, the charge pump circuit turns on the third transistor S3 and the fourth transistor S4, while the first transistor S1, the second transistor S2, the fifth transistor S5, the sixth transistor S6 and the seventh transistor S7 are all turned off. One end of the first capacitor Cflying is connected to the ground terminal, and the other end of the first capacitor Cflying is connected to the negative voltage output terminal Vn. The voltage value of the negative voltage output terminal Vn is controlled by the second regulating voltage Vreg2 of the loop.

[0135] The first regulating voltage Vreg1 and the second regulating voltage Vreg2 are voltage values ​​determined after the loop stabilizes, and are respectively related to the voltage values ​​provided by the positive voltage output terminal Vp and the negative voltage output terminal Vn.

[0136] When the first regulating voltage Vreg1 increases, the voltage value of the positive voltage output terminal Vp decreases (Vp>0);

[0137] When the second regulating voltage Vreg2 increases, the absolute value of the voltage at the negative voltage output terminal Vn increases (Vn<0).

[0138] The charge pump circuit of this application operates in the first high voltage mode and controls the positive and negative voltage values ​​provided by the charge pump circuit through a closed loop, so that the positive and negative voltage values ​​are adjustable and can be applied to a variety of different application scenarios.

[0139] In some embodiments, the front-end digital drive circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit is configured to provide a first regulating voltage Vreg1 and a second regulating voltage Vreg2 to the charge pump circuit, such that the charge pump circuit operates in a second high-voltage mode; wherein...

[0140] The control terminal of the fifth switch S5 in the charge pump circuit receives the first regulating voltage Vreg1 provided by the preceding analog drive circuit;

[0141] The control terminal of the second switch S2 of the charge pump circuit receives the second regulating voltage Vreg2 provided by the preceding analog drive circuit.

[0142] The control terminal of the sixth switch S6 of the charge pump circuit receives the clock signal of the first phase Φ1 provided by the preceding digital drive circuit;

[0143] The control terminals of the third switch S3 and the fourth switch S4 of the charge pump circuit both receive the clock signal of the second phase Φ2 provided by the preceding digital drive circuit.

[0144] The control terminals of the first switch S1 and the seventh switch S7 of the charge pump circuit both receive the turn-off signal provided by the preceding digital drive circuit.

[0145] The clock signal of the first phase Φ1 and the clock signal of the second phase Φ2 are two non-overlapping clock signals; the second set of clock signals includes the clock signal of the first phase Φ1 and the clock signal of the second phase Φ2.

[0146] In one specific embodiment, see Figure 9 As shown, each switch in the charge pump circuit is a transistor. Specifically, the first transistor S1 and the fifth transistor S5 are both PMOS transistors; the second transistor S2, the third transistor S3, the fourth transistor S4, the sixth transistor S6, and the seventh transistor S7 are all NMOS transistors.

[0147] The front-end digital drive circuit of the control circuit provides a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit of the control circuit provides a first regulating voltage Vreg1 and a second regulating voltage Vreg2 to the charge pump circuit, performing closed-loop modulation on the charge pump circuit. The charge pump circuit operates in the second high-voltage mode. It should be noted that... Figure 9 Only the fifth transistor S5 and the second transistor S2 of the charge pump circuit are shown, receiving the first regulating voltage Vreg1 and the second regulating voltage Vreg2 provided by the preceding analog drive circuit. Other transistors of the charge pump circuit are not shown, receiving the two-phase non-overlapping clock signal provided by the preceding digital drive circuit.

[0148] Figure 9 In this process, different high and low levels are driven by the transistors. The purpose is to make the transistors conduct more completely, reduce the Rdson (on-resistance), and thus improve efficiency.

[0149] For example, Figure 9In the circuit, the gates of the third transistor S3 and the sixth transistor S6 are turned on when they receive the battery voltage VBAT and turned off when they receive 0 voltage; the gate of the second transistor S2 is turned on when it receives the second regulating voltage Vreg2 and turned off when it receives the voltage of the negative voltage output terminal Vn. The gate of the fourth transistor S4 is turned on when it receives the battery voltage VBAT and turned off when it receives the voltage of the negative voltage output terminal Vn.

[0150] The control terminal of the fifth transistor S5 in the charge pump circuit receives the first regulating voltage Vreg1 provided by the preceding analog drive circuit;

[0151] The control terminal of the second transistor S2 in the charge pump circuit receives the second regulating voltage Vreg2 provided by the preceding analog drive circuit.

[0152] The control terminal of the sixth transistor S6 in the charge pump circuit receives the clock signal of the first phase Φ1 provided by the preceding digital drive circuit;

[0153] The control terminals of the third transistor S3 and the fourth transistor S4 in the charge pump circuit both receive the clock signal of the second phase Φ2 provided by the preceding digital drive circuit.

[0154] The control terminals of the first transistor S1 and the seventh transistor S7 in the charge pump circuit both receive the turn-off signal provided by the preceding digital drive circuit.

[0155] The clock signal of the first phase Φ1 and the clock signal of the second phase Φ2 are two-phase non-overlapping clock signals; the timing of the clock signals of the first phase Φ1 and the second phase Φ2 can be found in [reference needed]. Figure 3 And the related description above.

[0156] Specifically, the charge pump circuit operates in the second high-voltage mode. Under the control of the clock signal of the first phase Φ1, the second transistor S2, the fifth transistor S5, and the sixth transistor S6 are all turned on, while the first transistor S1, the third transistor S3, the fourth transistor S4, and the seventh transistor S7 are all turned off.

[0157] Under the control of the clock signal of the second phase Φ2, the charge pump circuit turns on the third transistor S3 and the fourth transistor S4, while the first transistor S1, the second transistor S2, the fifth transistor S5, the sixth transistor S6, and the seventh transistor S7 are all turned off. The voltage values ​​of the positive voltage output terminal Vp and the negative voltage output terminal Vn are modulated by the loop.

[0158] The first regulating voltage Vreg1 and the second regulating voltage Vreg2 are voltage values ​​determined after the loop stabilizes, and are respectively related to the voltage values ​​provided by the positive voltage output terminal Vp and the negative voltage output terminal Vn.

[0159] When the first regulating voltage Vreg1 increases, the voltage value of the positive voltage output terminal Vp decreases (Vp>0);

[0160] When the second regulating voltage Vreg2 increases, the absolute value of the voltage at the negative voltage output terminal Vn increases (Vn<0).

[0161] The charge pump circuit of this application operates in the second high-voltage mode and controls the positive and negative voltage values ​​provided by the charge pump circuit through a closed-loop circuit, so that the positive and negative voltage values ​​are adjustable and can be applied to a variety of different application scenarios.

[0162] Combination Figure 7 , Figure 8 , Figure 9 As shown, under loop control, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 in the feedback circuit, any adjustable positive and negative voltage values ​​can be obtained.

[0163] pass Figure 7 The feedback circuit yields Vp = VFB + Ib*R1 and Vn = VFB - Ib*R2. The feedback voltage VFB can be calculated and input to the operational amplifier. The operational amplifier outputs a drive signal EAOUT based on the reference voltage and the feedback voltage VFB. The drive signal EAOUT controls the output of a first regulating voltage Vreg1 and a second regulating voltage Vreg2 from the preceding analog drive circuit, thereby adjusting the voltage values ​​provided by the charge pump circuit through the positive output terminal Vp and the negative output terminal Vn. In this embodiment, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 in the feedback circuit, the voltage values ​​provided by the positive output terminal Vp and the negative output terminal Vn can be precisely controlled.

[0164] In some embodiments, see Figure 10a As shown, the front-end analog drive circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a first current source I1, and a second current source I2. Among these, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are PMOS transistors, while the first transistor M1, the second transistor M2, the sixth transistor M6, and the ninth transistor M9 are NMOS transistors.

[0165] Specifically, the gate of the first transistor M1 is connected to the output terminal of the operational amplifier to receive the drive signal EAOUT output by the operational amplifier. The source of the first transistor M1 is connected to the second voltage terminal Vn through the first current source I1. The drain of the first transistor M1 is connected to the source of the second transistor M2 and the source of the sixth transistor M6, respectively.

[0166] The gate of the second transistor M2 is connected to the gate of the third transistor M3 and receives the voltage of the first voltage terminal Vin. The drain of the second transistor M2 is connected to the drain of the third transistor M3 and to the gate of the fourth transistor M4, and outputs the first regulating voltage Vreg1. The gate and drain of the fourth transistor M4 are connected.

[0167] The drain and gate of the fifth transistor M5 are connected, and the drain of the sixth transistor M6 is also connected. The gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7. The gate of the fifth transistor M5 is connected to the drain of the seventh transistor M7 and the gate of the eighth transistor M8. The drain of the eighth transistor M8 is connected to the drain of the ninth transistor M9, and outputs a second regulating voltage Vreg2. The source of the ninth transistor M9 is connected to the second voltage terminal Vn, and the drain of the ninth transistor M9 is connected to the second voltage terminal Vn through the second current source I2.

[0168] The sources of the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are all connected to the first voltage terminal Vin.

[0169] See Figure 10a and Figure 10b Φ1, SWN1 represent the clock signal SWN1 with phase Φ1. Φ1B, SWN1B represent the clock signal SWN1B with phase Φ1B. Phases Φ1 and Φ1B are exactly out of phase. Both the clock signal SWN1 with phase Φ1 and the clock signal SWN1B with phase Φ1B are clock signals output from the clock circuit to the preceding analog drive circuit. That is, the first set of clock signals includes the clock signal SWN1 with phase Φ1 and the clock signal SWN1B with phase Φ1B.

[0170] The working principle of the pre-amplifier analog drive circuit is as follows:

[0171] The value of the drive signal EAOUT is determined by the loop. Both the fourth transistor M4 and the fifth transistor M5 are biased using diodes.

[0172] The third transistor M3 is always off, the second transistor M2 is always on, and the fourth transistor M4 is configured as a diode to provide the first regulating voltage Vreg1. The voltage value of the first regulating voltage Vreg1 is an analog level between 0 and Vin, and is controlled by the loop.

[0173] When the clock signal SWN1 of the first phase Φ1 is low, the sixth transistor M6 is turned off, the seventh transistor M7 pulls the gate of the eighth transistor M8 high, and at the same time the ninth transistor M9 is turned on, pulling the second regulation voltage Vreg2 down to Vn.

[0174] When the clock signal SWN1 of the first phase Φ1 is high, the sixth transistor M6 is turned on, the seventh transistor M7 is turned off, and the ninth transistor M9 is turned off at the same time. The voltage value of the second regulating voltage Vreg2 is an analog level between 0 and Vin, which is controlled by the loop.

[0175] In the embodiments of this application, a first regulating voltage and a second regulating voltage are generated by a front-end analog drive circuit in the first high-voltage mode and the second high-voltage mode, thereby controlling the voltage values ​​of the positive and negative voltages provided by the charge pump circuit, so as to realize the adjustable voltage values ​​of the positive and negative voltages, which can be applied to a variety of different application scenarios.

[0176] In some embodiments, the front-end digital drive circuit is configured to provide a three-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit is configured to provide a first regulating voltage Vreg1 and a second regulating voltage Vreg2 to the charge pump circuit, such that the charge pump circuit operates in a low-voltage mode; wherein...

[0177] The control terminal of the first switch S1 of the charge pump circuit receives the first regulating voltage provided by the preceding analog drive circuit.

[0178] The control terminal of the third switch S3 in the charge pump circuit receives the second regulating voltage provided by the preceding analog drive circuit;

[0179] The control terminal of the seventh switch S7 of the charge pump circuit receives the clock signal of the third phase Φ1' provided by the preceding digital drive circuit.

[0180] The control terminals of the second switch S2 and the sixth switch S6 of the charge pump circuit both receive the clock signal of the fourth phase Φ2' provided by the preceding digital drive circuit;

[0181] The control terminal of the fourth switch S4 of the charge pump circuit receives the clock signal of the fifth phase Φ3' provided by the preceding digital drive circuit;

[0182] The control terminal of the fifth switch S5 in the charge pump circuit receives the shutdown signal VBAT provided by the preceding digital drive circuit.

[0183] The clock signals of the third phase Φ1', the fourth phase Φ2', and the fifth phase Φ3' are three-phase non-overlapping clock signals; the second group of clock signals includes the clock signals of the third phase Φ1', the fourth phase Φ2', and the fifth phase Φ3'.

[0184] In one specific embodiment, see Figure 11 As shown, each switch in the charge pump circuit is a transistor. Specifically, transistors S1 and S5 are PMOS transistors; transistors S2, S3, S4, S6, and S7 are NMOS transistors. To improve efficiency, transistors S1, S2, S3, S4, S5, S6, and S7 must all operate in the linear region to minimize the on-resistance Ron.

[0185] The front-end digital drive circuit of the control circuit provides a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit of the control circuit provides a first regulating voltage Vreg1 and a second regulating voltage Vreg2 to the charge pump circuit, performing closed-loop modulation on the charge pump circuit, which operates in low-voltage mode; it should be noted that Figure 11 Only the first transistor S1 and the third transistor S3 of the charge pump circuit are shown, receiving the first regulating voltage Vreg1 and the second regulating voltage Vreg2 provided by the preceding analog drive circuit. Other transistors of the charge pump circuit are not shown, receiving the three-phase non-overlapping clock signal provided by the preceding digital drive circuit.

[0186] Figure 11 In this process, different high and low levels are driven by the transistors. The purpose is to make the transistors conduct more completely, reduce the Rdson (on-resistance), and thus improve efficiency.

[0187] For example, Figure 11 In this configuration, the gate of the first transistor S1 is turned off when it receives the battery voltage VBAT and turned on when it receives the first regulating voltage Vreg1; the gate of the third transistor S3 is turned on when it receives the second regulating voltage Vreg2 and turned off when it receives the voltage of the negative voltage output terminal Vn; the gate of the sixth transistor S6 is turned on when it receives the battery voltage VBAT and turned off when it receives 0 voltage. The gates of the second transistor S2, the seventh transistor S7, and the fourth transistor S4 are all turned on when they receive the battery voltage VBAT and turned off when they receive the voltage of the negative voltage output terminal Vn.

[0188] Specifically, the gate of the first transistor S1 in the charge pump circuit receives a first regulating voltage provided by the preceding analog drive circuit;

[0189] The gate of the third transistor S3 in the charge pump circuit receives a second regulating voltage provided by the preceding analog drive circuit.

[0190] The gate of the seventh transistor S7 in the charge pump circuit receives the clock signal of the third phase Φ1' provided by the preceding digital drive circuit.

[0191] The gates of the second transistor S2 and the sixth transistor S6 in the charge pump circuit both receive the fourth phase Φ2' clock signal provided by the preceding digital drive circuit.

[0192] The gate of the fourth transistor S4 in the charge pump circuit receives the clock signal of the fifth phase Φ3' provided by the preceding digital drive circuit.

[0193] The gate of the fifth transistor S5 in the charge pump circuit receives the turn-off signal VBAT provided by the preceding digital drive circuit.

[0194] The clock signals of the third phase Φ1', the fourth phase Φ2', and the fifth phase Φ3' are three-phase non-overlapping clock signals; the timing sequence of the clock signals of the third phase Φ1', the fourth phase Φ2', and the fifth phase Φ3' can be found in [reference needed]. Figure 4 And the related description above.

[0195] Combination Figure 7 and Figure 11 As shown, under loop control, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 in the feedback circuit, the voltage values ​​of the second positive voltage and the second negative voltage can be obtained arbitrarily adjustable.

[0196] The first regulating voltage Vreg1 controls the first transistor S1 to turn on, and the second regulating voltage Vreg2 controls the third transistor S3 to turn on.

[0197] As described above, under the control of the clock signal of the third phase Φ1', the voltage value provided by the positive voltage output terminal Vp of the charge pump circuit is input to the feedback circuit.

[0198] Under the control of the clock signal of the fifth phase Φ3', the voltage value provided by the negative voltage output terminal Vn of the charge pump circuit is input to the feedback circuit.

[0199] pass Figure 7The feedback circuit yields Vp = VFB + Ib*R1 and Vn = VFB - Ib*R2. The feedback voltage VFB can be calculated and input to the operational amplifier. The operational amplifier outputs a drive signal EAOUT based on the reference voltage and the feedback voltage VFB. The drive signal EAOUT controls the output of a first regulating voltage Vreg1 and a second regulating voltage Vreg2 from the preceding analog drive circuit, thereby adjusting the voltage values ​​provided by the charge pump circuit through the positive output terminal Vp and the negative output terminal Vn. In this embodiment, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 in the feedback circuit, the voltage values ​​provided by the positive output terminal Vp and the negative output terminal Vn can be precisely controlled.

[0200] See Figure 12a and Figure 12b Φ1', SWP1B represents the clock signal SWP1B of the third phase Φ1'. Φ3', SWN3 represents the clock signal SWN3 of the fifth phase Φ3'. Φ3'B, SWN3B represents the clock signal SWN3B of phase Φ3'B. Phases Φ3' and Φ3'B are exactly out of phase.

[0201] The working principle of the pre-amplifier analog drive circuit is as follows:

[0202] The value of the drive signal EAOUT is determined by the loop. Both the fourth transistor M4 and the fifth transistor M5 are biased using diodes.

[0203] When the clock signal SWP1B of the third phase Φ1' is high, SWN3 is low and SWN3B is high. Therefore, the second transistor M2 is turned on, the sixth transistor M6 is turned off, and the seventh transistor M7 pulls the gate of the eighth transistor M8 high, turning off M8. Simultaneously, the ninth transistor M9 is turned on, pulling the second regulating voltage Vreg2 down to Vn. The first regulating voltage Vreg1 is an analog level between 0 and Vin, controlled by the loop.

[0204] When the clock signal SWN3 of the fifth phase Φ3' is high, SWN3B and SWP1B are low. At this time, the second transistor M2 is off and the sixth transistor M6 is on. The third transistor M3 pulls the first regulating voltage Vreg1 high to Vin. The voltage value of the second regulating voltage Vreg2 is an analog level between 0 and Vin, controlled by the loop.

[0205] The charge pump circuit in this embodiment is a step-down charge pump circuit. In low-voltage mode, a first regulating voltage and a second regulating voltage are generated by the front-end analog drive circuit, thereby controlling the voltage values ​​of the positive and negative voltages provided by the charge pump circuit. This makes the voltage values ​​of the positive and negative voltages adjustable and applicable to a variety of different application scenarios.

[0206] In some embodiments, the first regulating voltage is inversely proportional to the positive voltage provided at the positive voltage output terminal; the second regulating voltage is directly proportional to the absolute value of the negative voltage provided at the negative voltage output terminal.

[0207] Specifically, the first regulating voltage Vreg1 and the second regulating voltage Vreg2 are voltage values ​​determined after the loop stabilizes, and are respectively related to the voltage values ​​provided by the positive voltage output terminal Vp and the negative voltage output terminal Vn.

[0208] The first regulating voltage Vreg1 regulates the voltage value of the positive voltage output terminal Vp, and the second regulating voltage Vreg2 regulates the voltage value of the negative voltage output terminal Vn.

[0209] When the first regulating voltage Vreg1 increases, the voltage value of the positive voltage output terminal Vp decreases (Vp>0);

[0210] When the second regulating voltage Vreg2 increases, the absolute value of the voltage at the negative voltage output terminal Vn increases (Vn<0).

[0211] The first regulating voltage Vreg1 and the second regulating voltage Vreg2 are both greater than 0 and less than Vin.

[0212] The charge pump circuit provided in this application embodiment controls the positive and negative voltage values ​​provided by the charge pump circuit through a closed loop, and the positive and negative voltage values ​​are adjustable, making it suitable for a variety of different application scenarios.

[0213] In some embodiments, in order to improve efficiency, among the three voltage modes of operation of the charge pump circuit described above, namely the first high-voltage mode, the second high-voltage mode, and the low-voltage mode, this application provides a new design method as follows:

[0214] The load current of the charge pump circuit is dynamically detected, and the size of each transistor is controlled based on the detected load current, thereby improving the efficiency of the charge pump circuit.

[0215] For example, the gate of the first transistor S1 can be combined with the original output signal to perform multi-bit encoding to achieve the selection of size range. Logic encoding is added to the drive output section of the first transistor S1 to determine the size of the first transistor S1 based on the original output signal and the logic signal. For example, the size of the first transistor S1 can be divided into four parts: 8:4:2:1, each requiring a 2-bit logic signal to control the gate of each of these four parts respectively. By performing an OR logic operation between the logic signal and the original output signal, when the OR logic result is 1, the selected size of the first transistor S1 is turned off; when the OR logic result is 0, it is turned on, and the first transistor S1 maintains its original output signal.

[0216] This application embodiment dynamically detects the load current of the charge pump circuit and dynamically controls the size of each transistor based on the detected changes in the load current, thereby reducing the capacitance of the charge pump circuit and improving the efficiency of the charge pump circuit under light load.

[0217] Based on the same inventive concept, this application provides a vehicle including the system-on-a-chip as described in the above embodiments. The implementation and effects of the vehicle provided in this application can be referred to the foregoing embodiments, and will not be repeated here.

[0218] In this application, "vehicle" can refer to "automobile," "vehicle," or "complete vehicle," or other similar terms, including general motor vehicles such as sedans, SUVs, MPVs, buses, trucks, and other freight or passenger vehicles; water transport vehicles including various boats and vessels; and aircraft, including hybrid vehicles, electric vehicles, gasoline vehicles, plug-in hybrid vehicles, fuel cell vehicles, and other alternative fuel vehicles. Hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles and range-extended electric vehicles; this application does not specifically limit their use.

[0219] This application also provides an electronic device, including a processor and a memory, wherein the memory stores an executable program, and the memory executes the executable program to perform the steps of the method described above. The implementation and effects of the electronic device provided in this application can be referred to the foregoing embodiments, and will not be repeated here.

[0220] This application also provides a storage medium carrying one or more computer programs, which, when executed by a processor, implement the steps of the method described above.

[0221] This application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the method described above.

[0222] It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0223] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0224] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.

[0225] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0226] It should also be understood that the first, second, third, fourth and various numerical designations used herein are merely for descriptive convenience and are not intended to limit the scope of this application.

[0227] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0228] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0229] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0230] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0231] In the several embodiments provided in this application, it should be understood that the disclosed methods, accelerators, and electronic devices can be implemented in other ways. For example, the accelerator embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0232] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0233] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0234] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0235] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charge pump circuit, characterized in that, include: First switch, second switch, third switch, fourth switch, fifth switch, sixth switch, seventh switch, first capacitor, second capacitor, and third capacitor; Both the first terminal of the first switch and the first terminal of the fifth switch are electrically connected to the power supply terminal. The second terminal of the first switch, the first terminal of the third switch, the second terminal of the sixth switch, and the first terminal of the first capacitor are all electrically connected to the first node; the second terminal of the third switch is electrically connected to the ground terminal. The second terminal of the fifth switch, the first terminal of the sixth switch, the first terminal of the seventh switch, and the first terminal of the second capacitor are all electrically connected to the second node, the second node is electrically connected to the positive voltage output terminal, and the second terminal of the second capacitor is electrically connected to the ground terminal. The second terminal of the first capacitor, the first terminal of the second switch, the second terminal of the fourth switch, and the second terminal of the seventh switch are all electrically connected to the third node; the second terminal of the second switch is electrically connected to the ground terminal; the first terminal of the fourth switch is electrically connected to the first terminal of the third capacitor and is also electrically connected to the negative voltage output terminal; the second terminal of the third capacitor is electrically connected to the ground terminal. The control terminals of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch are all electrically connected to the control circuit. The control circuit is configured to control the on and off states of the first, second, third, fourth, fifth, sixth, and seventh switches of the charge pump circuit, such that the charge pump circuit provides a positive voltage through the positive voltage output terminal and a negative voltage through the negative voltage output terminal.

2. The charge pump circuit according to claim 1, characterized in that, The first switch includes a first transistor, the second switch includes a second transistor, the third switch includes a third transistor, the fourth switch includes a fourth transistor, the fifth switch includes a fifth transistor, the sixth switch includes a sixth transistor, and the seventh switch includes a seventh transistor. The first transistor and the fifth transistor are PMOS transistors; The second transistor, the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor are all NMOS transistors.

3. The charge pump circuit according to claim 1, characterized in that, The control circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, causing the charge pump circuit to operate in a first high-voltage mode; wherein... Both the control terminals of the first switch and the second switch receive a clock signal of the first phase from the control circuit. The control terminals of the third switch and the fourth switch both receive a clock signal of the second phase from the control circuit. The fifth switch is turned on; both the sixth and seventh switches are turned off. The clock signal of the first phase and the clock signal of the second phase are two non-overlapping clock signals; The charge pump circuit provides a first positive voltage through the positive voltage output terminal and a first negative voltage through the negative voltage output terminal.

4. The charge pump circuit according to claim 1, characterized in that, The control circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, causing the charge pump circuit to operate in a second high-voltage mode; wherein... The control terminals of the sixth switch and the second switch both receive a clock signal of the first phase from the control circuit; The control terminals of the third switch and the fourth switch both receive a clock signal of the second phase from the control circuit. The fifth switch is turned on; both the first switch and the seventh switch are turned off. The clock signal of the first phase and the clock signal of the second phase are two non-overlapping clock signals; The charge pump circuit provides a first positive voltage through the positive voltage output terminal and a first negative voltage through the negative voltage output terminal.

5. The charge pump circuit according to claim 1, characterized in that, The control circuit is configured to provide a three-phase non-overlapping clock signal to the charge pump circuit, causing the charge pump circuit to operate in a low-voltage mode; wherein... Both the control terminal of the first switch and the control terminal of the seventh switch receive a clock signal of the third phase. Both the control terminal of the second switch and the control terminal of the sixth switch receive a clock signal of the fourth phase; The control terminals of the third switch and the fourth switch both receive the clock signal of the fifth phase. The fifth switch is turned off; The clock signal of the third phase, the clock signal of the fourth phase, and the clock signal of the fifth phase are three-phase non-overlapping clock signals; The charge pump circuit provides a second positive voltage through the positive voltage output terminal and a second negative voltage through the negative voltage output terminal.

6. A power supply, characterized in that, Includes the charge pump circuit, positive voltage output terminal, negative voltage output terminal, and control circuit as described in any one of claims 1 to 5; The charge pump circuit is electrically connected to the positive voltage output terminal and the negative voltage output terminal, respectively; The control circuit includes: The feedback circuit is electrically connected to the positive voltage output terminal and the negative voltage output terminal respectively, and is used to receive the positive voltage provided from the positive voltage output terminal and the negative voltage provided from the negative voltage output terminal, and output the feedback voltage. An operational amplifier, electrically connected to the feedback circuit, is used to receive the reference voltage and the feedback voltage, and output a drive signal. A clock circuit is used to output the first set of clock signals and the second set of clock signals. The front-end analog drive circuit is electrically connected to the clock circuit, the operational amplifier, and the charge pump circuit, respectively, and is used to receive the drive signal and the first set of clock signals, and generate a first adjustment voltage and a second adjustment voltage according to the drive signal and the first set of clock signals and provide them to the charge pump circuit. The front-end digital drive circuit is electrically connected to the clock circuit and the charge pump circuit respectively, and is used to receive the second set of clock signals, and to provide the second set of clock signals to the charge pump circuit after digital amplification.

7. The power supply according to claim 6, characterized in that, The front-end digital drive circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit is configured to provide a first regulated voltage and a second regulated voltage to the charge pump circuit, such that the charge pump circuit operates in a first high-voltage mode; wherein... The control terminal of the fifth switch of the charge pump circuit receives the first regulating voltage provided by the preceding analog drive circuit; The control terminal of the second switch of the charge pump circuit receives the second regulating voltage provided by the preceding analog drive circuit. The control terminal of the first switch of the charge pump circuit receives a clock signal of the first phase provided by the preceding digital drive circuit; The control terminals of the third and fourth switches of the charge pump circuit both receive the second-phase clock signal provided by the preceding digital drive circuit. The control terminals of the sixth and seventh switches of the charge pump circuit both receive the shutdown signal provided by the preceding digital drive circuit. The clock signal of the first phase and the clock signal of the second phase are two non-overlapping clock signals; the second set of clock signals includes the clock signal of the first phase and the clock signal of the second phase.

8. The power supply according to claim 6, characterized in that, The front-end digital drive circuit is configured to provide a two-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit is configured to provide a first regulated voltage and a second regulated voltage to the charge pump circuit, such that the charge pump circuit operates in a second high-voltage mode; wherein... The control terminal of the fifth switch of the charge pump circuit receives the first regulating voltage provided by the preceding analog drive circuit; The control terminal of the second switch of the charge pump circuit receives the second regulating voltage provided by the preceding analog drive circuit. The control terminal of the sixth switch of the charge pump circuit receives the first phase clock signal provided by the preceding digital drive circuit; The control terminals of the third and fourth switches of the charge pump circuit both receive the second-phase clock signal provided by the preceding digital drive circuit. The control terminals of the first and seventh switches of the charge pump circuit both receive the shutdown signal provided by the preceding digital drive circuit. The clock signal of the first phase and the clock signal of the second phase are two non-overlapping clock signals; the second set of clock signals includes the clock signal of the first phase and the clock signal of the second phase.

9. The power supply according to claim 6, characterized in that, The front-end digital drive circuit is configured to provide a three-phase non-overlapping clock signal to the charge pump circuit, and the front-end analog drive circuit is configured to provide a first regulated voltage and a second regulated voltage to the charge pump circuit, causing the charge pump circuit to operate in a low-voltage mode; wherein... The control terminal of the first switch of the charge pump circuit receives the first regulating voltage provided by the preceding analog drive circuit. The control terminal of the third switch of the charge pump circuit receives the second regulating voltage provided by the preceding analog drive circuit; The control terminal of the seventh switch of the charge pump circuit receives the third-phase clock signal provided by the preceding digital drive circuit. The control terminals of the second and sixth switches of the charge pump circuit both receive the fourth-phase clock signal provided by the preceding digital drive circuit. The control terminal of the fourth switch of the charge pump circuit receives the fifth-phase clock signal provided by the preceding digital drive circuit. The control terminal of the fifth switch of the charge pump circuit receives the shutdown signal provided by the preceding digital drive circuit. The clock signals of the third phase, the fourth phase, and the fifth phase are three-phase non-overlapping clock signals; the second set of clock signals includes the clock signals of the third phase, the fourth phase, and the fifth phase.

10. The power supply according to claim 6, characterized in that, The first regulating voltage is inversely proportional to the positive voltage provided by the positive voltage output terminal; The second regulating voltage is proportional to the absolute value of the negative voltage provided by the negative voltage output terminal.

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