A nonlinear amplifier assisted charge pump

Abstract

The application belongs to the technical field of circuit design, and relates to a nonlinear amplifier assisted charge pump, which comprises a charge pump core circuit, the charge pump core circuit has a terminal A and a terminal B, and a nonlinear amplifier is electrically connected between the terminal A and the terminal B; the nonlinear amplifier comprises a linear amplifier and a differential input stage and a cross-coupled latch series circuit which are electrically connected on the first-stage amplifier of the linear amplifier, the differential input stage is used for converting a voltage difference between the terminal A and the terminal B into a differential current, the cross-coupled latch is used for amplifying the differential current through a positive feedback mechanism, and a feedback signal is generated to act on the terminal A and the terminal B, so as to force the potentials of the terminal A and the terminal B to be consistent. The application greatly reduces current mismatch, has smaller mismatch voltage, wider output range, faster response speed, lower output noise and excellent robustness.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology, specifically relating to a nonlinear amplifier-assisted charge pump. Background Technology

[0002] Phase-locked loops (PLLs) are key components for frequency synthesis and clock generation in applications such as high-speed transceivers and IoT devices. With the ever-increasing performance requirements of communication systems and integrated circuits, low phase noise, low jitter, and high reference spurious suppression have become core performance indicators for PLL design.

[0003] In a charge pump phase-locked loop (PLL), the charge pump, as a key module that converts the phase difference output by the phase detector into current, directly affects the overall performance of the PLL. Ideally, the source current I_UP and the sink current I_DN of the charge pump should be exactly equal. However, in actual circuits, due to factors such as channel length modulation effect, charge injection, clock feedthrough, and switching nonlinearity, a dynamic current mismatch exists between the source current I_UP and the sink current I_DN. This current mismatch directly leads to two serious consequences:

[0004] First, it generates reference spurs, introducing unwanted spurious frequency components into the phase-locked loop output spectrum, reducing signal purity. Secondly, it generates static phase error, affecting the locking accuracy of the phase-locked loop (PLL). This problem is more prominent in broadband PLL applications because the charge pump needs to process long pulses at low frequencies and sub-nanosecond pulses at high frequencies simultaneously. The dominant mismatch mechanism changes with the operating frequency, and traditional solutions are difficult to effectively address across the entire frequency band.

[0005] Currently, one of the existing technical solutions to the charge pump current mismatch problem is to use linear amplifier-assisted technology, which is the most commonly used solution. Figure 1 As shown, the charge pump assisted by a linear amplifier includes a charge pump core circuit and a linear amplifier. The charge pump core circuit includes a pull-up current source array, a pull-up switch branch, a pull-down switch branch, and a pull-down bias network. The electrical connections of each part are as follows: (1) Pull-up current source array: includes three sets of PMOS transistor current source pairs: The first group consists of the twenty-fourth transistor M13 and the twenty-fifth transistor M14. Both transistors M13 and M14 are PMOS transistors. The gate of transistor M13 is electrically connected to the sixth bias voltage source Vbia1, and the gate of transistor M14 is electrically connected to the seventh bias voltage source Vbia2. The source of transistor M13 is electrically connected to the first voltage source VDD, and the source of transistor M14 is electrically connected to the drain of transistor M13. The drain of transistor M14 is the first output terminal of the pull-up current source array.

[0006] The second group consists of the twenty-sixth transistor M15 and the twenty-seventh transistor M16. Both transistors M15 and M16 are PMOS transistors. The gate of transistor M15 is electrically connected to the sixth bias voltage source Vbia1, and the gate of transistor M16 is electrically connected to the seventh bias voltage source Vbia2. The source of transistor M15 is electrically connected to the first voltage source VDD, and the source of transistor M16 is electrically connected to the drain of transistor M15. The drain of transistor M16 is the second output terminal of the pull-up current source array.

[0007] The third group consists of the twenty-eighth transistor M17 and the twenty-ninth transistor M18. Both transistors M17 and M18 are PMOS transistors. The gate of transistor M17 is electrically connected to the sixth bias voltage source Vbia1, and the gate of transistor M18 is electrically connected to the seventh bias voltage source Vbia2. The source of transistor M17 is electrically connected to the first voltage source VDD, and the source of transistor M18 is electrically connected to the drain of transistor M17. The drain of transistor M18 is the third output terminal of the pull-up current source array.

[0008] (2) Pull-up switch branch: Controlled by the Up signal and its complementary signal nUp output from the phase discriminator, it is used to direct the pull-up current to the output terminal B (or the output terminal Vout). This branch contains two sets of cascaded complementary switch structures: The first-stage complementary switch consists of the thirtieth transistor M25 and the thirty-first transistor M26. The thirtieth transistor M25 is an NMOS transistor, and the thirty-first transistor M26 is a PMOS transistor. The gate of the thirtieth transistor M25 is connected to the nUp signal, and the gate of the thirty-first transistor M26 is connected to the Up signal. The drain of the thirtieth transistor M25, the drain of the twenty-ninth transistor M18, and the source of the thirty-first transistor M26 are interconnected to form terminal Y. The source of the thirtieth transistor M25 and the drain of the thirty-first transistor M26 are interconnected and electrically connected to terminal A.

[0009] The second-stage complementary switch consists of transistors M27 (NMOS) and M28 (PMOS). The gate of the thirty-second transistor M27 is electrically connected to the gate of the thirty-first transistor M26, the gate of the thirty-third transistor M28 is electrically connected to the gate of the thirtyth transistor M25, the drain of the thirty-second transistor M27 is electrically connected to the drain of the twenty-ninth transistor M18, and the source of the thirty-second transistor M27 is electrically connected to the drain of the thirty-third transistor M28 and terminal B (or output terminal Vout).

[0010] When the Up signal is high and the nUp signal is low, the 30th transistor M25 and the 31st transistor M26 are cut off, while the 32nd transistor M27 and the 33rd transistor M28 are turned on. The pull-up current forms a charging path through the 28th transistor M17 → the 29th transistor M18 → terminal Y → the 32nd transistor M27 → the 33rd transistor M28 → the output terminal Vout.

[0011] (3) Pull-down switch branch: Controlled by the Down signal and its complementary signal nDown output from the phase discriminator, it is used to discharge the charge of terminal B (or output Vout) to ground. This branch also contains two sets of cascaded complementary switch structures:

[0012] The first-stage complementary switch consists of the thirty-fourth transistor M30 and the thirty-fifth transistor M31. The thirty-fourth transistor M30 is an NMOS transistor, and the thirty-fifth transistor M31 is a PMOS transistor. The gate of the thirty-fourth transistor M30 is connected to the nDown signal, and the gate of the thirty-fifth transistor M31 is connected to the Down signal. The source of the thirty-fourth transistor M30 and the drain of the thirty-fifth transistor M31 are electrically connected to form terminal X. The drain of the thirty-fourth transistor M30, the source of the thirty-fifth transistor M31, and the drain of the thirty-first transistor M26 are electrically connected to terminal A.

[0013] The second-stage complementary switch consists of the thirty-sixth transistor M32 and the thirty-seventh transistor M33. The thirty-sixth transistor M32 is an NMOS transistor, and the thirty-seventh transistor M33 is a PMOS transistor. The gate of the thirty-sixth transistor M32 is electrically connected to the gate of the thirty-fifth transistor M31 and receives the Down signal. The gate of the thirty-seventh transistor M33 is electrically connected to the gate of the thirty-fourth transistor M30. The source of the thirty-sixth transistor M32 is electrically connected to the drain of the thirty-seventh transistor M33 and is electrically connected to terminal X. The drain of the thirty-sixth transistor M32 and the source of the thirty-seventh transistor M33 are interconnected and electrically connected to terminal B.

[0014] When the Down signal is high and the nDown signal is low, the 34th transistor M30 and the 35th transistor M31 are turned off, while the 36th transistor M32 and the 37th transistor M33 are turned on. The charge at terminal B (or output terminal Vout) forms a discharge path through the 36th transistor M32, the 37th transistor M33 → terminal X → pull-down bias network.

[0015] (4) Linear amplifier: It is electrically connected between terminal A and terminal B. Its inverting input and output terminals are electrically connected to terminal A, and its non-inverting input terminal is electrically connected to terminal B.

[0016] like Figure 3 As shown, the linear amplifier adopts a two-stage folded cascode operational amplifier structure, specifically including the following parts: (1) First stage amplifier: adopts a dual differential input folded common source common gate structure.

[0017] In this configuration, the first transistor M0a, the second transistor M1a, the third transistor M2a, the fourth transistor M3, the fifth transistor M4, the sixth transistor M5, and the seventh transistor M6 form the first pair of folded cascode differential input pairs. The second transistor M1a and the third transistor M2a constitute a PMOS differential pair. The gate of the second transistor M1a is electrically connected to terminal A. The source of the second transistor M1a is electrically connected to the source of the third transistor M2a and the drain of the first transistor M0a. The drain of the second transistor M1a is electrically connected to the source of the seventh transistor M6. The source of the first transistor M0a is electrically connected to the first voltage source VDD. The gate of the first transistor M0a is electrically connected to the first bias voltage source. The first transistor M0a is a tail current source with a bias voltage of Vb0. The gate of the third transistor M2a is electrically connected to terminal B.

[0018] Among them, the first voltage source VDD = 2.8V and the bias voltage Vb0 = 1.8V.

[0019] The fourth transistor M3 and the fifth transistor M4 are the current sources for the common-source common-gate transistor composed of the sixth transistor M5 and the seventh transistor M6. The gates of the seventh transistor M6 and the sixth transistor M5 are both electrically connected to the second bias voltage source, which has a bias voltage of Vb4. The source of the sixth transistor M5 is electrically connected to the drain of the fourth transistor M3. The source of the fourth transistor M3 is grounded. The gate of the fourth transistor M3 is electrically connected to the gate of the fifth transistor M4 and the drain of the sixth transistor M5, respectively. The source of the fifth transistor M4 is grounded. The drain of the fifth transistor M4 is electrically connected to the source of the seventh transistor M6.

[0020] The bias voltage Vb4 mentioned above is 1.6V.

[0021] Another route uses transistors M0b (eighth transistor), M1c (ninth transistor), M2c (tenth transistor), M7 (eleventh transistor), M8 (twelfth transistor), M9 (thirteenth transistor), and M10 (fourteenth transistor) to form a second pair of folded cascode differential inputs. Specifically, the eighth transistor M0b is the tail current source, with its source grounded and its gate electrically connected to the third bias voltage source, whose bias voltage is Vb1. The drain of the eighth transistor M0b is electrically connected to the source of the ninth transistor M1c and the source of the tenth transistor M2c, respectively. The gate of the ninth transistor M1c is electrically connected to terminal A, and the drain of the ninth transistor M1c is electrically connected to the drain of the thirteenth transistor M9 and the source of the eleventh transistor M7, respectively. The gate of the tenth transistor M2c is electrically connected to terminal B, and the drain of the tenth transistor M2c is electrically connected to the drain of the fourteenth transistor M10, respectively. The gates of the eleventh transistor M7 and the twelfth transistor M8, the thirteenth transistor M9 and the fourteenth transistor M10 are all electrically connected to the first voltage source VDD. The gates of the thirteenth transistor M9 and the fourteenth transistor M10 are electrically connected to the third bias voltage source with a bias voltage of Vb2. The gates of the eleventh transistor M7 and the twelfth transistor M8 are electrically connected to the fourth bias voltage source with a bias voltage of Vb3. The drain of the eleventh transistor M7 is electrically connected to the drain of the sixth transistor M5, and the drain of the twelfth transistor M8 is electrically connected to the drain of the seventh transistor M6.

[0022] Among them, the first voltage source VDD=2.8V, the bias voltage Vb1=0.92V, the bias voltage Vb2=1.8V, and the bias voltage Vb3=0.75V.

[0023] The ninth transistor M1c and the tenth transistor M2c form an NMOS differential pair, the eleventh transistor M7 and the twelfth transistor M8 are PMOS common-source and common-gate transistors, and the thirteenth transistor M9 and the fourteenth transistor M10 are the current sources of the common-source and common-gate transistors.

[0024] The outputs of the first pair of folded cascode differential input pairs and the second pair of folded cascode differential input pairs converge at the Vout1 terminal. Specifically, the drain of the twelfth transistor M8 or the drain of the seventh transistor M6 is electrically connected to the Vout1 terminal.

[0025] (2) Second stage amplifier: A common-source amplifier consisting of the fifteenth transistor M12 and the sixteenth transistor M11. The fifteenth transistor M12 is a PMOS transistor and the sixteenth transistor M11 is an NMOS transistor. The Vout1 terminal is electrically connected to the gate of the sixteenth transistor M11. The gate of the sixteenth transistor M11 is electrically connected to the gate of the fifteenth transistor M12. The source of the sixteenth transistor M11 is grounded. The source of the fifteenth transistor M12 is electrically connected to the first voltage source VDD. The drain of the fifteenth transistor M12 is electrically connected to the drain of the sixteenth transistor M11. The drain of the sixteenth transistor M11 is electrically connected to the Vout2 terminal. An RC compensation network is electrically connected between the Vout1 terminal and the Vout2 terminal.

[0026] Specifically, the RC compensation network includes a resistor R and a capacitor C, which are connected in series. One end of the resistor R is electrically connected to the Vout1 terminal, and one end of the capacitor C is electrically connected to the Vout2 terminal.

[0027] Figure 3 The working process of a traditional linear amplifier is as follows: When a voltage difference ΔVin exists between terminals A and B, the two differential input pairs (second transistor M1a / third transistor M2a and ninth transistor M1c / tenth transistor M2c) convert this voltage difference ΔVin into a differential current. This differential current undergoes current amplification and high-impedance conversion via a folded cascode structure (fourth transistor M3 to fourteenth transistor M10), generating the first-stage output voltage at terminal Vout1. Terminal Vout1 is then further amplified by a second-stage cascode amplifier composed of an RC compensation network and sixteenth transistor M11 and fifteenth transistor M12 before being output to terminal Vout2.

[0028] (5) Pull-down bias network: including the thirty-eighth transistor M19, the thirty-ninth transistor M20, the fortieth transistor M21, the forty-first transistor M22, the forty-second transistor M23 and the thirty-ninth transistor M24, all of which are NMOS transistors.

[0029] Specifically, the gate and drain of the thirty-eighth transistor M19 and the gate of the thirty-ninth transistor M20 are electrically connected to the drain of the twenty-fifth transistor M14. The source of the thirty-eighth transistor M19 is electrically connected to the drain of the thirty-ninth transistor M20, and the source of the thirty-ninth transistor M20 is grounded. The gate and drain of the fortieth transistor M21 and the gate of the forty-first transistor M22 are electrically connected to the drain of the twenty-seventh transistor M16. The source of the fortieth transistor M21 is electrically connected to the drain of the forty-first transistor M22, and the source of the forty-first transistor M22 is grounded.

[0030] The gate of transistor M23 (42nd) is electrically connected to the gate of transistor M19 (38th), and the gate of transistor M24 (39th) is electrically connected to the gate of transistor M22 (41st) to obtain a bias voltage. The drain of transistor M23 (42nd) is electrically connected to the drain of transistor M33 (37th), and the drain of transistor M24 (39th) is electrically connected to the source of transistor M23 (42nd). The source of transistor M24 (39th) is grounded. This network, in conjunction with the pull-up current source array, provides a stable current sinking path and DC operating point for the charge pump.

[0031] A linear amplifier is electrically connected between terminals A and B of the charge pump. The negative feedback principle is used to keep the potentials of terminals A and B consistent, thereby reducing the mismatch between the source current I_UP and the sucker current I_DN of the charge pump.

[0032] However, the gain of a traditional linear amplifier is limited by the power consumption budget. With limited current consumption, the transconductance and output impedance of the linear amplifier are both limited, resulting in insufficient gain, usually only around 40dB to 60dB. There is still a non-negligible residual voltage difference between terminals A and B, which leads to the current mismatch not being fully suppressed, resulting in poor robustness. Summary of the Invention

[0033] In view of this, the present invention provides a nonlinear amplifier-assisted charge pump to solve the existing technical problems.

[0034] The technical solution of this invention is: A nonlinear amplifier-assisted charge pump includes a charge pump core circuit having terminals A and B, characterized in that a nonlinear amplifier is electrically connected between terminals A and B; the nonlinear amplifier includes a linear amplifier and a differential input stage and a cross-coupled latch series circuit electrically connected to the input terminal of the first stage amplifier of the linear amplifier. The differential input stage includes a seventeenth transistor M1b, an eighteenth transistor M2b, and a nineteenth transistor MOS. The gate of the seventeenth transistor M1b is electrically connected to terminal A, and the gate of the eighteenth transistor M2b is electrically connected to terminal B. The sources of the seventeenth transistor M1b and the eighteenth transistor M2b are common, and their drains are respectively electrically connected to the two output terminals of the cross-coupled latch. The sources of the seventeenth transistor M1b, the eighteenth transistor M2b, and the drain of the nineteenth transistor MOS are electrically connected. The gate of the nineteenth transistor MOS is electrically connected to a fifth bias voltage source. The drains of the seventeenth transistor M1b and the eighteenth transistor M2b are respectively electrically connected to the cross-coupled latch. Input terminal; the cross-coupled latch includes a twentieth transistor M3a, a twenty-first transistor M4a, a twenty-second transistor M5a, and a twenty-third transistor M6a; the gate and drain of the twenty-second transistor M5a and the drain of the seventeenth transistor M1b are electrically connected; the gate and drain of the twenty-third transistor M6a, the gate of the seventh transistor M6, and the drain of the eighteenth transistor M2b are electrically connected; the drain of the twenty-third transistor M6a is electrically connected to the gate of the twentieth transistor M3a; the drain of the twenty-second transistor M5a is electrically connected to the gate of the twenty-first transistor M4a; and the source of the twentieth transistor M3a and the source of the twenty-first transistor M4a are grounded respectively.

[0035] Furthermore, the core circuit of the charge pump includes a series-connected array of pull-up current sources, a pull-up switch branch, a pull-down switch branch, and a pull-down bias network; terminal A is the common connection terminal of the pull-up switch branch and the pull-down switch branch, and terminal B is the output terminal Vout of the charge pump.

[0036] Furthermore, the pull-up current source array includes a 24th transistor M13, a 25th transistor M14, a 26th transistor M15, a 27th transistor M16, a 28th transistor M17, and a 29th transistor M18, all of which are PMOS transistors. The gate of the 24th transistor M13 is electrically connected to the sixth bias voltage source Vbia1, the gate of the 25th transistor M14 is electrically connected to the seventh bias voltage source Vbia2, the source of the 24th transistor M13 is electrically connected to the first voltage source VDD, the source of the 25th transistor M14 is electrically connected to the drain of the 24th transistor M13, and the gate of the 26th transistor M15 is electrically connected to the drain of the 24th transistor M13. The gate of the twenty-seventh transistor M16 is connected to the sixth bias voltage source Vbia1, the gate of the twenty-seventh transistor M16 is connected to the seventh bias voltage source Vbia2, the source of the twenty-sixth transistor M15 is connected to the first voltage source VDD, the source of the twenty-seventh transistor M16 is connected to the drain of the twenty-sixth transistor M15, the gate of the twenty-eighth transistor M17 is connected to the sixth bias voltage source Vbia1, the gate of the twenty-ninth transistor M18 is connected to the seventh bias voltage source Vbia2, the source of the twenty-eighth transistor M17 is connected to the first voltage source VDD, and the source of the twenty-ninth transistor M18 is connected to the drain of the twenty-eighth transistor M17.

[0037] Furthermore, the pull-up switch branch includes two sets of cascaded complementary switch structures. The first stage of the complementary switch in the pull-up switch branch consists of a thirtieth transistor M25 and a thirty-first transistor M26. The thirtieth transistor M25 is an NMOS transistor, and the thirty-first transistor M26 is a PMOS transistor. The gates of the thirtieth transistor M25 and the thirty-first transistor M26 are electrically connected to the output of the phase discriminator. The drain of the thirtieth transistor M25 and the source of the thirty-first transistor M26 are electrically connected to the output of the pull-up current source array. The source of the thirtieth transistor M25 and the source of the thirty-first transistor M26 are electrically connected to the output of the pull-up current source array. The drain is electrically connected to terminal A; the second-stage complementary switch of the pull-up switch branch consists of transistor M27 (32nd) and transistor M28 (33rd). Transistor M27 is an NMOS transistor, and transistor M28 is a PMOS transistor. The gate of transistor M27 is electrically connected to the gate of transistor M26 (31st), and the gate of transistor M28 is electrically connected to the gate of transistor M25 (30th). The drain of transistor M27 is electrically connected to the output of the pull-up current source array, and the source of transistor M27 is electrically connected to the drain of transistor M28 (33rd) and terminal B.

[0038] Furthermore, the pull-down switch branch includes two sets of cascaded complementary switch structures. The first stage of the complementary switch in the pull-down switch branch consists of a 34th transistor M30 and a 35th transistor M31. The 34th transistor M30 is an NMOS transistor, and the 35th transistor M31 is a PMOS transistor. The gates of the 34th transistor M30 and the 35th transistor M31 are electrically connected to the output of the phase discriminator. The source of the 34th transistor M30 and the drain of the 35th transistor M31 are electrically connected to the input of the pull-down bias network. The drain of the 34th transistor M30 and the source of the 35th transistor M31, and the 31st transistor... The drain of transistor M26 is electrically connected; the second-stage complementary switch of the pull-down switch branch consists of transistors M32 (NMOS) and M33 (PMOS). The gate of transistor M32 is electrically connected to the gate of transistor M31 (M35), the gate of transistor M33 is electrically connected to the gate of transistor M30 (M34), the source of transistor M32 is electrically connected to the drain of transistor M33 (M37), the drain of transistor M32 is electrically connected to the source of transistor M33 (M37), and the drain of transistor M28 is electrically connected to the drain of transistor M28.

[0039] Furthermore, the pull-down bias network includes the thirty-eighth transistor M19, the thirty-ninth transistor M20, the fortieth transistor M21, the forty-first transistor M22, the forty-second transistor M23, and the thirty-ninth transistor M24, all of which are NMOS transistors; Among them, the gate and drain of the thirty-eighth transistor M19 and the gate of the thirty-ninth transistor M20 are electrically connected to the drain of the twenty-fifth transistor M14, the source of the thirty-eighth transistor M19 is electrically connected to the drain of the thirty-ninth transistor M20, and the source of the thirty-ninth transistor M20 is grounded; the gate and drain of the fortieth transistor M21 and the gate of the forty-first transistor M22 are electrically connected to the drain of the twenty-seventh transistor M16, the source of the fortieth transistor M21 is electrically connected to the drain of the forty-first transistor M22, and the source of the forty-first transistor M22 is grounded; The gate of transistor M23 is electrically connected to the gate of transistor M19, and the gate of transistor M24 is electrically connected to the gate of transistor M22, the forty-first transistor. The drain of transistor M23 is electrically connected to the drain of transistor M33, the drain of transistor M24 is electrically connected to the source of transistor M23, and the source of transistor M24 is grounded.

[0040] Furthermore, the first stage amplification structure of the nonlinear amplifier is a dual-path differential input folded common-source cascode structure, and the second stage amplification structure is a common-source amplification structure, with the first stage amplification structure and the second stage amplification structure connected in series.

[0041] Compared with existing technologies, the present invention provides a nonlinear amplifier-assisted charge pump, including a charge pump core circuit with terminals A and B, and a nonlinear amplifier electrically connected between terminals A and B. The nonlinear amplifier includes a linear amplifier and a differential input stage and a cross-coupled latch series circuit electrically connected to the first stage of the linear amplifier. This circuit structure design allows the nonlinear amplifier to be built simply by adding a differential input stage and a cross-coupled latch series circuit to a traditional linear amplifier. The structural implementation only requires adding a small number of transistors, without the need for additional bias branches, digital calibration circuits, or adjustment mechanisms. Under the same bias current conditions, the gain of the linear amplifier is significantly improved, thereby achieving a current mismatch of less than 0.5% across the entire output voltage range, different process angles, and temperatures. The adjustment capability of the potentials of terminals A and B is greatly enhanced without changing the power consumption, resulting in a significant reduction in current mismatch, a smaller mismatch voltage, a wider output range, faster response speed, lower output noise, and excellent robustness. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the device of the present invention.

[0043] Figure 2 This is a schematic diagram of a nonlinear amplifier.

[0044] Figure 3 This is a schematic diagram of a traditional linear amplifier.

[0045] Figure 4 This is a gain comparison chart for linear and nonlinear amplifiers.

[0046] Figure 5 This is a comparison of the mismatch voltages between a nonlinear amplifier and a linear amplifier.

[0047] Figure 6 This is a comparison graph of current mismatch in charge pumps when using nonlinear amplifiers and linear amplifiers.

[0048] Figure 7 This is a comparison chart of the slew rates of nonlinear amplifiers and linear amplifiers.

[0049] Figure 8 This is a comparison diagram of the current noise of the charge pump in this invention and other conventional charge pumps. Detailed Implementation

[0050] This invention provides a nonlinear amplifier-assisted charge pump to solve the above-mentioned problems. In order to enable those skilled in the art to better understand and implement the technical solution of this invention, the technical solution of this invention will be clearly and thoroughly described below with reference to the accompanying drawings.

[0051] Example 1 For the purposes of the following description, the relevant terms and abbreviations are explained below: PLL (Phase-Locked Loop): A phase-locked loop is a feedback control system used for frequency synthesis and clock generation.

[0052] CP (Charge Pump): A circuit module in a phase-locked loop that converts phase difference into current.

[0053] CPPLL (Charge Pump Phase-Locked Loop): Charge pump phase-locked loop.

[0054] Current mismatch: The mismatch between the source current I_UP and the sucker current I_DN in a charge pump is mainly caused by factors such as channel length modulation, charge injection, and switching nonlinearity.

[0055] Reference spurs: Stray components in the output spectrum of a phase-locked loop that deviate from the center frequency, caused by factors such as charge pump current mismatch.

[0056] Static Phase Error: The residual phase difference between the input reference signal and the feedback signal after the phase-locked loop is locked.

[0057] like Figure 1 As shown, this invention proposes a nonlinear amplifier-assisted charge pump. The core idea is to introduce a novel nonlinear amplifier between terminals A and B of the charge pump, replacing... Figure 2 The image shows a traditional linear amplifier. A nonlinear amplifier is a linear amplifier circuit with nonlinear gain characteristics, used to improve the potential equalization capability of terminals A and B in a charge pump.

[0058] like Figure 2 As shown, the nonlinear amplifier-assisted charge pump provided by this invention comprises five parts: a pull-up current source array, a pull-up switch branch, a pull-down switch branch, a nonlinear amplifier, and a pull-down bias network. The electrical connections of each part are as follows: (1) Pull-up current source array, including three sets of PMOS transistor current source pairs: The first group consists of the twenty-fourth transistor M13 and the twenty-fifth transistor M14. Both transistors M13 and M14 are PMOS transistors. The gate of transistor M13 is electrically connected to the sixth bias voltage source Vbia1, and the gate of transistor M14 is electrically connected to the seventh bias voltage source Vbia2. The source of transistor M13 is electrically connected to the first voltage source VDD, and the source of transistor M14 is electrically connected to the drain of transistor M13. The drain of transistor M14 is the first output terminal of the pull-up current source array.

[0059] The second group consists of the twenty-sixth transistor M15 and the twenty-seventh transistor M16. Both transistors M15 and M16 are PMOS transistors. The gate of transistor M15 is electrically connected to the sixth bias voltage source Vbia1, and the gate of transistor M16 is electrically connected to the seventh bias voltage source Vbia2. The source of transistor M15 is electrically connected to the first voltage source VDD, and the source of transistor M16 is electrically connected to the drain of transistor M15. The drain of transistor M16 is the second output terminal of the pull-up current source array.

[0060] The third group consists of the twenty-eighth transistor M17 and the twenty-ninth transistor M18. Both transistors M17 and M18 are PMOS transistors. The gate of transistor M17 is electrically connected to the sixth bias voltage source Vbia1, and the gate of transistor M18 is electrically connected to the seventh bias voltage source Vbia2. The source of transistor M17 is electrically connected to the first voltage source VDD, and the source of transistor M18 is electrically connected to the drain of transistor M17. The drain of transistor M18 is the third output terminal of the pull-up current source array.

[0061] (2) Pull-up switch branch: Controlled by the UP signal and its complementary signal nUp output from the phase discriminator, it is used to direct the pull-up current to the output terminal B (or the output terminal Vout). This branch contains two sets of cascaded complementary switch structures, and the input terminals of the complementary switch structures are used to electrically connect to the output of the phase discriminator:

[0062] The first-stage complementary switch of the pull-up switch branch consists of the thirtieth transistor M25 and the thirty-first transistor M26. The thirtieth transistor M25 is an NMOS transistor, and the thirty-first transistor M26 is a PMOS transistor. The gate of the thirtieth transistor M25 is connected to the nUp signal, and the gate of the thirty-first transistor M26 is connected to the Up signal. The drain of the thirtieth transistor M25, the drain of the twenty-ninth transistor M18, and the source of the thirty-first transistor M26 are interconnected to form terminal Y. The source of the thirtieth transistor M25 and the drain of the thirty-first transistor M26 are interconnected and electrically connected to terminal A.

[0063] The second-stage complementary switch of the pull-up switch branch consists of transistors M27 (NMOS) and M28 (PMOS). The gate of the thirty-second transistor M27 is electrically connected to the gate of the thirty-first transistor M26, the gate of the thirty-third transistor M28 is electrically connected to the gate of the thirtyth transistor M25, the drain of the thirty-second transistor M27 is electrically connected to the drain of the twenty-ninth transistor M18, and the source of the thirty-second transistor M27 is electrically connected to the drain of the thirty-third transistor M28 and terminal B (or output terminal Vout).

[0064] When the Up signal is high and the nUp signal is low, the 30th transistor M25 and the 31st transistor M26 are cut off, while the 32nd transistor M27 and the 33rd transistor M28 are turned on. The pull-up current forms a charging path through the 28th transistor M17 → the 29th transistor M18 → terminal Y → the 32nd transistor M27 → the 33rd transistor M28 → the output terminal Vout.

[0065] (3) Pull-down switch branch: Controlled by the Down signal and its complementary signal nDown output from the phase discriminator, it is used to discharge the charge of terminal B (or output Vout) to ground. This branch also contains two sets of cascaded complementary switch structures, the input of which is used to electrically connect to the output of the phase discriminator:

[0066] The first-stage complementary switch of the pull-down switch branch consists of the thirty-fourth transistor M30 and the thirty-fifth transistor M31. The thirty-fourth transistor M30 is an NMOS transistor, and the thirty-fifth transistor M31 is a PMOS transistor. The gate of the thirty-fourth transistor M30 is connected to the nDown signal, and the gate of the thirty-fifth transistor M31 is connected to the Down signal. The source of the thirty-fourth transistor M30 and the drain of the thirty-fifth transistor M31 are electrically connected to form terminal X. The drain of the thirty-fourth transistor M30, the source of the thirty-fifth transistor M31, and the drain of the thirty-first transistor M26 are electrically connected to terminal A.

[0067] The second-stage complementary switch of the pull-down switch branch consists of the thirty-sixth transistor M32 and the thirty-seventh transistor M33. The thirty-sixth transistor M32 is an NMOS transistor, and the thirty-seventh transistor M33 is a PMOS transistor. The gate of the thirty-sixth transistor M32 is electrically connected to the gate of the thirty-fifth transistor M31 and receives the Down signal. The gate of the thirty-seventh transistor M33 is electrically connected to the gate of the thirty-fourth transistor M30. The source of the thirty-sixth transistor M32 is electrically connected to the drain of the thirty-seventh transistor M33 and is electrically connected to terminal X. The drain of the thirty-sixth transistor M32 and the source of the thirty-seventh transistor M33 are interconnected and electrically connected to terminal B.

[0068] When the Down signal is high and the nDown signal is low, the 34th transistor M30 and the 35th transistor M31 are turned off, while the 36th transistor M32 and the 37th transistor M33 are turned on. The charge at terminal B (or output terminal Vout) forms a discharge path through the 36th transistor M32, the 37th transistor M33 → terminal X → pull-down bias network.

[0069] (0) Nonlinear amplifier AMP1: Electrically connected between terminal A and terminal B, such as Figure 2 As shown, this is an improvement on the linear amplifier technology. A differential input stage and a cross-coupled latch series circuit are added to the first stage of the linear amplifier. The inverting input and output terminals are electrically connected to terminal A, and the non-inverting input terminal is electrically connected to terminal B. The nonlinear amplifier detects the voltage difference between terminals A and B in real time and adjusts the potential balance between terminals A and B through a high-gain negative feedback mechanism.

[0070] The nonlinear amplifier AMP1 in this invention adds a nonlinear gain boost section to the first stage of the linear amplifier. The specific circuit structure is as follows: Figure 2 As shown, it includes the following components: (a) Differential Input Stage: A differential pair consisting of the seventeenth transistor M1b and the eighteenth transistor M2b, where both transistors are NMOS transistors. The gate of the seventeenth transistor M1b is electrically connected to terminal A of the charge pump, and the gate of the eighteenth transistor M2b is electrically connected to terminal B of the charge pump. The differential input stage converts the voltage difference between terminals A and B into a differential current. The sources of the seventeenth transistor M1b and the eighteenth transistor M2b are electrically connected, and the drain of the nineteenth transistor M0c is electrically connected. The gate of the nineteenth transistor M0c is electrically connected to the fifth bias voltage source, whose bias voltage is Vb0, specifically, Vb0 = 1.8V. The source of the nineteenth transistor M0c is electrically connected to the first voltage source VDD.

[0071] (b) Cross-coupled latch: a cross-coupled positive feedback structure consisting of the twentieth transistor M3a, the twenty-first transistor M4a, the twenty-second transistor M5a, and the twenty-third transistor M6a.

[0072] In this system, the twentieth transistor M3a and the twenty-second transistor M5a form one branch of the cross-coupled pair, while the twenty-first transistor M4a and the twenty-third transistor M6a form the other branch. The cross-coupled latch utilizes a positive feedback mechanism to rapidly amplify the tiny differential current output from the differential input stage, thereby achieving extremely high equivalent gain.

[0073] Specifically, the gate of the fourth transistor M3, the gate and drain of the sixth transistor M5, the gate and drain of the twenty-second transistor M5a, and the drain of the seventeenth transistor M1b are electrically connected. The gate of the fifth transistor M4, the gate and drain of the twenty-third transistor M6a, the gate of the seventh transistor M6, and the drain of the eighteenth transistor M2b are electrically connected. The drain of the twenty-third transistor M6a is electrically connected to the gate of the twentieth transistor M3a, the drain of the twenty-second transistor M5a is electrically connected to the gate of the twenty-first transistor M4a, and the source of the twentieth transistor M3a is grounded to the source of the twenty-first transistor M4a.

[0074] In the above manner, the nonlinear circuit can be used to provide bias voltages to the fourth transistor M3, the fifth transistor M4, the sixth transistor M5, and the seventh transistor M6, while the output voltage of the nonlinear part is converted to Vout1 output through the seventh transistor M6 and the fifth transistor M4.

[0075] (5) Pull-down bias network: including the thirty-eighth transistor M19, the thirty-ninth transistor M20, the fortieth transistor M21, the forty-first transistor M22, the forty-second transistor M23 and the thirty-ninth transistor M24, all of which are NMOS transistors.

[0076] Specifically, the gate and drain of the thirty-eighth transistor M19 and the gate of the thirty-ninth transistor M20 are electrically connected to the drain of the twenty-fifth transistor M14. The source of the thirty-eighth transistor M19 is electrically connected to the drain of the thirty-ninth transistor M20, and the source of the thirty-ninth transistor M20 is grounded. The gate and drain of the fortieth transistor M21 and the gate of the forty-first transistor M22 are electrically connected to the drain of the twenty-seventh transistor M16. The source of the fortieth transistor M21 is electrically connected to the drain of the forty-first transistor M22, and the source of the forty-first transistor M22 is grounded.

[0077] The gate of transistor M23 (42nd) is electrically connected to the gate of transistor M19 (38th), and the gate of transistor M24 (39th) is electrically connected to the gate of transistor M22 (41st) to obtain a bias voltage. The drain of transistor M23 (42nd) is electrically connected to the drain of transistor M33 (37th), and the drain of transistor M24 (39th) is electrically connected to the source of transistor M23 (42nd). The source of transistor M24 (39th) is grounded. This network, in conjunction with the pull-up current source array, provides a stable current sinking path and DC operating point for the charge pump.

[0078] The overall working principle of a charge pump is as follows: In a phase-locked loop (PLL) system, the phase discriminator generates Up and Down pulse signals with proportional pulse widths based on the phase difference between the reference clock and the feedback clock. When the reference clock leads the feedback clock, the Up pulse width is greater than the Down pulse width, resulting in a longer conduction time for the pull-up switch branch. This causes the net current I_UP to flow into terminal B, raising the potential of terminal B. At this point, the amplifier detects the differential voltage between A and B and rapidly raises the potential of terminal A through its internal high-gain feedback mechanism, making the potentials of A and B approximately equal.

[0079] Conversely, when the feedback clock leads the reference clock, the Down pulse dominates, the pull-down switch branch dominates the discharge process, the potential at terminal B drops, and the amplifier also adjusts through negative feedback to make the potential at terminal A follow suit. In PLL locked state, the Up pulse width is equal to the Down pulse width. Ideally, I_UP=I_DN, the potentials at terminals A and B are the same, the net output current of the charge pump is zero, and Vout remains stable.

[0080] In actual circuits, device mismatch and switch charge injection effects can cause a small voltage difference between terminals A and B. In this case, the nonlinear amplifier AMP1 in this invention, with its greater gain compared to traditional linear amplifiers, can achieve potential balance between terminals A and B with a smaller static error, thereby significantly reducing the current mismatch between I_UP and I_DN.

[0081] In this invention, such as Figure 2 As shown, the nonlinear amplifier is electrically connected between terminal A and terminal B, and its operation is as follows: (1) When a voltage difference ΔVin appears between terminal A and terminal B, the differential pair (seventeenth transistor M1b and eighteenth transistor M2b) converts the voltage difference into a differential current ΔI; (2) The differential current ΔI drives the cross-coupled latch (the nineteenth transistor M3a, the twentieth transistor M4a, the twenty-first transistor M5a, and the twenty-second transistor M6a). The cross-coupled latch rapidly amplifies the differential current ΔI through a positive feedback mechanism, generating a strong feedback signal. (3) A strong feedback signal is applied to terminals A and B, forcing their potentials to quickly become consistent, thereby effectively eliminating the current mismatch between I_UP and I_DN.

[0082] With Figure 2 Compared to the conventional linear amplifier shown, this invention introduces a positive feedback path with a cross-coupled latch structure in the first stage of the linear amplifier. Under the same bias current, the gain is significantly improved. The theoretical principle behind this gain improvement can be derived as follows: Output resistance of cross-coupled latch It can be represented as: , in, It is the output resistance of the cross-coupled latch. The transconductance of the nineteenth transistor M3a is therefore the output impedance of the entire nonlinear circuit. It can be represented as: , in, The total equivalent small-signal resistance of all MOSFETs in the cross-coupled latch is... The output impedance of the entire nonlinear circuit is given. This is the transconductance of the nineteenth transistor, M3a.

[0083] At this point, the gain of the nonlinear circuit... It can be represented as: , in, For the transconductance of the seventeenth transistor M1b, The gain of the nonlinear circuit. This is the total equivalent small-signal resistance of all MOSFETs in this section. This is the transconductance of the nineteenth transistor, M3a.

[0084] If in the design The value of the transconductance of the second transistor M1a If they are the same, then the gain from the differential pair input from the seventeenth transistor M1b and the eighteenth transistor M2b to Vout1 is... It can be represented as: , in, It is the total transconductance of the seventh transistor M6 and the fifth transistor M4. The output resistance of the first-stage amplifier. It is the gain from the input differential pair of the seventeenth transistor M1b and the eighteenth transistor M2b to Vout1. For the transconductance of the seventeenth transistor M1b, This is the total equivalent small-signal resistance of all MOSFETs in this section. This is the transconductance of the nineteenth transistor, M3a.

[0085] Therefore, the gain of the first stage of this nonlinear amplifier It can be represented as: , in, and They are respectively Figure 2 The contribution of the two differential input pairs (second transistor M1a / third transistor M2a and ninth transistor M1c / tenth transistor M2c) to the gain. The transconductance of the ninth transistor M1c It is the gain of the first stage of the nonlinear amplifier. It is the total transconductance of the seventh transistor M6 and the fifth transistor M4. The output resistance of the first-stage amplifier. It is the gain from the input differential pair of the seventeenth transistor M1b and the eighteenth transistor M2b to Vout1. For the transconductance of the seventeenth transistor M1b, This is the total equivalent small-signal resistance of all MOSFETs in this section. This is the transconductance of the nineteenth transistor, M3a. Under the same bias current, Figure 3 The first stage gain of a conventional linear amplifier Only for:

[0086] in, and They are respectively Figure 1 The contribution of the two differential input pairs (second transistor M1a / third transistor M2a and ninth transistor M1c / tenth transistor M2c) to the gain. It is the first-stage gain of a traditional linear amplifier. The transconductance of the ninth transistor M1c This is the output resistance of the first-stage amplifier. It can be seen that as long as... , Figure 2 The nonlinear amplifier in the middle will be able to obtain higher gain, and this condition can be easily improved by increasing... and The value is achieved by [the method described in the original text]. Therefore, the nonlinear amplifier has a higher gain than the traditional linear amplifier.

[0087] like Figure 4 The graph showing the gain comparison between linear and nonlinear amplifiers illustrates that, under the same bias current, the gain of the nonlinear amplifier (green curve) is higher than that of the conventional linear amplifier. Figure 4 The red curve in the figure shows an improvement of approximately 40 dB, which significantly enhances the potential regulation capability of terminals A and B without changing the power consumption. Therefore, it can more effectively suppress the potential error between terminals A and B, and fundamentally improve the current matching performance.

[0088] In addition, such as Figure 5 The diagram showing the mismatch voltage comparison between the nonlinear amplifier and the linear amplifier, with the green curve representing the effective output voltage, illustrates that the nonlinear amplifier's mismatch voltage is significantly lower than that of the linear amplifier across its entire operating range, and its effective output voltage range is wider. This is beneficial for the phase-locked loop (PLL) to operate stably over a wider frequency range. Figure 6 The diagram shows a comparison of the charge pump current mismatch when using a nonlinear amplifier and a linear amplifier. After using the nonlinear amplifier, the charge pump's I_UP and I_DN currents become mismatched, as shown below. Figure 6 The blue curve in the diagram shows that the linear amplifier scheme is significantly better across the entire output voltage range.

[0089] As shown in Table 1 below, under different process angles such as SS (slow NMOS and slow PMOS), TT (typical), and FF (fast NMOS and fast PMOS) and different temperature conditions such as -40℃, 25℃, and 125℃, the average current error of the charge pump is less than 0.5%, demonstrating the excellent robustness of the nonlinear amplifier in mitigating the current mismatch of the charge pump.

[0090] Table 1. Current error of the charge pump assisted by the nonlinear amplifier under different process angles and temperatures. like Figure 7 The graph showing the slew rate comparison between nonlinear and linear amplifiers is illustrated. The slew rate of the nonlinear amplifier is represented by the green curve, which is higher than that of the linear amplifier. This results in a faster response to dynamic current changes, which helps improve the lock-in time and transient performance of the phase-locked loop.

[0091] like Figure 8 The diagram showing the current noise comparison between the charge pump of the present invention and other conventional charge pumps demonstrates that, due to the effective suppression of current mismatch, the output current noise of the charge pump using a nonlinear amplifier is significantly lower than that of the conventional scheme, which is beneficial for reducing the in-band phase noise of the phase-locked loop.

[0092] In practical implementation, the electrical connection between the nonlinear amplifier and the charge pump core circuit is as follows: Figure 1 As shown. The charge pump includes a pull-up current source and a pull-down current source controlled by a switching transistor. The input terminals of the nonlinear amplifier are electrically connected to terminal A (pull-up branch output terminal) and terminal B (pull-down branch output terminal), respectively. The output of the nonlinear amplifier provides a feedback control signal.

[0093] When I_UP and I_DN show an imbalance trend due to device mismatch, the nonlinear amplifier utilizes its high-gain characteristics to quickly detect and correct the voltage difference between terminals A and B, maintaining a high degree of current matching between the two branches. This solution eliminates the need for additional digital calibration circuitry or duplicated bias branches, achieving a significant performance improvement while maintaining circuit simplicity and low power consumption.

[0094] Compared with existing technologies, the present invention provides a nonlinear amplifier-assisted charge pump, including a charge pump core circuit with terminals A and B, and a nonlinear amplifier electrically connected between terminals A and B. The nonlinear amplifier includes a linear amplifier and a differential input stage and a cross-coupled latch series circuit electrically connected to the first stage of the linear amplifier. This circuit structure design allows the nonlinear amplifier to be built simply by adding a differential input stage and a cross-coupled latch series circuit to a traditional linear amplifier. The structural implementation only requires adding a small number of transistors, without the need for additional bias branches, digital calibration circuits, or adjustment mechanisms. Under the same bias current conditions, the gain of the linear amplifier is significantly improved, thereby achieving a current mismatch of less than 0.5% across the entire output voltage range, different process angles, and temperatures. The adjustment capability of the potentials of terminals A and B is greatly enhanced without changing the power consumption, resulting in a significant reduction in current mismatch, a smaller mismatch voltage, a wider output range, faster response speed, lower output noise, and excellent robustness.

[0095] The above-disclosed embodiments are merely preferred embodiments of the present invention. However, the embodiments of the present invention are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A nonlinear amplifier-assisted charge pump, comprising a charge pump core circuit, the charge pump core circuit having terminal A and terminal B, characterized in that, A nonlinear amplifier is electrically connected between terminal A and terminal B; the nonlinear amplifier includes a linear amplifier and a differential input stage and a cross-coupled latch series circuit electrically connected to the input terminal of the first stage amplifier of the linear amplifier. The differential input stage includes a seventeenth transistor M1b, an eighteenth transistor M2b, and a nineteenth transistor MOS. The gate of the seventeenth transistor M1b is electrically connected to terminal A, and the gate of the eighteenth transistor M2b is electrically connected to terminal B. The sources of the seventeenth transistor M1b and the eighteenth transistor M2b are common, and their drains are respectively electrically connected to the two output terminals of the cross-coupled latch. The sources of the seventeenth transistor M1b, the eighteenth transistor M2b, and the drain of the nineteenth transistor MOS are electrically connected. The gate of the nineteenth transistor MOS is electrically connected to a fifth bias voltage source. The drains of the seventeenth transistor M1b and the eighteenth transistor M2b are respectively electrically connected to the cross-coupled latch. Input terminal; the cross-coupled latch includes a twentieth transistor M3a, a twenty-first transistor M4a, a twenty-second transistor M5a, and a twenty-third transistor M6a; the gate and drain of the twenty-second transistor M5a and the drain of the seventeenth transistor M1b are electrically connected; the gate and drain of the twenty-third transistor M6a, the gate of the seventh transistor M6, and the drain of the eighteenth transistor M2b are electrically connected; the drain of the twenty-third transistor M6a is electrically connected to the gate of the twentieth transistor M3a; the drain of the twenty-second transistor M5a is electrically connected to the gate of the twenty-first transistor M4a; and the source of the twentieth transistor M3a and the source of the twenty-first transistor M4a are grounded respectively.

2. The nonlinear amplifier-assisted charge pump according to claim 1, characterized in that, The core circuit of the charge pump includes a series-connected array of pull-up current sources, a pull-up switch branch, a pull-down switch branch, and a pull-down bias network; terminal A is the common connection terminal of the pull-up switch branch and the pull-down switch branch, and terminal B is the output terminal Vout of the charge pump.

3. The nonlinear amplifier-assisted charge pump according to claim 2, characterized in that, The pull-up current source array includes transistors M13 (24th), M14 (25th), M15 (26th), M16 (27th), M17 (28th), and M18 (29th), all of which are PMOS transistors. The gate of transistor M13 is electrically connected to the sixth bias voltage source Vbia1, the gate of transistor M14 is electrically connected to the seventh bias voltage source Vbia2, the source of transistor M13 is electrically connected to the first voltage source VDD, the source of transistor M14 is electrically connected to the drain of transistor M13, and the gate of transistor M15 is electrically connected to... The gate of the twenty-seventh transistor M16 is connected to the sixth bias voltage source Vbia1, the gate of the twenty-seventh transistor M16 is connected to the seventh bias voltage source Vbia2, the source of the twenty-sixth transistor M15 is connected to the first voltage source VDD, the source of the twenty-seventh transistor M16 is connected to the drain of the twenty-sixth transistor M15, the gate of the twenty-eighth transistor M17 is connected to the sixth bias voltage source Vbia1, the gate of the twenty-ninth transistor M18 is connected to the seventh bias voltage source Vbia2, the source of the twenty-eighth transistor M17 is connected to the first voltage source VDD, and the source of the twenty-ninth transistor M18 is connected to the drain of the twenty-eighth transistor M17.

4. The nonlinear amplifier-assisted charge pump according to claim 3, characterized in that, The pull-up switch branch includes two sets of cascaded complementary switch structures. The first stage of the complementary switch in the pull-up switch branch consists of a 30th transistor M25 and a 31st transistor M26. The 30th transistor M25 is an NMOS transistor, and the 31st transistor M26 is a PMOS transistor. The gates of the 30th transistor M25 and the 31st transistor M26 are electrically connected to the output of the phase discriminator. The drain of the 30th transistor M25 and the source of the 31st transistor M26 are electrically connected to the output of the pull-up current source array. The source of the 30th transistor M25 and the drain of the 31st transistor M26 are also electrically connected. Electrically connected to terminal A; the second-stage complementary switch of the pull-up switch branch consists of the thirty-second transistor M27 and the thirty-third transistor M28. The thirty-second transistor M27 is an NMOS transistor, and the thirty-third transistor M28 is a PMOS transistor. The gate of the thirty-second transistor M27 is electrically connected to the gate of the thirty-first transistor M26, the gate of the thirty-third transistor M28 is electrically connected to the gate of the thirtieth transistor M25, the drain of the thirty-second transistor M27 is electrically connected to the output of the pull-up current source array, and the source of the thirty-second transistor M27 is electrically connected to the drain of the thirty-third transistor M28 and terminal B.

5. The nonlinear amplifier-assisted charge pump according to claim 4, characterized in that, The pull-down switch branch includes two sets of cascaded complementary switch structures. The first stage of the complementary switch in the pull-down switch branch consists of the 34th transistor M30 and the 35th transistor M31. The 34th transistor M30 is an NMOS transistor, and the 35th transistor M31 is a PMOS transistor. The gates of the 34th transistor M30 and the 35th transistor M31 are electrically connected to the output of the phase discriminator. The source of the 34th transistor M30 and the drain of the 35th transistor M31 are electrically connected to the input of the pull-down bias network. The drain of the 34th transistor M30 and the source of the 35th transistor M31, and the 31st transistor M2... The drain of transistor 6 is electrically connected; the second-stage complementary switch of the pull-down switch branch consists of transistors M32 (NMOS) and M33 (PMOS). The gate of transistor M32 is electrically connected to the gate of transistor M31 (M35), the gate of transistor M33 is electrically connected to the gate of transistor M30 (M34), the source of transistor M32 is electrically connected to the drain of transistor M33 (M37), and the drain of transistor M32 is electrically connected to the source of transistor M33 (M38).

6. The nonlinear amplifier-assisted charge pump according to claim 2, characterized in that, The pull-down bias network includes transistors M19 (38th), M20 (39th), M21 (40th), M22 (41st), M23 (42nd), and M24 (39th), all of which are NMOS transistors. Among them, the gate and drain of the thirty-eighth transistor M19 and the gate of the thirty-ninth transistor M20 are electrically connected to the drain of the twenty-fifth transistor M14, the source of the thirty-eighth transistor M19 is electrically connected to the drain of the thirty-ninth transistor M20, and the source of the thirty-ninth transistor M20 is grounded; the gate and drain of the fortieth transistor M21 and the gate of the forty-first transistor M22 are electrically connected to the drain of the twenty-seventh transistor M16, the source of the fortieth transistor M21 is electrically connected to the drain of the forty-first transistor M22, and the source of the forty-first transistor M22 is grounded; The gate of transistor M23 is electrically connected to the gate of transistor M19, and the gate of transistor M24 is electrically connected to the gate of transistor M22, the forty-first transistor. The drain of transistor M23 is electrically connected to the drain of transistor M33, the drain of transistor M24 is electrically connected to the source of transistor M23, and the source of transistor M24 is grounded.

7. The nonlinear amplifier-assisted charge pump according to claim 2, characterized in that, The first stage amplification structure of the nonlinear amplifier is a dual-path differential input folded common-source cascode structure, and the second stage amplification structure is a common-source amplification structure. The first stage amplification structure and the second stage amplification structure are connected in series.

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