A load dynamic response enhancement circuit

Abstract

This invention discloses a load dynamic response enhancement circuit, comprising an error amplifier EA, a threshold detection module, an output control module, and a resistor R. C Capacitor C C Along with capacitor C1, the threshold detection module detects the output voltage VOUT, determining the threshold voltage of the dynamic enhancement circuit and acting as a switch for the circuit's operation. The output control module processes the current Ieao output by EA to charge and discharge the compensation capacitor. This invention improves the circuit's dynamic load response performance. During normal operation, the threshold detection voltage output is zero, not affecting the normal operating point of Vc.

Description

Technical Field

[0001] This invention relates to an enhancement circuit, and more particularly to a load dynamic response enhancement circuit, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Since the advent of switching power supplies, load dynamic response, as one of the most important parameters, has always received considerable attention. On the other hand, with the increasing prevalence of portable devices, the performance requirements for these devices are also rising, leading to increasingly stringent performance demands on switching power supplies. Firstly, the battery life of portable devices requires switching power supplies to consume as little power as possible under extremely light load conditions. Secondly, based on the performance requirements of portable devices, the output voltage fluctuation of the switching power supply should be as small as possible when switching between standby and heavy load modes.

[0003] Taking a buck switching power supply as an example, typical voltage or current control modes include: Figure 8 As shown. If the slope signal (Slope1) comes from the sampling signal of the inductor current, it is current control mode. Otherwise, it is voltage control mode. Regardless of whether it is current control mode or voltage control mode, in this system, due to the presence of operational amplifier EA, when the load transients, the output voltage Vc of EA cannot quickly reflect the change in output voltage VOUT, thus causing the dynamic response performance of the output load to fail to meet expectations. To improve this problem, a constant on-time control mode switching power supply was developed, such as... Figure 9 As shown in the diagram. In this architecture, the slower operational amplifier is replaced with a faster comparator, allowing changes in the output voltage to be quickly reflected in the loop's control response. However, the drawback of this architecture is the relatively poor accuracy of the output voltage. Further development... Figure 10 The architecture shown is as follows. In this architecture, the slope signal Slope2 can be selected from different sources: such as the output voltage or a slope signal synchronized with the switching cycle. If Slope2 is derived from a signal proportional to the output ripple voltage, although the load dynamic response is improved to some extent, the load dynamic response will still be limited by the Vc voltage. Furthermore, both loops in this control method are voltage control loops, which are not suitable for applications requiring current loops. Therefore, a more universal method is needed to improve the load dynamic response capability of switching power supplies with different control modes. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a load dynamic response enhancement circuit to improve the output dynamic response performance.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A load dynamic response enhancement circuit includes an error amplifier EA, a threshold detection module, an output control module, and a resistor R. C Capacitor C C With capacitor C1, the non-inverting input of error amplifier EA is connected to the reference voltage Vref, the inverting input of error amplifier EA is connected to the input of the threshold detection module and connected to the voltage divider signal Vfb, and the voltage output of error amplifier EA is connected to resistor R. C One end of capacitor C1, one end of capacitor C1, and the inverting input of comparator COMP are connected to generate signal V. C The current output terminal of the error amplifier EA is connected to the current input terminal of the output control module, the output terminal of the threshold detection module is connected to the voltage input terminal of the output control module, and the output terminal of the output control module is connected to the resistor R. C The other end and capacitor C C One end of capacitor C1 is connected to the other end of capacitor C. C The other end is grounded.

[0007] Furthermore, the error amplifier EA includes PMOS transistors MP0-MP10, NMOS transistors NM0-NM10, resistors R3 and R4. The sources of PMOS transistors MP0-MP6, PMOS transistor MP9, and PMOS transistor MP10 are connected to the power supply VCC. The gate of PMOS transistor MP0 is connected to the drain of PMOS transistor MP0, the drain of NMOS transistor NM1, the gate of PMOS transistor MP1, and the gate of PMOS transistor MP2. The gate of PMOS transistor MP3 is connected to the drain of PMOS transistor MP3 and the drain of NMOS transistor MN3. The gates of PMOS transistors MP4, MP5, and MP6 are connected. The drain of PMOS transistor MP1 is connected to one end of resistor R3 and one end of resistor R4. The other end of resistor R3 is connected to the source of PMOS transistor MP7, and the other end of resistor R4 is connected to the source of PMOS transistor MP8. The gate of PMOS transistor MP7 is connected to signal Vn, and the gate of PMOS transistor MP8 is connected to signal Vp. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN4, the gate of NMOS transistor MN4, and the gate of NMOS transistor MN3. The gate connections are as follows: the drain of PMOS transistor MP8 is connected to the drain of NMOS transistors MN5, MN5, MN6, MN7, and MN8; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN6 and connected to signal Vc; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistors MN7, MN2, MP9, MP9, and MP10; and the gate of PMOS transistor M... The drain of P10 generates current Ieao2. The drain of PMOS transistor MP6 is connected to the drain of NMOS transistors MN8, MN2, and MN9, as well as the gate of NMOS transistor MN9 and the gate of NMOS transistor MN10. The drain of NMOS transistor MN10 generates current Ieao1. The drain of NMOS transistor NM0 is connected to the gate of NMOS transistor NM0, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2, and is connected to the bias current Ibias. The sources of NMOS transistors NM0 to NM10 are grounded.

[0008] Furthermore, the threshold detection module includes comparator CMP1, comparator CMP2, inverter INV1, inverter INV2, AND gate AND1, AND gate AND2, monostable multivibrator oneshot1, monostable multivibrator oneshot2, falling edge delay module falling_edge delay1, and falling edge delay module falling_edge. The circuit consists of delay2, inverters INV3 and INV4. The non-inverting input of comparator CMP1 is connected to the reference voltage Vref1. The inverting inputs of comparator CMP1 and CMP2 are connected to the voltage divider signal Vfb. The inverting input of comparator CMP2 is connected to the reference voltage Vref2. The output of comparator CMP1 is connected to the first input of AND gate AND1 and the input of inverter INV1. The output of comparator CMP2 is connected to the third input of AND gate AND2 and the input of inverter INV2. The output of inverter INV1 is connected to the second input of AND gate AND2. The output of inverter INV2 is connected to the second input of AND gate AND2. The output of AND gate AND1 is connected to the input of the monostable multivibrator oneshot1 and the input of the falling edge delay module falling_edge delay1. The output of monostable multivibrator oneshot1 generates the signal Vo_low. The falling edge delay module falling_edge... The output of delay1 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the first input of AND gate AND2. The output of AND gate AND2 is connected to the input of monostable circuit oneshot2 and the input of falling edge delay module falling_edge delay2. The output of monostable circuit oneshot2 generates signal Vo_high. The output of falling edge delay module falling_edge delay2 is connected to the input of inverter INV4. The output of inverter INV4 is connected to the third input of AND gate AND1.

[0009] Furthermore, the output control module includes PMOS transistors MP11-MP19, NMOS transistors MN11-MN19, and switch S0. The sources of PMOS transistors MP11-MP15 are connected to the power supply VCC. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP11, the gate of PMOS transistor MP12, the gate of PMOS transistor MP13, the gate of PMOS transistor MP14, and the gate of PMOS transistor MP15, and is connected to a current Ieao1. The drain of PMOS transistor MP12 is connected to the source of PMOS transistor MP16. The drain of MP13 is connected to the source of PMOS transistor MP17; the drain of PMOS transistor MP14 is connected to the source of PMOS transistor MP18; the drain of PMOS transistor MP15 is connected to the source of PMOS transistor MP19; the gate connection signal of PMOS transistor MP16 is GP5; the gate connection signal of PMOS transistor MP17 is GP6; the gate connection signal of PMOS transistor MP18 is GP7; the gate connection signal of PMOS transistor MP19 is GP8; and the drain of PMOS transistor MP16 is connected to the drains of PMOS transistors MP17 and MP18. The drains of PMOS transistor MP19, NMOS transistors MN16, MN17, and MN18, and the drain of NMOS transistor MN19 are connected to one end of switch S0. The other end of switch S0 generates a current Iout. The gate connection signal for NMOS transistor MN16 is GN5, for NMOS transistor MN17 it is GN6, for NMOS transistor MN18 it is GN7, and for NMOS transistor MN19 it is GN8. The source of NMOS transistor MN16 is connected to the drain of NMOS transistor MN12. The source of NMOS transistor MN17 is connected to the drain of NMOS transistor MN13, the source of NMOS transistor MN18 is connected to the drain of NMOS transistor MN14, the source of NMOS transistor MN19 is connected to the drain of NMOS transistor MN15, and the drain of NMOS transistor MN11 is connected to the gate of NMOS transistor MN11, the gate of NMOS transistor MN12, the gate of NMOS transistor MN13, the gate of NMOS transistor MN14, and the gate of NMOS transistor MN15, with a current Ieao2 connected. The sources of NMOS transistors MN11 to MN15 are grounded.

[0010] Furthermore, the duration of the low level of signals GP5, GP6, GP7 and GP8 gradually increases.

[0011] Furthermore, the duration of the high level of signals GN5, GN6, GN7 and GN8 gradually increases.

[0012] Furthermore, the non-inverting input of the comparator COMP is connected to the ramp signal Slope1, and the output of the comparator COMP is connected to the logic driver module LOGIC&DRIVER.

[0013] Furthermore, the voltage divider signal Vfb is generated by a voltage divider circuit, which includes resistors R1 and R2. One end of resistor R1 is connected to the output voltage VOUT, and the other end of resistor R1 is connected to one end of resistor R2 to generate the voltage divider signal Vfb. The other end of resistor R2 is grounded.

[0014] Compared with the prior art, the present invention has the following advantages and effects: The load dynamic response enhancement circuit proposed in the present invention introduces a fast charging and discharging circuit for the compensation capacitor Cc, so that the Vc voltage has a faster response when the output load transient jump occurs, thereby improving the load dynamic response performance of the circuit. During normal operation, the threshold detection voltage output is zero, so it will not affect the normal operating point of Vc. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a load dynamic response enhancement circuit according to the present invention.

[0016] Figure 2 This is the circuit diagram of the error amplifier EA of the present invention.

[0017] Figure 3 This is a circuit diagram of the threshold detection module of the present invention.

[0018] Figure 4 This is a circuit diagram of the output control module of the present invention.

[0019] Figure 5 This is a schematic diagram of the control signals of the output control module of the present invention.

[0020] Figure 6 This is a flowchart of a load dynamic response enhancement circuit according to the present invention.

[0021] Figure 7 This is a simulation diagram illustrating the enhancement effect of a load dynamic response enhancement circuit according to the present invention.

[0022] Figure 8 This is a diagram of the voltage / current control mode switching power supply architecture of existing technology.

[0023] Figure 9 This is a diagram of the architecture of a constant on-time control mode switching power supply in existing technology.

[0024] Figure 10 This is an improved constant on-time control mode switching power supply architecture diagram based on existing technology. Detailed Implementation

[0025] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0026] like Figure 1 As shown, a load dynamic response enhancement circuit of the present invention includes an error amplifier EA, a threshold detection module, an output control module, and a resistor R. C Capacitor C C With capacitor C1, the non-inverting input of error amplifier EA is connected to the reference voltage Vref, the inverting input of error amplifier EA is connected to the input of the threshold detection module and connected to the voltage divider signal Vfb, and the voltage output of error amplifier EA is connected to resistor R. C One end of capacitor C1, one end of capacitor C1, and the inverting input of comparator COMP are connected to generate signal V. C The current output terminal of the error amplifier EA is connected to the current input terminal of the output control module, the output terminal of the threshold detection module is connected to the voltage input terminal of the output control module, and the output terminal of the output control module is connected to the resistor R. C The other end and capacitor C C One end of capacitor C1 is connected to the other end of capacitor C. C The other end is grounded.

[0027] like Figure 2As shown, the error amplifier EA includes PMOS transistors MP0-MP10, NMOS transistors NM0-NM10, resistors R3 and R4. The sources of PMOS transistors MP0-MP6, MP9, and MP10 are connected to the power supply VCC. The gate of PMOS transistor MP0 is connected to the drain of PMOS transistor MP0, the drain of NMOS transistor NM1, the gate of PMOS transistor MP1, and the gate of PMOS transistor MP2. The gate of PMOS transistor MP3 is connected to the drain of PMOS transistor MP3, the drain of NMOS transistor MN3, and PMO... The gates of S-channel transistor MP4, PMOS transistors MP5 and MP6 are connected. The drain of PMOS transistor MP1 is connected to one end of resistor R3 and one end of resistor R4. The other end of resistor R3 is connected to the source of PMOS transistor MP7. The other end of resistor R4 is connected to the source of PMOS transistor MP8. The gate of PMOS transistor MP7 is connected to signal Vn, and the gate of PMOS transistor MP8 is connected to signal Vp. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN4, the gate of NMOS transistor MN4, and the gate of NMOS transistor MN3. The drain of PMOS transistor MP8 is connected to the drain, gate, MN5, gate, MN6, gate, and gate of NMOS transistors MN7 and MN8. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN6 and connected to signal Vc. The drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN7, the drain of PMOS transistor MP2, the drain of PMOS transistor MP9, the gate of PMOS transistor MP9, and the gate of PMOS transistor MP10. The drain of transistor 10 generates current Ieao2. The drain of PMOS transistor MP6 is connected to the drain of NMOS transistors MN8, MN2, and MN9, as well as the gate of NMOS transistor MN9 and the gate of NMOS transistor MN10. The drain of NMOS transistor MN10 generates current Ieao1. The drain of NMOS transistor NM0 is connected to the gate of NMOS transistor NM0, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2, and is connected to the bias current Ibias. The sources of NMOS transistors NM0 to NM10 are grounded.

[0028] The error amplifier EA works as follows: When the output load changes abruptly from large to small, the output voltage is instantaneously boosted, so Vfb will be higher than Vref in the transient state. At this time, the current flowing through MN6 will be greater than MP4, the current through MN7 will be greater than MP5, and the current through MN8 will be greater than MP6. When this current difference exceeds a certain value, MP9 and MP10 will generate a current Ieao2 proportional to this current difference. Similarly, when the output load changes abruptly from small to large, the output voltage drops abruptly, so Vfb will be lower than Vref in the transient state. At this time, the current flowing through MP4 will be greater than MN6, the current through MP5 will be greater than MN7, and the current through MP6 will be greater than MN8. When this current difference exceeds a certain value, MN9 and MN10 will generate a current Ieao1 proportional to this current difference. When the system is operating normally, there is a certain ripple voltage on the Vfb voltage. Therefore, the current difference between MP4 and MN6, the current difference between MP5 and MN7, and the current difference between MP6 and MN8 are not always equal to zero. However, the absolute value of the current difference is less than the absolute value of the currents of MP2 and MN2. Therefore, Ieao1 and Ieao2 are also approximately equal to zero.

[0029] like Figure 3As shown, the threshold detection module includes comparator CMP1, comparator CMP2, inverter INV1, inverter INV2, AND gate AND1, AND gate AND2, monostable multivibrator oneshot1, monostable multivibrator oneshot2, falling edge delay module falling_edge delay1, and falling edge delay module falling_edge. The circuit consists of delay2, inverters INV3 and INV4. The non-inverting input of comparator CMP1 is connected to the reference voltage Vref1. The inverting inputs of comparator CMP1 and CMP2 are connected to the voltage divider signal Vfb. The inverting input of comparator CMP2 is connected to the reference voltage Vref2. The output of comparator CMP1 is connected to the first input of AND gate AND1 and the input of inverter INV1. The output of comparator CMP2 is connected to the third input of AND gate AND2 and the input of inverter INV2. The output of inverter INV1 is connected to the second input of AND gate AND2. The output of inverter INV2 is connected to the second input of AND gate AND2. The output of AND gate AND1 is connected to the input of the monostable multivibrator oneshot1 and the input of the falling edge delay module falling_edge delay1. The output of monostable multivibrator oneshot1 generates the signal Vo_low. The falling edge delay module falling_edge... The output of delay1 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the first input of AND gate AND2. The output of AND gate AND2 is connected to the input of monostable circuit oneshot2 and the input of falling edge delay module falling_edge delay2. The output of monostable circuit oneshot2 generates signal Vo_high. The output of falling edge delay module falling_edge delay2 is connected to the input of inverter INV4. The output of inverter INV4 is connected to the third input of AND gate AND1.

[0030] The threshold detection module works as follows: When the output load changes abruptly from large to small, the output voltage is momentarily boosted. When the output voltage exceeds a certain threshold voltage, Vfb will be greater than Vref2 (Vref2>vref1). Therefore, the threshold detection module's output Vo_high will output a high-level signal with a fixed pulse width. Similarly, when the output load changes abruptly from small to large, the output voltage drops momentarily. When the output voltage drops to a certain threshold voltage, Vfb will be less than Vref1. Therefore, the threshold detection module's output Vo_low will output a high-level signal with a fixed pulse width. When the system is operating normally, the output voltage will have a certain ripple voltage, and therefore Vfb will also have a certain ripple voltage. Under this ripple voltage, the voltage range of Vfb remains between Vref1 and Vref2, and therefore the Vo_high and Vo_low signals will not be triggered.

[0031] like Figure 4As shown, the output control module includes PMOS transistors MP11-MP19, NMOS transistors MN11-MN19, and switch S0. The sources of PMOS transistors MP11-MP15 are connected to the power supply VCC. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP11, the gate of PMOS transistor MP12, the gate of PMOS transistor MP13, the gate of PMOS transistor MP14, and the gate of PMOS transistor MP15, and is connected to the current Ieao1. The drain of PMOS transistor MP12 is connected to the source of PMOS transistor MP16. PMOS transistor MP1... The drain of transistor 3 is connected to the source of PMOS transistor MP17; the drain of PMOS transistor MP14 is connected to the source of PMOS transistor MP18; the drain of PMOS transistor MP15 is connected to the source of PMOS transistor MP19; the gate of PMOS transistor MP16 is connected to signal GP5; the gate of PMOS transistor MP17 is connected to signal GP6; the gate of PMOS transistor MP18 is connected to signal GP7; the gate of PMOS transistor MP19 is connected to signal GP8; and the drain of PMOS transistor MP16 is connected to the drain of PMOS transistor MP17, the drain of PMOS transistor MP18, and P... The drains of MOSFET MP19, NMOS transistors MN16, MN17, MN18, and MN19 are connected to one end of switch S0. The other end of switch S0 generates a current Iout. The gate of NMOS transistor MN16 is connected to signal GN5, the gate of NMOS transistor MN17 to signal GN6, the gate of NMOS transistor MN18 to signal GN7, and the gate of NMOS transistor MN19 to signal GN8. The source of NMOS transistor MN16 is connected to the drain of NMOS transistor MN12. The source of NMOS transistor MN17 is connected to the drain of NMOS transistor MN13, the source of NMOS transistor MN18 is connected to the drain of NMOS transistor MN14, the source of NMOS transistor MN19 is connected to the drain of NMOS transistor MN15, and the drain of NMOS transistor MN11 is connected to the gates of NMOS transistors MN11, MN12, MN13, MN14, and MN15, with a current Ieao2 connected. The sources of NMOS transistors MN11 to MN15 are grounded.

[0032] The output control module works as follows: its control signal originates from the threshold detection module. The timing relationship of the relevant signals is as follows: Figure 5As shown. When the output voltage increases instantaneously, Ieao1 is zero, and Ieao2 is not zero. The signal Vo_high outputs a valid pulse width, thereby triggering signals GN5-GN8 to become active, and the Iout current exhibits a current-pull behavior. Similarly, when the output voltage decreases instantaneously, Ieao1 is not zero, and Ieao2 is zero. The signal Vo_low outputs a valid pulse width, thereby triggering signals GP5-GP8 to become active, and the Iout current exhibits a current-sinking behavior. When the system is operating normally, both Ieao1 and Ieao2 are 0, switch S0 is inactive, the module is in a non-operating state, and it does not affect the normal operation of the circuit.

[0033] like Figure 5 As shown, the duration of the low level of signals GP5, GP6, GP7, and GP8 gradually increases. The duration of the high level of signals GN5, GN6, GN7, and GN8 gradually increases.

[0034] The non-inverting input of comparator COMP is connected to the ramp signal Slope1, and the output of comparator COMP is connected to the logic driver module LOGIC&DRIVER.

[0035] The voltage divider signal Vfb is generated by a voltage divider circuit, which includes resistors R1 and R2. One end of resistor R1 is connected to the output voltage VOUT, and the other end of resistor R1 is connected to one end of resistor R2 to generate the voltage divider signal Vfb. The other end of resistor R2 is grounded.

[0036] The threshold detection module detects the output voltage VOUT, determining the threshold voltage of the dynamic boost circuit and acting as the switch for the boost circuit's operation. The output control module processes the currents Ieao1 and Ieao2 output from the error amplifier EA to charge and discharge the compensation capacitor. The entire circuit's workflow is as follows: Figure 6 As shown. When the system is in normal operating condition, if the threshold detection unit outputs 1, the control output unit charges and discharges the compensation capacitor Cc, thereby helping the Vc voltage reach the expected value more quickly. When the circuit is in normal operating condition and the load is constant, the threshold detection unit outputs zero, and the control output unit outputs in a high-impedance state, which does not affect the Vc voltage.

[0037] The load dynamic response enhancement circuit proposed in this invention introduces a fast charging and discharging circuit for the compensation capacitor Cc, which enables the Vc voltage to respond more quickly when a transient change occurs in the output load, thereby improving the load dynamic response performance of the circuit. During normal operation, the threshold detection voltage output is zero, so it will not affect the normal operating point of Vc. Figure 7 The paper presents the beneficial effects on the output dynamic response before and after adding the load dynamic response enhancement circuit proposed in this invention under actual working conditions.

[0038] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A load dynamic response enhancement circuit, characterized in that: Includes error amplifier EA, threshold detection module, output control module, and resistor R. C Capacitor C C With capacitor C1, the non-inverting input of error amplifier EA is connected to the reference voltage Vref, the inverting input of error amplifier EA is connected to the input of the threshold detection module and connected to the voltage divider signal Vfb, and the voltage output of error amplifier EA is connected to resistor R. C One end of capacitor C1, one end of capacitor C1, and the inverting input of comparator COMP are connected to generate signal V. C The current output terminal of the error amplifier EA is connected to the current input terminal of the output control module, the output terminal of the threshold detection module is connected to the voltage input terminal of the output control module, and the output terminal of the output control module is connected to the resistor R. C The other end and capacitor C C One end of capacitor C1 is connected to the other end of capacitor C. C The other end is grounded.

2. The load dynamic response enhancement circuit according to claim 1, characterized in that: The error amplifier EA includes PMOS transistors MP0-MP10, NMOS transistors NM0-NM10, resistors R3 and R4. The sources of PMOS transistors MP0-MP6, PMOS transistor MP9, and PMOS transistor MP10 are connected to the power supply VCC. The gate of PMOS transistor MP0 is connected to the drain of PMOS transistor MP0, the drain of NMOS transistor NM1, the gate of PMOS transistor MP1, and the gate of PMOS transistor MP2. The gate of PMOS transistor MP3 is connected to the drain of PMOS transistor MP3, the drain of NMOS transistor MN3, and PMO. The gates of S-channel transistor MP4, PMOS transistors MP5 and MP6 are connected. The drain of PMOS transistor MP1 is connected to one end of resistor R3 and one end of resistor R4. The other end of resistor R3 is connected to the source of PMOS transistor MP7. The other end of resistor R4 is connected to the source of PMOS transistor MP8. The gate of PMOS transistor MP7 is connected to signal Vn, and the gate of PMOS transistor MP8 is connected to signal Vp. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN4, the gate of NMOS transistor MN4, and the gate of NMOS transistor MN3. The drain of PMOS transistor MP8 is connected to the drain, gate, MN5, gate, MN6, gate, and gate of NMOS transistors MN7 and MN8. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN6 and connected to signal Vc. The drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN7, the drain of PMOS transistor MP2, the drain of PMOS transistor MP9, the gate of PMOS transistor MP9, and the gate of PMOS transistor MP10. The drain of transistor 10 generates current Ieao2. The drain of PMOS transistor MP6 is connected to the drain of NMOS transistors MN8, MN2, and MN9, as well as the gate of NMOS transistor MN9 and the gate of NMOS transistor MN10. The drain of NMOS transistor MN10 generates current Ieao1. The drain of NMOS transistor NM0 is connected to the gate of NMOS transistor NM0, the gate of NMOS transistor NM1, and the gate of NMOS transistor NM2, and is connected to the bias current Ibias. The sources of NMOS transistors NM0 to NM10 are grounded.

3. The load dynamic response enhancement circuit according to claim 1, characterized in that: The threshold detection module includes comparator CMP1, comparator CMP2, inverter INV1, inverter INV2, AND gate AND1, AND gate AND2, monostable multivibrator oneshot1, monostable multivibrator oneshot2, falling edge delay module falling_edge delay1, and falling edge delay module falling_edge. The circuit consists of delay2, inverters INV3 and INV4. The non-inverting input of comparator CMP1 is connected to the reference voltage Vref1. The inverting inputs of comparator CMP1 and CMP2 are connected to the voltage divider signal Vfb. The inverting input of comparator CMP2 is connected to the reference voltage Vref2. The output of comparator CMP1 is connected to the first input of AND gate AND1 and the input of inverter INV1. The output of comparator CMP2 is connected to the third input of AND gate AND2 and the input of inverter INV2. The output of inverter INV1 is connected to the second input of AND gate AND2. The output of inverter INV2 is connected to the second input of AND gate AND2. The output of AND gate AND1 is connected to the input of the monostable multivibrator oneshot1 and the input of the falling edge delay module falling_edge delay1. The output of monostable multivibrator oneshot1 generates the signal Vo_low. The falling edge delay module falling_edge... The output of delay1 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the first input of AND gate AND2. The output of AND gate AND2 is connected to the input of monostable circuit oneshot2 and the input of falling edge delay module falling_edge delay2. The output of monostable circuit oneshot2 generates signal Vo_high. The output of falling edge delay module falling_edge delay2 is connected to the input of inverter INV4. The output of inverter INV4 is connected to the third input of AND gate AND1.

4. The load dynamic response enhancement circuit according to claim 1, characterized in that: The output control module includes PMOS transistors MP11-MP19, NMOS transistors MN11-MN19, and switch S0. The sources of PMOS transistors MP11-MP15 are connected to the power supply VCC. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP11, the gate of PMOS transistor MP12, the gate of PMOS transistor MP13, the gate of PMOS transistor MP14, and the gate of PMOS transistor MP15, and is connected to a current Ieao1. The drain of PMOS transistor MP12 is connected to the source of PMOS transistor MP16, and PMOS transistor MP13... The drain of PMOS transistor MP14 is connected to the source of PMOS transistor MP18, the drain of PMOS transistor MP15 is connected to the source of PMOS transistor MP19, the gate of PMOS transistor MP16 is connected to signal GP5, the gate of PMOS transistor MP17 is connected to signal GP6, the gate of PMOS transistor MP18 is connected to signal GP7, the gate of PMOS transistor MP19 is connected to signal GP8, and the drain of PMOS transistor MP16 is connected to the drain of PMOS transistor MP17, the drain of PMOS transistor MP18, and PM. The drains of transistors MP19, MN16, MN17, MN18, and MN19 are connected to one end of switch S0. The other end of switch S0 generates a current Iout. The gate of NMOS transistor MN16 is connected to signal GN5, the gate of NMOS transistor MN17 to signal GN6, the gate of NMOS transistor MN18 to signal GN7, and the gate of NMOS transistor MN19 to signal GN8. The source of NMOS transistor MN16 is connected to the drain of NMOS transistor MN12. Connect the source of NMOS transistor MN17 to the drain of NMOS transistor MN13, the source of NMOS transistor MN18 to the drain of NMOS transistor MN14, the source of NMOS transistor MN19 to the drain of NMOS transistor MN15, and the drain of NMOS transistor MN11 to the gates of NMOS transistors MN11, MN12, MN13, MN14, and MN15, and connect them with a current Ieao2. The sources of NMOS transistors MN11 to MN15 are grounded.

5. The load dynamic response enhancement circuit according to claim 1, characterized in that: The duration of the low level of signals GP5, GP6, GP7 and GP8 gradually increases.

6. The load dynamic response enhancement circuit according to claim 1, characterized in that: The duration of the high level of signals GN5, GN6, GN7 and GN8 gradually increases.

7. The load dynamic response enhancement circuit according to claim 1, characterized in that: The non-inverting input of the comparator COMP is connected to the ramp signal Slope1, and the output of the comparator COMP is connected to the logic driver module LOGIC&DRIVER.

8. The load dynamic response enhancement circuit according to claim 1, characterized in that: The voltage divider signal Vfb is generated by a voltage divider circuit, which includes resistors R1 and R2. One end of resistor R1 is connected to the output voltage VOUT, and the other end of resistor R1 is connected to one end of resistor R2 to generate the voltage divider signal Vfb. The other end of resistor R2 is grounded.

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