Multi-phase power converter control

Abstract

This application relates to multiphase power converter control. In described examples, an apparatus (100) includes a first phase transformer (126) and a second phase transformer (132), a first phase primary side circuit (122) and a second phase primary side circuit (128), a first phase secondary side circuit (124) and a second phase secondary side circuit (130), a delay circuit (170), and a controller (172). The first phase primary side circuit (122) is coupled to a primary winding (134) of the first phase transformer (126). The first phase secondary side circuit (124) is coupled to a secondary winding (136) of the first phase transformer (126). The second phase primary side circuit (128) is coupled to a primary winding (140) of the second phase transformer (132). The second phase secondary side circuit (130) is coupled to a secondary winding (142) of the second phase transformer (132). The controller (172) is coupled to the first phase primary side circuit (122) and the second phase primary side circuit (128) and the delay circuit (170).

Description

Technical Field

[0001] This application generally relates to pulse width modulation (PWM) control of power converters, and more particularly to PWM control of multiphase power converters. Background Technology

[0002] In some instances, PWM signals are used to control switching devices, such as power converters. Resonant converters are variable-frequency DC-DC converters. Examples of applications for resonant converters include servers, telecommunications, automotive, industrial, and other power environments.

[0003] Some applications, such as certain high-power applications, require the use of multiphase interleaved converters. In some instances, multiphase converters use multiple primary-side circuits coupled to corresponding primary windings. The control signals of the different primary-side circuits are phase-shifted relative to each other. In some instances of interleaved converters, a fixed phase relationship exists between different phases at one or more operating frequencies. Prolonged deviations from this fixed phase relationship can lead to converter inefficiency or instability. Summary of the Invention

[0004] In the described example, an apparatus includes a first-phase transformer and a second-phase transformer, a first-phase primary-side circuit and a second-phase primary-side circuit, a first-phase secondary-side circuit and a second-phase secondary-side circuit, a delay circuit, and a controller. The first-phase primary-side circuit is coupled to the primary winding of the first-phase transformer. The first-phase secondary-side circuit is coupled to the secondary winding of the first-phase transformer. The second-phase primary-side circuit is coupled to the primary winding of the second-phase transformer. The controller is coupled to the first-phase primary-side circuit, the second-phase primary-side circuit, and the delay circuit. The controller controls the first-phase primary-side circuit in response to the duration of a switching cycle, determines a phase delay in response to the duration of a switching cycle, and controls the second-phase circuit using the delay circuit in response to the phase delay.

[0005] In the described example, an apparatus includes a counter circuit, a comparator, a first pulse width modulation (PWM) circuit, and a second PWM circuit. The counter circuit is configured to provide a count value. The comparator is coupled to the counter circuit and configured to compare the count value with a threshold value, and to provide a signal based on the comparison. The first PWM circuit is coupled to the comparator and configured to provide a first PWM signal with a transition based on the count value satisfying the threshold value. The second PWM circuit is coupled to the comparator and the first PWM circuit. The second PWM circuit includes a delay circuit configured to determine a delay value based on the count value when the count value satisfies the threshold value. The second PWM circuit is configured to provide a second PWM signal with a transition based on the transition of the first PWM signal and the delay value.

[0006] In the described example, an apparatus includes a first phase transformer and a second phase transformer, a first phase primary side circuit and a second phase primary side circuit, a first phase secondary side circuit and a second phase secondary side circuit, a delay circuit, and a controller. The first phase primary side circuit is coupled to the primary winding of the first phase transformer. The first phase secondary side circuit is coupled to the secondary winding of the first phase transformer. The first phase primary side circuit includes a first inductor, a first capacitor, a first switch, and a second switch. The first inductor is coupled to a first terminal of the primary winding of the first phase transformer. The first terminal of the first capacitor is coupled to a second terminal of the primary winding of the first phase transformer. The first terminal of the second switch is coupled to the first switch and the first inductor, and the second terminal of the second switch is coupled to a second terminal of the first capacitor. The second phase primary side circuit is coupled to the primary winding of the second phase transformer. The second phase secondary side circuit is coupled to the secondary winding of the second phase transformer. The second phase primary side circuit includes a second inductor, a second capacitor, a third switch, and a fourth switch. The second inductor is coupled to a first terminal of the primary winding of the second phase transformer. The first terminal of the second capacitor is coupled to a second terminal of the primary winding of the second phase transformer. The first terminal of the fourth switch is coupled to the third switch and the second inductor, and the second terminal of the fourth switch is coupled to the second terminal of the second capacitor. The controller is coupled to the first phase primary side circuit, the second phase primary side circuit, and the delay circuit. The controller controls the first phase primary side circuit in response to the switching cycle duration, determines the phase delay in response to the switching cycle duration, and controls the second phase circuit using the delay circuit in response to the phase delay. Attached Figure Description

[0007] Figure 1 This is a functional block diagram and circuit diagram of an example power converter system.

[0008] Figure 2 For corresponding Figure 1 A set of curves representing an example signal of PWM control on the first primary side of a power converter system.

[0009] Figure 3 for Figure 1 A set of curves for example signals of a power converter system.

[0010] Figure 4 for Figure 1 Example functional block diagram of the PWM module.

[0011] Figure 5A and 5B for Figure 1 A set of curves for the PWM control signal of an example power converter system.

[0012] Figure 6 For use in adjusting the application to Figure 1 The flowchart shows an example program for the delay of the second-phase PWM control signal in a power converter system. Detailed Implementation

[0013] Multiphase inductor-inductor-capacitor (LLC) converters are useful in a variety of applications, such as industrial and automotive applications. A multiphase converter includes a first-phase circuit connected to the primary winding of a first-phase transformer and a second-phase circuit connected to the primary winding of a second-phase transformer. Switching of the first-phase circuit controls the application of energy to the primary winding of the first-phase transformer to store magnetic energy of either a first or second polarity in the core of the first-phase transformer. Similarly, switching of the second-phase circuit controls the application of energy to the primary winding of the second-phase transformer to store magnetic energy of either a first or second polarity in the core of the second-phase transformer.

[0014] The second phase switch is controlled to open and close with a phase delay relative to the control of the first phase switch. This phase delay can be provided using a delay circuit that provides a second phase control signal with a delay time responsive to the switching frequency of the first phase primary-side switch. Variations in this delay between sequential control events (e.g., control corresponding to a rising signal edge after a falling signal edge, or vice versa) can be limited by a maximum delay step size to avoid deviating too far from the designed duty cycle of the switch. In some instances, this helps to avoid system instability caused by deviations from the designed duty cycle, such as system instability in response to current imbalances between phases.

[0015] As is the convention in this document, metal-oxide-semiconductor field-effect transistors (MOSFETs) are numbered M[channel type][number], where the number increases for each different transistor of the same channel type. Channel types include n-channel MOSFETs (NMOS) and p-channel MOSFETs (PMOS). The channel type of each transistor is merely an example, and other examples can be substituted for any transistor shown with another transistor of a different type. Furthermore, the same reference numerals or other reference indicators are used in the figures to indicate structurally and / or functionally related features.

[0016] Figure 1 The following is a functional block diagram and circuit diagram of an example power converter system 100. The power converter system 100 includes a two-phase LLC converter 102, which has a first phase circuit 104, a second phase circuit 106, a load 108, a voltage sensor 110, a control integrated circuit (IC) 112, a primary-side gate driver circuit 114, a secondary-side gate driver circuit 116, and a voltage source 118.

[0017] The first phase circuit 104 includes a first primary side 122, a first secondary side 124, and a first transformer 126. The second phase circuit 106 includes a second primary side 128, a second secondary side 130, and a second transformer 132. The first transformer 126 includes a first primary winding 134 coupled to the first primary side 122, a first secondary winding 136 coupled to the first secondary side 124, and a first isolator 138. The second transformer 132 includes a second primary winding 140 coupled to the second primary side 128, a second secondary winding 142 coupled to the second secondary side 130, and a second isolator 144.

[0018] The first primary side 122 includes a first n-channel MOSFET (MN1) 146, a second n-channel MOSFET (MN2) 148, a first inductor 150, and a first capacitor 152. The first primary side 124 includes a third n-channel MOSFET (MN3) 154 and a fourth n-channel MOSFET (MN4) 156.

[0019] The second primary side 128 includes a fifth n-channel MOSFET (MN5) 158, a sixth n-channel MOSFET (MN6) 160, a second inductor 162, and a second capacitor 164. The second primary side 130 includes a seventh n-channel MOSFET (MN7) 166 and an eighth n-channel MOSFET (MN8) 168. The first inductor 150 and the second inductor 162 may be, for example, external inductors or leakage inductors of the first transformer 126 and the second transformer 132, respectively. MN1 146, MN2 148, MN5 158, and MN6 160 are collectively referred to as primary-side switches.

[0020] The first inductor 150, the magnetizing inductance of the first primary winding 134, and the first capacitor 152 together form a first resonant slot circuit. The second inductor 162, the magnetizing inductance of the second primary winding 140, and the second capacitor 164 together form a second resonant slot circuit. Based on the first and second resonant slot circuits, the two-phase LLC converter 102 is referred to as a resonant power converter.

[0021] Control IC 112 includes a PWM module 170, a processor 172, a memory 174, and a clock circuit 176. In some instances, processor 172 is a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller unit (MCU). Memory 174 includes memory circuitry that stores instructions for executing interrupt service routines (ISRs) or other background programs (or other programs) for controlling PWM module 170. In some instances, the PWM control program is stored in a flash memory bank of memory 174. In some instances, the signal in response to a voltage measurement by voltage sensor 110 is sampled by circuitry of control IC 112 (e.g., circuitry of processor 172). The sampled values ​​are processed by processor 172 and / or stored in memory 174.

[0022] On the primary side (first primary side 122 and second primary side 128), the positive terminal of voltage source 118 is connected to the drain of MN1146 and the drain of MN5158. The source of MN1146 is connected to the drain of MN2148 and the first terminal of the first inductor 150. The second terminal of the first inductor 150 is connected to the first terminal of the first primary winding 134. The second terminal of the first primary winding 134 is connected to the first terminal of the first capacitor 152 and the first input of the voltage sensor 110. The second terminal of the first capacitor 152 is connected to the source of MN2148 and the negative terminal of voltage source 118. The gates of MN1146 and MN2148 are connected to one or more outputs (e.g., corresponding individual complementary outputs) of the primary-side gate driver circuit 114.

[0023] The source of MN5 158 is connected to the first terminal of the second inductor 162 and the drain of MN6 160. The second terminal of the second inductor 162 is connected to the first terminal of the second primary winding 140. The second terminal of the second primary winding 140 is connected to the first terminal of the second capacitor 164 and the second input of the voltage sensor 110. The second terminal of the second capacitor 164 is connected to the source of MN6 160 and the negative terminal of the voltage source 118. The gates of MN5 158 and MN6 160 are connected to the output of the primary-side gate driver circuit 114 (e.g., corresponding individual complementary outputs). MN1 146 and MN5 158, both connected to the positive terminal of the voltage source 118, are referred to herein as high-side switches. MN2 148 and MN6 160, both connected to the negative terminal of the voltage source 118, are referred to herein as low-side switches.

[0024] MN1 146, MN2 148, MN5 158, and MN6 160 provide switching functionality for LLC converter 102. MN1 146 and MN2 148 control the current through the first primary coil 134, and MN5 158 and MN6 160 control the current through the second primary coil 140. Therefore, MN1 146, MN2 148, MN5 158, and MN6 160 control the transfer of energy from the primary coils 134 and 140 to the corresponding (first and second) secondary coils 136 and 142.

[0025] On the secondary side (first stage 124 and second stage 130), the center taps of the first stage winding 136 and the second stage winding 142 are connected to the first output terminal 178. The first output terminal 178 is connected to the first terminal of the load 108. The first terminal of the first stage winding 136 is connected to the drain of MN3 154. The second terminal of the first stage winding 136 is connected to the drain of MN4 156. The sources of MN3 154 and MN4 156 are connected to the second output terminal 180. The second output terminal 180 is connected to the second terminal of the load 108.

[0026] The first terminal of the second stage winding 142 is connected to the drain of MN7 166. The second terminal of the second stage winding 142 is connected to the drain of MN8 168. The sources of MN7 166 and MN8 are connected to the second output terminal 180. The gates of MN3 154, MN4 156, MN7 166, and MN8 168 are connected to one or more outputs of the secondary-side gate driver circuit 116 (e.g., corresponding individual complementary outputs). Therefore, in this example, the gates of MN3 154 and MN4 156 are connected to the first pair of complementary outputs of the secondary-side gate driver circuit 116, and the gates of MN7 166 and MN8 168 are connected to the second pair of complementary outputs of the secondary-side gate driver circuit 116. The voltage between the first output terminal 178 and the second output terminal 180 corresponds to the output voltage of the LLC converter 102, and therefore, to the voltage across the load 108.

[0027] The output of voltage sensor 110 is connected to the input of control IC 112. Processor 172 is connected to communicate with memory 174. The output of processor 172 is connected to the input of PWM module 170. The first output of control IC 112 is connected to the input of primary-side gate driver circuit 114, and the second output of control IC 112 is connected to the input of secondary-side gate driver circuit 116.

[0028] Processor 172 controls PWM module 170 in response to instructions in memory 174 (e.g., the ISR described above) and in response to feedback signals provided by voltage sensor 110. PWM module 170 controls primary-side gate driver 114 and secondary-side gate driver 116. Primary-side gate driver 114 controls MN1 146, MN2 148, MN5 158, and MN6 160 to open and close. MN1 146 and MN2 148 are controlled to achieve energy transfer across the first transformer 126 from the first primary side 122 to the first secondary side 124. MN5 158 and MN6 160 are controlled to achieve energy transfer across the second transformer 132 from the second primary side 128 to the second secondary side 130.

[0029] The secondary-side gate driver 116 controls MN3 154 and MN4 156 to rectify the current induced in the first primary winding 136 based on the energy delivered from the first primary winding 134. Therefore, MN3 154 and MN4 156 are controlled to rectify the current through the first primary winding 136. The secondary-side gate driver 116 controls MN7 166 and MN8 168 to rectify the current induced in the second primary winding 142 based on the energy delivered from the second primary winding 140. Therefore, MN7 166 and MN8 168 are controlled to rectify the current through the second primary winding 142.

[0030] When the high-side switch (MN1 146 or MN5 158) is turned on and the corresponding low-side switch (MN2 148 or MN6 160) is turned off, the current flowing from the positive terminal of voltage source 118 through the corresponding inductor 150 or 162 and through the corresponding primary winding 134 or 140 increases. When the current flows through the primary winding 134 or 140 to the corresponding capacitor 152 or 164, the capacitor 152 or 164 is charged, and the primary winding 134 or 140 generates a magnetic flux that causes the corresponding magnetic core (not shown) to store magnetic energy of a first polarity.

[0031] When the high-side switch (MN1 146 or MN5 158) is off and the corresponding low-side switch (MN2 148 or MN6 160) is on, the current flowing from the corresponding capacitor 152 or 164 through the corresponding primary winding 134 or 140, through the corresponding inductor 150 or 162, and to the negative terminal of the voltage source 118 increases. As the current flows through the primary winding 134 or 140 to the negative terminal of the voltage source 118, the capacitor 152 or 164 discharges, and the primary winding 134 or 140 generates a magnetic flux, which causes the corresponding magnetic core to store magnetic energy with a second polarity. The magnetic flux generated by the primary winding 134 or 140 induces current in the corresponding secondary winding 136 or 142, which is rectified by MN3 154 and MN4 156 or by MN7 166 and MN8 168, respectively. The rectified current supplies DC power to the load 108.

[0032] In some resonant power converters, as the output current demand (current demand of load 108) decreases, the switching frequency of the transistor controlling power delivery is increased to reduce power output. In LLC converter 102, this corresponds to increasing the switching frequencies of the high-side and low-side switches 146, 148, 158, and 160.

[0033] Figure 2 For corresponding Figure 1 A set of graphs 200 representing example signals of PWM control of the first primary side 122 of the power converter system 100. Graphs 200 include a first graph 202, a second graph 204, a third graph 206, and a fourth graph 208. In some examples, graphs 200 describe the behavior of the first phase circuit 104 of the power converter system 100. The horizontal axis of each of graphs 202, 204, 206, and 208 indicates time. The vertical axis of the first graph 202, the third graph 206, and the fourth graph 208 indicates voltage. The vertical axis of the second graph 204 indicates counting. Figure 2 Example signals for current-mode control of an LLC converter are shown. Note that the methods and structures disclosed herein are applicable to voltage-mode control, alternatives to current-mode control, and other types of multiphase converters.

[0034] The first graph 202 includes the resonant capacitor voltage (VCR) feedback signal curve 210 and the reference voltage curve 212. The second graph 204 includes the PWM counter value 214, which tracks the counter value generated by the PWM counter. In some instances, the PWM counter is included in the PWM module 170. The third graph 206 includes the high-side PWM control signal 216 for controlling the high-side switches MN1 146 and MN5 158. The fourth graph 208 includes the low-side PWM control signal 218 for controlling the low-side switches MN2 148 and MN6 160. For clarity, graphs 202, 204, 206, and 208 do not show the period when MN1 146, MN2 148, MN5 158, and MN6 160 are all off to prevent breakdown (also known as dead time or dead band).

[0035] Recall that the first capacitor 152 participates in the resonance of the first phase circuit 104. The VCR feedback signal curve 210 responds to the voltage measured by the voltage sensor 110, and therefore, to the voltage across the first capacitor 152. Specifically, the VCR feedback signal curve 210 is positive in the direction from the first primary winding 134 toward the negative terminal of the voltage source 118.

[0036] Before time T1, the reference voltage curve 212 is constant, and the PWM counter value 214 is increasing. At T1, the VCR feedback signal 210 has a negative slope, and the PWM counter value 214 is equal to the first value (PWMcount) corresponding to the duration of the switching cycles sequentially preceding T1. PRD Therefore, the PWM counter value 214 corresponds to PWMcount. PRD The value equals PWMcount at the end of the switching cycle. PRD value.

[0037] In response to a clock edge following T1 (e.g., a rising edge or a falling edge), the PWM counter value 214 is reset to zero (or other baseline value), and the high-side PWM signal 216 transitions to a first voltage (e.g., a high voltage, such as...). Figure 2 As shown in the diagram, the low-side PWM signal 218 transitions to a second voltage (e.g., a low voltage, as shown) having a logic value opposite to the high voltage. Furthermore, the reference voltage 212 is allowed to decrease at a designed rate, such as in response to the rate of charging or discharging of a capacitor in a resistor-capacitor (RC) circuit (not shown).

[0038] In the clock cycle following T1 to T2, PWM module 170 provides a high-side PWM signal 216 with a high voltage to the primary-side gate driver 114 to control MN1 146 to close. PWM module 170 also provides a low-side PWM signal 218 with a low voltage to the primary-side gate driver 114 to control MN2 148 to open. This causes an increase in current from the positive terminal of voltage source 118 through MN1 146 via the first primary winding 134 to the first capacitor 152, resulting in an increase in the slope of the VCR feedback signal curve 210 from the clock cycle following T1 to T2.

[0039] T2 corresponds to the reduced reference voltage curve 212 that intersects 220 with the VCR feedback signal curve 210. At T2, the PWM counter value 214 is equal to the second value corresponding to half a switching cycle (PWMcount). TRNS Therefore, at T2, the PWM high-side signal 216 transitions to low voltage, the PWM low-side signal 218 transitions to high voltage, and PWMcount... TRNS It is stored in memory 174. In addition, the reference voltage 212 is reset and maintained at the constant voltage it held before T1.

[0040] From T2 to T3, PWM module 170 provides a high-side PWM signal 216 with a low voltage to the primary-side gate driver 114 to control MN1 146 to turn off. PWM module 170 provides a low-side PWM signal 218 with a high voltage to the primary-side gate driver 114 to control MN2 148 to turn on. This causes an increase in the current from the first capacitor 152 through the first primary winding 134 through MN2 148 to the negative terminal of the voltage source 118, causing the slope of the VCR feedback signal curve 210 to decrease from T2 to T3.

[0041] T3 corresponds to the end of the switching cycle that started at T1. At T3, the PWM counter value 214 equals PWMcount. TRNS This is twice the value of the PWM counter, and therefore equal to twice the value of 214 at T2 (half a switching cycle time). This counter value corresponds to the end of the switching cycle, represented by the duration from T1 to T3. Therefore, PWMcount... TRNS Twice that is equal to the PWM count corresponding to the end of the switching cycle that begins at T1. PRD The value of PWMcount. Note the value of PWMcount. TRNS and PWMcount PRDThe switching cycle can be changed to the next sequential switching cycle. In some instances, changes in the VCR feedback signal 210 cause the control IC 112 to control the switching frequency of the primary switches MN1 146, MN2 148, MN5 158 and / or MN6 160.

[0042] The low-side PWM signal 218 from T2 to T3 is a copy of the high-side PWM signal 216 from T1 to T2. The high-side PWM signal 216 from T2 to T3 is a copy of the low-side PWM signal 218 from T1 to T2. The signal behavior of the second phase circuit 106 of the power converter system 100 is further described with reference to Figures 5 and 6.

[0043] Figure 3 for Figure 1 A set of graphs 300 for example signals of the power converter system 100. Graphs 300 include a first graph 302 and a second graph 304. The horizontal axis of each of graphs 302 and 304 indicates time. The vertical axis of the first graph 302 indicates voltage. The vertical axis of the second graph 304 indicates current. The first graph 302 contains a set of graphs corresponding to V. OUT Therefore, V corresponds to the voltage across load 108. OUT Curve 306. The second curve 304 contains the output current curve 308 corresponding to the current passing through the load 108.

[0044] In some instances, the power converter system 100 uses frequency modulation to regulate V. OUT Therefore, after the load decreases or increases, the control IC 112 (or other control circuitry) adjusts the switching frequency of the primary-side switch in response to feedback information, such as the VCR feedback signal 210 provided by the voltage sensor 110. In some instances, adjusting the switching frequency of the primary-side switch adjusts the power delivered from the primary sides 122 and 128 to the corresponding secondary sides 124 and 130, which adjusts the VCR over time. OUT .

[0045] Figure 4 This is an example functional block diagram of PWM module 170. PWM module 170 includes timing control circuitry 402, counter comparison circuitry 404, first phase action qualifier (AQ) 406, second phase AQ 408, and additional PWM control circuitry 410. Primary AQ 406 and secondary AQ 408 determine the rising edge timing and falling edge timing of the corresponding PWM control signals. Therefore, primary AQ 406 determines the edge timing of the PWM control signals corresponding to MN1 146 and MN2 148, and secondary AQ 408 determines the edge timing of the PWM control signals corresponding to MN5 158 and MN6 160.

[0046] The timing control circuit 402 includes a clock circuit 412 that generates a clock signal, and one or more counters 414 that provide corresponding counts in response to the clock signal. The counter comparison circuit 404 includes a threshold generator 416 and a comparator 418. The threshold generator 416 generates one or more threshold signals, such as threshold voltage, threshold current, or threshold count. The comparator 418 compares the signal received from the timing control circuit 402 with the corresponding threshold. The second phase AQ 408 includes a delay circuit 420. The delay circuit 420 determines the delay of the second phase PWM control signal in response to the first phase PWM control signal (e.g., the high-side PWM control signal 216), as further described below and with respect to Figures 5 and 6. In some instances, the additional PWM control circuit 410 includes a deadband generator, a PWM chopper, a trip zone circuit, a digital comparator circuit, or an input / output circuit.

[0047] In some instances, the delay provided by delay circuit 420 is determined such that the second-phase PWM control signal has a phase delay of 90° (π / 2 radians) relative to the first-phase PWM control signal. In some instances, delay circuit 420 provides the delay in response to the delay of a sequential previous switching cycle. In some instances, delay circuit 420 provides this adjusted (increased or decreased) delay such that the phase delay relative to the first-phase PWM control signal is closer to 90°. In some instances, this adjustment is made in response to a change in the switching frequency controlled by the first-phase PWM control signal. In some instances, delay circuit 420 adjusts the delay (adds or subtracts) (1) setting the phase delay to a delay step size equal to 90° or (2) the smaller of a designed delay step size. The designed delay step size can be described as the maximum delay adjustment. In some instances, the designed delay step size is set in hardware or stored (e.g., programmed) in memory 174 or other memory. In some instances, the delay step size can be programmed in response to software (e.g., firmware update).

[0048] The first output of timing control circuit 402 is connected to the input of counter comparator circuit 404. The second output of timing control circuit 402 is connected to the first input of first phase AQ 406. The third output of timing control circuit 402 is connected to the first input of second phase AQ 408. In some instances, the output of timing control circuit 402 provides a clock signal and / or one or more counter values, such as PWM counter value 214. The first output of counter comparator circuit 404 is connected to the second input of first phase AQ 406. The second output of counter comparator circuit 404 is connected to the second input of second phase AQ 408. In some instances, the output of counter comparator circuit 404 provides an indicator used by AQ 408 to determine the timing of signal events, such as PWM control signals 216, 218, 506, or 508. Figure 5A The rising or falling edge of ).

[0049] The first output of the first phase AQ 406 is connected to the first input of the additional PWM control circuit 410. The second output of the first phase AQ 406 is connected to the third input of the second phase AQ 408 and provides the first phase PWM control signal 216 and / or 218. In one example, the second phase PWM control signal is generated in response to these control signals 216 and / or 218 and the delay circuit 420. The output of the second phase AQ 408 is connected to the second input of the additional PWM control circuit 410. In some examples, PWM control signals 216, 218, 506, or 508 are provided from AQ 406 or 408 to the output of the additional PWM control circuit 410 for additional shaping or as a feedback signal before being provided to the gate driver 114 or 116. The output of the additional PWM control circuit 410 is connected to the input of the timing control circuit 402.

[0050] Figure 5A and 5B for Figure 1 A set of curves 500 for the PWM control signal of an example power converter system 100. Figure 5B exhibit Figure 5AThe second graph is a continuation of the graph. Graph 500 includes a first graph 502 and a second graph 504. The vertical axes of the first graph 502 and the second graph 504 indicate voltage. The horizontal axes of the first graph 502 and the second graph 504 indicate time. The first graph 502 includes a first-phase PWM control signal curve 506, such as the high-side first-phase PWM control signal 216. The second graph 504 includes a second-phase PWM control signal curve 508 that controls a second-phase primary switch (e.g., MN5 158 or MN6 160). This second-phase primary switch corresponds to a first-phase primary switch (e.g., MN1 146 or MN2 148) controlled by the first-phase PWM control signal 506.

[0051] The graph 500 spans the time period of multiple switching cycles corresponding to the first-phase PWM control signal 506, specifically the first switching cycle 510, the second switching cycle 512, the third switching cycle 514, and the fourth switching cycle 515. The first switching cycle 510 corresponds to the steady-state or constant load 108 behavior of the power converter system 100. The first-phase switching frequency changes in the second switching cycle 512 and remains constant in the second, third, and fourth switching cycles 512 and 514. The primary-side control of the power converter system 100 returns to steady-state behavior in the fourth switching cycle 515.

[0052] In some instances, the change in the first-phase switching frequency is triggered by changes in the load 108, the input voltage, or the controlled output voltage. Therefore, in steady state, the switching frequency controlled by the first-phase PWM control signal 506 is approximately constant from one switching cycle to the next sequential switching cycle. Furthermore, in response to the first switching cycle 510, the delay provided by the delay circuit 420 to generate the second-phase PWM control signal 508 in response to the first-phase PWM control signal 506 is approximately constant.

[0053] At T1, the first-phase PWM control signal 506 has a rising edge, and the second-phase PWM control signal 508 has a low voltage, for example, zero voltage to control the corresponding primary switch to be disconnected (deactivated). From T1 to T3, the first-phase PWM control signal 506 has a high voltage, for example, voltage to control the corresponding primary switch to be closed (activated). At T2, the second-phase PWM control signal 508 has a rising edge responsive to the T1 rising edge of the first-phase PWM control signal 506 and a rising edge of a first delay 516 provided by the delay circuit 420. The first delay 516 corresponds to a quarter-switching cycle of the sequential previous switching cycle of the first-phase PWM control signal 506. This delay duration corresponds to the PWMcount count. PRD / 4, which equals PWMcountTRNS / 2, as about Figure 2 As described. The second-phase PWM control signal 508 has a high voltage from T2 to T4.

[0054] At T3, the first-phase PWM control signal 506 has a falling edge. At T4, the second-phase PWM control signal 508 has a falling edge in response to the first-phase PWM control signal 506 at T3 and in response to the falling edge of the first delay 516. In this document, updating the delay refers to storing a delay count corresponding to the delay in a register used by the second-phase AQ 408 (e.g., a register of the delay circuit 420) to apply the delay to the second-phase PWM control signal 508. In some instances, such as regarding... Figure 6 As further described, the delay is not updated while the delay counter is counting. In some instances, this implementation or ensures that the on-time controlled by the second-phase PWM control signal 508 matches the on-time controlled by the first-phase PWM control signal 506. Therefore, for the rising edge of T2, the delay is determined and updated before T1, and for the falling edge of T4, the delay is determined and updated between T2 and T3. In some instances, a second count (other than the PWM counter value 214) is maintained to facilitate delay updates after each half-switch cycle.

[0055] The switching frequencies of the first phase switches (MN1 148 and MN2 150) differ in the second switching cycle 512 from those in the first switching cycle 510. As described above, the control IC 112 can control the switching frequency of the primary switches in response to changes in the VCR feedback signal 210. At T5, the first phase PWM control signal 506 has a rising edge and the second switching cycle 510 begins. At T6, the second phase PWM control signal 508 has a rising edge responsive to the first phase PWM control signal 506 at T5 and a rising edge responsive to the second delay 518 provided by the delay circuit 420. The second delay 518 corresponds to one-quarter of the switching cycle (PWMcount) of the first switching cycle 510. TRNS / 2). Note that the duration of the second switching cycle 512 is not determined until T7 when the first phase PWM control signal 506 has a falling edge corresponding to the reference voltage 212 and the VCR feedback signal 210 intersects at 220.

[0056] At T7, the first-phase PWM control signal 506 has a falling edge. At T8, the second-phase PWM control signal 508 has a falling edge responsive to the first-phase PWM control signal 506 at T7 and a falling edge responsive to the second delay 518. In graph 500, the second switching cycle 512 corresponds to a lower switching frequency than the first switching cycle 510. The delay between the corresponding rising or falling edges of the first-phase PWM control signal 506 and the second-phase PWM control signal 508 is not changed in the second-phase switching cycle corresponding to the primary-phase switching cycle in which the switching frequency controlled by the first-phase PWM control signal 506 changes. This is because the amount of delay to be applied to the second-phase PWM control signal 508 is known after the first-phase frequency has changed, and therefore after the first-phase switching cycle in which such a change occurs has been completed.

[0057] As described above, the switching frequency of the third switching cycle 514 is equal to the switching frequency of the second switching cycle 512. At T9, the first-phase PWM control signal 506 has a rising edge and the third switching cycle 514 begins. At T10, the second-phase PWM control signal 508 has a rising edge in response to the first-phase PWM control signal 506 at T9 and a rising edge in response to the third delay 520 provided by the delay circuit 420. Note that the third delay 520 is less than one-quarter of the switching period 522 of the second switching cycle 512 (from T7 to T8) (PWMcount). TRNS / 2). This is because PWMcount TRNS / 2 is greater than the second delay 518 plus the delay step 524. Therefore, the third delay 520 is limited to and equal to the second delay 518 plus the delay step 524.

[0058] If the second switching cycle 512 has a sufficiently high switching frequency than the first switching cycle 510, then the third delay 520 will be greater than one-quarter of the switching cycle 522 of the second switching cycle 512 (from T7 to T8). This will be determined by PWMcount. TRNS / 2 is less than the second delay 518 minus the delay step 524. Therefore, the third delay 520 will be limited to and will be equal to the second delay 518 minus the delay step 524.

[0059] At time T11, the first-phase PWM control signal 506 has a falling edge. At time T12, the second-phase PWM control signal 508 has a falling edge that responds to the first-phase PWM control signal 506 at T11 and to the falling edge of the third delay 520.

[0060] As described above, the switching frequency of the fourth switching cycle 515 is equal to the switching frequencies of the second switching cycle 512 and the third switching cycle 514. At T13, the first-phase PWM control signal 506 has a rising edge and the fourth switching cycle 515 begins. At T14, the second-phase PWM control signal 508 has a rising edge responsive to the first-phase PWM control signal 506 at T13 and also responsive to the rising edge of the fourth delay 526 provided by the delay circuit 420. The fourth delay 526 is equal to one-quarter of the switching period 522 of the third switching cycle 514, because the one-quarter switching period 522 is less than the third delay 520 plus the delay step 524.

[0061] At time T15, the first-phase PWM control signal 506 has a falling edge. At time T16, the second-phase PWM control signal 508 has a falling edge that responds to the first-phase PWM control signal 506 at T15 and to the falling edge of the fourth delay 526.

[0062] Figure 6 For use in adjusting the application to Figure 1 The flowchart illustrates an example program 600 for delaying the second-phase PWM control signal of a power converter system 100. Program 600 can be executed by one or more components of the control IC 112, such as the PWM module 170. In step 602, a delay timing delay_new is determined in response to the first-phase switching frequency and the designed phase delay between the first and second phases. In step 604, it is determined whether the absolute value of (delay_new minus delay_old) is greater than the maximum phase step size phase_step. Delay_old is the delay value used at the most recent rising or falling edge of the first-phase control signal. If the answer to step 604 is yes, then proceed to step 606. Otherwise, proceed to step 612.

[0063] In step 606, it is determined whether delay_new is greater than delay_old. If the answer to step 606 is yes, then proceed to step 608. Otherwise, proceed to step 610.

[0064] In step 608, delay_adjusted is set to equal delay_old plus phase_step. In step 610, delay_adjusted is set to equal delay_old minus phase_step. In step 612, delay_adjusted is set to equal delay_new. After each of steps 608, 610, or 612, proceed to step 614.

[0065] In step 614, after the delay counter finishes counting, the delay values ​​of the rising and falling edges of the PWM control signal to be applied to the second phase are updated to be equal to delay_adjusted. In step 616, the primary-side switch of the second phase is controlled in response to delay_adjusted, and delay_old is set to be equal to delay_adjusted. Setting delay_old to be equal to delay_adjusted prepares for the execution of program 600 in response to the next switching cycle.

[0066] After step 616, program 600 repeats from step 604 using the value of delay_new previously determined in step 602. In some instances, step 602 of program 600 is triggered if the switching frequency of the first phase primary side switches 146 and 148 changes, or if the change in the switching frequency of the first phase primary side switches 146 and 148 exceeds a threshold.

[0067] Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

[0068] In some instances, the control circuitry and procedures described herein can be used to control multiphase PWM controlled devices other than full-bridge LLC converters, such as buck, boost, or buck-boost converters, half-bridge or full-bridge devices, DC or AC input devices, DC or AC output devices, or other devices that provide or regulate power across inductors or transformers or otherwise.

[0069] In some instances, the control circuitry and procedures described herein can be used to control multiphase PWM controlled devices with more than one phase (and therefore two or more phases).

[0070] In some instances, the designed phase delay is not 90° (π / 2 radians). In some instances, the designed phase delay of the Mth phase (integer M) out of N phases is (180 / N)×(M-1) degrees or (π / N)×(M-1) radians.

[0071] In some instances, the delay of the second-phase PWM control signal changes within the same cycle in which the switching frequency of the first-phase PWM control signal changes.

[0072] The term "coupled" is used throughout this specification. This term may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then in a first instance, device A is coupled to device B; or in a second instance, if intermediate component C substantially does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C, such that device B is controlled by device A via control signals provided by device A.

[0073] In this description, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, and C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A, B, and C. Furthermore, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment comprising any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0074] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. This configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0075] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” “solder ball,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0076] The circuits or devices described herein as containing certain components may be practically adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may practically contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0077] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, metal-oxide-semiconductor FETs (“MOSFETs”) (e.g., n-channel MOSFETs (nMOSFETs) or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0078] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0079] While some elements of the described examples may be included in the integrated circuit and others may be external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0080] The use of the phrase “ground” in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection applicable to or suited to the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

Claims

1. An apparatus comprising: The first phase transformer includes a primary winding, a secondary winding, and an isolator. The primary side circuit of the first phase is coupled to the primary winding of the first phase transformer; The first phase secondary side circuit is coupled to the secondary winding of the first phase transformer; The second phase transformer includes a primary winding, a secondary winding, and an isolator. The second phase primary side circuit is coupled to the primary winding of the second phase transformer; The second phase secondary side circuit is coupled to the secondary winding of the second phase transformer; Delay circuit; and A controller, coupled to the first phase primary-side circuit and the second phase primary-side circuit and coupled to the delay circuit, is configured to: The primary-side circuit of the first phase is controlled in response to the duration of the switching cycle; The phase delay is determined in response to the duration of the switching cycle; and The second phase primary-side circuit is controlled using the delay circuit in response to the phase delay.

2. The apparatus of claim 1, wherein the controller is configured to: The phase delay is compared with a threshold. The phase delay is adjusted in response to the comparison to produce an adjusted phase delay; and The second phase primary-side circuit is controlled using the delay circuit in response to the adjusted phase delay.

3. The apparatus of claim 2, wherein the threshold corresponds to the maximum change in the phase delay per switching cycle of the second phase primary-side circuit.

4. The apparatus according to claim 1, further comprising: A first capacitor is coupled between a first terminal of the primary winding of the first phase transformer and a first side of the first phase primary side circuit. and A second capacitor is coupled between a first terminal of the primary winding of the second phase transformer and a first side of the primary side circuit of the second phase transformer.

5. The apparatus according to claim 4, further comprising: A first inductor is coupled between the second terminal of the primary winding of the first phase transformer and the second side of the first phase primary side circuit. and A second inductor is coupled between the second terminal of the primary winding of the second phase transformer and the second side of the primary side circuit of the second phase.

6. The apparatus of claim 1, further comprising a voltage sensor having a first input, a second input, and an output, the first input of the voltage sensor being coupled between the first phase primary-side circuit and the primary winding of the first phase transformer, the second input of the voltage sensor being coupled between the second phase primary-side circuit and the primary winding of the second phase transformer, and the output of the voltage sensor being coupled to the controller.

7. The apparatus of claim 1, wherein the apparatus comprises two or more phases, and the controller determines a phase delay for each phase other than the first phase in response to the plurality of phases.

8. The apparatus of claim 1, wherein the apparatus is an LLC converter.

9. An apparatus comprising: A counter circuit configured to provide a count value; A comparator, coupled to the counter circuit and configured to: The count value is compared with a threshold; and A signal is provided based on the comparison between the count value and the threshold; A first pulse width modulation circuit is coupled to the comparator and configured to provide a first pulse width modulation signal with a transition based on the count value satisfying the threshold; and A second pulse width modulation circuit is coupled to the comparator and the first pulse width modulation circuit, wherein: The second pulse width modulation circuit includes a delay circuit configured to determine a delay value based on the count value when the count value meets the threshold; and The second pulse width modulation circuit is configured to provide a second pulse width modulation signal with a transition based on the transition and the delay value of the first pulse width modulation signal.

10. The apparatus of claim 9, wherein when the count value satisfies the threshold, the delay value is based on one-quarter of the count value.

11. The apparatus of claim 9, wherein the delay circuit is configured to: The change in the delay value between switching cycles is compared with the delay value step size; and The change in the delay value is limited to the delay value step size.

12. The apparatus of claim 9, further comprising: A first gate driver, which is coupled to the first pulse width modulation circuit; and The second gate driver is coupled to the second pulse width modulation circuit.

13. The apparatus of claim 12, further comprising: The first switch, the second switch, the third switch, and the fourth switch each have a current path and a control terminal coupled to the corresponding output of the first gate driver; and The fifth, sixth, seventh, and eighth switches each have a current path and a control terminal coupled to the corresponding output of the second gate driver.

14. The apparatus of claim 13, further comprising: A voltage source having a first terminal and a second terminal; A first transformer includes a primary winding and a secondary winding, each having a first terminal and a second terminal respectively, and an isolator. The current paths of the fifth switch and the sixth switch are coupled to the first terminal of the secondary winding of the first transformer. A first capacitor is coupled between the second terminal of the primary winding of the first transformer at the first end and the current path of the second terminal of the voltage source and the second switch at the second end. A first inductor is coupled between the first terminal of the primary winding of the first transformer at the first end and the current path of the first switch and the current path of the second switch at the second end, and the current path of the first switch is coupled between the first inductor and the first terminal of the voltage source. The second transformer includes a primary winding and a secondary winding, each having a first terminal and a second terminal respectively, and an isolator. The current paths of the seventh switch and the eighth switch are coupled to the first terminal of the secondary winding of the first transformer. A second capacitor is coupled between the second terminal of the primary winding of the second transformer at the first end and the current path of the second terminal of the voltage source at the second end and the fourth switch; and A second inductor is coupled between the first terminal of the primary winding of the second transformer at the first end and the current paths of the third and fourth switches at the second end, and the current path of the third switch is coupled between the first inductor and the first terminal of the voltage source.

15. The apparatus of claim 9, wherein the threshold corresponds to the maximum change in the phase delay per switching cycle of the second phase of the power converter controlled in response to the second pulse width modulation circuit relative to the first phase of the power converter controlled in response to the first pulse width modulation circuit.

16. An apparatus comprising: A first phase transformer includes a primary winding, a secondary winding, and an isolator, wherein the primary winding has a first terminal and a second terminal; The primary-side circuit of the first phase includes: A first inductor, which is coupled to the first terminal of the primary winding of the first phase transformer; First switch; A first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the second terminal of the primary winding of the first phase transformer; and A second switch has a first terminal and a second terminal, the first terminal of the second switch being coupled to the first switch and the first inductor, and the second terminal of the second switch being coupled to the second terminal of the first capacitor. The first phase secondary side circuit is coupled to the secondary winding of the first phase transformer; The second phase transformer includes a primary winding, a secondary winding, and an isolator. The second phase primary-side circuit includes: A second inductor, which is coupled to the first terminal of the primary winding of the second phase transformer; The third switch; A second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the second terminal of the primary winding of the second phase transformer; and A fourth switch having a first terminal and a second terminal, the first terminal of the fourth switch being coupled to the third switch and the second inductor, and the second terminal of the fourth switch being coupled to the second terminal of the second capacitor; The second phase secondary side circuit is coupled to the secondary winding of the second phase transformer; and A controller, coupled to the first phase primary-side circuit and the second phase primary-side circuit, is configured to: The primary-side circuit of the first phase is controlled in response to the duration of the switching cycle; The phase delay is determined in response to the duration of the switching cycle; and The second phase primary-side circuit is controlled in response to the phase delay.

17. The apparatus according to claim 16, It further includes a delay circuit coupled to the controller; The controller is configured to: The phase delay is compared with a threshold. The phase delay is adjusted in response to the comparison to produce an adjusted phase delay; and The second phase primary-side circuit is controlled using the delay circuit in response to the adjusted phase delay.

18. The apparatus of claim 17, wherein the threshold corresponds to the maximum change in the phase delay per switching cycle of the second phase primary-side circuit.

19. The apparatus of claim 16, further comprising a voltage sensor having a first input, a second input, and an output, the first input of the voltage sensor being coupled between the first phase primary-side circuit and the primary winding of the first phase transformer, the second input of the voltage sensor being coupled between the second phase primary-side circuit and the primary winding of the second phase transformer, and the output of the voltage sensor being coupled to the controller.

20. The apparatus of claim 16, wherein the apparatus comprises two or more phases, and the controller determines a phase delay for each phase other than the first phase in response to the plurality of phases.

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