Resonant wireless power transfer receiving chip based on hybrid inductor-capacitor buck rectifier topology and implementation method thereof

Abstract

The application discloses a resonant wireless energy transmission receiving chip based on a hybrid inductance-capacitance step-down rectification topology and an implementation method thereof, which comprises a control stage circuit and a power stage circuit. The control stage circuit is used for collecting a current sampling signal, converting, shaping and falling edge detecting the current sampling signal, generating a system clock signal, and then performing error amplification and phase shifting according to the system clock signal and an output voltage to generate a pulse width modulation signal and obtaining a gate control signal according to the pulse width modulation signal. The power stage circuit comprises a first hybrid step-down half-wave rectification converter and a second hybrid step-down half-wave rectification converter, which are respectively used for adjusting a second input voltage and a first input voltage according to the gate control signal, performing reverse current control on alternating current output by a receiving resonant loop, and realizing voltage stabilization of the output voltage. The application can realize large-current output, high conversion efficiency and wide band load range, and can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology and its implementation method. Background Technology

[0002] Wireless power transfer systems can flexibly power portable smart devices, increasing spatial freedom. In receiver chip design, traditional single-stage rectifier-regulator architectures can achieve high energy conversion efficiency, but their coil drive voltage is limited by the receiver's output voltage, restricting the system's output power. Buck-rectifier topologies can integrate buck and rectification into a single stage, improving conversion efficiency during high-current power transfer; however, existing technologies in hybrid buck-rectifier topologies cannot stabilize voltage under no-load conditions, limiting the load range. Summary of the Invention

[0003] To address the aforementioned technical problems, the purpose of this application is to provide a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology and its implementation method, achieving stable high-current output, high conversion efficiency, and wide bandwidth.

[0004] To achieve the above objectives, one aspect of this application proposes a resonant wireless power receiving chip based on a hybrid inductor-capacitor buck rectifier topology. The wireless power receiving chip is connected to a receiving resonant circuit, which receives wireless energy. The wireless power receiving chip converts the wireless energy into DC power. The wireless power receiving chip includes: The control stage circuit is connected to the receiving resonant circuit and is used to acquire the current sampling signal, convert, shape and detect the falling edge of the current sampling signal to generate a system clock signal, and then perform error amplification and phase shifting based on the system clock signal and the output voltage to generate a pulse width modulation signal, and obtain the gate control signal based on the pulse width modulation signal. The power stage circuit, connected to the receiving resonant circuit and the control stage circuit, includes a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, which are respectively used to adjust the second input voltage and the first input voltage according to the gate control signal, to perform reverse current control on the AC current output by the receiving resonant circuit, and to achieve voltage regulation of the output voltage.

[0005] In some embodiments, the control stage circuit includes: A rectifier current sampling circuit, connected to the power stage circuit, is used to sample the power transistor current of the power stage circuit to obtain the current sampling signal, and then convert the current sampling signal into a voltage signal. A zero-crossing detection circuit, connected to the rectifier current sampling circuit, is used to shape the voltage signal and generate a resonant current zero-crossing signal. A clock generation circuit, connected to the zero-crossing detection circuit, is used to detect the falling edge of the zero-crossing signal of the resonant current and generate the system clock signal.

[0006] In some embodiments, the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, and the control stage circuit further includes: A soft-start circuit, connected to the clock generation circuit, is used to generate a reference voltage value based on the system clock signal; The three-type compensator is connected to the soft-start circuit and the power stage circuit to amplify the error between the output voltage and the reference voltage value, and to perform frequency compensation on the loop to obtain a pulse width modulation control signal. A ramp generation circuit, connected to the clock generation circuit, is used to generate a first ramp signal and a second ramp signal based on the system clock signal. A pulse width modulation signal generation circuit, connected to the type-three compensator and the ramp generation circuit, is used to compare the pulse width modulation control signal with the first ramp signal and the second ramp signal respectively to obtain the first pulse width modulation signal and the second pulse width modulation signal. A gate signal generation signal is connected to the clock generation circuit and the pulse width modulation signal generation circuit, and is used to perform logical processing on the system clock signal, the first pulse width modulation signal and the second pulse width modulation signal to obtain the gate control signal. The first ramp signal and the second ramp signal have a phase difference of 180°, and the first pulse width modulation signal and the second pulse width modulation signal have the same duty cycle and a phase difference of 180°.

[0007] In some embodiments, the first hybrid buck half-wave rectifier converter includes a first power inductor, a first flying capacitor, a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor. One end of the first power transistor is connected to the second input voltage, and the other end of the first power transistor is grounded. One end of the second power transistor is connected between the second input voltage and the first power transistor, and the other end of the second power transistor is connected to one end of the first power inductor. The other end of the first power inductor is connected to one end of the fourth power transistor, and the other end of the fourth power transistor is connected to one end of the third power transistor. The other end of the third power transistor is grounded. One end of the first flying capacitor is connected between the second power transistor and the first power inductor, and the other end of the first flying capacitor is connected between the third power transistor and the fourth power transistor.

[0008] In some embodiments, the second hybrid buck half-wave rectifier converter includes a second power inductor, a second flying capacitor, a fifth power transistor, a sixth power transistor, a seventh power transistor, and an eighth power transistor. One end of the fifth power transistor is connected to the first input voltage, and the other end of the fifth power transistor is grounded. One end of the sixth power transistor is connected between the first input voltage and the fifth power transistor, and the other end of the sixth power transistor is connected to one end of the second power inductor. The other end of the second power inductor is connected to one end of the eighth power transistor, and the other end of the eighth power transistor is connected to one end of the seventh power transistor. The other end of the seventh power transistor is grounded. One end of the second flying capacitor is connected between the sixth power transistor and the second power inductor, and the other end of the second flying capacitor is connected between the seventh power transistor and the eighth power transistor.

[0009] In some embodiments, during a first operating phase, the fifth power transistor, the seventh power transistor, the second power transistor, and the fourth power transistor are turned on, the sixth power transistor, the eighth power transistor, the first power transistor, and the third power transistor are turned off, the first power inductor is magnetized, the second power inductor is demagnetized, the first flying capacitor is charged, the second flying capacitor is discharged, and the AC current flows into the first hybrid buck half-wave rectifier converter.

[0010] In some embodiments, during the second operating phase, the fifth power transistor, the seventh power transistor, the second power transistor, and the third power transistor are turned on, the sixth power transistor, the eighth power transistor, the first power transistor, and the fourth power transistor are turned off, the first power inductor and the second power inductor are demagnetized, the first flying capacitor and the second flying capacitor are discharged, and the alternating current flows to ground from the first hybrid buck half-wave rectifier converter through the fifth power transistor and the second power transistor.

[0011] In some embodiments, during the third operating phase, the sixth power transistor, the eighth power transistor, the first power transistor, and the third power transistor are turned on, the fifth power transistor, the seventh power transistor, the second power transistor, and the fourth power transistor are turned off, the first power inductor is demagnetized, the second power inductor is magnetized, the first flying capacitor is discharged, the second flying capacitor is charged, and the AC current flows into the second hybrid buck half-wave rectifier converter.

[0012] In some embodiments, during the fourth operating phase, the sixth power transistor, the seventh power transistor, the first power transistor, and the third power transistor are turned on, the fifth power transistor, the eighth power transistor, the second power transistor, and the fourth power transistor are turned off, the first power inductor and the second power inductor are demagnetized, the first flying capacitor and the second flying capacitor are discharged, and the alternating current flows to ground through the sixth power transistor and the first power transistor from the second hybrid buck half-wave rectifier converter.

[0013] To achieve the above objectives, another aspect of this application proposes a method for implementing a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology, the method comprising the following steps: The current sampling signal is acquired through the control stage circuit, and the current sampling signal is converted, shaped and falling edge detected to generate a system clock signal. Then, the error is amplified and phase-shifted according to the system clock signal and the output voltage to generate a pulse width modulation signal. The gate control signal is obtained according to the pulse width modulation signal. By using a power stage circuit comprising a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, the second input voltage and the first input voltage are adjusted according to the gate control signal, respectively, to reverse current control of the AC current output by the receiving resonant circuit, thereby achieving voltage regulation of the output voltage.

[0014] The beneficial effects of this application are as follows: This application discloses a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology and its implementation method. The wireless power receiver chip includes a control stage circuit and a power stage circuit. The control stage circuit is used to acquire current sampling signals, convert, shape, and detect the falling edge of the current sampling signals to generate a system clock signal. Then, based on the system clock signal and the output voltage, error amplification and phase shifting are performed to generate a pulse width modulation signal. The gate control signal is obtained based on the pulse width modulation signal. The power stage circuit includes a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, which are used to adjust the second input voltage and the first input voltage according to the gate control signal, respectively, to perform reverse current control on the AC current output by the receiving resonant circuit, and to achieve voltage stabilization of the output voltage. This application, through the proposed two-phase pulse width modulation technology and reverse current control technology, can achieve high current output, high conversion efficiency, and wide bandwidth. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a structural block diagram of a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology provided in one embodiment of this application; Figure 2 This is a circuit block diagram of a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology provided in one embodiment of this application. Figure 3 This is a schematic diagram illustrating the working principle of a hybrid buck rectifier converter provided in one embodiment of this application; Figure 4 This is a schematic diagram illustrating the relationship between the output current and the duty cycle of a buck rectifier converter provided in one embodiment of this application when the peak received current is 2A. Figure 5 A flowchart and key waveform diagram of a buck rectifier converter provided in one embodiment of this application; Figure 6 This is a structural block diagram of a wireless power transfer system provided in one embodiment of this application; Figure 7 The steady-state simulation waveform under heavy load is provided for an embodiment of this application with a coupling coefficient of 0.2. Figure 8 This is a steady-state simulation waveform diagram under no-load when the coupling coefficient is 0.2, provided in one embodiment of this application. Figure 9 A graph showing the relationship between receiver conversion efficiency and output current provided in one embodiment of this application; Figure 10 This is a schematic diagram illustrating the steps of a method for implementing a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology according to an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0018] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0019] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0020] Wireless power transfer systems can flexibly power portable smart devices, increasing spatial freedom. In receiver chip design, traditional single-stage rectifier-regulator architectures can achieve high energy conversion efficiency, but their coil drive voltage is limited by the receiver's output voltage, restricting the system's output power. Buck-rectifier topologies can integrate buck and rectification into a single stage, improving conversion efficiency during high-current power transfer; however, existing technologies in hybrid buck-rectifier topologies cannot stabilize voltage under no-load conditions, limiting the load range.

[0021] First, the traditional single-stage rectification and voltage regulation architecture integrates rectification and voltage regulation in a single stage, reducing cascading losses and improving system efficiency. However, the voltage across the receiver's resonant cavity is limited by the set output voltage value, resulting in a generally high reflective impedance and limited output power. This forces the system to increase the upper limit of output power by increasing the transmit voltage, leading to a larger receive current amplitude at the receiver and a significant increase in losses, thus reducing system efficiency during high-power energy transfer. Therefore, in wireless power receivers using the traditional single-stage rectification and voltage regulation architecture, there is a trade-off between increasing output power and maintaining high energy conversion efficiency.

[0022] Secondly, existing hybrid buck rectifier topologies have significant limitations in their control methods. Although phase switching can reduce the received power, the current at the receiver flows entirely into the load in each phase, causing the voltage regulation function of the circuit to fail under light loads. Furthermore, the idling mode in traditional single-stage architectures leads to an unbalanced current and charge state in passive devices in hybrid architectures, affecting system stability.

[0023] In view of this, this application proposes a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology. The wireless power receiver chip includes a control stage circuit and a power stage circuit. The control stage circuit is used to acquire current sampling signals, convert, shape, and detect the falling edge of the current sampling signals to generate a system clock signal. Then, it compares and phase-shifts the system clock signal and the output voltage to generate a pulse width modulation signal, and obtains a gate control signal from the pulse width modulation signal. The power stage circuit includes a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, which are used to adjust the second input voltage and the first input voltage according to the gate control signal, respectively, to perform reverse current control on the AC current output by the receiving resonant circuit, and to achieve voltage stabilization of the output voltage. This application can achieve high current output, high conversion efficiency, and wide bandwidth by proposing two-phase pulse width modulation technology and reverse current control technology.

[0024] Reference Figure 1 , Figure 1 This is a structural block diagram of a resonant wireless power receiving chip based on a hybrid inductor-capacitor buck rectifier topology provided in one embodiment of this application. This embodiment proposes a resonant wireless power receiving chip based on a hybrid inductor-capacitor buck rectifier topology. The wireless power receiving chip is connected to a receiving resonant circuit, which receives wireless energy. The wireless power receiving chip converts the wireless energy into DC power. The wireless power receiving chip includes: The control stage circuit is connected to the receiving resonant circuit. It is used to acquire the current sampling signal, convert, shape and detect the falling edge of the current sampling signal to generate the system clock signal, and then perform error amplification and phase shifting based on the system clock signal and the output voltage to generate the pulse width modulation signal. The gate control signal is obtained based on the pulse width modulation signal. The power stage circuit, connected to the receiving resonant circuit and the control stage circuit, includes a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, which are used to adjust the second input voltage and the first input voltage according to the gate control signal, respectively, to perform reverse current control on the AC current output by the receiving resonant circuit, and to achieve voltage regulation of the output voltage.

[0025] Reference Figure 2 , Figure 2The circuit block diagram of a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology provided in one embodiment of this application is further illustrated in the optional implementation, where the control stage circuit includes: The rectifier current sampling circuit is connected to the power stage circuit and is used to sample the current of the power transistor in the power stage circuit to obtain a current sampling signal, which is then converted into a voltage signal. The zero-crossing detection circuit, connected to the rectifier current sampling circuit, is used to shape the voltage signal and generate a resonant current zero-crossing signal. The clock generation circuit, connected to the zero-crossing detection circuit, is used to detect the falling edge of the zero-crossing signal of the resonant current and generate the system clock signal.

[0026] Reference Figure 2 As an optional implementation, the pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, and the control stage circuit further includes: The soft-start circuit, connected to the clock generation circuit, is used to generate a reference voltage value based on the system clock signal. The three-type compensator is connected to the soft-start circuit and the power stage circuit to amplify the error of the output voltage and reference voltage values, and to perform frequency compensation of the loop to obtain the pulse width modulation control signal. The ramp generation circuit, connected to the clock generation circuit, is used to generate a first ramp signal and a second ramp signal based on the system clock signal. The pulse width modulation signal generation circuit is connected to the three-type compensator and the ramp generation circuit. It is used to compare the pulse width modulation control signal with the first ramp signal and the second ramp signal respectively to obtain the first pulse width modulation signal and the second pulse width modulation signal. The gate signal generation signal is connected to the clock generation circuit and the pulse width modulation signal generation circuit. It is used to perform logical processing on the system clock signal, the first pulse width modulation signal and the second pulse width modulation signal to obtain the gate control signal. The first ramp signal and the second ramp signal have a phase difference of 180°, and the first pulse width modulation signal and the second pulse width modulation signal have the same duty cycle and a phase difference of 180°.

[0027] Specifically, the wireless power transmission and receiving chip proposed in this application mainly consists of a control stage circuit and a power stage circuit. In the control stage circuit, the rectifier current sampling circuit samples the fifth power transistor S in the power stage circuit. 1L and the first power transistor S 1R The current is sampled to obtain the current sampling signal I. SEN and the current sampling signal I SEN Converted to voltage signal V SEN Voltage signal V SENThe zero-crossing signal V of the resonant current is obtained by inputting it into the zero-crossing detection circuit. ZCD The clock generation circuit generates the zero-crossing signal V of the resonant current. ZCD The falling edge of the signal is detected to obtain a system clock signal V with a frequency of 6.78MHz and a duty cycle of 0.5. CLK The soft-start circuit detected the system clock signal V. CLK Then, a gradually increasing reference voltage value V is generated. REF Achieve output voltage V OUT The slow rise of the output voltage V enables a soft start for the system; OUT and reference voltage value V REF Error amplification is performed in the three-type compensator, and the output pulse width modulation control signal V is output. EA System clock signal V CLK In the ramp generation circuit, a first ramp signal V with a two-phase phase difference of 180° is triggered and generated. RAMP1 Second ramp signal V RAMP2 The pulse width modulation signal generation circuit generates the first ramp signal V. RAMP1 Second ramp signal V RAMP2 With pulse width modulation control signal V EA By comparison, two first pulse width modulation signals V with the same duty cycle and a phase offset of 180° are obtained. DUTY1 Second pulse width modulation signal V DUTY2 The first pulse width modulation signal V is generated by the gate signal generation circuit. DUTY1 The second pulse width modulation signal V DUTY2 and system clock signal V CLK After logical processing, S can be obtained. 1R -S 4R and S 1L -S 4L Gate control signals for eight power transistors.

[0028] Reference Figure 2 As a further optional implementation, the first hybrid buck half-wave rectifier converter includes a first power inductor, a first flying capacitor, a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor. One end of the first power transistor is used to connect to the second input voltage, and the other end of the first power transistor is grounded. One end of the second power transistor is connected between the second input voltage and the first power transistor, and the other end of the second power transistor is connected to one end of the first power inductor. The other end of the first power inductor is connected to one end of the fourth power transistor, and the other end of the fourth power transistor is connected to one end of the third power transistor. The other end of the third power transistor is grounded. One end of the first flying capacitor is connected between the second power transistor and the first power inductor, and the other end of the first flying capacitor is connected between the third power transistor and the fourth power transistor.

[0029] Reference Figure 2 As a further optional implementation, the second hybrid buck half-wave rectifier converter includes a second power inductor, a second flying capacitor, a fifth power transistor, a sixth power transistor, a seventh power transistor, and an eighth power transistor. One end of the fifth power transistor is connected to the first input voltage, and the other end of the fifth power transistor is grounded. One end of the sixth power transistor is connected between the first input voltage and the fifth power transistor, and the other end of the sixth power transistor is connected to one end of the second power inductor. The other end of the second power inductor is connected to one end of the eighth power transistor, and the other end of the eighth power transistor is connected to one end of the seventh power transistor. The other end of the seventh power transistor is grounded. One end of the second flying capacitor is connected between the sixth power transistor and the second power inductor, and the other end of the second flying capacitor is connected between the seventh power transistor and the eighth power transistor.

[0030] Specifically, in the power stage circuit, the first power transistor, the second power transistor, the third power transistor, and the fourth power transistor (S) 1R S 2R S 3R S 4R ) and the fifth power transistor, sixth power transistor, seventh power transistor and eighth power transistor (S 1L S 2L S 3L S 4L Each of them constitutes a pair of identical hybrid buck half-wave rectifier converters, S 1R -S 4R This constitutes branch 1 (i.e., the first hybrid buck half-wave rectifier converter), S 1L -S 4L This constitutes branch 2 (i.e., the second hybrid buck half-wave rectifier converter), with the two branches connected to the input terminal V respectively. IN2 and V IN1 Together, they form a hybrid buck full-wave rectifier-converter. By adjusting the first input voltage V... IN1 Second input voltage V IN2 The voltage value, while rectifying the AC current input to the receiving resonant circuit, simultaneously achieves the regulation of the output voltage V. OUT Voltage stabilization.

[0031] Furthermore, in the off-chip portion, the first power inductor L1, the second power inductor L2, and the first flying capacitor C F1 Second flying capacitor C F2 Together with the on-chip power transistor, it forms a hybrid buck rectifier converter. The receiving coil inductance L... RX and receiving compensation capacitor C RX It forms a receiving resonant circuit to receive the wireless energy transmitted from the transmitting resonant circuit and power the subsequent receiving chip and load.

[0032] Reference Figure 3 , Figure 3 This is a schematic diagram of the working principle of a hybrid buck rectifier converter provided in one embodiment of this application. Further, as an optional implementation, in the first working stage, the fifth power transistor, the seventh power transistor, the second power transistor, and the fourth power transistor are turned on, the sixth power transistor, the eighth power transistor, the first power transistor, and the third power transistor are turned off, the first power inductor is magnetized, the second power inductor is demagnetized, the first flying capacitor is charged, the second flying capacitor is discharged, and the AC current flows into the first hybrid buck half-wave rectifier converter.

[0033] Reference Figure 3 As an optional implementation, in the second operating phase, the fifth, seventh, second, and third power transistors are turned on, the sixth, eighth, first, and fourth power transistors are turned off, the first and second power inductors are demagnetized, the first and second flying capacitors are discharged, and the alternating current flows to ground through the fifth and second power transistors from the first hybrid buck half-wave rectifier converter.

[0034] Reference Figure 3 As an optional implementation, in the third operating phase, the sixth power transistor, the eighth power transistor, the first power transistor, and the third power transistor are turned on, the fifth power transistor, the seventh power transistor, the second power transistor, and the fourth power transistor are turned off, the first power inductor is demagnetized, the second power inductor is magnetized, the first flying capacitor is discharged, the second flying capacitor is charged, and the AC current flows into the second hybrid buck half-wave rectifier converter.

[0035] Reference Figure 3 As an optional implementation, in the fourth operating phase, the sixth power transistor, the seventh power transistor, the first power transistor, and the third power transistor are turned on, the fifth power transistor, the eighth power transistor, the second power transistor, and the fourth power transistor are turned off, the first power inductor and the second power inductor are demagnetized, the first flying capacitor and the second flying capacitor are discharged, and the alternating current flows to ground through the sixth power transistor and the first power transistor from the second hybrid buck half-wave rectifier converter.

[0036] It is understandable that, such as Figure 3 As shown, the wireless power receiving chip cycles through different operating stages in the order of 1→2→3→4→1. If we divide the operation by the charging / demagnetizing of the power inductor, the first operating stage 1 corresponds to the charging stage of the first power inductor L1, which is also the charging stage of the fourth power transistor S. 4R The conduction time corresponds to the duty cycle D1. The second operating stage 2, the third operating stage 3, and the fourth operating stage 4 correspond to the demagnetization stage of the first power inductor L1; the third operating stage 3 corresponds to the magnetization stage of the second power inductor L2, which is also the eighth power transistor S. 4LThe conduction time corresponds to the duty cycle D2. The first operating stage 1, the second operating stage 2, and the fourth operating stage 4 correspond to the demagnetization stage of the second power inductor L2. The second operating stage 2, the third operating stage 3, the first operating stage 1, and the fourth operating stage 4 correspond to the two half-cycles when the input AC current is positive and negative, respectively. Therefore, the duty cycles D1 and D2 do not exceed 0.5 at most.

[0037] Specifically, in the first working phase 1, the fifth power transistor S 1L Seventh power transistor S 3L Second power transistor S 2R Fourth power transistor S 4R The sixth power transistor S is turned on. 2L Eighth power transistor S 4L First power transistor S 1R Third power transistor S 3R When switched off, the first power inductor L1 is magnetized, the second power inductor L2 is demagnetized, and the first flying capacitor C... F1 Charging, the voltage at both ends is V RX1 -V OUT The second flying capacitor C F2 Discharge, voltage across terminals is V RX2 The resonant current flows into branch 1.

[0038] When the input current switches from positive to negative, the converter switches to the second operating stage 2, and the fifth power transistor S... 1L Seventh power transistor S 3L Second power transistor S 2R Third power transistor S 3R The sixth power transistor S is turned on. 2L Eighth power transistor S 4L First power transistor S 1R Fourth power transistor S 4R When switched off, both the first power inductor L1 and the second power inductor L2 are demagnetized, and the first flying capacitor C... F1 Second flying capacitor C F2 Both terminals are discharged, and the voltage across them is V. RX1 / V RX2 Because the receiving resonant current is reversed, the receiving current flows from branch 1 through the fifth power transistor S. 1L Second power transistor S 2R It flows to the ground.

[0039] The third operating phase 3 / fourth operating phase 4 is based on the same principle as the first operating phase 1 / second operating phase 2, except that the power transistors in the two buck half-bridge rectifier branches are switched in reverse. In the third operating phase 3, the sixth power transistor S... 2L Eighth power transistor S 4L First power transistor S1R Third power transistor S 3R Turn on, fifth power transistor S 1L Seventh power transistor S 3L Second power transistor S 2R Fourth power transistor S 4R When switched off, the first power inductor L1 is demagnetized, the second power inductor L2 is magnetized, and the first flying capacitor C... F1 Discharge, voltage across terminals is V RX1 The second flying capacitor C F2 Charging, the voltage at both ends is V RX2 -V OUT The resonant current flows into branch 2.

[0040] When the input current switches from negative to positive, the converter switches to the fourth operating stage, and the sixth power transistor S... 2L Seventh power transistor S 3L First power transistor S 1R Third power transistor S 3R Turn on, fifth power transistor S 1L Eighth power transistor S 4L Second power transistor S 2R Fourth power transistor S 4R When switched off, both the first power inductor L1 and the second power inductor L2 are demagnetized, and the first flying capacitor C... F1 Second flying capacitor C F2 Both terminals are discharged, and the voltage across them is V. RX1 / V RX2 Because the receiving resonant current is reversed, the receiving current flows from branch 2 through the sixth power transistor S. 2L and the first power transistor S 1R It flows to the ground.

[0041] Assuming the duty cycle of branch 1 and branch 2 is D, the following formula can be derived based on the volt-second balance of the first power inductor L1: ; The above formula yields the value of the step-down rectifier converter from V. RX1 To V OUT The rotation ratio M is: ; Through the first flying capacitor C F1 The charge balance can be expressed as follows: ; The current I on the first power inductor L1 in branch 1 can be obtained from the above formula. L1 With the peak value of the received current I RX The relationship between the duty cycle D and the duty cycle D is: ; Therefore, we can obtain that when the peak value of the received current is I... RX When the duty cycle is D, the total output current I OUT for: .

[0042] Furthermore, such as Figure 4 The diagram shows the relationship between the output current and duty cycle of a buck rectifier converter when the peak received current is 2A. Figure 4 It can be seen that no-load output can be achieved with a duty cycle of 0.188, and maximum current output can be achieved with a duty cycle of 0.475. Therefore, V RX1 and V RX2 It can be approximated as two functions with a duty cycle of D and an amplitude of (2-D)V. OUT A square wave signal with a frequency of 6.78MHz, with a phase difference of 180°, can maintain the output signal V under heavy load. IN1 and V IN2 For an extended period of time, the voltage is higher than the output voltage V. OUT .

[0043] like Figure 5 The diagram shows the workflow and key waveforms of a buck rectifier converter. Figure 5 It can be seen that the current sampling circuit has an input current I IN When crossing zero, the zero-crossing detection signal V will be... ZCD Reset to low level, the clock generation circuit at each V ZCD The falling edge will trigger the system clock signal V. CLK The flipping mechanism achieves a 0.5 duty cycle, 6.78MHz system clock signal V. CLK System clock signal V CLK V is set on the rising and falling edges respectively. RAMP1 and V RAMP2 This generates a ramp wave with a phase difference of 180° between the two phases.

[0044] When I LOAD Under heavy load, the output current I OUT Calculation formula and Figure 4 It can be known that the duty cycle is approximately 0.5, therefore the fifth power transistor S... 1L and the first power transistor S 1R The circuit's on and off states are basically aligned with the zero-crossing current, so the circuit switches between the first operating stage 1 and the third operating stage 3. The first input voltage V IN1 Second input voltage V IN2 The high-level voltage value is approximately 1.5 times the output voltage V. OUT Compared to traditional single-stage regulated rectifier receivers, the coil drive voltage is higher, which can achieve greater output power.

[0045] When I LOAD After switching to a light load, the output voltage V OUT The overshoot is generated by the pulse width modulation control signal V output by the type-three compensator. EA The first pulse width modulation signal V decreases. DUTY1 Second pulse width modulation signal V DUTY2 The duty cycle decreases accordingly, causing the demagnetization phases of the first power inductor L1 and the second power inductor L2 to overlap. Therefore, the second operating phase 2 and the fourth operating phase 4 are introduced. This occurs in the fifth power transistor S. 1L and the sixth power transistor S 2L A reverse current is introduced to regulate the current flowing out of the converter to accommodate a smaller load current. The first output voltage V under light load... IN1 Second output voltage V IN2 It exhibits a stepped waveform, with the highest voltage value being (2-D)*V. OUT The intermediate voltage value is the first flying capacitor C. F1 Second flying capacitor C F2 Voltage (1-D)*V OUT Under light load, the working stages will cycle through in the order of 1→2→3→4→1.

[0046] In summary, as Figure 6 The diagram shows the structural block diagram of a wireless power transfer system, which uses the wireless power receiving chip proposed in the embodiments of this application. The transmitting resonant circuit is an inductor L. TX With capacitor C TX The series resonance is driven by a wireless power transmitter for frequency selection and power transmission. The receiving resonant circuit is an inductor L. RX With capacitor C RX The series resonance of the circuit has a coupling coefficient of k between the resonant circuits. F1 / C F2 L1 and L2 are the flying capacitor and power inductor that constitute the power stage. V OUT For the load voltage, C O For the output capacitor, R LOAD This is the load resistance.

[0047] The effectiveness of the resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology in the embodiments of this application is explained below.

[0048] like Figure 7 The figure shows the steady-state simulation waveform under heavy load with a coupling coefficient of 0.2. Figure 8 The figure shows the steady-state simulation waveform under no-load conditions with a coupling coefficient of 0.2. Figure 7 and Figure 8It can be seen that the voltage can be effectively regulated and a stable output voltage can be achieved under both large and zero load current conditions, and the first input voltage V IN1 Second input voltage V IN2 The high level must be higher than the output voltage V. OUT Therefore, the voltage reduction function was successfully implemented and power was transferred to the load. Under heavy load, the duty cycle is close to 50%, while under light load, due to the delay in zero-crossing detection, the duty cycle is higher than the theoretical value, at about 30%.

[0049] like Figure 9 The figure shows the relationship between the receiver's conversion efficiency and the output current. Figure 9 As can be seen, in the embodiment of this application, with an 8V transmitting voltage and a Class D full-bridge inverter for the transmitting circuit, the conversion efficiency with a coupling coefficient of 0.2 was simulated, and a maximum load of 2A was achieved, at which point a peak conversion efficiency of 91.8% was reached.

[0050] The structure, working principle, and workflow of the resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology in this application have been described above. It can be recognized that the embodiments of this application have the following advantages: I. A hybrid buck converter topology is proposed, which integrates a hybrid DC-DC buck converter and a full-wave rectifier bridge into a single stage by merging power transistors. Under maximum output power, the output node voltage of the full-wave rectifier bridge can reach nearly 1.5 times the output voltage, reducing the reflected impedance, increasing the output power, reducing the current amplitude on the receiving coil at the same power level, reducing coil copper losses, and improving conversion efficiency.

[0051] Second, a control strategy combining two-phase pulse width modulation (PWM) and reverse current control is proposed. A pair of PWM signals are generated by phase shifting, controlling the step-down power transistors to conduct sequentially with a duty cycle of less than 50%, achieving a relatively stable high differential voltage value at the rectifier bridge output node. By triggering the rectifier transistors to maintain their conduction time at 50% using the two-phase duty cycle signals, a phase shifting effect relative to the input current is achieved. This reduces the input power when the load current decreases, realizing voltage regulation across the entire load range.

[0052] Furthermore, in addition to the circuit structure and method mentioned in the above embodiments, the present application can also make the following modifications: 1. The form of the transmitting inverter is not limited to Class D full bridge; Class D half bridge and Class E inverters can also achieve energy transmission.

[0053] 2. The transmitting voltage, coil distance, and coupling coefficient can be designed and changed to meet different power requirements.

[0054] 3. The proposed wireless receiver chip can not only realize wireless power transmission in a single-transmitter-single-receiver system, but is also suitable for single-transmitter-multiple-receiver systems.

[0055] Reference Figure 10 This application provides a method for implementing a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology. The method includes the following steps S101 to S102: Step S101: The current sampling signal is acquired through the control stage circuit, and the current sampling signal is converted, shaped and falling edge detected to generate a system clock signal. Then, the error is amplified and phase shifted according to the system clock signal and the output voltage to generate a pulse width modulation signal. The gate control signal is obtained according to the pulse width modulation signal. Step S102: Through the power stage circuit including the first hybrid buck half-wave rectifier converter and the second hybrid buck half-wave rectifier converter, the second input voltage and the first input voltage are adjusted according to the gate control signal, respectively, to perform reverse current control on the AC current output by the receiving resonant circuit, and to achieve voltage regulation of the output voltage.

[0056] The contents of the above wireless power receiving chip embodiments are all applicable to the implementation method embodiments. The specific functions implemented by the implementation method embodiments are the same as those of the above wireless power receiving chip embodiments, and the beneficial effects achieved are also the same as those achieved by the above wireless power receiving chip embodiments.

[0057] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0058] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0059] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A resonant wireless power transmission and reception chip based on a hybrid inductor-capacitor buck rectifier topology, characterized in that, The wireless power receiving chip is connected to a receiving resonant circuit, the receiving resonant circuit is used to receive wireless energy, and the wireless power receiving chip is used to convert the wireless energy into DC power. The wireless power receiving chip includes: The control stage circuit is connected to the receiving resonant circuit and is used to acquire the current sampling signal, convert, shape and detect the falling edge of the current sampling signal to generate a system clock signal, and then perform error amplification and phase shifting based on the system clock signal and the output voltage to generate a pulse width modulation signal, and obtain the gate control signal based on the pulse width modulation signal. The power stage circuit, connected to the receiving resonant circuit and the control stage circuit, includes a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, which are respectively used to adjust the second input voltage and the first input voltage according to the gate control signal, to perform reverse current control on the AC current output by the receiving resonant circuit, and to achieve voltage regulation of the output voltage.

2. The wireless power transmission and reception chip according to claim 1, characterized in that, The control stage circuit includes: A rectifier current sampling circuit, connected to the power stage circuit, is used to sample the power transistor current of the power stage circuit to obtain the current sampling signal, and then convert the current sampling signal into a voltage signal. A zero-crossing detection circuit, connected to the rectifier current sampling circuit, is used to shape the voltage signal and generate a resonant current zero-crossing signal. A clock generation circuit, connected to the zero-crossing detection circuit, is used to detect the falling edge of the zero-crossing signal of the resonant current and generate the system clock signal.

3. The wireless power transmission and reception chip according to claim 2, characterized in that, The pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, and the control stage circuit further includes: A soft-start circuit, connected to the clock generation circuit, is used to generate a reference voltage value based on the system clock signal; The three-type compensator is connected to the soft-start circuit and the power stage circuit to amplify the error between the output voltage and the reference voltage value, and to perform frequency compensation on the loop to obtain a pulse width modulation control signal. A ramp generation circuit, connected to the clock generation circuit, is used to generate a first ramp signal and a second ramp signal based on the system clock signal. A pulse width modulation signal generation circuit, connected to the type-three compensator and the ramp generation circuit, is used to compare the pulse width modulation control signal with the first ramp signal and the second ramp signal respectively to obtain the first pulse width modulation signal and the second pulse width modulation signal. A gate signal generation signal is connected to the clock generation circuit and the pulse width modulation signal generation circuit, and is used to perform logical processing on the system clock signal, the first pulse width modulation signal and the second pulse width modulation signal to obtain the gate control signal. The first ramp signal and the second ramp signal have a phase difference of 180°, and the first pulse width modulation signal and the second pulse width modulation signal have the same duty cycle and a phase difference of 180°.

4. The wireless power transmission and reception chip according to claim 1, characterized in that, The first hybrid buck half-wave rectifier converter includes a first power inductor, a first flying capacitor, a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor. One end of the first power transistor is connected to the second input voltage, and the other end of the first power transistor is grounded. One end of the second power transistor is connected between the second input voltage and the first power transistor, and the other end of the second power transistor is connected to one end of the first power inductor. The other end of the first power inductor is connected to one end of the fourth power transistor, and the other end of the fourth power transistor is connected to one end of the third power transistor. The other end of the third power transistor is grounded. One end of the first flying capacitor is connected between the second power transistor and the first power inductor, and the other end of the first flying capacitor is connected between the third power transistor and the fourth power transistor.

5. The wireless power transmission and reception chip according to claim 4, characterized in that, The second hybrid buck half-wave rectifier converter includes a second power inductor, a second flying capacitor, a fifth power transistor, a sixth power transistor, a seventh power transistor, and an eighth power transistor. One end of the fifth power transistor is connected to the first input voltage, and the other end of the fifth power transistor is grounded. One end of the sixth power transistor is connected between the first input voltage and the fifth power transistor, and the other end of the sixth power transistor is connected to one end of the second power inductor. The other end of the second power inductor is connected to one end of the eighth power transistor, and the other end of the eighth power transistor is connected to one end of the seventh power transistor. The other end of the seventh power transistor is grounded. One end of the second flying capacitor is connected between the sixth power transistor and the second power inductor, and the other end of the second flying capacitor is connected between the seventh power transistor and the eighth power transistor.

6. The wireless power transmission and reception chip according to claim 5, characterized in that, In the first operating phase, the fifth power transistor, the seventh power transistor, the second power transistor, and the fourth power transistor are turned on, the sixth power transistor, the eighth power transistor, the first power transistor, and the third power transistor are turned off, the first power inductor is magnetized, the second power inductor is demagnetized, the first flying capacitor is charged, the second flying capacitor is discharged, and the AC current flows into the first hybrid buck half-wave rectifier converter.

7. The wireless power transmission and reception chip according to claim 5, characterized in that, In the second operating phase, the fifth power transistor, the seventh power transistor, the second power transistor, and the third power transistor are turned on, while the sixth power transistor, the eighth power transistor, the first power transistor, and the fourth power transistor are turned off. The first power inductor and the second power inductor are both demagnetized, and the first flying capacitor and the second flying capacitor are both discharged. The alternating current flows to ground from the first hybrid buck half-wave rectifier converter through the fifth power transistor and the second power transistor.

8. The wireless power transmission and reception chip according to claim 5, characterized in that, In the third operating phase, the sixth power transistor, the eighth power transistor, the first power transistor, and the third power transistor are turned on, the fifth power transistor, the seventh power transistor, the second power transistor, and the fourth power transistor are turned off, the first power inductor is demagnetized, the second power inductor is magnetized, the first flying capacitor is discharged, the second flying capacitor is charged, and the AC current flows into the second hybrid buck half-wave rectifier converter.

9. The wireless power transmission and reception chip according to claim 5, characterized in that, In the fourth operating phase, the sixth power transistor, the seventh power transistor, the first power transistor, and the third power transistor are turned on, while the fifth power transistor, the eighth power transistor, the second power transistor, and the fourth power transistor are turned off. The first power inductor and the second power inductor are both demagnetized, and the first flying capacitor and the second flying capacitor are both discharged. The alternating current flows to ground through the sixth power transistor and the first power transistor from the second hybrid buck half-wave rectifier converter.

10. A method for implementing a resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology, used to implement the resonant wireless power receiver chip based on a hybrid inductor-capacitor buck rectifier topology as described in any one of claims 1 to 9, characterized in that, The method includes the following steps: The current sampling signal is acquired through the control stage circuit, and the current sampling signal is converted, shaped and falling edge detected to generate a system clock signal. Then, the error is amplified and phase-shifted according to the system clock signal and the output voltage to generate a pulse width modulation signal. The gate control signal is obtained according to the pulse width modulation signal. By using a power stage circuit comprising a first hybrid buck half-wave rectifier converter and a second hybrid buck half-wave rectifier converter, the second input voltage and the first input voltage are adjusted according to the gate control signal, respectively, to reverse current control of the AC current output by the receiving resonant circuit, thereby achieving voltage regulation of the output voltage.

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