Solid state transformer rectification mode control method

Abstract

This disclosure relates to a solid-state transformer rectification mode control method. The method includes: a system controller sending a start-up command to each module controller; the system controller executing outer-loop voltage control and inner-loop current control to generate a reference modulation wave for each power module, and performing module-level equalization and phase-to-phase equalization based on the input voltage of the cascaded H-bridge of each power module to generate a corrected modulation wave and sending it to each module controller; each module controller generating a target shift ratio for the dual active bridge DAB based on the input voltage and input current of each cascaded H-bridge; and the FPGA corresponding to each module controller generating drive pulses for the dual active bridge DAB based on the target shift ratio to drive the switching transistors of the dual active bridge DAB, and generating drive pulses for the cascaded H-bridge based on the corrected modulation wave to drive the switching transistors of the cascaded H-bridge. This disclosure ensures the stable operation of the solid-state transformer on the rectifier side under drag test conditions.

Description

Technical Field

[0001] This disclosure relates to the field of solid-state transformer technology, and in particular to a solid-state transformer rectification mode control method. Background Technology

[0002] In related technologies, solid state transformers (SSTs) include a two-stage isolated topology that combines cascaded H-bridges and dual active bridges (DABs). During the factory commissioning and system integration of SSTs, the performance of the equipment is usually verified by a full-load drive test, in which two SSTs are directly connected on the low-voltage DC side, one operating in rectification mode and the other operating in inverter mode.

[0003] However, existing control strategies are mainly designed for conventional grid-connected operating conditions, and face the following problems in the rectifier mode of drag-and-drop experiments: single-stage topology control methods only target the cascaded H-bridge rectifier stage and cannot solve the inter-stage coupling control problem after the introduction of the DAB isolation stage; the role division between the H-bridge and DAB in the traditional control architecture cannot adapt to the need for interchangeable control objectives in drag-and-drop experiments; existing equalization methods have limited granularity and lack a systematic voltage equalization architecture from the module level to the phase level; and the inrush current suppression strategy during the startup process of the cascaded topology is still imperfect. These problems restrict the reliable application of isolated SST in drag-and-drop experimental scenarios. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a solid-state transformer rectification mode control method.

[0005] According to a first aspect of the present disclosure, a solid-state transformer rectification mode control method is provided, applied to a dual-drive experimental system. The dual-drive experimental system includes a first solid-state transformer and a second solid-state transformer, the low-voltage DC side buses of the first solid-state transformer and the second solid-state transformer are directly connected, the first solid-state transformer operates in rectification mode, the first solid-state transformer includes a system controller, multiple module controllers, and multiple power modules, each power module including a cascaded H-bridge and a dual active bridge (DAB), the method comprising: The system controller controls the drive pulses of each H-bridge to turn off, so that the bus capacitors on the DC side of each H-bridge are pre-charged through the anti-parallel diodes of each H-bridge. After the voltage of each bus capacitor reaches the preset threshold, the system controller sends a start command to each module controller to put it into operation. The system controller performs outer loop control of the overall voltage and inner loop control of the current based on the input voltage of all cascaded H-bridges in the first solid-state transformer, generates a reference modulation wave for each power module, and performs module-level equalization processing and phase-to-phase equalization processing based on the input voltage of the cascaded H-bridges of each power module, generating a corrected modulation wave and sending it to each module controller. After receiving the start command, each module controller generates a target shift ratio for each dual active bridge DAB based on the input voltage and input current of each cascaded H-bridge in its plane; wherein, each power module includes two symmetrical planes, each plane including two cascaded H-bridges and two dual active bridge DABs; For each module controller, the FPGA corresponding to the module controller generates a drive pulse for the dual active bridge DAB according to the target shift ratio to drive the switching transistors of the dual active bridge DAB, and generates a drive pulse for the cascaded H-bridge according to the modified modulation wave to drive the switching transistors of the cascaded H-bridge.

[0006] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: By shutting off the drive pulses of each cascaded H-bridge during the startup phase, using anti-parallel diodes for pre-charging, and sending the startup command only after reaching the threshold, the inrush current at the moment of power-on is effectively suppressed, realizing safe soft-start of the cascaded topology; By generating a reference modulation wave based on the outer loop of the whole machine voltage and the inner loop of the current in the system controller, and then performing module-level equalization and phase-to-phase equalization on this basis and sending a correction modulation wave, the step-by-step voltage equalization from within the module to between phases is realized, solving the problem of voltage imbalance caused by parameter differences; By having each module controller independently generate the target shift ratio of each DAB based on the H-bridge voltage and current in its plane after receiving the startup command, and having each FPGA generate DAB drive pulses based on the shift ratios and generate H-bridge drive pulses based on the correction modulation waves, the hierarchical responsibilities of the system controller and the module controller are clarified, so that the DAB undertakes the input-side voltage regulation task in rectification mode, and the H-bridge undertakes the output voltage regulation task, adapting to the working condition requirements of the control role reversal in the drag experiment.

[0007] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] Figure 1 This is a flowchart illustrating a solid-state transformer rectification mode control method according to an exemplary embodiment.

[0010] Figure 2 This is a topology diagram of a solid-state transformer system according to an exemplary embodiment. Detailed Implementation

[0011] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure.

[0012] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms unless the context clearly indicates otherwise.

[0013] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of embodiments of this disclosure, and similarly, second information may also be referred to as first information. Depending on the context, the words “if” and “suppose” as used herein may be interpreted as “when”, “when”, or “in response to a determination”.

[0014] Furthermore, various forms of processes shown in the embodiments of this disclosure can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0015] It should be noted that the collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0016] In the following specific embodiments of this disclosure, the English abbreviations are explained as follows: SST stands for Solid State Transformer; CHB stands for Cascaded H-Bridge; DAB stands for Dual Active Bridge; DSP stands for Digital Signal Processor; FPGA stands for Field-Programmable Gate Array; PWM stands for Pulse Width Modulation; SPWM stands for Sinusoidal Pulse Width Modulation; PI controller stands for Proportional-Integral Controller; ESR stands for Equivalent Series Resistance.

[0017] The control method proposed in this disclosure can be applied to a 35kV cascaded H-bridge dual active bridge (DAB) solid-state transformer (SST). For example... Figure 2 As shown, the solid-state transformer consists of 36 identical power modules, divided into three phases (A, B, and C). The H-bridge AC outputs of 12 power modules per phase are connected in series and then connected to the grid via a grid-connected reactor. Each power module is internally divided into two symmetrical planes, A and B, each containing two DAB isolation converters and two H-bridges. The module controller for each power module is based on a digital signal processor (DSP) and paired with two field-programmable gate arrays (FPGAs): the low-voltage side FPGA generates pulse-width modulation (PWM) pulses for the DAB low-voltage side switches, while the high-voltage side FPGA generates PWM pulses for the DAB high-voltage side and all H-bridge switches. The system controller is independent of the power modules and communicates point-to-multipoint with the module controllers of all power modules via a high-speed FPGA ring network. The communication cycle can be 50 microseconds, ensuring control synchronization.

[0018] Figure 1 This is a flowchart illustrating a solid-state transformer rectification mode control method according to an exemplary embodiment, such as... Figure 1As shown, it should be noted that this disclosure is applied to a towing test system, which includes a first solid-state transformer and a second solid-state transformer. The low-voltage DC side buses of the first and second solid-state transformers are directly connected. The first solid-state transformer operates in rectification mode and includes a system controller, multiple module controllers, and multiple power modules. Each power module includes a cascaded H-bridge and a dual active bridge (DAB). Figure 1 As shown, the method may include the following steps: Step 101: The system controller controls the drive pulses of each stage of the H-bridge to turn off, so that the bus capacitors on the DC side of each stage of the H-bridge are pre-charged through the anti-parallel diodes of each stage of the H-bridge. After the voltage of each bus capacitor reaches the preset threshold, the system controller sends a start command to each module controller to put the system into operation.

[0019] In this embodiment, after the AC side switch of the first solid-state transformer is closed, the system controller first executes pre-charging and soft-start logic, that is, it prohibits the output of drive pulses to the switching transistors of each H-bridge, keeping all H-bridge switching transistors in a completely off state. At this time, the grid current cannot flow through the active channel of the switching transistors, but it can form an uncontrolled rectifier path through the anti-parallel diodes inside each H-bridge switching transistor to pre-charge the bus capacitors on the DC side of each H-bridge, causing the bus capacitor voltage to gradually rise. During the pre-charging process, the system controller continuously acquires the bus capacitor voltage of each power module and compares it with a preset threshold; when all bus capacitor voltages reach a preset percentage of their respective rated voltages, the system controller determines that the pre-charging is complete and the start-up conditions are met, and then sends a start-up command to each module controller to put it into operation.

[0020] By employing the aforementioned pre-charging strategy, sufficient voltage is established in the bus capacitor before the switching transistor operates, effectively suppressing the inrush current generated at the moment of power-on due to the initial zero voltage of the capacitor, thus avoiding damage to the switching transistor and achieving safe soft-start of the cascaded topology.

[0021] In some embodiments of this disclosure, step 101 may specifically include the following sub-steps: Step a1: The system controller obtains the DC-side bus capacitor voltage of each cascaded H-bridge of each power module. When the voltage of each bus capacitor reaches the preset percentage of its respective rated voltage, the system controller determines that the start-up conditions are met and sends a start-up command to each module controller.

[0022] As an example, before the cascaded H-bridge experimental system is started, the high-voltage AC side of the first solid-state transformer (i.e., the solid-state transformer operating in rectification mode) is not connected to the power grid, and the DC-side bus capacitor voltage of each power module is zero. When the AC-side switch of the first solid-state transformer is closed, the high-voltage power grid is connected to the input terminals of the cascaded H-bridges of each power module. At this time, the system controller first performs pre-charging and soft-start operations: the system controller prohibits the output of drive pulses to the switching transistors of each stage of the cascaded H-bridge, meaning all H-bridge switching transistors are in a completely off state. In this state, the grid current cannot flow through the active channels of the switching transistors, but it can form an uncontrolled rectified path through the anti-parallel diodes inside each stage of the cascaded H-bridge switching transistors, pre-charging the DC-side bus capacitors of each stage of the cascaded H-bridge, causing the bus capacitor voltage to gradually rise to near the peak value of the grid voltage.

[0023] It should be noted that if the drive pulse of the H-bridge switch is enabled and ripple generation begins directly when the initial voltage of the bus capacitor is zero, it is equivalent to applying the grid voltage directly to the zero-voltage capacitor, which will generate an inrush current with an amplitude several to tens of times the rated value. This inrush current may not only damage the H-bridge switch but also cause harmonic pollution and voltage drop to the power grid. By using an anti-parallel diode for uncontrolled rectification pre-charging, the bus capacitor voltage is established to a certain level before the switch operates, which can effectively suppress the inrush current at the moment of startup and achieve safe soft start for the cascaded topology.

[0024] As an example, during the pre-charging process, the system controller continuously collects the DC-side bus capacitor voltage of each power module's cascaded H-bridge. Taking a power module with a rated voltage of 650V as an example, the system controller sets a preset threshold of 80% of the rated voltage, i.e., 520V. When the system controller detects that the bus capacitor voltage of all power modules has reached 520V or higher, it determines that pre-charging is complete and the startup conditions are met. At this time, the system controller broadcasts a startup command to all module controllers via the communication network, causing each module controller to switch from standby mode to running mode, ready to receive subsequent modulation wave commands and begin normal switching control.

[0025] It is understandable that the specific value of the preset percentage can be set according to the actual project requirements, and is not limited to 80%.

[0026] Step 102: The system controller performs outer loop control of the overall voltage and inner loop control of the current based on the input voltage of all cascaded H-bridges in the first solid-state transformer, generates the reference modulation wave of each power module, and performs module-level equalization processing and phase-to-phase equalization processing based on the input voltage of the cascaded H-bridges of each power module, generates the corrected modulation wave and sends it to each module controller.

[0027] In this embodiment, the system controller first collects the input voltage of the cascaded H-bridge of all 36 modules and calculates the average value of the whole machine. After comparing the average voltage of the whole machine with the given reference value, the active current is given through the voltage outer loop PI regulator. Then, the three-phase grid current dq transformation and decoupling control are combined to generate the three-phase total modulation wave. The total modulation wave of each phase is divided by the number of modules in that phase to obtain the reference modulation wave of each module, thereby realizing the balance control of the active power of the whole machine.

[0028] Subsequently, the system controller superimposes two levels of equalization correction on the reference modulation wave: The first level is module-level equalization, which calculates the deviation of the voltage of each module in each phase from the average value of that phase, generates adjustment coefficients for each module through PI regulation, and fine-tunes the reference modulation wave module by module, so that the modulation wave amplitude of the module with high voltage is reduced and the modulation wave amplitude of the module with low voltage is increased, thus solving the voltage imbalance between modules in the phase; The second level is phase-level equalization, which calculates the deviation of the total voltage of each phase from the average total voltage of the three phases, generates adjustment coefficients for the total modulation wave of each phase through PI regulation, and corrects the total modulation wave of the three phases as a whole, so that the modulation wave amplitude of the phase with low total voltage is increased and the modulation wave amplitude of the phase with high total voltage is decreased, thus solving the power imbalance between the three phases.

[0029] After the above two-stage equalization correction, the system controller broadcasts the final modulated wave to each module controller via the FPGA ring network. The overall power reference is determined by the outer voltage loop and the inner current loop of the whole machine, and then corrected layer by layer by the module-level and phase-to-phase-level equalization.

[0030] In some embodiments of this disclosure, the system controller in step 102 performs outer-loop voltage control and inner-loop current control based on the input voltage of all cascaded H-bridges in the first solid-state transformer, generating a reference modulation wave for each power module. Specifically, this may include the following sub-steps: Step b1: The system controller obtains the input voltage of all cascaded H-bridges, calculates the average value of the input voltage of all cascaded H-bridges, and obtains the average voltage of the whole machine.

[0031] As an example, the hardware architecture of the first solid-state transformer is a three-phase input, with 12 power modules per phase, totaling 36 power modules. Each power module is further divided into two sides, each containing two H-bridges. Therefore, the system controller needs to acquire the H-bridge input voltage V from all 36 power modules. H_ij The subscript i indicates the phase (i = A, B, C represent phases A, B, and C respectively), and the subscript j indicates the module number within that phase (j = 1, 2, ..., 12). The average voltage V of the entire unit... avg_all The calculation formula is:

[0032] Among them, V H_ij This represents the input voltage of the cascaded H-bridge of the j-th power module in phase i, with the denominator 36 representing the total number of power modules across all three phases. This overall average voltage reflects the overall level of the DC bus voltage of all H-bridges in the first solid-state transformer and serves as feedback for subsequent outer-loop voltage control.

[0033] Step b2: The difference between the average voltage of the whole machine and the given reference value is used to obtain the voltage deviation. The voltage deviation is then calculated by the first PI regulator of the outer voltage loop to output the given value of the inner current loop.

[0034] As an example, the system controller will use the overall average voltage V calculated in step b1. avg_all Compared with the system-given voltage reference value V avg_ref By subtracting the values, we obtain the voltage deviation Δ. V avg =V avg_ref -V avg_all Among them, V avg_ref V is the system's given average voltage reference value for the entire machine. avg_all The actual average voltage of the entire machine calculated in step b1, Δ V avg This represents the deviation between the two.

[0035] This voltage deviation reflects the difference between the current average voltage of the entire machine and the target value: when Δ V avg When Δ > 0, it indicates that the actual voltage is lower than the target value, and the input power needs to be increased; when Δ V avg When the value is less than 0, it indicates that the actual voltage is higher than the target value, and the input power needs to be reduced. The voltage deviation is sent to the first PI regulator in the voltage outer loop for proportional-integral calculation. The output of the first PI regulator is the d-axis current setpoint of the current inner loop. The function of the voltage outer loop is to ensure that the average voltage of the entire unit can stably track the given reference value, thereby controlling the total active power absorbed by the first solid-state transformer from the high-voltage grid.

[0036] Step b3: Obtain the three-phase grid-connected current of the first solid-state transformer, transform it to a synchronous rotating coordinate system to obtain the d-axis current and q-axis current, subtract the given value of the inner loop of the d-axis current from the d-axis current and calculate it through the second PI regulator to obtain the d-axis voltage command, and subtract the given value of the q-axis current from the q-axis current and calculate it through the third PI regulator to obtain the q-axis voltage command. After decoupling and compensating the d-axis voltage command and the q-axis voltage command, the total modulation wave of each of the three phases is obtained through inverse transformation.

[0037] As an example, the system controller samples the three-phase grid-connected current of the first solid-state transformer using current sensors. To improve the accuracy of current control and the dynamic response speed, the current components in the three-phase stationary coordinate system need to be transformed to a synchronous rotating coordinate system (i.e., the dq coordinate system). In the dq coordinate system, the d-axis current corresponds to active power, and the q-axis current corresponds to reactive power.

[0038] The difference between the d-axis current setpoint obtained in step b2 and the actual d-axis current is used to obtain the d-axis current deviation. This deviation is then fed into the second PI regulator for proportional-integral calculation to obtain the d-axis voltage command. Similarly, the difference between the q-axis current setpoint (usually set to 0 in unity power factor rectification control) and the actual q-axis current is used to obtain the q-axis current deviation. This deviation is then fed into the third PI regulator for proportional-integral calculation to obtain the q-axis voltage command.

[0039] Because there is cross-coupling between the d-axis and q-axis in the synchronous rotating coordinate system, decoupling compensation is required for the d-axis and q-axis voltage commands to eliminate their mutual influence and achieve independent control of the d-axis and q-axis currents. By inversely transforming the decoupled and compensated d-axis and q-axis voltage commands, the three-phase total modulation wave M in the three-phase stationary coordinate system can be obtained. total_a M total_b M total_c .

[0040] Step b4: Divide the total modulation wave of each phase by the number of power modules it includes to obtain the reference modulation wave of each power module.

[0041] As an example, since each phase contains 12 power modules, and the H-bridges of each module are connected in series on the input side, it is necessary to distribute the total modulation wave of each phase evenly among the power modules within that phase. For phase A, the reference modulation wave for its 12 power modules is M. total_a / 12; For phase B, the reference modulation wave for its 12 power modules is M. total_b / 12; For phase C, the reference modulation wave for its 12 power modules is M. total_c / 12. By evenly distributing the total modulation wave to each module, it can be ensured that, under ideal conditions (i.e., when all module parameters are completely identical), each module bears the same voltage stress. However, due to differences in parameters such as capacitance, equivalent series resistance, and drive delay among modules in actual engineering, simply distributing the modulation wave cannot guarantee the actual voltage balance of each module. Therefore, subsequent module-level equalization processing and inter-phase-level equalization processing are required for correction.

[0042] In some embodiments of this disclosure, the module-level equalization process in step 102, which involves "performing module-level equalization processing and phase-to-phase equalization processing based on the input voltage of the cascaded H-bridge of each power module," may specifically include the following sub-steps: Step c1: The system controller calculates the phase average of the input voltage of the cascaded H-bridge for all power modules in each phase.

[0043] As an example, for phase A, the system controller collects the input voltage V of the cascaded H-bridge of the 12 power modules in that phase. H_A1 V H_A2 ,…,V H_A12 Calculate the intra-phase average value V of phase A. avg_phase_A :

[0044] Among them, V H_Aj This represents the input voltage of the cascaded H-bridge for the j-th power module in phase A, with 12 representing the total number of power modules in phase A. Similarly, the intra-phase average voltage Vj for phases B and C can be calculated. avg_phase_B and V avg_phase_C .

[0045] Step c2: For each power module in each phase, calculate the first deviation between the input voltage of the cascaded H-bridge of the power module and the average value within the phase.

[0046] As an example, for the j-th power module of phase A, its first deviation value Δ V Aj = V H_Aj V avg_phase_A .in, V H_Aj The H-bridge input voltage (in volts) is the j-th power module of phase A. V avg_phase_A Δ is the intra-phase average value of phase A. V Aj This is the first deviation value. When Δ V Aj When Δ > 0, it indicates that the module voltage is higher than the average level of the in-phase module; when Δ V Aj When Δ < 0, it indicates that the module voltage is lower than the average level of the in-phase module; when Δ V Aj When = 0, it means that the voltage of the module is consistent with the average level of the in-phase module.

[0047] Step c3: The first deviation value is processed by the fourth PI regulator to obtain the modulation wave adjustment coefficient of the power module.

[0048] As an example, the first deviation value Δ calculated in step c2 is... V Aj The signal is fed into the fourth PI controller for proportional-integral calculation. The output of the fourth PI controller is the modulation adjustment coefficient K of the power module. Aj The sign of this adjustment factor is determined by the sign of the first deviation value: when the module voltage is higher than the average value within the phase (Δ... V Aj >0), K Aj It is positive; when the module voltage is lower than the average value within the phase (Δ V Aj <0), K Aj It is negative.

[0049] Step c4: Multiply the reference modulation wave by 1 and the difference between the modulation wave adjustment coefficient to obtain the modulation wave of the power module after module-level equalization correction.

[0050] As an example, for the j-th power module of phase A, the reference modulation wave obtained in step b4 is compared with the modulation wave adjustment coefficient K obtained in step c3. Aj The correction is performed according to the following formula: Corrected modulation wave = Reference modulation wave × (1 - K Aj ).

[0051] It should be noted that the physical meaning of this correction formula is as follows: when the voltage of a certain module is higher than the average value within the phase, Δ V Aj >0, K Aj >0, then (1 - K Aj If the modulated wave is less than the reference modulated wave (Δ), the conduction time of the cascaded H-bridge switch in this module is shortened, the input power is reduced, and the bus voltage drops. Conversely, when the voltage of a module is lower than the average value within a phase, Δ... V Aj <0,K Aj <0, then (1 - K Aj When the modulated wave is greater than the reference modulated wave (>1), the input power of the module increases, and the bus voltage rises. Through this closed-loop regulation method, the H-bridge voltages of each power module within the same phase are gradually brought closer to the phase average, achieving module-level voltage balancing. Module-level balancing solves the problem of voltage imbalance among modules within the same phase caused by differences in parameters such as capacitance, equivalent series resistance (ESR), and drive delay, effectively preventing some modules from being damaged due to excessive voltage.

[0052] In some embodiments of this disclosure, the inter-phase level equalization process in step 102, which involves "performing module-level equalization processing and inter-phase level equalization processing based on the input voltage of the cascaded H-bridge of each power module," may specifically include the following sub-steps: Step d1: The system controller calculates the sum of the input voltages of the cascaded H-bridge of all power modules in each phase to obtain the total phase voltage of each phase.

[0053] As an example, the system controller sums the input voltages of the cascaded H-bridge of the 12 power modules in phase A to obtain the total phase voltage of phase A. Among them, V H_Aj V represents the H-bridge input voltage of the j-th power module in phase A. sum_a Let V be the total phase voltage of phase A. Similarly, the total phase voltage V of phase B can be calculated. sum_b The total voltage V of phase C sum_c .

[0054] Step d2: Calculate the average value of the total phase voltage of all phases to obtain the three-phase average total voltage.

[0055] As an example, the three-phase average total voltage V avg_3ph The calculation formula is: V avg_3ph =(V sum_a +V sum_b +V sum_c ) / 3 Among them, V sum_a V sum_b V sum_c These are the total phase voltages of phases A, B, and C, respectively. The denominator 3 represents the number of the three phases, V. avg_3ph This is the average total voltage of the three phases.

[0056] Step d3: For each phase, calculate the second deviation between the phase total voltage and the three-phase average total voltage.

[0057] As an example, the second deviation value ΔV of phase A phase_a =V sum_a -V avg_3ph Among them, V sum_a V is the total phase voltage of phase A. avg_3ph The average total voltage across the three phases, ΔV phase_a This is the second deviation value for phase A. When ΔV phase_a When ΔV > 0, it indicates that the total voltage of phase A is higher than the average level of the three phases; when ΔV phase_a When the value is less than 0, it indicates that the total voltage of phase A is lower than the average level of the three phases. Similarly, the second deviation value of phase B and the second deviation value of phase C can be calculated.

[0058] Step d4: The second deviation value is processed by the fifth PI regulator to obtain the total modulation wave adjustment coefficient of the phase.

[0059] As an example, the second deviation value of phase A calculated in step d3 is fed into the fifth PI controller for proportional-integral calculation. The output of the fifth PI controller is the total modulation wave adjustment coefficient K of phase A. phase_a The sign of the adjustment coefficient is determined by the sign of the second deviation value: when the total phase voltage is higher than the average level of the three phases, the adjustment coefficient is positive; when the total phase voltage is lower than the average level of the three phases, the adjustment coefficient is negative.

[0060] Step d5: Multiply the total modulation wave of the phase by 1 and the difference between the total modulation wave adjustment coefficient to obtain the total modulation wave of the phase after phase-to-phase equalization correction.

[0061] As an example, for phase A, the total modulation wave M obtained in step b3 is... total_a The total modulation wave adjustment coefficient K obtained in step d4 phase_a The correction should be made according to the following formula: M' total_a = M total_a ×(1 - K phase_a ) Among them, M total_a To correct the total modulation wave (dimensionless) of phase A before the change, K phase_a M' is the total modulation wave adjustment coefficient (dimensionless) for phase A. total_a The A-phase total modulation wave (dimensionless) is after phase-to-phase equalization correction.

[0062] It should be noted that the physical meaning of this correction formula is similar to that of module-level equalization: when the total voltage of a phase is higher than the average level of the three phases, the adjustment coefficient is positive, the total modulation wave of that phase is suppressed, the total power absorbed by that phase from the grid decreases, and the total voltage of that phase drops; when the total voltage of a phase is lower than the average level of the three phases, the adjustment coefficient is negative, the total modulation wave of that phase is raised, the total power absorbed by that phase from the grid increases, and the total voltage of that phase rises. Through this closed-loop regulation method, the total voltage of the three phases is gradually brought closer to the average level of the three phases, achieving phase-level voltage equalization. Phase-level equalization solves the problem of three-phase total bus voltage imbalance caused by three-phase grid voltage asymmetry or differences in the parameters of each phase module.

[0063] Step d6: Divide the total phase modulation wave of the phase after phase-to-phase equalization correction by the number of power modules in the phase to obtain the reference modulation wave of each power module after phase-to-phase equalization correction.

[0064] As an example, for phase A, the total modulation wave M' of phase A obtained in step d5 after phase-to-phase equalization correction is... total_a Divide by the number of power modules in phase A, 12, to obtain the reference modulation wave of each power module in phase A after phase-to-phase equalization correction.

[0065] It should be noted that module-level equalization and phase-to-phase equalization can be executed in parallel. The system controller first calculates the total modulation wave of each phase based on the outer voltage loop and inner current loop of the whole machine. Then, it superimposes phase-to-phase equalization corrections (steps d1 to d6) on the total modulation wave to obtain the reference modulation wave of each module after phase-to-phase equalization correction. Then, it superimposes module-level equalization corrections (steps c1 to c4) on the reference modulation waves of each module to obtain the final corrected modulation wave. Module-level equalization and phase-to-phase equalization constitute a two-stage progressively converging equalization architecture, eliminating voltage differences from within the module to between phases, ensuring that the H-bridge voltage of all power modules tends to be consistent. The corrected modulation wave is simultaneously broadcast to all module controllers through the FPGA ring network.

[0066] Step 103: After receiving the start command, each module controller generates the target shift ratio of each dual active bridge DAB based on the input voltage and input current of each cascaded H-bridge in its plane.

[0067] Each power module includes two symmetrical planes, each plane including two cascaded H-bridges and two dual active bridges (DABs).

[0068] In some embodiments of this disclosure, after receiving a start command, the module controller stabilizes the DC bus voltage of the H-bridge by controlling the shift ratio of the DAB, that is, in the rectification mode, the DAB undertakes the responsibility of input-side voltage regulation.

[0069] Specifically, the module controller first acquires and sums the input voltages of the two H-bridges within the plane. It then compares the total input voltage of the plane with a reference value issued by the system controller. The total voltage loop adjusts the output of the total current loop setpoint, which reflects the total current required to be transmitted by the two DABs within the plane. Simultaneously, the module controller calculates the difference between the input voltages of the two H-bridges and adjusts the output of the voltage equalization compensation through the voltage equalization loop to correct the current distribution between the two DABs. Next, the module controller divides the total current loop setpoint into two base current setpoints and adds the voltage equalization compensation to each base current setpoint with opposite signs, obtaining the current loop setpoint for each DAB. Finally, the current loop setpoint for each of the two DABs is compared with the actual input current of the corresponding path, and the target shift ratio is output through the current loop adjustment. This is the three-loop control structure of the DAB. The cascaded cooperation of the total voltage loop, voltage equalization loop, and current loop ensures accurate tracking of the total input voltage of the plane to the reference value and achieves voltage balance between the two H-bridges within the plane.

[0070] It should be noted that the reference value of the input voltage issued by the system controller is equal to the current average H-bridge voltage of the whole machine, so that the DAB control target of each module controller is consistent with the control target of the system controller for the H-bridge voltage of the whole machine.

[0071] In some embodiments of this disclosure, before step 103, the system controller further includes: using the overall average voltage as the input voltage reference value for each module controller, and broadcasting it to each module controller via the FPGA ring network.

[0072] As an example, after completing the calculation of the overall average voltage in step 102, the system controller will set the overall average voltage V... avg_all As the input voltage reference value for each module controller, it is simultaneously broadcast to all module controllers via the FPGA ring network.

[0073] Understandably, since each module controller's plane contains two H-bridges, the input voltage reference value for that plane is equal to twice the overall average voltage. In subsequent DAB control, each module controller uses this reference value as the target value to adjust the total input voltage of the two DABs within its plane.

[0074] In some embodiments of this disclosure, step 103 may specifically include the following sub-steps: Step e1: Each module controller obtains the input voltage of the two cascaded H-bridges in its respective plane and sums them to obtain the total input voltage of its respective plane.

[0075] As an example, each module controller acquires the input voltage V of the two cascaded H-bridges in its plane. in1 and V in2 And calculate the sum V of the two. in_sum =V in1 +V in2 Among them, V in1 and V in2 These are the input voltages of the first and second H-bridges in this plane, V. in_sum This is the total input voltage of this surface. This total input voltage is the total input voltage of the two DABs within this surface, and it is also the feedback quantity of the DAB input total voltage loop.

[0076] Step e2: Compare the total input voltage of the corresponding surface with the reference value of the input voltage of the corresponding surface issued by the system controller, and output the total current loop setpoint after calculation by the sixth PI regulator.

[0077] As an example, the module controller will use the total input voltage V obtained in step e1. in_sum The reference value V of the input voltage issued by the system controller in_ref By comparison, the voltage deviation ΔV is obtained. in =V in_ref -V in_sum Among them, V in_ref The reference value of the input voltage issued by the system controller, V in_sum The total input voltage of this surface obtained in step e1 is ΔV.in This is the voltage deviation. The voltage deviation is fed into the sixth PI controller for proportional-integral calculation. The output of the sixth PI controller is the total current loop setpoint I. sum_ref The total current loop setpoint reflects the total current that the two DABs on this plane need to transmit, so as to achieve tracking of the total input voltage of this plane to the reference value.

[0078] Step e3: Each module controller calculates the difference between the input voltages of the two cascaded H-bridges in its respective plane, and then calculates the difference through the seventh PI regulator to output the voltage equalization compensation amount.

[0079] As an example, the module controller calculates the difference ΔV between the two H-bridge input voltages in its plane. in_diff =V in1 -V in2 Among them, V in1 and V in2 These are the input voltages ΔV of the first and second H-bridges in this plane, respectively. in_diff This represents the difference between the input voltages of the two H-bridges. When ΔV in_diff When ΔV > 0, it indicates that the voltage of the first H-bridge is higher than that of the second; when ΔV in_diff When the value is less than 0, it indicates that the voltage of the first H-bridge is lower than that of the second. The voltage difference is fed into the seventh PI controller for proportional-integral calculation; the output of the seventh PI controller is the voltage equalization compensation amount ΔI. balance This voltage equalization compensation is used to correct the current distribution between the two DABs to eliminate the difference between the input voltages of the two H-bridges.

[0080] Step e4: Each module controller divides the total current loop setpoint into two base current setpoints. For each base current setpoint, the equalization compensation is added to the base current setpoint to obtain the current loop setpoint of the dual active bridge DAB.

[0081] As an example, the module controller will use the total current loop setpoint I obtained in step e2. sum_ref The base current is divided into two paths, each with a value of I. sum_ref / 2. Then, the equalization compensation amount ΔI obtained in step e3 is... balance The current loop reference values ​​I of the first DAB are superimposed on the two base current reference values ​​with opposite signs: ref1 =I sum_ref / 2 +ΔI balance The current loop setpoint I of the second DAB ref2 =I sum_ref / 2 -ΔI balance .

[0082] It should be noted that the physical meaning of the voltage equalization compensation amount being superimposed with opposite signs is as follows: When the voltage of the first H-bridge is higher than that of the second, the seventh PI regulator outputs ΔI. balance If the current loop setpoint of the first DAB is greater than 0, the current loop setpoint of the first DAB increases, allowing it to transmit more power and causing the voltage of the first H-bridge to decrease. Conversely, if the current loop setpoint of the second DAB decreases, the current loop setpoint of the second DAB transmits less power and causes the voltage of the second H-bridge to increase. Conversely, when the voltage of the second H-bridge is higher than that of the first, the compensation direction automatically reverses. Through this cross-compensation mechanism, the input voltages of the two H-bridges are gradually brought closer, achieving voltage equalization between the two DABs within the module.

[0083] Step e5: Compare the current loop setpoint of each of the two dual active bridge DABs with the actual input current of the corresponding dual active bridge DAB. After calculation by the eighth PI regulator, output the target shift ratio of each of the two dual active bridge DABs.

[0084] As an example, the module controller samples the actual input current I of the two DABs respectively. in1 and I in2 Set the current loop setpoint I for the first DAB path. ref1 The actual input current I of the first DAB in1 By subtracting the values, we obtain the first current deviation ΔI1=I ref1 -I in1 The deviation is then fed into the eighth PI controller for proportional-integral calculation. The output of the eighth PI controller is the target shift ratio D1 of the first DAB. Similarly, the current loop setpoint I of the second DAB is... ref2 The actual input current I of the second DAB in2 By subtracting the values, we obtain the current deviation ΔI2 = I in the second path. ref2 -I in2 The deviation is then fed into the eighth PI controller for proportional-integral calculation to obtain the target shift ratio D2 of the second DAB.

[0085] It should be noted that in a dual active bridge DAB, the shift ratio (i.e., the ratio of the phase difference of the drive pulse between the two H-bridges to half a switching cycle) directly determines the magnitude and direction of the power transmitted by the DAB. A larger shift ratio results in greater power transmitted by the DAB; a smaller shift ratio results in less power transmitted. Through current closed-loop regulation, the eighth PI regulator dynamically adjusts the target shift ratio based on the current deviation, ensuring that the actual input current of each DAB accurately tracks the current loop setpoint, thereby achieving precise control over the total input voltage and the voltage balance of the two H-bridges.

[0086] It should be noted that steps e2 to e5 constitute the three-loop control structure of the module controller's DAB: the outermost layer is the input total voltage loop (step e2), used to stabilize the total input voltage of the two DABs on this plane; the middle layer is the input voltage equalization loop (step e3), used to balance the voltage between the two H-bridges on this plane; and the innermost layer is the current loop (step e5), used to precisely control the input current of each DAB. The three control loops are nested and converge step by step, jointly achieving stable control of the input voltage of the DAB in rectification mode.

[0087] Step 104: For each module controller, the FPGA corresponding to the module controller generates a drive pulse for the dual active bridge DAB according to the target shift ratio to drive the switching transistors of the dual active bridge DAB, and generates a drive pulse for the cascaded H bridge according to the corrected modulation wave to drive the switching transistors of the cascaded H bridge.

[0088] In this embodiment, the FPGA includes a high-voltage side FPGA and a low-voltage side FPGA. As an example, after calculating the target shift ratio, each module controller (module DSP) simultaneously sends the target shift ratios of the two DAB channels to the high-voltage side FPGA and the low-voltage side FPGA within the power module via a parallel bus. The low-voltage side FPGA generates drive pulses for the two H-bridges on the low-voltage side of the DAB based on the received target shift ratio. The high-voltage side FPGA generates drive pulses for the two H-bridges on the high-voltage side of the DAB based on the same target shift ratio. The phase difference between the high-voltage and low-voltage side drive pulses is precisely controlled by the shift ratio, jointly determining the magnitude of the DAB transmission power. Simultaneously, it receives the corrected modulation wave from the system controller via the FPGA ring network and generates SPWM drive pulses for the cascaded H-bridges, making the H-bridge output voltage approximate a sine wave. The high-voltage side FPGA simultaneously undertakes the task of generating drive pulses for both the high-voltage side of the DAB and the H-bridges, working collaboratively with the low-voltage side FPGA to drive and control all switches within the power module, ensuring stable operation of each power module according to the corrected modulation wave and the target shift ratio.

[0089] In some embodiments of this disclosure, the FPGA includes a high-voltage side FPGA and a low-voltage side FPGA. Step 104 may specifically include the following sub-steps: In step f1, the module controller sends the target shift ratio to the high-voltage side FPGA and low-voltage side FPGA within the power module via a parallel bus.

[0090] As an example, after each module controller (module DSP) completes the calculation of the two DAB target shift ratios D1 and D2 in step 103, it simultaneously sends the target shift ratios to the high-voltage side FPGA and the low-voltage side FPGA within the power module via the parallel bus inside the module controller. The parallel bus has the advantages of high transmission speed and low latency, which can ensure that the shift ratio data is transmitted from the DSP to the FPGA in a very short time, meeting the requirements of real-time control.

[0091] Step f2: The low-voltage side FPGA generates the drive pulse for the low-voltage side of the dual active bridge DAB according to the target shift ratio.

[0092] As an example, after receiving the target shift ratio from the DSP module, the low-voltage side FPGA generates drive pulses for the two H-bridges on the low-voltage side of the DAB based on the shift ratio value. In a dual active bridge DAB, there is a specific phase relationship between the drive pulses of the low-voltage side H-bridge and the high-voltage side H-bridge, which is determined by the shift ratio. The low-voltage side FPGA generates two PWM drive signals for the low-voltage side H-bridges of the DAB according to the target shift ratio, which are then amplified by the drive circuit to drive the low-voltage side switching transistors to turn on and off.

[0093] In step f3, the high-voltage side FPGA generates the drive pulse of the dual active bridge DAB high-voltage side according to the target shift ratio, and at the same time generates the SPWM drive pulse of the cascaded H bridge according to the received modified modulation wave.

[0094] As an example, after receiving the target shift ratio sent by the DSP module, the high-voltage side FPGA generates drive pulses for the two H-bridges on the high-voltage side of the DAB based on the shift ratio value. The phase difference between the drive pulses of the high-voltage side H-bridge and the drive pulses of the low-voltage side H-bridge is precisely controlled by the shift ratio, and the two together determine the power transmitted by the DAB.

[0095] Meanwhile, the high-voltage side FPGA also receives the corrected modulation wave (i.e., the final modulation wave after module-level equalization correction in step c4 and phase-to-phase equalization correction in step d6) sent by the system controller through the FPGA ring network. Based on this corrected modulation wave, the high-voltage side FPGA uses a sinusoidal pulse width modulation (SPWM) strategy to generate SPWM drive pulses for the cascaded H-bridge. The basic principle of SPWM is to compare the sinusoidal modulation wave with a high-frequency triangular carrier wave. When the amplitude of the modulation wave is greater than the amplitude of the carrier wave, a high level is output; otherwise, a low level is output, thus generating a series of pulse sequences whose width varies with the amplitude of the sinusoidal wave. After being amplified by the drive circuit, this pulse sequence drives the switching transistors of the cascaded H-bridge to turn on and off, making the voltage waveform output by the H-bridge approximate a sine wave, achieving high-quality rectification and conversion from high-voltage AC to DC.

[0096] It should be noted that the high-voltage side FPGA in each power module performs two tasks simultaneously: first, it generates the drive pulse for the DAB high-voltage side based on the target shift ratio; second, it generates the SPWM drive pulse for the H-bridge based on the corrected modulation wave. This integrated design simplifies the hardware architecture and reduces communication latency between chips. The low-voltage side FPGA focuses on generating the drive pulse for the DAB low-voltage side based on the target shift ratio. The high-voltage side FPGA and the low-voltage side FPGA work together to achieve precise drive control of all switches in the power module, enabling each power module to operate stably according to the corrected modulation wave and the target shift ratio, and maintaining the stability of the DC bus voltage of each stage of the H-bridge of the first solid-state transformer.

[0097] It should be noted that communication between the system controller and the module controllers is achieved through an FPGA ring network. The system controller broadcasts the corrected modulation wave simultaneously to all module controllers via the FPGA ring network. Each module controller receives the corrected modulation wave and generates its own drive pulse for its power module using its FPGA. The advantages of this broadcast communication architecture are: all module controllers receive the same modulation wave command simultaneously, eliminating the cumulative delay caused by cascading forwarding, resulting in low communication latency and strong determinism; furthermore, this architecture is easily expandable, as the number of power modules increases, simply by connecting the new modules to the FPGA ring network, without modifying the communication protocol or control architecture.

[0098] According to the solid-state transformer rectification mode control method proposed in this disclosure, the system controller shuts off the driving pulses of each stage of the cascaded H-bridge during the startup phase, uses anti-parallel diodes for pre-charging, and sends the startup command only after reaching the threshold, effectively suppressing the inrush current at the moment of power-on and realizing safe soft-start of the cascaded topology. By generating a reference modulation wave based on the outer loop of the overall voltage and the inner loop of the current in the system controller, and then performing module-level equalization and phase-to-phase equalization on this basis, a corrected modulation wave is sent, realizing step-by-step voltage equalization from within the module to between phases, solving the problem of voltage imbalance caused by parameter differences. After receiving the startup command, each module controller independently generates the target shift ratio of each DAB based on the H-bridge voltage and current in its plane, and each FPGA generates DAB driving pulses based on the shift ratio and H-bridge driving pulses based on the corrected modulation wave. This clarifies the hierarchical responsibilities of the system controller and the module controller, enabling the DAB to undertake the input-side voltage regulation task in rectification mode, and the H-bridge to undertake the output voltage regulation task, adapting to the working condition requirements of the reversed control role in the drag experiment.

[0099] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein.

[0100] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A solid-state transformer rectification mode control method, characterized in that, The method is applied to a towing experimental system, which includes a first solid-state transformer and a second solid-state transformer. The low-voltage DC side buses of the first and second solid-state transformers are directly connected. The first solid-state transformer operates in rectification mode and includes a system controller, multiple module controllers, and multiple power modules. Each power module includes a cascaded H-bridge and a dual active bridge (DAB). The system controller controls the drive pulses of each H-bridge to turn off, so that the bus capacitors on the DC side of each H-bridge are pre-charged through the anti-parallel diodes of each H-bridge. After the voltage of each bus capacitor reaches the preset threshold, the system controller sends a start command to each module controller to put it into operation. The system controller performs outer loop control of the overall voltage and inner loop control of the current based on the input voltage of all cascaded H-bridges in the first solid-state transformer, generates a reference modulation wave for each power module, and performs module-level equalization processing and phase-to-phase equalization processing based on the input voltage of the cascaded H-bridges of each power module, generating a corrected modulation wave and sending it to each module controller. After receiving the start command, each module controller generates a target shift ratio for each dual active bridge DAB based on the input voltage and input current of each cascaded H-bridge in its plane; wherein, each power module includes two symmetrical planes, each plane including two cascaded H-bridges and two dual active bridge DABs; For each module controller, the FPGA corresponding to the module controller generates a drive pulse for the dual active bridge DAB according to the target shift ratio to drive the switching transistors of the dual active bridge DAB, and generates a drive pulse for the cascaded H-bridge according to the modified modulation wave to drive the switching transistors of the cascaded H-bridge.

2. The method according to claim 1, characterized in that, The system controller controls the shut-off of the drive pulses of each stage of the H-bridge to pre-charge the bus capacitors on the DC side of each stage of the H-bridge via the anti-parallel diodes of each stage of the H-bridge. After the voltage of each bus capacitor reaches a preset threshold, the system controller sends a start-up command to each module controller, including: The system controller acquires the DC-side bus capacitor voltage of each power module's cascaded H-bridge. When the voltage of each bus capacitor reaches a preset percentage of its rated voltage, the system controller determines that the startup conditions are met and sends the startup command to each module controller.

3. The method according to claim 1, characterized in that, The system controller performs outer-loop voltage control and inner-loop current control based on the input voltage of all cascaded H-bridges in the first solid-state transformer, generating reference modulation waves for each power module, including: The system controller acquires the input voltage of all cascaded H-bridges, calculates the average value of the input voltage of all cascaded H-bridges, and obtains the average voltage of the entire machine. The voltage deviation is obtained by subtracting the average voltage of the whole machine from the given reference value. The voltage deviation is then calculated by the first PI regulator of the outer voltage loop to output the given value of the inner current loop. The three-phase grid-connected current of the first solid-state transformer is obtained and transformed into a synchronous rotating coordinate system to obtain the d-axis current and q-axis current. The given value of the inner loop of the d-axis current is subtracted from the d-axis current and processed by the second PI regulator to obtain the d-axis voltage command. The given value of the q-axis current is subtracted from the q-axis current and processed by the third PI regulator to obtain the q-axis voltage command. After decoupling and compensation of the d-axis voltage command and the q-axis voltage command, the total modulation wave of each of the three phases is obtained by inverse transformation. Divide the total modulation wave of each phase by the number of power modules it includes to obtain the reference modulation wave for each power module.

4. The method according to claim 1, characterized in that, The system controller performs module-level equalization processing based on the input voltage of the cascaded H-bridge of each power module, including: The system controller calculates the phase average of the input voltage of the cascaded H-bridge of all power modules in each phase. For each power module within each phase, calculate the first deviation between the cascaded H-bridge input voltage of the power module and the average value within the phase. The first deviation value is processed by the fourth PI regulator to obtain the modulation wave adjustment coefficient of the power module; Multiplying the reference modulation wave by 1 and the difference between the modulation wave adjustment coefficient yields the modulation wave of the power module after module-level equalization correction.

5. The method according to claim 1, characterized in that, The system controller performs inter-phase equalization processing based on the input voltage of the cascaded H-bridge of each power module, including: The system controller calculates the sum of the input voltages of the cascaded H-bridge of all power modules in each phase to obtain the total phase voltage of each phase. Calculate the average of the total phase voltages of all phases to obtain the three-phase average total voltage; For each phase, calculate the second deviation value between the total phase voltage of the phase and the average total voltage of the three phases; The second deviation value is processed by the fifth PI regulator to obtain the total modulation wave adjustment coefficient of the phase; Multiply the total modulation wave of the phase by 1 and the difference between the total modulation wave adjustment coefficient to obtain the total modulation wave of the phase after phase equalization correction; Divide the total phase modulation wave of the phase after phase equalization correction by the number of power modules of the phase to obtain the reference modulation wave of each power module after phase equalization correction.

6. The method according to claim 3, characterized in that, Before generating the target shift ratio of each dual active bridge (DAB) based on the input voltage and input current of each cascaded H-bridge in its respective plane after receiving the start command, the following steps are also included: The system controller uses the average voltage of the entire machine as the input voltage reference value for each module controller and broadcasts it to each module controller through the FPGA ring network. Upon receiving the start command, each module controller generates a target shift ratio for each dual active bridge (DAB) based on the input voltage and input current of each cascaded H-bridge within its plane, including: Each module controller obtains the input voltage of the two cascaded H-bridges in its respective plane and sums them to obtain the total input voltage of its respective plane; The voltage deviation is obtained by subtracting the total input voltage of the corresponding surface from the reference value of the input voltage of the corresponding surface issued by the system controller. The voltage deviation is then calculated by the sixth PI regulator to output the total current loop setpoint. Each module controller calculates the difference between the input voltages of the two cascaded H-bridges in its respective plane, and then calculates the difference through the seventh PI regulator to output the voltage equalization compensation amount. Each module controller divides the total current loop setpoint into two base current setpoints. For each base current setpoint, the voltage equalization compensation is added to the base current setpoint to obtain the current loop setpoint of the dual active bridge DAB. The current loop setpoints of the two dual active bridge DABs are compared with the actual input current of the corresponding dual active bridge DABs. After calculation by the eighth PI regulator, the target shift ratios of the two dual active bridge DABs are output.

7. The method according to claim 6, characterized in that, The step of adding the equalizing compensation amount to the base current setpoint includes: The voltage equalization compensation is superimposed on the two base current given values ​​with opposite signs.

8. The method according to claim 1, characterized in that, The FPGA includes a high-voltage side FPGA and a low-voltage side FPGA; the FPGA corresponding to the module controller generates drive pulses for dual active bridge DABs based on the target shift ratio, and generates drive pulses for cascaded H-bridges based on the corrected modulation wave, including: The module controller sends the target shift ratio to the high-voltage side FPGA and low-voltage side FPGA within the power module via a parallel bus; The low-voltage side FPGA generates drive pulses for the low-voltage side of the dual active bridge DAB according to the target shift ratio; The high-voltage side FPGA generates a drive pulse for the dual active bridge DAB high-voltage side based on the target shift ratio, and simultaneously generates an SPWM drive pulse for the cascaded H-bridge based on the received modified modulation wave.

9. The method according to claim 1, characterized in that, The system controller and the module controllers communicate via an FPGA ring network. The system controller broadcasts the modified modulation wave to all module controllers simultaneously via the FPGA ring network. Each module controller receives the modified modulation wave and generates its own power module's drive pulse using its FPGA.

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