An output voltage processing method and device of an inverter circuit

Abstract

The application relates to an output voltage processing method and device of an inverter circuit, and the method comprises the following steps: acquiring an actual output voltage of a first target phase in a first working state and a first phase current, the first working state being a state of controlling the on-off state of a first bridge arm and a second bridge arm of the first target phase based on a first target control signal; acquiring a second phase current of the first target phase in a second working state, the second working state being a state of controlling the on-off state of the first bridge arm of the first target phase based on a second target control signal and controlling the on-off state of the second bridge arm of the first target phase based on a third target control signal; and determining a target output voltage of the first target phase based on the actual output voltage, the first phase current and the second phase current. Different control modes are implemented on the bridge arms in the inverter circuit, the phase currents under different control modes are detected, the dead zone compensation voltage is determined according to the phase currents, and accurate compensation of the dead zone can be realized.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a method and apparatus for processing the output voltage of an inverter circuit. Background Technology

[0002] In permanent magnet synchronous motor drive circuits, the inverter is one of the core components. Its main function is to convert direct current (DC) to alternating current (AC) to drive the motor. In an inverter, dead time refers to a period of time during switching operations where the switching devices are switched off. This period is artificially set to prevent simultaneous conduction of the upper and lower bridge arms' switching devices, which could cause a shoot-through short circuit. During this time, both upper and lower bridge arm switching devices are in the off state to ensure safe switching. However, dead time affects the inverter's control accuracy, causing distortion of the inverter's output voltage waveform and an increase in the high-order harmonic content of the current.

[0003] To address the current distortion problem caused by dead time, it is necessary to compensate for the distortion of the output voltage or current waveform caused by dead time in the inverter. The existing dead time compensation method is usually the average error voltage compensation method. Although the average error voltage compensation method is simple and easy to implement, it has the limitation of limited compensation accuracy. Summary of the Invention

[0004] To address the aforementioned technical problems, this application discloses an output voltage processing method and apparatus for an inverter circuit. Different control methods are applied to the bridge arms in the inverter circuit, the phase current under different control methods is detected, and the dead zone compensation voltage is determined based on the phase current, thereby achieving accurate compensation for the dead zone.

[0005] On one hand, this application provides a method for processing the output voltage of an inverter circuit, the inverter circuit including multiple phases and a power supply, each phase including a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply, the method including:

[0006] The actual output voltage and current of the first target phase in the first operating state are obtained; the first operating state is that the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and the first target phase and the second bridge arm of the first target phase are switched on and off based on a first target control signal based on at least one signal cycle. The first target phase is any one of the plurality of phases, and the second target phase is any other phase among the plurality of phases except the first target phase. The first target control signal is determined by setting a first preset dead time on a preset control signal.

[0007] The second phase current of the first target phase in the second operating state is obtained; the second operating state is that the first bridge arm of the second target phase is turned off and the second bridge arm of the second target phase is turned on, the first bridge arm of the first target phase is controlled to switch between on and off states based on a second target control signal based on at least one signal cycle, and the on and off states of the second bridge arm of the first target phase are controlled based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is a preset turn-off signal or the second target control signal based on at least one signal cycle;

[0008] Based on the actual output voltage, the first phase current, and the second phase current, the target output voltage of the first target phase is determined; the target output voltage is used to drive the target motor.

[0009] In some embodiments, the control of the first bridge arm of the first target phase and the second bridge arm of the first target phase to switch on / off states based on the first target control signal of at least one signal cycle includes:

[0010] Based on the first target control signal of at least one signal cycle, the on / off state of the first target phase is controlled to switch between a first on / off state, a second on / off state, and a third on / off state; the first on / off state is that both the first bridge arm and the second bridge arm of the first target phase are off; the second on / off state is that the first bridge arm of the first target phase is on and the second bridge arm of the first target phase is off; the third on / off state is that the first bridge arm of the first target phase is off and the second bridge arm of the first target phase is on.

[0011] In some embodiments, the first target control signal includes a first bridge arm control signal and a second bridge arm control signal, the preset control signal includes a first preset control signal and a second preset control signal, the sum of the duty cycles of the first preset control signal and the second preset control signal is 1, and obtaining the actual output voltage and first phase current of the first target phase in the first operating state includes:

[0012] The preset turn-off signal is input to the first bridge arm of the second target phase, and the preset turn-on signal is input to the second bridge arm of the second target phase. Simultaneously, the first bridge arm control signal and the second bridge arm control signal are input to the first bridge arm of the first target phase, so that the inverter circuit is in the first operating state. The first bridge arm control signal is determined based on the first preset control signal and the first preset dead time, and the second bridge arm control signal is determined based on the second preset control signal and the first preset dead time.

[0013] When the inverter circuit is in the first operating state, the actual output voltage of the first target phase and the first phase current of the first target phase are obtained.

[0014] In some embodiments, when the second operating state is characterized by the first bridge arm of the second target phase being off and the second bridge arm of the second target phase being on, and the first bridge arm of the first target phase being switched between on and off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase being switched between on and off states based on a third target control signal, wherein the second target control signal is the preset control signal and the third target control signal is the preset off signal, the step of acquiring the second phase current of the first target phase in the second operating state includes:

[0015] The preset turn-off signal is input to the first bridge arm of the second target phase and the second bridge arm of the first target phase, the preset turn-on signal is input to the second bridge arm of the second target phase, and the first preset control signal is input to the first bridge arm of the first target phase, so that the inverter circuit is in the second working state.

[0016] When the inverter circuit is in the second operating state, the second phase current of the first target phase is obtained.

[0017] In some embodiments, determining the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current includes:

[0018] Obtain the winding resistance of the target motor;

[0019] Based on the winding resistance, the first phase current, and the second phase current, determine the first target compensation voltage of the first target phase;

[0020] The target output voltage is determined based on the actual output voltage and the first target compensation voltage.

[0021] In some embodiments, determining the first target compensation voltage of the first target phase based on the winding resistance, the first phase current, and the second phase current includes:

[0022] The effective value of the first phase current is determined as the first effective current, and the effective value of the second phase current is determined as the second effective current;

[0023] The difference between the second effective current and the first effective current is determined as the first target difference current;

[0024] The product of the winding resistance and the first target differential current is determined as the first target compensation voltage.

[0025] In some embodiments, when the second operating state is that the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on, the state of controlling the on / off state of the first bridge arm of the first target phase based on the second target control signal of at least one signal cycle, and controlling the on / off state of the second bridge arm of the first target phase based on the third target control signal, wherein the second target control signal includes a third bridge arm control signal and a fourth bridge arm control signal, and the third target control signal is the second target control signal of at least one signal cycle, the step of obtaining the second phase current of the first target phase in the second operating state further includes:

[0026] The preset turn-off signal is input to the first bridge arm of the second target phase, the preset turn-on signal is input to the second bridge arm of the second target phase, the third bridge arm control signal is simultaneously input to the first bridge arm of the first target phase, and the fourth bridge arm control signal is input to the second bridge arm of the first target phase, so that the inverter circuit is in the second operating state; the third bridge arm control signal is determined based on the first preset control signal and the second preset dead time, and the fourth bridge arm control signal is determined based on the second preset control signal and the second preset dead time, wherein the first preset dead time and the second preset dead time are different;

[0027] When the inverter circuit is in the second operating state, the second phase current of the first target phase is obtained.

[0028] In some embodiments, determining the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current further includes:

[0029] Obtain the winding resistance of the target motor and the preset signal period of the preset control signal;

[0030] Based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current, the second target compensation voltage of the first target phase is determined;

[0031] The target output voltage is determined based on the actual output voltage and the second target compensation voltage.

[0032] In some embodiments, determining the second target compensation voltage of the first target phase based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current includes:

[0033] The effective value of the first phase current is determined as the third effective current, and the effective value of the second phase current is determined as the fourth effective current;

[0034] The difference between the third effective current and the fourth effective current is determined as the second target difference current, and the reciprocal of the difference between the first preset dead time and the second preset dead time is determined as the target difference dead time.

[0035] The second target compensation voltage is determined by the product of the winding resistance, the preset signal period, the second target difference current, and the target difference dead time.

[0036] On the other hand, this application also provides an output voltage processing device for an inverter circuit, the inverter circuit including multiple phases and a power supply, each phase including a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply, the device including:

[0037] The first phase current acquisition module is used to acquire the actual output voltage and first phase current of the first target phase in the first operating state; the first operating state is the state in which the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and the state in which the first bridge arm and the second bridge arm of the first target phase are controlled by a first target control signal based on at least one signal cycle to switch between on and off states; the first target phase is any one of the plurality of phases, the second target phase is any other phase among the plurality of phases except the first target phase, and the first target control signal is determined by setting a first preset dead time on a preset control signal;

[0038] The second phase current acquisition module is used to acquire the second phase current of the first target phase in a second operating state; the second operating state is that the first bridge arm of the second target phase is off, the second bridge arm of the second target phase is on, the first bridge arm of the first target phase is controlled to switch between on and off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is controlled to switch between on and off states based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is a preset off signal or the second target control signal of at least one signal cycle;

[0039] The output voltage determination module is used to determine the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current; the target output voltage is used to drive the target motor.

[0040] Implementing the embodiments of this application has the following beneficial effects:

[0041] The output voltage processing method for the inverter circuit disclosed in this application detects the first phase current of the phase to be compensated in a first operating state and the second phase current in a second operating state. The first operating state refers to the state in which the upper bridge arm of all phases except the phase to be compensated in the inverter circuit is off and the lower bridge arm is on, and the upper and lower bridge arms of the phase to be compensated are controlled by a first target control signal, which is obtained by setting a first preset dead time on a preset control signal. The second operating state refers to the state in which the upper bridge arm of all phases except the phase to be compensated in the inverter circuit is off and the lower bridge arm is on, the upper bridge arm of the phase to be compensated is controlled by a second target control signal, and the lower bridge arm of the phase to be compensated is controlled by a third target control signal, where the second target control signal is determined based on the preset control signal, and the third target control signal is either a preset turn-off signal or the second target control signal. By implementing different dead-time-related control methods on the on / off states of the upper and lower bridge arms of the phase to be compensated in the inverter circuit and detecting the phase current under different control methods, the corresponding dead-time compensation voltage can be obtained based on the phase current under different control methods, achieving accurate dead-time compensation for each phase in the inverter circuit. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A schematic flowchart illustrating an output voltage processing method for an inverter circuit provided in an embodiment of this application;

[0044] Figure 2 This is a schematic diagram of an inverter circuit provided in an embodiment of this application;

[0045] Figure 3 A waveform diagram of an on / off state control signal and a first phase current provided for an embodiment of this application;

[0046] Figure 4 This application provides a schematic diagram of the on / off state of a bridge arm in an embodiment of the present application.

[0047] Figure 5This application provides a schematic diagram of the on / off state of a bridge arm in an embodiment of the present application.

[0048] Figure 6 This application provides a schematic diagram of the on / off state of a bridge arm in an embodiment of the present application.

[0049] Figure 7 A waveform diagram of an on / off state control signal and a second phase current provided for an embodiment of this application;

[0050] Figure 8 A waveform diagram of an on / off state control signal and phase current provided for an embodiment of this application;

[0051] Figure 9 This is a schematic diagram of the structure of an output voltage processing device for an inverter circuit provided in an embodiment of this application;

[0052] Figure 10 This is a schematic diagram of the hardware structure of a device for implementing the method provided in the embodiments of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0054] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such information can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that illustrated or described herein.

[0055] See Figure 1 , Figure 1 This application provides a flowchart illustrating an output voltage processing method for an inverter circuit. The inverter circuit includes multiple phases and a power supply. Each phase includes a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply. The method includes:

[0056] S101, acquire the actual output voltage and first phase current of the first target phase in the first operating state; the first operating state is the state in which the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and the state in which the first bridge arm of the first target phase and the second bridge arm of the first target phase are switched on and off based on a first target control signal based on at least one signal cycle; the first target phase is any one of the plurality of phases, the second target phase is any other phase among the plurality of phases except the first target phase, and the first target control signal is determined by setting a first preset dead time on a preset control signal;

[0057] In some embodiments, the inverter circuit is a multiphase inverter circuit, that is, the inverter circuit includes multiple phases, each phase including a first bridge arm and a second bridge arm, wherein the first bridge arm is connected to the positive terminal of the power supply in the inverter circuit, and the second bridge arm is connected to the negative terminal of the power supply in the inverter circuit. The first bridge arm can be the upper bridge arm, and the second bridge arm can be the lower bridge arm.

[0058] For example, see Figure 2 , Figure 2 This is a schematic diagram of an inverter circuit provided in an embodiment of this application. Figure 2 The inverter circuit shown is a three-phase inverter circuit that can be used to drive a permanent magnet synchronous motor. This three-phase inverter circuit includes three phases: a, b, and c. Each phase includes a first bridge arm and a second bridge arm. Each bridge arm includes a switching device and an anti-parallel diode. The switching device can be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The anti-parallel diode is connected in anti-parallel to the switching device for freewheeling current. Figure 2 As shown, the upper bridge arm of phase a includes a switching element a. u The lower bridge arm of phase a includes a switching element a. d The upper bridge arm of phase b includes a switching element b. u The lower bridge arm of phase b includes a switching element b. d The upper bridge arm of phase C includes a switching element C. u The lower bridge arm of phase C includes a switching element C. d .

[0059] In some embodiments, by inputting different control signals to each bridge arm in the inverter circuit, the inverter circuit can be in different operating states. Specifically, a first target phase is determined as the phase to be compensated, which is any one of the multiple phases in the inverter circuit. The other phases in the multiple phases of the inverter circuit besides the first target phase are determined as second target phases. The first bridge arm of the second target phase is controlled to turn off, the second bridge arm of the second target phase is controlled to turn on, and a first target control signal based on at least one signal cycle controls the first bridge arm and the second bridge arm of the first target phase to switch between on and off states, so that the inverter circuit is in a first operating state. The first target control signal is determined by setting a first preset dead time on a preset control signal. The preset control signal is a signal without a set dead time. Both the preset control signal and the first target control signal can control the bridge arm to switch between on and off states. The first preset dead time can be determined based on the characteristics of the power devices in the inverter circuit. When the inverter circuit is in the first operating state, the actual output voltage of the first target phase and the first phase current are obtained. The actual output voltage refers to the output voltage that is distorted due to the first preset dead time, and the first phase current refers to the current flowing through the first target phase.

[0060] S103, acquire the second phase current of the first target phase in the second operating state; the second operating state is that the first bridge arm of the second target phase is off, the second bridge arm of the second target phase is on, the first bridge arm of the first target phase is controlled to switch between on and off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is controlled to switch between on and off states based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is a preset off signal or the second target control signal of at least one signal cycle;

[0061] In some embodiments, the inverter circuit is in a second operating state by controlling the first bridge arm of the second target phase to turn off, the second bridge arm of the second target phase to turn on, a preset control signal based on at least one signal cycle to control the first bridge arm of the first target phase to switch between on and off states, and a preset turn-off signal to control the second bridge arm of the first target phase to turn off. The preset turn-off signal can control the bridge arm to be in the off state. In this case, the second target control signal is the preset control signal, and the third target control signal is the preset turn-off signal. When the inverter circuit is in the second operating state, the second phase current of the first target phase is acquired. The second phase current refers to the current flowing through the first target phase.

[0062] In other embodiments, the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and a second target control signal based on at least one signal cycle controls the first and second bridge arms of the first target phase to switch between on and off states, so that the inverter circuit is in a second operating state. In this case, the second target control signal is determined by setting a second preset dead time on a preset control signal, and the third target control signal is a second target control signal with at least one signal cycle. The second preset dead time can be determined based on the characteristics of the power devices in the inverter circuit, and the first preset dead time is different from the second preset dead time. When the inverter circuit is in the second operating state, the second phase current of the first target phase is acquired.

[0063] S105, based on the actual output voltage, the first phase current and the second phase current, determine the target output voltage of the first target phase; the target output voltage is used to drive the target motor.

[0064] In some embodiments, the dead zone compensation voltage corresponding to the first target can be determined based on the first phase current and the second phase current. The actual output voltage of the first target phase is compensated based on the dead zone compensation voltage to obtain the target output voltage of the first target phase. The target output voltage refers to the output voltage without distortion. The target output voltage can be used to drive the target motor.

[0065] In some embodiments, according to the method provided in the embodiments of this application, each corresponding dead-zone compensation voltage in the inverter circuit can be determined respectively, thereby realizing dead-zone voltage compensation for each phase in the inverter circuit.

[0066] In some embodiments, the control of the first bridge arm of the first target phase and the second bridge arm of the first target phase to switch on / off states based on the first target control signal of at least one signal cycle includes:

[0067] Based on the first target control signal of at least one signal cycle, the on / off state of the first target phase is controlled to switch between a first on / off state, a second on / off state, and a third on / off state; the first on / off state is that both the first bridge arm and the second bridge arm of the first target phase are off; the second on / off state is that the first bridge arm of the first target phase is on and the second bridge arm of the first target phase is off; the third on / off state is that the first bridge arm of the first target phase is off and the second bridge arm of the first target phase is on.

[0068] In some embodiments, the preset control signal includes a high-level signal and a low-level signal within one cycle. The high-level signal is used to control the bridge arm to conduct, i.e., the switching device in the bridge arm is turned on, and the low-level signal is used to control the bridge arm to turn off, i.e., the switching device in the bridge arm is turned off. For example, the preset control signal can be a PWM (Pulse Width Modulation) signal. The first target control signal is determined by setting a first preset dead time on the preset control signal. Specifically, each rising edge of the preset control signal is delayed by the first preset dead time, i.e., the conduction time of the bridge arm is delayed by inserting the first preset dead time into the preset control signal.

[0069] In some embodiments, complementary PWM signals are typically used to control the upper and lower bridge arms of the same phase in the inverter circuit. For complementary PWM signals, the waveforms of the two PWM signals are opposite to each other; when one PWM signal is high, the other is low, and vice versa. To prevent the upper and lower bridge arms of the same phase from conducting simultaneously, a dead time is set between the complementary PWM signals, ensuring that both the upper and lower bridge arms are off when the two complementary PWM signals switch. When the preset control signal is a complementary PWM signal, a first target control signal can be obtained by setting a first preset dead time between the complementary PWM signals. The first target control signal includes two signals, which are used to control the upper and lower bridge arms of the first target phase respectively. Since the dead time can prevent the two bridge arms from being turned on at the same time, under the control of the first target control signal, the upper and lower bridge arms of the first target phase will not both be in a conducting state. That is, under the control of the first target control signal, the upper and lower bridge arms of the first target phase have three on / off states: the first on / off state, the second on / off state, and the third on / off state. The first on / off state means that both the upper and lower bridge arms of the first target phase are in a turned-off state. The second on / off state means that the upper bridge arm of the first target phase is in a conducting state and the lower bridge arm is in a turned-off state. The third on / off state means that the upper bridge arm of the first target phase is in a turned-off state and the lower bridge arm is in a conducting state.

[0070] It should be noted that the order of the first on / off state, the second on / off state, and the third on / off state is not limited. The actual switching order needs to be determined according to the first target control signal. Furthermore, the above three on / off states are matched with one signal cycle of the first target control signal. That is, under the action of the first target control signal in one signal cycle, the first target phase will have the above three on / off states.

[0071] In this embodiment, a first target control signal can be obtained by setting a first preset dead time to the preset control signal. Under the action of the first target control signal, the upper and lower bridge arms of the first target phase will not be simultaneously turned on, thereby avoiding the situation where the switching devices of the upper and lower bridge arms are simultaneously turned on and cause a shoot-through short circuit.

[0072] In some embodiments, the first target control signal includes a first bridge arm control signal and a second bridge arm control signal, the preset control signal includes a first preset control signal and a second preset control signal, the sum of the duty cycles of the first preset control signal and the second preset control signal is 1, and obtaining the actual output voltage and first phase current of the first target phase in the first operating state includes:

[0073] The preset turn-off signal is input to the first bridge arm of the second target phase, and the preset turn-on signal is input to the second bridge arm of the second target phase. Simultaneously, the first bridge arm control signal and the second bridge arm control signal are input to the first bridge arm of the first target phase, so that the inverter circuit is in the first operating state. The first bridge arm control signal is determined based on the first preset control signal and the first preset dead time, and the second bridge arm control signal is determined based on the second preset control signal and the first preset dead time.

[0074] When the inverter circuit is in the first operating state, the actual output voltage of the first target phase and the first phase current of the first target phase are obtained.

[0075] In some embodiments, the preset control signal includes a first preset control signal and a second preset control signal, wherein the sum of the duty cycles of the first preset control signal and the second preset control signal is 1, that is, the first preset control signal and the second preset control signal are complementary signals. For example, the first preset control signal and the second preset control signal can be complementary PWM signals. Since the first target control signal is determined by setting a first preset dead time on the preset control signal, the first target control signal also includes two signals, namely a first bridge arm control signal and a second bridge arm control signal. The first bridge arm control signal is determined based on the first preset control signal and the first preset dead time, that is, the first bridge arm control signal is determined by setting the first preset dead time on the first preset control signal. The second bridge arm control signal is determined based on the second preset control signal and the first preset dead time, that is, the second bridge arm control signal is determined by setting the first preset dead time on the second preset control signal.

[0076] In some embodiments, a preset turn-off signal is input to the upper arm of the second target phase, a preset turn-on signal is input to the lower arm of the second target phase, and simultaneously a first arm control signal is input to the upper arm of the first target phase, and a second arm control signal is input to the lower arm of the first target phase, so that the inverter circuit is in a first operating state. The preset turn-off signal is used to control the upper arm of the second target phase to be in a turn-off state; the preset turn-off signal can be a low-level signal. The preset turn-on signal is used to control the lower arm of the second target phase to be in a turn-on state; the preset turn-on signal can be a high-level signal. When the inverter circuit is in the first operating state, the actual output voltage of the first target phase and the first phase current of the first target phase are acquired.

[0077] It should be noted that in the embodiments of this application, "bridge arm conduction" refers to the switching device in the bridge arm being turned on, and "bridge arm deactivation" refers to the switching device in the bridge arm being turned off.

[0078] For example, see Figure 3 , Figure 3 This application provides a schematic diagram of the waveforms of an on / off state control signal and the first phase current, as shown in the embodiments of this application. Figure 2 The inverter circuit shown defines phase a as the first target phase, and phases b and c as the second target phases. A low-level signal is input to the upper arm of phases b and c, and a high-level signal is input to the lower arm of phases b and c. A first arm control signal is input to the upper arm of phase a, and a second arm control signal is input to the lower arm of phase a, thus putting the inverter circuit in a first operating state. When the inverter circuit is in the first operating state, the first phase current of phase a is as follows: Figure 3 As shown. Figure 3 The preset control signal for one signal cycle includes two parts: time ① and time ②. Dead time ① and dead time ② are the same, both being the first preset dead time.

[0079] See Figure 4 , Figure 4 This application provides a schematic diagram of the on / off state of a bridge arm. During the non-dead time period ①, the upper bridge arm of phase a is on and the lower bridge arm is off; the upper bridge arm of phase b is off and the lower bridge arm is on; and the upper bridge arm of phase c is off and the lower bridge arm is on. The on / off states of each bridge arm in the inverter circuit are as follows: Figure 4 As shown. See also Figure 5 , Figure 5 This application provides a schematic diagram of the on / off state of a bridge arm. During the non-dead time period of time ②, the upper bridge arm of phase a is off and the lower bridge arm is on; the upper bridge arm of phase b is off and the lower bridge arm is on; and the upper bridge arm of phase c is off and the lower bridge arm is on. The on / off states of each bridge arm in the inverter circuit are as follows: Figure 5 As shown. See also Figure 6 , Figure 6This application provides a schematic diagram of the on / off states of a bridge arm. During the dead time periods of time ① and time ②, the upper and lower bridge arms of phase a are off, the upper bridge arm of phase b is off and the lower bridge arm is on, and the upper and lower bridge arms of phase c are off and the lower bridge arm is on. The on / off states of each bridge arm in the inverter circuit are as follows: Figure 6 As shown.

[0080] In this embodiment of the application, the upper arm of the inverter circuit is turned off and the lower arm of the other phases (excluding the phase to be compensated) is turned on. The upper and lower arms of the phase to be compensated are controlled by a first target control signal. The first target control signal is obtained by setting a first preset dead time on a preset control signal so that the inverter circuit is in a first working state. The first phase current of the phase to be compensated in the first working state is obtained. Then, the inverter circuit is further controlled to a second working state by different control signals to obtain the second phase current of the phase to be compensated in the second working state. Based on the first phase current and the second phase current, the dead time compensation voltage corresponding to the phase to be compensated can be obtained, so as to achieve accurate dead time compensation for each phase in the inverter circuit.

[0081] In some embodiments, when the second operating state is characterized by the first bridge arm of the second target phase being off and the second bridge arm of the second target phase being on, and the first bridge arm of the first target phase being switched between on and off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase being switched between on and off states based on a third target control signal, wherein the second target control signal is the preset control signal and the third target control signal is the preset off signal, the step of acquiring the second phase current of the first target phase in the second operating state includes:

[0082] The preset turn-off signal is input to the first bridge arm of the second target phase and the second bridge arm of the first target phase, the preset turn-on signal is input to the second bridge arm of the second target phase, and the first preset control signal is input to the first bridge arm of the first target phase, so that the inverter circuit is in the second working state.

[0083] When the inverter circuit is in the second operating state, the second phase current of the first target phase is obtained.

[0084] In some embodiments, when the second target control signal is a preset control signal and the third target control signal is a preset turn-off signal, the preset turn-off signal is input to the upper arm of the second target phase and the lower arm of the first target phase, the preset turn-on signal is input to the lower arm of the second target phase, and the first preset control signal is input to the upper arm of the first target phase, so that the inverter circuit is in a second operating state. The preset turn-off signal is used to control the upper arm of the second target phase and the lower arm of the first target phase to be in a turn-off state, and the preset turn-on signal is used to control the lower arm of the second target phase to be in a turn-on state. When the inverter circuit is in the second operating state, the second phase current of the first target phase is acquired.

[0085] For example, see Figure 7 , Figure 7 This application provides a schematic diagram of the waveforms of an on / off state control signal and the second phase current, as shown in the embodiments of this application. Figure 2 The inverter circuit shown designates phase a as the first target phase, and phases b and c as the second target phases. A low-level signal is input to the upper bridge arm of phases b and c, and a high-level signal is input to the lower bridge arm of phases b and c. A first preset control signal is input to the upper bridge arm of phase a, and a low-level signal is input to the lower bridge arm of phase a, thus putting the inverter circuit into a second operating state. In this second operating state, the second-phase current of phase a is as follows: Figure 7 As shown, Figure 7 The preset control signal for one signal cycle includes two parts: time ① and time ②.

[0086] During time period ①, the upper arm of phase a is on and the lower arm is off; the upper arm of phase b is off and the lower arm is on; the upper arm of phase c is off and the lower arm is on. The on / off states of each arm in the inverter circuit are as follows: Figure 4 As shown. During time period ②, the upper and lower arms of phase a are off, the upper arm of phase b is off and the lower arm is on, and the upper arm of phase c is off and the lower arm is on. The on / off states of each arm in the inverter circuit are as follows. Figure 6 As shown.

[0087] This embodiment first controls the upper arm of the other phases in the inverter circuit (excluding the phase to be compensated) to be turned off and the lower arm to be turned on. The upper arm of the phase to be compensated is controlled by a first arm control signal, and the lower arm is controlled by a second arm control signal. The first phase current of the phase to be compensated is obtained. The first arm control signal is determined by setting a first preset dead time on a first preset control signal, and the second arm control signal is determined by setting a first preset dead time on a second preset control signal. The first preset control signal and the second preset control signal are complementary signals. Then, the upper arm of the other phases in the inverter circuit (excluding the phase to be compensated) is turned off and the lower arm to be turned on. The upper arm of the phase to be compensated is controlled by the first preset control signal, and the lower arm is turned off. The second phase current of the phase to be compensated is obtained. Based on the first phase current and the second phase current, the dead time compensation voltage corresponding to the phase to be compensated can be obtained, realizing accurate dead time compensation for each phase in the inverter circuit.

[0088] In some embodiments, determining the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current includes:

[0089] Obtain the winding resistance of the target motor;

[0090] Based on the winding resistance, the first phase current, and the second phase current, determine the first target compensation voltage of the first target phase;

[0091] The target output voltage is determined based on the actual output voltage and the first target compensation voltage.

[0092] In some embodiments, the dead zone compensation voltage corresponding to the first target can be determined based on the first phase current, the second phase current, and the winding resistance of the target motor. The actual output voltage of the first target phase can be compensated based on the dead zone compensation voltage to obtain the target output voltage of the first target phase. The target output voltage can be used to drive the target motor.

[0093] In some embodiments, the actual output voltage of the first target phase is an AC voltage, and the first-phase current and second-phase current of the first target phase are AC currents, whose effective values ​​can be used in calculations. After obtaining the first target compensation voltage of the first target phase, the effective value of the actual output voltage of the first target phase can be compensated according to the sign of the first-phase current. Specifically, the effective value of the actual output voltage is determined as the actual effective voltage. When the first-phase current is greater than or equal to 0, the sum of the actual effective voltage and the first target compensation voltage is determined as the target output voltage; when the first-phase current is less than or equal to 0, the difference between the actual effective voltage and the first target compensation voltage is determined as the target output voltage.

[0094] This application embodiment implements different dead-zone-related control methods on the on / off states of the upper and lower bridge arms of the phase to be compensated in the inverter circuit, and detects the phase current under different control methods. The dead-zone compensation voltage corresponding to the phase to be compensated can be obtained based on the phase current under different control methods and the winding resistance of the motor. Based on the dead-zone compensation voltage and the actual output voltage of the phase to be compensated, a target output voltage without distortion can be obtained. The motor can be driven based on the target output voltage, which can improve the overall performance and efficiency of the motor system.

[0095] In some embodiments, determining the first target compensation voltage of the first target phase based on the winding resistance, the first phase current, and the second phase current includes:

[0096] The effective value of the first phase current is determined as the first effective current, and the effective value of the second phase current is determined as the second effective current;

[0097] The difference between the second effective current and the first effective current is determined as the first target difference current;

[0098] The product of the winding resistance and the first target differential current is determined as the first target compensation voltage.

[0099] In some embodiments, the effective value of the first phase current is determined as the first effective current i1, the effective value of the second phase current is determined as the second effective current i2, the winding resistance of the target motor is R, then the first target differential current is i2-i1, and the first target compensation voltage of the first target phase is R·(i2-i1).

[0100] This application embodiment implements different dead-time-related control methods on the on / off states of the upper and lower bridge arms of the phase to be compensated in the inverter circuit, and detects the phase current under different control methods. Based on the phase current under different control methods and the winding resistance of the motor, the corresponding dead-time compensation voltage can be obtained, thereby achieving accurate dead-time compensation for each phase in the inverter circuit.

[0101] In some embodiments, when the second operating state is that the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on, the state of controlling the on / off state of the first bridge arm of the first target phase based on the second target control signal of at least one signal cycle, and controlling the on / off state of the second bridge arm of the first target phase based on the third target control signal, wherein the second target control signal includes a third bridge arm control signal and a fourth bridge arm control signal, and the third target control signal is the second target control signal of at least one signal cycle, the step of obtaining the second phase current of the first target phase in the second operating state further includes:

[0102] The preset turn-off signal is input to the first bridge arm of the second target phase, the preset turn-on signal is input to the second bridge arm of the second target phase, the third bridge arm control signal is simultaneously input to the first bridge arm of the first target phase, and the fourth bridge arm control signal is input to the second bridge arm of the first target phase, so that the inverter circuit is in the second operating state; the third bridge arm control signal is determined based on the first preset control signal and the second preset dead time, and the fourth bridge arm control signal is determined based on the second preset control signal and the second preset dead time, wherein the first preset dead time and the second preset dead time are different;

[0103] When the inverter circuit is in the second operating state, the second phase current of the first target phase is obtained.

[0104] In some embodiments, where the second target control signal is determined by setting a second preset dead time on a preset control signal, and the third target control signal is a second target control signal for at least one signal cycle, the second target control signal includes a third bridge arm control signal and a fourth bridge arm control signal. The third bridge arm control signal is determined based on a first preset control signal and a second preset dead time, that is, the third bridge arm control signal is determined by setting a second preset dead time on the first preset control signal. The fourth bridge arm control signal is determined based on a second preset control signal and a second preset dead time, that is, the fourth bridge arm control signal is determined by setting a second preset dead time on the second preset control signal.

[0105] In some embodiments, a preset turn-off signal is input to the upper arm of the second target phase, a preset turn-on signal is input to the lower arm of the second target phase, a third arm control signal is simultaneously input to the upper arm of the first target phase, and a fourth arm control signal is input to the lower arm of the first target phase, so that the inverter circuit is in the second operating state. The preset turn-off signal is used to control the upper arm of the second target phase to be in the off state, and the preset turn-on signal is used to control the lower arm of the second target phase to be in the on state. When the inverter circuit is in the second operating state, the second phase current of the first target phase is acquired.

[0106] For example, see Figure 8 , Figure 8 This application provides a schematic diagram of the waveforms of an on / off state control signal and phase current, which is relevant to embodiments of the present application. Figure 2 The inverter circuit shown defines phase a as the first target phase, phases b and c as the second target phases, inputs a low-level signal to the upper bridge arm of phases b and c, inputs a high-level signal to the lower bridge arm of phases b and c, inputs a third bridge arm control signal to the upper bridge arm of phase a, and inputs a fourth bridge arm control signal to the lower bridge arm of phase a, so that the inverter circuit is in the second operating state. Figure 8The preset control signal for one signal cycle includes two parts: time ① and time ②. Dead zone ① and dead zone ② are the same, both being the first preset dead zone time. The adjustment of dead zone ① and dead zone ② are the same, both being the second preset dead zone time. The first preset dead zone time and the second preset dead zone time are different. Figure 8 The input signal to the first half of the upper and lower bridge arms of phase a is the first target control signal. That is, the signal portions of dead zones ① and ② are the first target control signal, and the corresponding phase current in the first half is the first phase current. Figure 8 The signals input to the latter half of the upper and lower bridge arms of phase a are the second target control signals. That is, the signals for adjusting dead zone ① and dead zone ② are the second target control signals. The phase current corresponding to the latter half is the second phase current. Specifically, the signals input to the first half of the upper bridge arm of phase a (i.e., the signals for adjusting dead zone ①) are the first bridge arm control signals, the signals input to the first half of the lower bridge arm of phase a (i.e., the signals for adjusting dead zone ②) are the second bridge arm control signals, the signals input to the latter half of the upper bridge arm of phase a (i.e., the signals for adjusting dead zone ①) are the third bridge arm control signals, and the signals input to the latter half of the lower bridge arm of phase a (i.e., the signals for adjusting dead zone ②) are the fourth bridge arm control signals.

[0107] During the non-dead time period of time ①, the upper arm of phase a is on and the lower arm is off, the upper arm of phase b is off and the lower arm is on, and the upper arm of phase c is off and the lower arm is on. The on / off states of each arm in the inverter circuit are as follows: Figure 4 As shown. During the non-dead time period of time ②, the upper arm of phase a is off and the lower arm is on, the upper arm of phase b is off and the lower arm is on, and the upper arm of phase c is off and the lower arm is on. The on / off states of each arm in the inverter circuit are as follows. Figure 5 As shown. During the dead time periods of time ① and time ②, the upper and lower arms of phase a are off, the upper arm of phase b is off and the lower arm is on, and the upper arm of phase c is off and the lower arm is on. The on / off states of each arm in the inverter circuit are as follows. Figure 6 As shown.

[0108] This embodiment first controls the upper arm of the inverter circuit (excluding the phase to be compensated) to turn off and the lower arm to turn on. The upper arm of the phase to be compensated is controlled by a first arm control signal, and the lower arm is controlled by a second arm control signal. The first phase current of the phase to be compensated is obtained. The first arm control signal is determined by setting a first preset dead time on a first preset control signal, and the second arm control signal is determined by setting a first preset dead time on a second preset control signal. The first and second preset control signals are complementary signals. Then, the upper arm of the inverter circuit (excluding the phase to be compensated) is controlled... When the upper bridge arm is turned off and the lower bridge arm is turned on, the upper bridge arm of the phase to be compensated is controlled by the third bridge arm control signal, and the lower bridge arm is controlled by the fourth bridge arm control signal. The second phase current of the phase to be compensated is obtained. The third bridge arm control signal is determined by setting a second preset dead time on the first preset control signal, and the fourth bridge arm control signal is determined by setting a second preset dead time on the second preset control signal. The first preset dead time and the second preset dead time are different. Based on the first phase current and the second phase current, the dead time compensation voltage corresponding to the phase to be compensated can be obtained, realizing accurate dead time compensation for each phase in the inverter circuit.

[0109] In some embodiments, determining the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current further includes:

[0110] Obtain the winding resistance of the target motor and the preset signal period of the preset control signal;

[0111] Based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current, the second target compensation voltage of the first target phase is determined;

[0112] The target output voltage is determined based on the actual output voltage and the second target compensation voltage.

[0113] In some embodiments, the dead zone compensation voltage corresponding to the first target can be determined based on the first phase current, the second phase current, the winding resistance of the target motor, the preset signal period of the preset control signal, the first preset dead zone time, and the second preset dead zone time. The target output voltage of the first target phase can be obtained by compensating the actual output voltage of the first target phase based on the dead zone compensation voltage. The target output voltage can be used to drive the target motor.

[0114] In some embodiments, after obtaining the second target compensation voltage of the first target phase, the effective value of the actual output voltage of the first target phase can be compensated according to the sign of the first phase current. Specifically, the effective value of the actual output voltage is determined as the actual effective voltage. When the first phase current is greater than or equal to 0, the sum of the actual effective voltage and the second target compensation voltage is determined as the target output voltage; when the first phase current is less than or equal to 0, the difference between the actual effective voltage and the second target compensation voltage is determined as the target output voltage.

[0115] This application embodiment implements different dead-time-related control methods on the on / off states of the upper and lower bridge arms of the phase to be compensated in the inverter circuit, and detects the phase current under different control methods. Based on the phase current, dead time, motor winding resistance, and the period of the on / off state control signal under different control methods, the corresponding dead-time compensation voltage can be obtained. Based on the dead-time compensation voltage and the actual output voltage of the phase to be compensated, a target output voltage without distortion can be obtained. The motor can be driven based on the target output voltage, which can improve the overall performance and efficiency of the motor system.

[0116] In some embodiments, determining the second target compensation voltage of the first target phase based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current includes:

[0117] The effective value of the first phase current is determined as the third effective current, and the effective value of the second phase current is determined as the fourth effective current;

[0118] The difference between the third effective current and the fourth effective current is determined as the second target difference current, and the reciprocal of the difference between the first preset dead time and the second preset dead time is determined as the target difference dead time.

[0119] The second target compensation voltage is determined by the product of the winding resistance, the preset signal period, the second target difference current, and the target difference dead time.

[0120] In some embodiments, the effective value of the first phase current is determined as the third effective current i3, the effective value of the second phase current is determined as the fourth effective current i4, the winding resistance of the target motor is R, the preset signal period of the preset control signal is T, and the first preset dead time is T. d1 The second preset dead time is T. d2 Then the second target difference current is i3-i4, and the target difference dead time is 1 / (T d1 -T d2 The second target compensation voltage of the first target phase is...

[0121] This application embodiment implements different dead-time-related control methods on the on / off states of the upper and lower bridge arms of the phase to be compensated in the inverter circuit, and detects the phase current under different control methods. Based on the phase current and dead time under different control methods, the winding resistance of the motor, and the period of the on / off state control signal, the corresponding dead-time compensation voltage can be obtained, thereby achieving accurate dead-time compensation for each phase in the inverter circuit.

[0122] This application provides an embodiment of an inverter circuit output voltage processing method. The inverter circuit includes multiple phases and a power supply. Each phase includes a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply. The method includes: acquiring the actual output voltage and first phase current of a first target phase in a first operating state; the first operating state is that the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on; and controlling the first bridge arm and the second bridge arm of the first target phase to switch between on and off states based on a first target control signal of at least one signal cycle. The first target phase is any one of the multiple phases, and the second target phase is any other phase among the multiple phases except the first target phase. The first target control signal controls a preset control... The system sets a first preset dead time for the control signal; acquires the second phase current of the first target phase in a second operating state; the second operating state is that the first bridge arm of the second target phase is off, and the second bridge arm of the second target phase is on; controls the first bridge arm of the first target phase to switch between on and off states based on a second target control signal based on at least one signal cycle, and controls the on and off states of the second bridge arm of the first target phase based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is either a preset off signal or the second target control signal based on at least one signal cycle; determines the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current; the target output voltage is used to drive the target motor. In this embodiment, the first phase current of the phase to be compensated in the first operating state and the second phase current in the second operating state are detected respectively. The first operating state refers to the state in which the upper bridge arm of all phases except the phase to be compensated in the inverter circuit is off and the lower bridge arm is on, and the upper and lower bridge arms of the phase to be compensated are controlled by a first target control signal, which is obtained by setting a first preset dead time on a preset control signal. The second operating state refers to the state in which the upper bridge arm of all phases except the phase to be compensated in the inverter circuit is off and the lower bridge arm is on, the upper bridge arm of the phase to be compensated is controlled by a second target control signal, and the lower bridge arm of the phase to be compensated is controlled by a third target control signal, where the second target control signal is determined based on a preset control signal, and the third target control signal is either a preset turn-off signal or the second target control signal. By implementing different dead-time-related control methods on the on / off states of the upper and lower bridge arms of the phase to be compensated in the inverter circuit and detecting the phase current under different control methods, the corresponding dead-time compensation voltage can be obtained based on the phase current under different control methods, thus achieving accurate dead-time compensation for each phase in the inverter circuit.

[0123] This application embodiment also provides an output voltage processing device for an inverter circuit. The inverter circuit includes multiple phases and a power supply. Each phase includes a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply. See [link to relevant documentation]. Figure 9 The device includes:

[0124] The first phase current acquisition module 910 is used to acquire the actual output voltage and first phase current of the first target phase in a first operating state; the first operating state is that the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and the first target control signal based on at least one signal cycle controls the first bridge arm and the second bridge arm of the first target phase to switch between on and off states. The first target phase is any one of the plurality of phases, and the second target phase is any other phase among the plurality of phases except the first target phase. The first target control signal is determined by setting a first preset dead time for a preset control signal.

[0125] The second phase current acquisition module 920 is used to acquire the second phase current of the first target phase in a second operating state; the second operating state is that the first bridge arm of the second target phase is off, the second bridge arm of the second target phase is on, the first bridge arm of the first target phase is controlled to switch on / off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is controlled to switch on / off states based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is a preset off signal or the second target control signal of at least one signal cycle;

[0126] The output voltage determination module 930 is used to determine the target output voltage of the first target phase based on the actual output voltage, the first phase current and the second phase current; the target output voltage is used to drive the target motor.

[0127] In some embodiments, the first phase current acquisition module 910 includes:

[0128] An on / off state control unit is used to control the on / off state of the first target phase to switch between a first on / off state, a second on / off state, and a third on / off state based on a first target control signal of at least one signal cycle; the first on / off state is when both the first bridge arm and the second bridge arm of the first target phase are off; the second on / off state is when the first bridge arm of the first target phase is on and the second bridge arm of the first target phase is off; and the third on / off state is when the first bridge arm of the first target phase is off and the second bridge arm of the first target phase is on.

[0129] In some embodiments, the first target control signal includes a first bridge arm control signal and a second bridge arm control signal, the preset control signal includes a first preset control signal and a second preset control signal, the sum of the duty cycles of the first preset control signal and the second preset control signal is 1, and the first phase current acquisition module 910 includes:

[0130] A first signal input unit is configured to input the preset turn-off signal to the first bridge arm of the second target phase, input the preset turn-on signal to the second bridge arm of the second target phase, and simultaneously input the first bridge arm control signal to the first bridge arm of the first target phase and the second bridge arm control signal to the second bridge arm of the first target phase, so that the inverter circuit is in the first operating state; the first bridge arm control signal is determined based on the first preset control signal and the first preset dead time, and the second bridge arm control signal is determined based on the second preset control signal and the first preset dead time;

[0131] The first phase current acquisition unit is used to acquire the actual output voltage of the first target phase and the first phase current of the first target phase when the inverter circuit is in the first operating state.

[0132] In some embodiments, when the second operating state is that the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on, the first bridge arm of the first target phase is controlled to switch between on and off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is controlled to switch between on and off states based on a third target control signal, wherein the second target control signal is the preset control signal and the third target control signal is the preset off signal, the second phase current acquisition module 920 includes:

[0133] The second signal input unit is used to input the preset turn-off signal into the first bridge arm of the second target phase and the second bridge arm of the first target phase, input the preset turn-on signal into the second bridge arm of the second target phase, and input the first preset control signal into the first bridge arm of the first target phase, so that the inverter circuit is in the second working state.

[0134] The second phase current acquisition unit is used to acquire the second phase current of the first target phase when the inverter circuit is in the second operating state.

[0135] In some embodiments, the output voltage determination module 930 includes:

[0136] A winding resistance acquisition unit is used to acquire the winding resistance of the target motor.

[0137] The first compensation voltage determining unit is used to determine the first target compensation voltage of the first target phase based on the winding resistance, the first phase current and the second phase current.

[0138] The first output voltage determination unit is used to determine the target output voltage based on the actual output voltage and the first target compensation voltage.

[0139] In some embodiments, the first compensation voltage determining unit includes:

[0140] The first effective current determination subunit is used to determine the effective value of the first phase current as the first effective current and the effective value of the second phase current as the second effective current.

[0141] The first effective current processing subunit is used to determine the difference between the second effective current and the first effective current as the first target difference current;

[0142] The first compensation voltage determining subunit is used to determine the product of the winding resistance and the first target difference current as the first target compensation voltage.

[0143] In some embodiments, when the second operating state is that the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on, the state of controlling the first bridge arm of the first target phase to switch between on and off states based on the second target control signal of the at least one signal cycle, and controlling the on and off states of the second bridge arm of the first target phase based on the third target control signal, wherein the second target control signal includes a third bridge arm control signal and a fourth bridge arm control signal, and the third target control signal is the second target control signal of the at least one signal cycle, the second phase current acquisition module 920 further includes:

[0144] The third signal input unit is used to input the preset turn-off signal into the first bridge arm of the second target phase, input the preset turn-on signal into the second bridge arm of the second target phase, and simultaneously input the third bridge arm control signal into the first bridge arm of the first target phase and the fourth bridge arm control signal into the second bridge arm of the first target phase, so that the inverter circuit is in the second operating state; the third bridge arm control signal is determined based on the first preset control signal and the second preset dead time, and the fourth bridge arm control signal is determined based on the second preset control signal and the second preset dead time, wherein the first preset dead time and the second preset dead time are different;

[0145] The third phase current acquisition unit is used to acquire the second phase current of the first target phase when the inverter circuit is in the second operating state.

[0146] In some embodiments, the output voltage determination module 930 further includes:

[0147] A winding resistance and signal period acquisition unit is used to acquire the winding resistance of the target motor and the preset signal period of the preset control signal.

[0148] The second compensation voltage determination unit is used to determine the second target compensation voltage of the first target phase based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current.

[0149] The second output voltage determination unit is used to determine the target output voltage based on the actual output voltage and the second target compensation voltage.

[0150] In some embodiments, the second compensation voltage determining unit includes:

[0151] The second effective current determination subunit is used to determine the effective value of the first phase current as the third effective current and the effective value of the second phase current as the fourth effective current.

[0152] The second effective current processing subunit is used to determine the difference between the third effective current and the fourth effective current as the second target difference current, and to determine the reciprocal of the difference between the first preset dead time and the second preset dead time as the target difference dead time.

[0153] The second compensation voltage determination subunit is used to determine the second target compensation voltage by the product of the winding resistance, the preset signal period, the second target difference current and the target difference dead time.

[0154] The apparatus provided in the above embodiments can execute the method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in the above embodiments, please refer to the output voltage processing method for an inverter circuit provided in any embodiment of this application.

[0155] This embodiment also provides a computer-readable storage medium storing computer-executable instructions, which are loaded by a processor and executed by the processor to perform the output voltage processing method of an inverter circuit described above in this embodiment.

[0156] This embodiment also provides an electronic device, which includes a processor and a memory, wherein the memory stores a computer program adapted to be loaded by the processor and executed by the processor to perform the output voltage processing method of an inverter circuit described above in this embodiment.

[0157] The electronic device may be a computer terminal, a mobile terminal, or a server, and may also participate in constituting the apparatus or system provided in the embodiments of this application. For example... Figure 10 As shown, the electronic device 10 may include one or more processors 1002 (shown as 1002a, 1002b, ..., 1002n in the figure) (processor 1002 may include, but is not limited to, a microprocessor MCU or a programmable logic device FPLD, etc.), a memory 1004 for storing information, and a transmission device 1006 for communication functions. In addition, it may also include: input / output interfaces (I / O interfaces) and network interfaces. Those skilled in the art will understand that... Figure 10 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device described above. For example, electronic device 10 may also include... Figure 10 The more or fewer components shown, or having the same Figure 10 The different configurations shown.

[0158] It should be noted that the aforementioned one or more processors 1002 and / or other information processing circuits are generally referred to herein as "information processing circuits". These information processing circuits may be wholly or partially embodied in software, hardware, firmware, or any other combination thereof. Furthermore, the information processing circuits may be a single, independent processing module, or may be wholly or partially integrated into any other element within the electronic device 10.

[0159] The memory 1004 can be used to store software programs and modules of application software, such as the program instruction / information storage device corresponding to the method described in the embodiments of this application. The processor 1002 executes various functional applications and information processing by running the software programs and modules stored in the memory 1004, thereby realizing the above-described output voltage processing method for an inverter circuit. The memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1004 may further include memory remotely located relative to the processor 1002, and these remote memories can be connected to the electronic device 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0160] The transmission device 1006 is used to receive or send information via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the electronic device 10. In one example, the transmission device 1006 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 1006 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0161] This specification provides the operational steps of the methods described in the embodiments or flowcharts, but more or fewer operational steps may be included based on conventional or non-inventive labor. The steps and order listed in the embodiments are merely one possible execution order among many steps and do not represent the only execution order. In actual system or interrupt product execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0162] The structure shown in this embodiment is only a partial structure related to the solution of this application and does not constitute a limitation on the device to which the solution of this application is applied. Specific devices may include more or fewer components than shown, or combinations of certain components, or arrangements of different components. It should be understood that the methods, apparatuses, etc., disclosed in this embodiment can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or unit modules through some interfaces.

[0163] Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0164] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0165] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for processing the output voltage of an inverter circuit, characterized in that, The inverter circuit includes multiple phases and a power supply. Each phase includes a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply. The method includes: The actual output voltage and current of the first target phase in the first operating state are obtained; the first operating state is that the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and the first target phase and the second bridge arm of the first target phase are switched on and off based on a first target control signal based on at least one signal cycle. The first target phase is any one of the plurality of phases, and the second target phase is any other phase among the plurality of phases except the first target phase. The first target control signal is determined by setting a first preset dead time on a preset control signal. The second phase current of the first target phase in the second operating state is obtained; the second operating state is that the first bridge arm of the second target phase is turned off and the second bridge arm of the second target phase is turned on, the first bridge arm of the first target phase is controlled to switch between on and off states based on a second target control signal based on at least one signal cycle, and the on and off states of the second bridge arm of the first target phase are controlled based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is a preset turn-off signal or the second target control signal based on at least one signal cycle; Based on the actual output voltage, the first phase current, and the second phase current, the target output voltage of the first target phase is determined; the target output voltage is used to drive the target motor.

2. The output voltage processing method for the inverter circuit according to claim 1, characterized in that, The first target control signal, based on at least one signal cycle, controls the first bridge arm of the first target phase and the second bridge arm of the first target phase to switch between on and off states, including: Based on the first target control signal of at least one signal cycle, the on / off state of the first target phase is controlled to switch between a first on / off state, a second on / off state, and a third on / off state; the first on / off state is that both the first bridge arm and the second bridge arm of the first target phase are off; the second on / off state is that the first bridge arm of the first target phase is on and the second bridge arm of the first target phase is off; the third on / off state is that the first bridge arm of the first target phase is off and the second bridge arm of the first target phase is on.

3. The output voltage processing method for the inverter circuit according to claim 1, characterized in that, The first target control signal includes a first bridge arm control signal and a second bridge arm control signal. The preset control signal includes a first preset control signal and a second preset control signal. The sum of the duty cycles of the first preset control signal and the second preset control signal is 1. Obtaining the actual output voltage and first phase current of the first target phase in the first operating state includes: The preset turn-off signal is input to the first bridge arm of the second target phase, and the preset turn-on signal is input to the second bridge arm of the second target phase. Simultaneously, the first bridge arm control signal and the second bridge arm control signal are input to the first bridge arm of the first target phase, so that the inverter circuit is in the first operating state. The first bridge arm control signal is determined based on the first preset control signal and the first preset dead time, and the second bridge arm control signal is determined based on the second preset control signal and the first preset dead time. When the inverter circuit is in the first operating state, the actual output voltage of the first target phase and the first phase current of the first target phase are obtained.

4. The output voltage processing method for the inverter circuit according to claim 3, characterized in that, In the second operating state, where the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on, and the first bridge arm of the first target phase is switched between on and off states based on the second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is switched between on and off states based on the third target control signal, wherein the second target control signal is the preset control signal and the third target control signal is the preset off signal, the step of acquiring the second phase current of the first target phase in the second operating state includes: The preset turn-off signal is input to the first bridge arm of the second target phase and the second bridge arm of the first target phase, the preset turn-on signal is input to the second bridge arm of the second target phase, and the first preset control signal is input to the first bridge arm of the first target phase, so that the inverter circuit is in the second working state. When the inverter circuit is in the second operating state, the second phase current of the first target phase is obtained.

5. The output voltage processing method for the inverter circuit according to claim 4, characterized in that, Determining the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current includes: Obtain the winding resistance of the target motor; Based on the winding resistance, the first phase current, and the second phase current, determine the first target compensation voltage of the first target phase; The target output voltage is determined based on the actual output voltage and the first target compensation voltage.

6. The output voltage processing method for the inverter circuit according to claim 5, characterized in that, Determining the first target compensation voltage for the first target phase based on the winding resistance, the first phase current, and the second phase current includes: The effective value of the first phase current is determined as the first effective current, and the effective value of the second phase current is determined as the second effective current; The difference between the second effective current and the first effective current is determined as the first target difference current; The product of the winding resistance and the first target differential current is determined as the first target compensation voltage.

7. The output voltage processing method for the inverter circuit according to claim 3, characterized in that, In the second operating state, where the first bridge arm of the second target phase is off and the second bridge arm of the second target phase is on, the first bridge arm of the first target phase is switched between on and off states based on the second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is switched between on and off states based on the third target control signal, wherein the second target control signal includes a third bridge arm control signal and a fourth bridge arm control signal, and the third target control signal is the second target control signal of at least one signal cycle, the step of acquiring the second phase current of the first target phase in the second operating state further includes: The preset turn-off signal is input to the first bridge arm of the second target phase, the preset turn-on signal is input to the second bridge arm of the second target phase, the third bridge arm control signal is simultaneously input to the first bridge arm of the first target phase, and the fourth bridge arm control signal is input to the second bridge arm of the first target phase, so that the inverter circuit is in the second operating state; the third bridge arm control signal is determined based on the first preset control signal and the second preset dead time, and the fourth bridge arm control signal is determined based on the second preset control signal and the second preset dead time, wherein the first preset dead time and the second preset dead time are different; When the inverter circuit is in the second operating state, the second phase current of the first target phase is obtained.

8. The output voltage processing method for the inverter circuit according to claim 7, characterized in that, The step of determining the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current further includes: Obtain the winding resistance of the target motor and the preset signal period of the preset control signal; Based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current, the second target compensation voltage of the first target phase is determined; The target output voltage is determined based on the actual output voltage and the second target compensation voltage.

9. The output voltage processing method for the inverter circuit according to claim 8, characterized in that, The step of determining the second target compensation voltage of the first target phase based on the winding resistance, the preset signal period, the first preset dead time, the second preset dead time, the first phase current, and the second phase current includes: The effective value of the first phase current is determined as the third effective current, and the effective value of the second phase current is determined as the fourth effective current; The difference between the third effective current and the fourth effective current is determined as the second target difference current, and the reciprocal of the difference between the first preset dead time and the second preset dead time is determined as the target difference dead time. The second target compensation voltage is determined by the product of the winding resistance, the preset signal period, the second target difference current, and the target difference dead time.

10. An output voltage processing device for an inverter circuit, characterized in that, The inverter circuit includes multiple phases and a power supply. Each phase includes a first bridge arm connected to the positive terminal of the power supply and a second bridge arm connected to the negative terminal of the power supply. The device includes: The first phase current acquisition module is used to acquire the actual output voltage and first phase current of the first target phase in the first operating state; the first operating state is the state in which the first bridge arm of the second target phase is turned off, the second bridge arm of the second target phase is turned on, and the state in which the first bridge arm and the second bridge arm of the first target phase are controlled by a first target control signal based on at least one signal cycle to switch between on and off states; the first target phase is any one of the plurality of phases, the second target phase is any other phase among the plurality of phases except the first target phase, and the first target control signal is determined by setting a first preset dead time on a preset control signal; The second phase current acquisition module is used to acquire the second phase current of the first target phase in a second operating state; the second operating state is that the first bridge arm of the second target phase is off, the second bridge arm of the second target phase is on, the first bridge arm of the first target phase is controlled to switch between on and off states based on a second target control signal of at least one signal cycle, and the second bridge arm of the first target phase is controlled to switch between on and off states based on a third target control signal; the second target control signal is determined based on the preset control signal, and the third target control signal is a preset off signal or the second target control signal of at least one signal cycle; The output voltage determination module is used to determine the target output voltage of the first target phase based on the actual output voltage, the first phase current, and the second phase current; the target output voltage is used to drive the target motor.

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