Low-power-consumption high-efficiency bus balancing bridge circuit and control method thereof

Abstract

The application relates to the technical field of half-bus voltage balance bridge, in particular to a low-power-consumption high-efficiency bus balance bridge circuit and a control method thereof, which comprises a main power module, a half-bus voltage sampling module and a controller module.The main power module is a power conversion unit with a bus midpoint, which is used for converting direct-current bus electric energy into two-phase alternating-current electric energy and outputting the two-phase alternating-current electric energy; the half-bus voltage sampling module is connected with upper and lower half-bus capacitors of the main power module and receives a signal input of the controller module; the controller module is connected with a control end of a half-bus voltage balance bridge module; and the half-bus voltage balance bridge module is used for receiving a driving signal of the controller module and adjusting half-bus voltage balance of the main power module.The application has the effect of significantly reducing the volume and loss of the balance control circuit, improving the system power density and energy efficiency under the premise of realizing effective half-bus voltage balance.

Description

Technical Field

[0001] This application relates to the field of half-bus voltage balancing bridge technology, and in particular to a low-power, high-efficiency bus balancing bridge circuit and its control method. Background Technology

[0002] Half-bus voltage balance control in a split-phase power grid T-type three-level circuit is a core technology for ensuring stable system operation in the field of power electronic conversion. It is widely used in power electronic conversion scenarios such as photovoltaic inverters, energy storage converters, industrial frequency converters, uninterruptible power supplies, and vehicle power supplies. Its core function is to eliminate the potential offset between the upper and lower half-buses caused by factors such as discrete power device parameters, differences in drive signal delays, deviations in magnetic component characteristics, and load imbalances through real-time acquisition, precise regulation, and equalization control of the half-bus voltage. This ensures the output stability, operational safety, and energy conversion efficiency of the power conversion system.

[0003] In related technologies, the half-bus voltage balance control of the T-type three-level circuit in a split-phase power grid mainly adopts two technical solutions: pure software algorithm control and hardware control with the addition of a fourth bridge arm. By adjusting the algorithm logic or by adding an additional hardware bridge arm, the potential balance of the upper and lower half-buses is achieved, maintaining the normal power conversion operation of the circuit system. However, in practical applications, the pure software algorithm control scheme has obvious technical limitations. Under complex operating conditions such as sudden load changes and non-resistive asymmetrical loads, the algorithm's dynamic response speed cannot match the instantaneous change rate of the operating conditions, which easily leads to control delays or even failures. It cannot correct the bus voltage imbalance in time, and it cannot achieve decoupling between main power control and bus voltage balance control. It also introduces a DC current component into the system, causing the system's technical indicators to exceed the limits. At the same time, this scheme is only suitable for circuit topologies with zero vectors, such as NPC-I type three-level circuits, and is not suitable for T-type three-level circuits, resulting in extremely poor topology adaptability.

[0004] Regarding the aforementioned technologies, neither of the two solutions can simultaneously achieve low power consumption, small size, low cost, and wide topology adaptability while maintaining effective voltage balance. This not only leads to a decrease in the power conversion stability of the T-type three-level circuit in the split-phase power grid, potentially causing power supply system failures and hardware damage in severe cases, but also reduces the competitiveness of the product in engineering applications due to high losses, large size, and high cost, thus hindering the development of power electronic conversion systems towards high efficiency, miniaturization, and high adaptability. Summary of the Invention

[0005] In order to significantly reduce the size and loss of the balancing control circuit and improve the system power density and energy efficiency while achieving effective half-bus voltage balancing, this application provides a low-power, high-efficiency bus balancing bridge circuit and its control method.

[0006] Firstly, this application provides a low-power, high-efficiency bus balance bridge circuit: A low-power, high-efficiency bus balancing bridge circuit includes: The main power module is a power conversion unit with a bus midpoint, used to convert DC bus power into two-phase AC power and output it to the outside. Its bus is divided into an upper bus and a lower bus, which are respectively configured with upper bus capacitors and lower bus capacitors. A half-bus voltage sampling module, wherein the acquisition end of the half-bus voltage sampling module is connected to the upper and lower half-bus capacitors of the main power module, and the output end is connected to the signal input end of the controller module; The controller module, the output of which is connected to the control terminal of the half-bus voltage balance bridge module; A half-bus voltage balancing bridge module is used to receive the PWM drive signal from the controller module and adjust the half-bus voltage balance of the main power module. The half-bus voltage balancing bridge module includes a first switching transistor unit, a second switching transistor unit, and a filter inductor unit. The input terminal of the first switching transistor unit is connected to the high-voltage bus terminal, and the output terminal is connected to the first terminal of the filter inductor unit. The input terminal of the second switching transistor unit is connected to the first terminal of the filter inductor unit, and the output terminal is connected to the low-voltage bus terminal. The second terminal of the filter inductor unit is connected to the midpoint of the bus of the main power module.

[0007] By adopting the above technical solution, a complete half-bus voltage balance closed-loop control system integrating sampling, calculation, judgment, and control is formed. Utilizing a simplified balanced bridge topology with dual MOSFETs and a single inductor, it eliminates the need for MOSFET arrays and filter inductors of the same specifications as the main power bridge arm. Half-bus voltage balance regulation can be achieved with minimal hardware increment, which helps to solve the core defects of existing solutions that add a fourth bridge arm, such as large size, high hardware cost, and significant switching and magnetic losses. At the same time, it achieves complete decoupling between half-bus voltage balance control and main power control, eliminating the need to superimpose a midpoint potential adjustment strategy in the main power control logic. This helps to solve the problems of introducing DC current components and exceeding technical specifications in pure software solutions, greatly simplifying the design of the main power loop control algorithm, and improving the system's power density, operational stability, and engineering application adaptability.

[0008] Optionally, the main power module is a T-type three-level circuit with two phases sharing a neutral line N, or a two-level neutral point clamping topology or a multi-level cascaded topology with a bus midpoint; the half-bus voltage balancing bridge module operates in DCM discontinuous conduction mode, and the switching transistor drive duty cycle D satisfies the following constraints: ; Where k is the voltage difference ratio between the upper and lower half bus capacitors, ensuring that the current of the filter inductor unit drops to zero in each switching cycle.

[0009] By adopting the above technical solution, on the one hand, it can directly adapt to various power topologies with bus midpoints, such as T-type three-level, two-level midpoint clamping, and multi-level cascade, without modifying the hardware structure of the main power unit. This solves the topology compatibility limitation of existing pure software algorithm solutions, which can only adapt to NPC-I type three-level and cannot adapt to T-type three-level, thus greatly expanding the application scenarios of the solution. On the other hand, through the duty cycle constraint of the DCM discontinuous conduction mode, it ensures that the current of the filter inductor unit drops to zero completely in each switching cycle, effectively limiting the current peak of the balance bridge circuit, reducing the copper loss, iron loss, and other magnetic component losses of the filter inductor, and reducing the size design requirements of the filter inductor, further improving the energy conversion efficiency and power density of the system.

[0010] Optionally, the switching transistors of the half-bus voltage balancing bridge module operate in ZVS (zero-voltage switching) mode, and the drive duty cycle satisfies the following constraints: ; At the same time, the drive duty cycle satisfies the low-frequency loss constraint: ; in, For the working cycle of the balance bridge, , , These are the inherent parameters of the resonant circuit formed by the parasitic capacitance of the switching transistor and the filter inductor unit. This is the capacitance value of the busbar. The desired voltage balance control time is given by m, where m is the number of resonance cycles. The half-bus voltage balancing bridge module selects the active switching transistor based on the magnitude of the upper and lower half-bus voltages, while the other switching transistor operates as a freewheeling transistor.

[0011] By adopting the above technical solutions, the duty cycle constraint of the ZVS zero-voltage switching mode can enable the switching transistor to turn on at the rising edge of the inductor current, and achieve zero-voltage turn-on by utilizing the conduction of the active transistor's body diode, which significantly reduces the switching losses of the switching transistor. The low-frequency loss constraint can optimize the lower limit of the duty cycle based on the actual voltage difference of the half-bus capacitor, and combined with the turn-on timing selection of the resonant period, effectively reduce the operating frequency of the balance bridge, and further reduce the overall system loss. At the same time, the active transistor and freewheeling transistor are dynamically selected according to the voltage difference between the upper and lower half-buses, which greatly simplifies the control logic and improves the control response speed. The multi-constraint collaborative optimization can significantly improve the operating frequency of the balance bridge, further reduce the circuit size, and meet the development needs of power electronic equipment for high efficiency and miniaturization.

[0012] Secondly, this application provides a low-power, high-efficiency bus balancing bridge circuit control method, applied to a preceding bus balancing bridge circuit, comprising: The parameter initialization step includes a bridge balance initialization strategy, which controls threshold preset, sampling channel initialization, and drive system pre-configuration to build a pre-working state for bridge balance operation. The data acquisition and processing steps involve real-time acquisition of the upper and lower half-bus voltage signals, followed by signal conversion and filtering / de-scratching to extract the average half-bus voltage value used for control judgment. The imbalance control steps include a voltage balance regulation strategy. The voltage imbalance is calculated based on the average voltage of the half bus, and the voltage imbalance information is obtained by analysis. The voltage balance of the half bus is then regulated. The loss constraint control steps are configured with a loss constraint strategy, which optimizes the drive duty cycle according to the circuit operation mode, thereby reducing circuit switching losses and magnetic component losses while ensuring voltage balance.

[0013] By adopting the above technical solutions, the four steps of parameter initialization, data acquisition and processing, imbalance regulation, and loss constraint control form a complete closed-loop control logic. The bridge balance initialization strategy establishes a stable pre-working state for the system, the data acquisition and processing stage ensures the accuracy and reliability of control data, the voltage balance regulation strategy realizes the hierarchical closed-loop regulation of the half-bus voltage, and the loss constraint strategy takes into account both the balance effect and the low power consumption operation of the system. This helps to solve the core problems of slow dynamic response, control delay, and even failure of existing pure software solutions under complex working conditions such as load changes and non-resistive asymmetrical loads.

[0014] Optionally, the bridge balancing initialization strategy includes: Pre-configure the exit and entry thresholds in the controller module and set the hysteresis control range; Complete the channel initialization and calibration of the half-bus voltage sampling module to put it into the real-time data acquisition ready state; The PWM generation module within the controller module completes initialization and outputs an initial drive signal to put the half-bus voltage balance bridge module into pre-operation state.

[0015] By adopting the above technical solution, the bridge balance initialization strategy pre-establishes a dual-threshold hysteresis control range through the step-by-step execution of control threshold preset, sampling channel calibration, and drive system initialization. This ensures the acquisition accuracy and readiness state of the sampling channel, while simultaneously completing the pre-configuration of the drive system. This avoids problems such as control anomalies and drive malfunctions during system startup, providing a stable and reliable pre-operation foundation for subsequent full-process closed-loop control. It also improves the consistency of system startup and long-term operational reliability. Furthermore, the threshold can be flexibly adjusted according to system voltage stability requirements and load fluctuation range, enhancing the circuit's adaptability to various scenarios.

[0016] Optional, also includes: The half-bus voltage sampling module collects the upper half-bus capacitor voltage and the lower half-bus capacitor voltage in real time, converts the collected analog voltage signal into a digital signal, and then transmits it to the average value calculation unit of the controller module. The average value calculation unit uses a sliding window averaging algorithm or a low-pass filtering algorithm to filter and average the voltage data, filter out the inherent double power frequency ripple component on the upper and lower half bus capacitors, and extract the DC voltage component as the effective voltage data, which is then synchronously input to the threshold judgment unit.

[0017] By adopting the above technical solution, through step-by-step processing using analog-to-digital conversion, sliding window averaging, or low-pass filtering algorithms, the inherent double-frequency ripple component on the upper and lower half-bus capacitors can be effectively filtered out, and the DC voltage component can be accurately extracted as effective control data. This avoids control judgment deviations and erroneous adjustments caused by ripple interference, significantly improving the accuracy and anti-interference capability of voltage sampling data. It provides reliable data support for subsequent imbalance control, ensuring the accuracy of half-bus voltage balance control from the source and avoiding voltage regulation failures caused by sampling data deviations.

[0018] Optionally, the bridge balance initialization strategy includes a high-voltage imbalance adjustment sub-strategy: The controller module calculates and determines the voltage imbalance of the upper and lower busbars based on the processed effective voltage data. When the voltage imbalance exceeds the preset threshold for entering operation, it outputs a high-voltage imbalance adjustment command. Based on the high voltage imbalance adjustment command, the energy transfer direction of the upper and lower half bus is analyzed, and the active tube and freewheeling tube of the switching tube unit are determined according to the energy transfer direction. The duty cycle of the PWM drive signal of the active tube is increased with preset drive parameters. If the voltage imbalance is less than or equal to the preset threshold for entering operation, the output of the current PWM drive signal remains unchanged.

[0019] By adopting the above technical solution, the high-voltage imbalance regulation sub-strategy, through closed-loop logic of real-time voltage imbalance calculation, threshold comparison, energy transfer direction judgment, active tube dynamic matching and duty cycle adjustment, can quickly respond to and enhance energy transfer in the corresponding direction when the half-bus voltage is in a high imbalance state, and quickly correct the voltage imbalance state. This effectively solves the problem of voltage imbalance aggravation under load sudden change and extreme unbalanced load conditions, and avoids risks such as system fluctuations, decreased power conversion stability, and even hardware damage caused by voltage imbalance exceeding the threshold.

[0020] Optionally, a low-pressure imbalance regulation sub-strategy may also be included: During the adjustment of the PWM signal drive duty cycle, when the voltage balance of the upper and lower half-buses is restored to the preset balance state, the controller module stops the drive signal output of the PWM generation module and turns off the switching transistor of the half-bus voltage balance bridge. When the voltage imbalance is equal to or greater than the preset exit threshold, a low-voltage imbalance adjustment command is output to maintain the current output state of the PWM drive signal and continuously perform closed-loop fine-tuning until the voltage is restored to the balance range. At the same time, the circuit is prevented from frequently starting and stopping at the voltage balance critical point through dual-threshold hysteresis logic.

[0021] By adopting the above technical solution, the low-voltage imbalance regulation sub-strategy combined with dual-threshold hysteresis control logic achieves fine closed-loop fine-tuning when the voltage approaches the equilibrium range. After the voltage recovers to equilibrium, the switching transistor is turned off in time to terminate the regulation. This can effectively avoid the problem of frequent start-stop at the voltage equilibrium critical point, further reduce the system standby power loss, and ensure that the half-bus voltage is stable within the preset equilibrium range. It takes into account both the economy of system operation and steady-state control accuracy, avoids the loss of switching transistor life and additional energy consumption caused by frequent start-stop, and improves the reliability of long-term system operation.

[0022] Optionally, the loss constraint strategy includes: Before each adjustment of the active transistor drive duty cycle, the controller module first retrieves the pre-stored circuit inherent parameters and real-time half-bus voltage data, calculates the upper limit constraint of the duty cycle corresponding to the DCM discontinuous conduction mode, and defines the maximum allowable boundary of the drive duty cycle. Based on the defined duty cycle boundary, combined with the inherent resonance parameters of the switching transistor parasitic capacitance and the filter inductor unit, the effective duty cycle range corresponding to the ZVS zero-voltage switching mode is calculated, and the turn-on timing range of the active transistor is determined. Based on the real-time half-bus capacitor voltage difference, the pre-stored bus capacitor value and the expected voltage balance control time, the duty cycle lower limit constraint corresponding to the low frequency loss is calculated. At the same time, based on the current voltage balance requirement, the current rising edge of the resonant oscillation corresponding to the number of resonant cycles is selected to trigger the turn-on of the active tube, and the optimal value range of the drive duty cycle is locked. Within the defined constraint range, the controller module generates the final PWM drive signal and sends it to the corresponding switching transistor. While adjusting the half-bus voltage balance, it turns on the switching transistor on the rising edge of the inductor current and achieves zero-voltage turn-on by using the active body diode.

[0023] By adopting the above technical solution, the loss constraint strategy, through multi-dimensional collaborative constraints of the upper limit of DCM duty cycle, the effective range of ZVS duty cycle, and the lower limit of low-frequency loss duty cycle, sequentially defines the safe boundary, low-loss range, and optimal value range of the driving duty cycle, accurately locks the turn-on timing of the active transistor, achieves zero-voltage turn-on of the switching transistor, significantly reduces the switching loss of the switching transistor, the magnetic component loss of the filter inductor, and the operating frequency of the balance bridge. While ensuring the half-bus voltage balance regulation effect, it significantly improves the energy conversion efficiency and operating frequency of the system, creating favorable conditions for further reducing circuit size and increasing system power density, and solving the technical defects of existing fourth-arm solutions such as high loss, low efficiency, and insufficient power density.

[0024] In summary, this application includes at least one of the following beneficial technical effects: 1. The complete half-bus voltage balance closed-loop control, which integrates sampling, calculation, judgment, and control, utilizes a simplified balanced bridge topology with dual MOSFETs and a single inductor. This eliminates the need for MOSFET arrays and filter inductors of the same specifications as the main power bridge arm, achieving half-bus voltage balance regulation with minimal hardware increments. This addresses the shortcomings of existing solutions that add a fourth bridge arm, such as large size, high hardware cost, and significant switching and magnetic losses. Simultaneously, it achieves complete decoupling between half-bus voltage balance control and main power control, eliminating the need to add a midpoint potential adjustment strategy to the main power control logic. This helps solve the problems of introducing DC current components and exceeding technical specifications in pure software solutions, significantly simplifying the main power loop control algorithm design and improving system power density, operational stability, and engineering application adaptability. 2. On the one hand, it can directly adapt to various power topologies with bus midpoints, such as T-type three-level, two-level midpoint clamping, and multi-level cascade, without modifying the hardware structure of the main power unit. This solves the topology compatibility limitation of existing pure software algorithm solutions, which can only adapt to NPC-I type three-level and cannot adapt to T-type three-level, thus greatly expanding the application scenarios of the solution. On the other hand, through the duty cycle constraint of the DCM discontinuous conduction mode, it ensures that the current of the filter inductor unit drops to zero completely in each switching cycle, effectively limiting the current peak of the balance bridge circuit, reducing the copper loss, iron loss and other magnetic component losses of the filter inductor, and reducing the size design requirements of the filter inductor, further improving the energy conversion efficiency and power density of the system. 3. By controlling the threshold preset, sampling channel calibration, and drive system initialization in stages, a dual-threshold hysteresis control range is pre-established to ensure the acquisition accuracy and readiness of the sampling channel. At the same time, the drive system is pre-configured to avoid control abnormalities and drive malfunctions during system startup, providing a stable and reliable pre-operation foundation for subsequent full-process closed-loop control. 4. Only a half-bus midpoint voltage regulation circuit consisting of a small number of MOSFETs and inductors needs to be added to the existing main power topology. There is no need to configure power devices of the same specifications as the main power bridge arm. The half-bus voltage balance control target can be achieved with minimal hardware cost increase, which has significant economic benefits for engineering applications. 5. By optimizing the circuit topology and control strategy, the switching losses of switching devices and the iron and copper losses of magnetic components are effectively reduced. At the same time, the simplified regulation circuit structure greatly reduces the space occupied by the system, creating favorable conditions for improving the power density of the entire power electronic system, which meets the current technical development needs of high efficiency and miniaturization. Attached Figure Description

[0025] Figure 1 It is a T-type three-level main power circuit topology of a split-phase power grid.

[0026] Figure 2 This is a schematic diagram of the current waveform flowing through the inductor of the balanced bridge.

[0027] Figure 3 This is a schematic diagram of the connection method of the low-power, high-efficiency bus balance bridge circuit of the present invention.

[0028] Figure 4 This is a schematic diagram of the existing synchronous rectification BUCK circuit.

[0029] Figure 5 The simulation waveform of dynamic load tripping in this invention is a T-type three-level grid with split phase power grid. The load jumps from two phases fully resistive to one phase fully resistive at 1 second, while the other phase is unloaded.

[0030] Figure 6 The simulation waveform of dynamic load tripping in this invention is a T-type three-level grid of split-phase power grid. The load jumps from two phases resistively full load to one phase resistively full load and the other phase inductively full load at 1 second.

[0031] Figure 7 The simulation waveform of dynamic load skipping in this invention is a T-type three-level grid with split phase power grid. The load changes from two phases resistive full load to one phase resistive full load and the other phase compatibility full load at 1s.

[0032] Figure 8 It is a simulated current waveform flowing through the inductor described in this invention, which is a combination of the T-type three-level grid of the split-phase power grid and the dynamic load tripping of this invention. Detailed Implementation

[0033] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figures 1-8 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0034] The embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.

[0035] This application discloses a low-power, high-efficiency bus balancing bridge circuit. By constructing a complete half-bus voltage balancing closed-loop control system involving sampling, calculation, judgment, and control, it utilizes a simplified balancing bridge topology with dual MOSFETs and a single inductor. This eliminates the need for MOSFET arrays and filter inductors of the same specifications as the main power bridge arm, achieving half-bus voltage balancing regulation with minimal hardware increments. This addresses the core shortcomings of existing solutions that add a fourth bridge arm, such as large size, high hardware cost, and significant switching and magnetic losses. Simultaneously, it achieves complete decoupling between half-bus voltage balancing control and main power control, eliminating the need to add a midpoint potential adjustment strategy to the main power control logic. This helps solve the problems of introducing DC current components and exceeding technical specifications in pure software solutions, significantly simplifying the design of the main power loop control algorithm and improving system power density, operational stability, and engineering application adaptability.

[0036] This application discloses a low-power, high-efficiency bus balancing bridge circuit, comprising: a main power module, a half-bus voltage sampling module, a controller module, and a half-bus voltage balancing bridge module. The main power module is a power conversion unit with a bus midpoint, used to convert DC bus power into two-phase AC power for external output. Its bus is divided into an upper half bus and a lower half bus, with corresponding upper half bus capacitors and lower half bus capacitors configured respectively.

[0037] The half-bus voltage sampling module has its acquisition end connected to the upper and lower half-bus capacitors of the main power module, and its output end connected to the signal input end of the controller module.

[0038] The controller module's output is connected to the control terminal of the half-bus voltage balance bridge module.

[0039] The half-bus voltage balancing bridge module receives PWM drive signals from the controller module and adjusts the half-bus voltage balance of the main power module. Specifically, the half-bus voltage balancing bridge module includes a first switching transistor unit, a second switching transistor unit, and a filter inductor unit. The input terminal of the first switching transistor unit is connected to the high-voltage bus terminal, and the output terminal is connected to the first terminal of the filter inductor unit. The input terminal of the second switching transistor unit is connected to the first terminal of the filter inductor unit, and the output terminal is connected to the low-voltage bus terminal. The second terminal of the filter inductor unit is connected to the midpoint of the main power module bus.

[0040] The main power module is a T-type three-level circuit with two phases sharing a neutral line N, or a two-level neutral point clamping topology or a multi-level cascaded topology with a bus midpoint; the half-bus voltage balancing bridge module operates in DCM discontinuous conduction mode, and the switching transistor drive duty cycle D satisfies the following constraints: ; Where D is the drive duty cycle of the switching transistor in the half-bus voltage balancing bridge module, with a value ranging from 0 to 1, and k is the voltage difference ratio between the upper and lower half-bus capacitors. , This is the voltage of the upper bus capacitor. The voltage of the lower half bus capacitor ensures that the current of the filter inductor unit drops to zero in each switching cycle.

[0041] It needs to be further explained that, such as Figure 3 As shown, the switching transistors of the half-bus voltage balancing bridge module operate in ZVS (zero-voltage switching) mode, and the drive duty cycle satisfies the following constraints: ; At the same time, the drive duty cycle satisfies the low-frequency loss constraint: ; in, For the working cycle of the balance bridge, , , Here, D represents the inherent parameters of the resonant circuit formed by the parasitic capacitance of the switching transistor and the filter inductor unit. D is the drive duty cycle of the switching transistor in the half-bus voltage balancing bridge module. This is the capacitance value of the busbar. Let m be the desired voltage balance control time, and m be the number of resonant cycles. This represents the voltage difference ratio between the upper and lower half of the bus capacitor. is the equivalent resonant inductance of the filter inductor unit, and is the inherent inductance parameter of the resonant circuit formed by the parasitic capacitance of the switching transistor and the filter inductor unit.

[0042] The half-bus voltage balancing bridge module selects the active switching transistor based on the magnitude of the upper and lower half-bus voltages, while the other switching transistor operates as a freewheeling transistor.

[0043] like Figure 1 The diagram shows the existing T-type three-level main power topology of a split-phase power grid. As described in the background section, the existing T-type three-level circuit of the split-phase power grid uses two T-type three-level circuits to form a split-phase power grid. This control method has a problem with the bus midpoint potential balance. When the system is equipped with an unbalanced load or the system parameters are asymmetrical, it will cause the upper and lower half of the bus to have a bias voltage problem, which may lead to the system failing to work in severe cases.

[0044] like Figure 3 and Figure 4As shown, the present invention discloses a half-bus voltage balancing bridge circuit, including its controller. This controller is used to calculate the average voltage, determine the threshold, and generate drive signals. It can be any controller that meets the relevant requirements, such as an STM series microcontroller, and is not limited to a single type or model of controller and control chip. The input terminal of the controller is connected to the upper and lower half-bus voltage sampling units, and the output terminal of the controller is connected to the main power unit. The comparator internally includes an average value calculation module and a threshold comparison module. The upper and lower half-bus voltage sampling units collect the voltage information of the upper and lower half-buses from the main power unit. The average value calculation module filters out the double power frequency ripple to obtain the DC component of the upper and lower half-bus voltages. The threshold determination unit has different threshold ranges. By setting an appropriate threshold, the balance control effect of the upper and lower half-bus voltages and the operating frequency of the balancing bridge circuit can be changed. This threshold can be determined according to the actual situation.

[0045] The half-bus voltage balancing bridge circuit consists of MOSFETs Q1 and Q2 and an inductor L. The gates of MOSFETs Q1 and Q2 are connected to the controller of the half-bus voltage balancing bridge circuit. The drain of MOSFET Q1 is connected to Vbus+, and its source is connected to one end of inductor L. The drain of MOSFET Q2 is connected to one end of inductor L, and its source is connected to Vbus-. The other end of inductor L is connected to the midpoint of the bus. The inductor is a filter inductor. The sampling points of the half-bus voltage balancing bridge circuit are located on the capacitors of the upper and lower half-buses.

[0046] The signal conditioning circuit conditions the relevant voltage signal from the half-bus voltage sampling to obtain an analog signal that the sampling circuit can receive. The sampling and conversion of the AD converter are controlled by the DSP / MCU, which converts the conditioned analog signal into a digital quantity. The processing of the digital signal and the generation of the PWM modulation signal for the single-phase unbalanced bridge arm are both implemented by the DSP. The final generated PWM signal is sent to the drive circuit to control the switching on and off of the MOSFETs, thereby achieving balanced control of the half-bus voltage.

[0047] The circuit topology and controller performance of this invention were verified using the circuit simulation software PLECS. This invention enables balanced control of the half-bus voltage even when the main power system's output load is completely unbalanced or carries purely inductive or purely capacitive loads. Furthermore, it decouples the control from the main power circuit control, allowing the main power circuit to achieve accurate AC inverter voltage output under various load conditions. Simulation parameters are shown in Table 1. Simulation verification demonstrates that this invention has the capability to handle completely unbalanced loads, as well as purely inductive and purely capacitive loads in the main power system.

[0048] Table 1 Simulation Parameters

[0049] Figure 5 , Figure 6 , Figure 7 , Figure 8 The simulation waveforms of the half-bus voltage balancing bridge circuit and its controller proposed in this invention under different load conditions in a split-phase T-type three-level circuit. Figure 5 , Figure 6 , Figure 7 The simulation results show the voltage of the upper and lower half bus under different load conditions of the split-phase T-type three-level circuit. According to the simulation results, the present invention can maintain the voltage balance of the half bus in both the case of a purely resistive load of <1s and the case after a load trip of >1s. Figure 8 This represents the current flowing through the inductor of the present invention.

[0050] The half-bus voltage balancing bridge circuit of this invention can achieve decoupling control between the main power circuit control and the half-bus voltage control, and can realize a main power topology with a half-bus midpoint, such as a split-phase T-type three-level circuit, to handle completely unbalanced loads and purely capacitive or purely inductive loads. Furthermore, the additional circuitry required is low-cost, has low losses, and occupies a small size, which is beneficial for improving the system's power density.

[0051] To demonstrate the advantages of the half-bus voltage midpoint control circuit of this invention, simulation tests of AC load tripping at the output of each phase were designed, and the results were as follows: Figure 5 , Figure 6 , Figure 7 , Figure 8 The simulation results. For example... Figure 5 As shown, the DC bus voltage is set to 480V. Within a time of <1s, the two-phase output AC load is a resistive full-load load. At 1s, the load of phase A jumps from full load to no load. According to the simulation waveform, the present invention can achieve the steady-state and dynamic requirements of the main power system with a completely unbalanced load.

[0052] like Figure 6 As shown, the DC bus voltage is set to 480V. Within a time of <1s, the two-phase output AC load is a resistive full load. At 1s, the load of phase A jumps from resistive full load to pure inductive full load. According to the simulation waveform, the present invention can achieve the steady-state and dynamic requirements of the main power system with a pure inductive load.

[0053] Figure 7 As shown, the DC bus voltage is set to 480V. Within a time of <1s, the two-phase output AC load is a resistive full load. At 1s, the load of phase A jumps from resistive full load to pure capacitive full load. According to the simulation waveform, the present invention can achieve the steady-state and dynamic requirements of the main power system with a pure capacitive load.

[0054] like Figure 8As shown, the present invention can limit the current flowing through the inductor to a certain range by controlling the balancing capability of the half-bus voltage balancing bridge circuit, thereby reducing the size of the magnetic components and reducing the loss of the balancing circuit, which is of great help to improve the power density of the system.

[0055] Secondly, the present invention provides a low-power, high-efficiency bus balancing bridge circuit control method, applied to the bus balancing bridge circuit described above, including: The S1 parameter initialization step is configured with a bridge balance initialization strategy, which controls the threshold preset, sampling channel initialization and drive system pre-configuration to build a pre-working state for bridge balance operation. The S2 data acquisition and processing steps involve real-time acquisition of upper and lower bus voltage signals, signal conversion and filtering / de-scratching, and extraction of the average half-bus voltage value for control judgment. The S3 imbalance control step is equipped with a voltage balance regulation strategy. It calculates the voltage imbalance degree based on the average voltage of the half bus, analyzes the voltage imbalance information, and performs voltage balance regulation on the half bus. The S4 loss constraint control step is configured with a loss constraint strategy. It optimizes the drive duty cycle according to the circuit operation mode, thereby reducing circuit switching losses and magnetic component losses while ensuring voltage balance.

[0056] Specifically, in step S1, two voltage thresholds are pre-configured in the controller: the exit threshold Verror1 and the entry threshold Verror2. When Verror1 < Verror2, a hysteresis control interval is formed. The half-bus voltage sampling unit completes initialization and enters the data acquisition ready state to collect the upper half-bus capacitor voltage Vc1 and the lower half-bus capacitor voltage Vc2. At the same time, the PWM generation module in the controller outputs an initial drive signal to drive MOSFETs Q1 and Q2 to turn on according to a preset initial duty cycle, so that the half-bus voltage balance bridge circuit enters the pre-operation state.

[0057] In step S2, the half-bus voltage sampling unit collects the voltage data parameters Vc1 and Vc2 of the upper and lower half-buses in real time. After converting the collected analog voltage signals into digital signals, the unit transmits them to the average value calculation module. The average value calculation module uses low-pass filtering, window averaging, or other equivalent data processing schemes to filter and average the voltage data. After filtering out the twice-power frequency ripple component, the average value Uc_avg of the upper and lower half-bus voltages is obtained. The average value Uc_avg is then synchronously input into the threshold judgment module to provide reliable data for subsequent control logic.

[0058] In step S3, the controller calculates the voltage imbalance ΔU = |Vc1 - Vc2| of the upper and lower bus through the threshold judgment module, and compares this imbalance ΔU with the entry threshold Verror2. If ΔU > Verror2, it is identified that the half-bus voltage is in a high imbalance state. The controller further judges the voltage levels of the upper and lower bus: if Vc1 > Vc2, the upper bus voltage is higher than the lower bus voltage, so the duty cycle of the drive signal of MOSFET Q1 is increased to enhance the transfer of energy to the lower bus; if Vc2 > Vc1, the lower bus voltage is higher than the upper bus voltage, so the duty cycle of the drive signal of MOSFET Q2 is increased to enhance the transfer of energy to the upper bus; if ΔU ≤ Verror2, the current drive signal output state of the PWM generation module remains unchanged.

[0059] Among them, there are high-voltage imbalance and low-voltage imbalance when there is imbalance. High-voltage imbalance means that the voltage imbalance of the half bus is greater than the entry threshold Verror2, which is a high degree of imbalance and requires the initiation of energy transfer regulation. Low-voltage imbalance means that the voltage imbalance of the half bus is less than the exit threshold Verror1, which is a low degree of imbalance and has reached a balanced state that can be exited for regulation.

[0060] When under high voltage imbalance, the controller calculates the voltage imbalance ΔU=|Vc1-Vc2| of the upper and lower bus through the threshold judgment module, and compares this imbalance ΔU with the entry threshold Verror2. If ΔU>Verror2, it is identified that the half bus voltage is in a high imbalance state. The controller further judges the voltage of the upper and lower bus: if Vc1>Vc2, it means that the voltage of the upper bus is higher than that of the lower bus, so the duty cycle of the drive signal of MOSFET Q1 is increased to enhance the transfer of energy to the lower bus; if Vc2>Vc1, it means that the voltage of the lower bus is higher than that of the upper bus, so the duty cycle of the drive signal of MOSFET Q2 is increased to enhance the transfer of energy to the upper bus; if ΔU≤Verror2, the current drive signal state output by the PWM generation module remains unchanged.

[0061] When there is a low voltage imbalance, the controller continuously compares the voltage imbalance degree ΔU with the exit threshold Verror1 through the threshold judgment module. If ΔU < Verror1, it is identified that the half bus voltage has been restored to the balanced state, and the controller controls the PWM generation module to stop outputting drive signals and turn off the operation of MOSFETs Q1 and Q2. If ΔU ≥ Verror1, it is identified that the half bus voltage still needs to be adjusted, and the current working state of the PWM generation module is maintained to ensure that the half bus voltage is stable within the balance range.

[0062] Through the above control process, the present invention can independently achieve half-bus voltage balance control while ensuring the normal output of the main power unit, effectively decoupling the half-bus voltage balance control from the main power control.

[0063] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0064] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A low-power, high-efficiency bus balanced bridge circuit, characterized in that, include: The main power module is a power conversion unit with a bus midpoint, used to convert DC bus power into two-phase AC power and output it to the outside. Its bus is divided into an upper bus and a lower bus, which are respectively configured with upper bus capacitors and lower bus capacitors. A half-bus voltage sampling module, wherein the acquisition end of the half-bus voltage sampling module is connected to the upper and lower half-bus capacitors of the main power module, and the output end is connected to the signal input end of the controller module; The controller module, the output of which is connected to the control terminal of the half-bus voltage balance bridge module; A half-bus voltage balancing bridge module is used to receive the PWM drive signal from the controller module and adjust the half-bus voltage balance of the main power module. The half-bus voltage balancing bridge module includes a first switching transistor unit, a second switching transistor unit, and a filter inductor unit. The input terminal of the first switching transistor unit is connected to the high-voltage bus terminal, and the output terminal is connected to the first terminal of the filter inductor unit. The input terminal of the second switching transistor unit is connected to the first terminal of the filter inductor unit, and the output terminal is connected to the low-voltage bus terminal. The second terminal of the filter inductor unit is connected to the midpoint of the bus of the main power module.

2. The low-power, high-efficiency bus balance bridge circuit according to claim 1, characterized in that, The main power module is a T-type three-level circuit with two phases sharing a neutral line N, or a two-level neutral point clamping topology or a multi-level cascaded topology with a bus midpoint; the half-bus voltage balancing bridge module operates in DCM discontinuous conduction mode, and the switching transistor drive duty cycle D satisfies the following constraints: ； Where k is the voltage difference ratio between the upper and lower half bus capacitors, ensuring that the current of the filter inductor unit drops to zero in each switching cycle.

3. The low-power, high-efficiency bus balance bridge circuit according to claim 2, characterized in that, The switching transistors of the half-bus voltage balancing bridge module operate in ZVS (zero-voltage switching) mode, and the drive duty cycle meets the following constraints: ； At the same time, the drive duty cycle satisfies the low-frequency loss constraint: ； in, For the working cycle of the balance bridge, , , These are the inherent parameters of the resonant circuit formed by the parasitic capacitance of the switching transistor and the filter inductor unit. This is the capacitance value of the busbar. The desired voltage balance control time is given by m, where m is the number of resonance cycles. The half-bus voltage balancing bridge module selects the active switching transistor based on the magnitude of the upper and lower half-bus voltages, while the other switching transistor operates as a freewheeling transistor.

4. A low-power, high-efficiency bus balance bridge circuit control method, employing the low-power, high-efficiency bus balance bridge circuit as described in any one of claims 1-3, characterized in that, include: The parameter initialization step includes a bridge balance initialization strategy, which controls threshold preset, sampling channel initialization, and drive system pre-configuration to build a pre-working state for bridge balance operation. The data acquisition and processing steps involve real-time acquisition of the upper and lower half-bus voltage signals, followed by signal conversion and filtering / de-scratching to extract the average half-bus voltage value used for control judgment. The imbalance control steps include a voltage balance regulation strategy. The voltage imbalance is calculated based on the average voltage of the half bus, and the voltage imbalance information is obtained by analysis. The voltage balance of the half bus is then regulated. The loss constraint control steps are configured with a loss constraint strategy, which optimizes the drive duty cycle according to the circuit operation mode, thereby reducing circuit switching losses and magnetic component losses while ensuring voltage balance.

5. The low-power, high-efficiency bus balance bridge circuit control method according to claim 4, characterized in that, The bridge balancing initialization strategy includes: Pre-configure the exit and entry thresholds in the controller module and set the hysteresis control range; Complete the channel initialization and calibration of the half-bus voltage sampling module to put it into the real-time data acquisition ready state; The PWM generation module within the controller module completes initialization and outputs an initial drive signal to put the half-bus voltage balance bridge module into pre-operation state.

6. The low-power, high-efficiency bus balance bridge circuit control method according to claim 5, characterized in that, Also includes: The half-bus voltage sampling module collects the upper half-bus capacitor voltage and the lower half-bus capacitor voltage in real time, converts the collected analog voltage signal into a digital signal, and then transmits it to the average value calculation unit of the controller module. The average value calculation unit uses a sliding window averaging algorithm or a low-pass filtering algorithm to filter and average the voltage data, filter out the inherent double power frequency ripple component on the upper and lower half bus capacitors, and extract the DC voltage component as the effective voltage data, which is then synchronously input to the threshold judgment unit.

7. The low-power, high-efficiency bus balance bridge circuit control method according to claim 4, characterized in that, The bridge balance initialization strategy includes a high-voltage imbalance adjustment sub-strategy: The controller module calculates and determines the voltage imbalance of the upper and lower busbars based on the processed effective voltage data. When the voltage imbalance exceeds the preset threshold for entering operation, it outputs a high-voltage imbalance adjustment command. Based on the high voltage imbalance adjustment command, the energy transfer direction of the upper and lower half bus is analyzed, and the active tube and freewheeling tube of the switching tube unit are determined according to the energy transfer direction. The duty cycle of the PWM drive signal of the active tube is increased with preset drive parameters. If the voltage imbalance is less than or equal to the preset threshold for entering operation, the output of the current PWM drive signal remains unchanged.

8. The low-power, high-efficiency bus balance bridge circuit control method according to claim 7, characterized in that, It also includes a low-pressure imbalance regulation sub-strategy: During the adjustment of the PWM signal drive duty cycle, when the voltage balance of the upper and lower half-buses is restored to the preset balance state, the controller module stops the drive signal output of the PWM generation module and turns off the switching transistor of the half-bus voltage balance bridge. When the voltage imbalance is equal to or greater than the preset exit threshold, a low-voltage imbalance adjustment command is output to maintain the current output state of the PWM drive signal and continuously perform closed-loop fine-tuning until the voltage is restored to the balance range. At the same time, the circuit is prevented from frequently starting and stopping at the voltage balance critical point through dual-threshold hysteresis logic.

9. The low-power, high-efficiency bus balance bridge circuit control method according to claim 4, characterized in that, The loss constraint strategy includes: Before each adjustment of the active transistor drive duty cycle, the controller module first retrieves the pre-stored circuit inherent parameters and real-time half-bus voltage data, calculates the upper limit constraint of the duty cycle corresponding to the DCM discontinuous conduction mode, and defines the maximum allowable boundary of the drive duty cycle. Based on the defined duty cycle boundary, combined with the inherent resonance parameters of the switching transistor parasitic capacitance and the filter inductor unit, the effective duty cycle range corresponding to the ZVS zero-voltage switching mode is calculated, and the turn-on timing range of the active transistor is determined. Based on the real-time half-bus capacitor voltage difference, the pre-stored bus capacitor value and the expected voltage balance control time, the duty cycle lower limit constraint corresponding to the low frequency loss is calculated. At the same time, based on the current voltage balance requirement, the current rising edge of the resonant oscillation corresponding to the number of resonant cycles is selected to trigger the turn-on of the active tube, and the optimal value range of the drive duty cycle is locked. Within the defined constraint range, the controller module generates the final PWM drive signal and sends it to the corresponding switching transistor. While adjusting the half-bus voltage balance, it turns on the switching transistor on the rising edge of the inductor current and achieves zero-voltage turn-on by using the active body diode.

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