Oscillator circuit with noise cancellation structure

Abstract

The application discloses an oscillator circuit with a noise cancellation structure, which comprises a main amplifier, a first slave amplifier branch, a second slave amplifier branch, a combining circuit and a feedback network; the input end of the main amplifier is used for receiving an oscillation loop signal, and the first and second output ends are used for outputting first and second composite signals respectively; the first and second composite signals both comprise an oscillation signal component and a noise component; the input and output ends of the first and second slave amplifier branches are connected with the main amplifier and the combining circuit respectively; the combining circuit combines the output signals of the first and second slave amplifier branches, so that the oscillation signal components in the two output signals are superposed in phase and the amplitudes are enhanced, and the noise components are superposed in opposite phase and are cancelled; the output end of the combining circuit is connected with the input end of the feedback network, and the output end of the feedback network is connected with the input end of the main amplifier, forming a closed oscillation loop; the application can significantly reduce the phase noise of the oscillation signal.

Description

Technical Field

[0001] This invention belongs to the technical field of oscillator circuits for generating frequency signals, and specifically relates to an oscillator circuit containing a noise cancellation structure. Background Technology

[0002] Information systems typically use oscillators to provide a reference frequency source or clock signal. As information systems become increasingly demanding in terms of spectral efficiency and data rates, higher requirements are placed on the spectral purity and phase noise performance of the frequency source, requiring the oscillator output signal to have lower phase noise. In oscillator circuits, to maintain continuous oscillation of the oscillation loop, an amplifying device (loop amplifier) ​​is necessary to amplify the oscillation signal. However, the amplifier generates internal noise such as thermal noise, shot noise, and low-frequency flicker noise. These noises couple into the phase noise of the oscillation signal. On one hand, they are directly superimposed on the oscillation signal, leading to phase noise degradation. On the other hand, these noises are also up-converted to near the oscillation signal frequency through the nonlinear modulation effect of active devices, which is another mechanism for deteriorating the phase noise of the oscillation signal.

[0003] In existing technologies, common methods to reduce oscillator phase noise include increasing the size of active devices to reduce flicker noise; increasing the amplitude of the oscillation signal to obtain a higher signal-to-noise ratio, but this requires increasing the transistor operating current, which will lead to increased shot noise; optimizing the impedance matching of the oscillation loop to avoid parasitic oscillations and reduce the load effect of the resonator; suppressing the amplitude noise of the oscillation signal through automatic gain control circuits or amplitude stabilization circuits; suppressing spurious frequencies and out-of-band noise through frequency selection networks; and using resonators with high quality factors. While the above methods can reduce noise floor or improve oscillation stability to some extent, they often have the following shortcomings: First, increasing device size introduces larger parasitic capacitance, reduces input impedance, and increases crystal load effect, thereby affecting start-up margin, frequency pull range, and frequency stability. Second, increasing operating current increases system power consumption and shot noise. Third, excessively large oscillation signal amplitude may cause resonator saturation, nonlinear effects will generate spurious frequencies, and accelerated resonator aging, increased heat dissipation, and dielectric nonlinearity will also lead to frequency drift. Fourth, automatic gain control and amplitude control mainly alleviate the coupling of amplitude noise to phase noise by stabilizing the oscillation amplitude, but it is difficult to eliminate noise inside the loop amplifier at its source. Fifth, adding a high-Q narrowband filter can suppress noise far from the oscillation frequency, but it is difficult to suppress noise near the oscillation frequency.

[0004] like Figure 1The diagram shows a feedforward amplifier proposed by A. Hati et al. The feedforward amplifier 200 splits the input signal 201 into a main amplification path signal 202a and a reference path signal 202b via a signal splitter coupler 202. The main amplification path signal is amplified by the main amplifier 203 and sampled by the directional coupler 204. It is then subtracted from the reference signal 207b (delayed by the delay circuit 207) in the signal subtraction circuit 208 to form an error signal 208b, primarily composed of main amplifier noise. This error signal is amplified by the error amplifier 209 to become signal 209b, which is then combined with the main amplification path signal 205a at the output via the directional coupler 206 to form the output signal 210 to cancel noise. This scheme can achieve noise suppression with strict matching of the delay circuit. However, because it uses a signal splitter coupler with insertion loss at the input, the signal power entering the main amplifier is reduced, and the signal-to-noise ratio deteriorates. It is typically used for linearization and spurious emission in power amplifier circuits and is not suitable for applications requiring extremely low noise. Summary of the Invention

[0005] To address the aforementioned problems, this invention proposes an oscillator circuit with a noise cancellation structure, which can significantly reduce the phase noise of the oscillation signal.

[0006] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution:

[0007] An oscillator circuit with a noise cancellation structure includes a noise cancellation amplifier circuit and a feedback network;

[0008] The noise cancellation amplifier circuit includes a main amplifier, a first slave amplifier branch, a second slave amplifier branch, and a merging circuit;

[0009] The main amplifier has an input terminal, a first output terminal, and a second output terminal. Its input terminal is used to receive an oscillation loop signal, its first output terminal is used to output a first composite signal, and its second output terminal is used to output a second composite signal. The first composite signal includes a first oscillation signal component and a first noise component, and the second composite signal includes a second oscillation signal component and a second noise component. Both the first noise component and the second noise component come from the internal noise of the main amplifier.

[0010] The merging circuit has a first input terminal, a second input terminal, and an output terminal;

[0011] The input terminal of the first slave amplifier branch is connected to the first output terminal of the main amplifier, and its output terminal is connected to the first input terminal of the merging circuit; the input terminal of the second slave amplifier branch is connected to the second output terminal of the main amplifier, and its output terminal is connected to the second input terminal of the merging circuit.

[0012] The merging circuit merges the output signals of the first slave amplification branch and the second slave amplification branch, so that the oscillation signal components in the two output signals are superimposed in phase and the amplitude is enhanced, while the noise components are superimposed in opposite phase and canceled out.

[0013] The output of the merging circuit is connected to the input of the feedback network, and the output of the feedback network is connected to the input of the main amplifier to form a closed oscillation loop. Optionally, the first or second output of the main amplifier is connected to its input.

[0014] Optionally, the merging circuit may be a conductor intersection point, an adder, a subtractor, a differential amplifier, a transformer, a directional coupler, or a combiner.

[0015] Optionally, the main amplifier, the first slave amplifier branch, the second slave amplifier branch, and the merging circuit are integrated on the same printed circuit board or integrated circuit substrate.

[0016] Optionally, the main amplifier includes a first transistor and a first bias circuit; the first slave amplification branch includes a second transistor, a second bias circuit, and a first control circuit; the second slave amplification branch includes a third transistor, a third bias circuit, and a second control circuit; wherein the first bias circuit, the second bias circuit, and the third bias circuit are used to provide a bias voltage; the first control circuit and the second control circuit are used to provide a bias voltage and gain adjustment.

[0017] The first transistor, the second transistor, and the third transistor each have a first terminal, a second terminal, and a third terminal. For any one of the first transistor, the second transistor, and the third transistor, when the transistor is a field-effect transistor, the first terminal is the gate, the second terminal is the source, and the third terminal is the drain. In this case, the first control circuit and the second control circuit are respectively the first source circuit and the second source circuit. When the transistor is a bipolar junction transistor, the first terminal is the base, the second terminal is the emitter, and the third terminal is the collector. In this case, the first control circuit and the second control circuit are respectively the first emitter circuit and the second emitter circuit.

[0018] The first bias circuit is connected to the first terminal of the first transistor, the second bias circuit is connected to the first terminal of the second transistor, the first control circuit is connected between the second terminal of the first transistor and the reference ground, the third bias circuit is connected to the first terminal of the third transistor, and the second control circuit is connected between the second terminal of the third transistor and the reference ground.

[0019] The first terminal of the first transistor serves as the input terminal of the main amplifier, used to connect the oscillation loop signal;

[0020] The third terminal of the first transistor serves as the first output terminal of the main amplifier and is connected to the first terminal of the second transistor and its own first terminal, respectively; the first terminal of the first transistor is also connected to the first terminal of the third transistor; the third terminal of the second transistor is connected to the first input terminal of the merging circuit, and the third terminal of the third transistor is connected to the second input terminal of the merging circuit.

[0021] Optionally, the main amplifier includes a first transistor and a first bias circuit; the first slave amplification branch includes a second transistor, a second bias circuit, and a first control circuit; the second slave amplification branch includes a third transistor, a third bias circuit, and a second control circuit; wherein the first bias circuit, the second bias circuit, and the third bias circuit are used to provide a bias voltage; the first control circuit and the second control circuit are used to provide a bias voltage and gain adjustment.

[0022] The first transistor, the second transistor, and the third transistor each have a first terminal, a second terminal, and a third terminal. For any one of the first transistor, the second transistor, and the third transistor, when the transistor is a field-effect transistor, the first terminal is the gate, the second terminal is the source, and the third terminal is the drain. In this case, the first control circuit and the second control circuit are respectively the first source circuit and the second source circuit. When the transistor is a bipolar junction transistor, the first terminal is the base, the second terminal is the emitter, and the third terminal is the collector. In this case, the first control circuit and the second control circuit are respectively the first emitter circuit and the second emitter circuit.

[0023] The first bias circuit is connected to the first terminal of the first transistor, the second bias circuit is connected to the first terminal of the second transistor, the first control circuit is connected between the second terminal of the second transistor and the reference ground, the third bias circuit is connected to the first terminal of the third transistor, and the second control circuit is connected between the second terminal of the third transistor and the reference ground.

[0024] The third terminal of the first transistor is connected to the first output terminal of the main amplifier and the first terminal of the second transistor, respectively; the second terminal of the first transistor is connected to the first terminal of the third transistor, serving as the input terminal of the main amplifier, so that the oscillation loop signal enters the first transistor and the third transistor simultaneously, and also serves as one of the noise output terminals of the first transistor, outputting the corresponding noise component to the third transistor; the third terminal of the second transistor is connected to the first input terminal of the merging circuit, and the third terminal of the third transistor is connected to the second input terminal of the merging circuit.

[0025] Optionally, the feedback network includes a frequency selection circuit, an auxiliary circuit, and a resonator;

[0026] The auxiliary circuit is used to implement a predetermined auxiliary function;

[0027] The auxiliary circuit, resonator, and frequency selection circuit are connected in series, and the series order can be adjusted arbitrarily.

[0028] Optionally, the resonator is a quartz crystal resonator, a metal microwave cavity, a dielectric resonator, a sapphire resonator, a MEMS resonator, a surface acoustic wave resonator, a bulk acoustic wave resonator, or a resonant circuit network consisting of more than one inductor and more than one capacitor.

[0029] Optionally, the oscillator circuit further includes: a first external bias circuit, a second external bias circuit, a first buffer amplifier circuit, and a first impedance matching circuit;

[0030] The output of the merging circuit is connected to the input of the frequency selection circuit via the auxiliary circuit, and the output of the frequency selection circuit is connected to the input of the main amplifier to form a closed oscillation loop.

[0031] The first end of the resonator is connected to the input end of the main amplifier, the second end of the resonator is connected to the input end of the first buffer amplifier circuit, the output end of the first buffer amplifier circuit is connected to the input end of the first impedance matching circuit, and the output end of the first impedance matching circuit serves as the output end of the oscillator circuit.

[0032] The first external bias circuit is connected between the input terminal of the main amplifier and the reference ground;

[0033] The second external bias circuit is connected between the second end of the resonator and the reference ground.

[0034] Optionally, the oscillator circuit further includes a third external bias circuit, a fourth external bias circuit, a second buffer amplifier circuit, and a second impedance matching circuit.

[0035] The output of the merging circuit is connected to the input of the frequency selection circuit via the auxiliary circuit; the output of the frequency selection circuit is connected to the input of the main amplifier to form a closed oscillation loop.

[0036] The first end of the resonator is connected to the input end of the main amplifier;

[0037] The third external bias circuit is connected between the first end of the resonator and the reference ground.

[0038] The second end of the resonator is connected to the reference ground via the fourth external bias circuit;

[0039] The input terminal of the second buffer amplifier circuit is connected to the internal node of the oscillation loop between the output terminal of the auxiliary circuit and the input terminal of the frequency selection circuit;

[0040] The output terminal of the second buffer amplifier circuit is connected to the input terminal of the second impedance matching circuit, and the output terminal of the second impedance matching circuit serves as the output terminal of the oscillator circuit.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] In this invention, the main amplifier receives the oscillation loop signal output from the frequency selection circuit and generates two output signals, each containing an oscillation signal component and a noise component. The first and second slave amplification branches amplify the two output signals respectively. The merging circuit merges the output signals from the two slave amplification branches, causing the two oscillation signal components to be superimposed in phase and thus increasing their amplitude, and causing the two noise components to be superimposed in opposite phase and thus canceling them out. This suppresses the influence of the main amplifier noise on the phase noise of the oscillation signal and improves the spectral purity of the oscillation signal.

[0043] Furthermore, the present invention proposes to feed the merged signal generated by the merging circuit back to the main amplifier via an auxiliary circuit, a resonator, and a frequency selection circuit to form a closed oscillation loop that satisfies the oscillation conditions. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0045] Figure 1 This is a schematic diagram of a feedforward amplifier circuit in the prior art;

[0046] Figure 2 This is a block diagram of an oscillator circuit containing a noise cancellation structure proposed in this invention;

[0047] Figure 3 This is a basic circuit diagram of a noise-canceling Pierce quartz crystal oscillator using BJT devices according to an embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram of a noise-canceling Pierce quartz crystal oscillator with a BJT cascade structure according to an embodiment of the present invention.

[0049] Figure 5 This is a schematic diagram of the first BJT noise cancellation amplifier circuit according to an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram of a second BJT noise cancellation amplifier circuit according to an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of a noise cancellation amplifier circuit combining BJT and JFET transistors according to an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of a MOS transistor noise cancellation amplifier circuit according to an embodiment of the present invention;

[0053] Figure 9 This is a schematic diagram of a noise cancellation amplifier circuit using an inverter according to an embodiment of the present invention;

[0054] Figure 10 This is a schematic diagram of an oscillator circuit composed of a noise cancellation amplifier circuit and an LC frequency selection network according to an embodiment of the present invention.

[0055] Figure 11 This is a schematic diagram of an oscillator circuit composed of a noise cancellation amplifier circuit and a quartz crystal frequency selection network according to an embodiment of the present invention.

[0056] Figure 12 This is a schematic diagram of an oscillator circuit consisting of a noise cancellation amplifier circuit, a resonator, and an LC frequency selection network, according to one embodiment of the present invention.

[0057] Figure 13 This is a schematic diagram of an oscillator circuit according to an embodiment of the present invention, in which an oscillation loop is formed by a noise cancellation amplifier circuit and a frequency selection circuit, and the output is obtained through a resonator branch, an amplifier and an impedance matching circuit.

[0058] Figure 14 This is a schematic diagram of an oscillator circuit containing a noise cancellation structure that samples from the internal nodes of the oscillation loop and outputs through the output amplifier circuit, according to an embodiment of the present invention.

[0059] in,

[0060] Figure 1 In the diagram: 200—Feedforward amplifier, 201—Input signal, 202—Signal splitter coupler, 202a—Main amplification path signal, 202b—Reference path signal, 203—Main amplifier, 203a—Main amplifier output signal, 204—First directional coupler, 204a—First directional coupler direct output signal, 204s—First directional coupler sampling signal, 205—Main path delay circuit, 205a—Signal delayed by the main path delay circuit, 206—Second directional coupler, 207—Reference path delay circuit, 207b—Reference signal delayed by the reference path delay circuit, 208—Signal subtraction circuit, 208b—Error signal, 209—Error amplifier, 209b—Error signal amplified by the error amplifier, 210—Output signal;

[0061] Figure 2In the diagram: 1—First slave amplifier branch, 1a—Input terminal of the first slave amplifier branch, 1b—Output terminal of the first slave amplifier branch, 2—Second slave amplifier branch, 2a—Input terminal of the second slave amplifier branch, 2b—Output terminal of the second slave amplifier branch, 5—Combining circuit, 5a—First input terminal of the combining circuit, 5b—Second input terminal of the combining circuit, 5c—Output terminal of the combining circuit, 6—Auxiliary circuit, 6a—First terminal of the auxiliary circuit, 6b—Second terminal of the auxiliary circuit, 7—Resonator, 7a—First terminal of the resonator, 7b—Second terminal of the resonator, 8—Frequency selection circuit, 8a—First terminal of the frequency selection circuit, 8b—Second terminal of the frequency selection circuit, 9—Main amplifier, 9g—Input terminal of the main amplifier, 9a—First output terminal of the main amplifier, 9b—Second output terminal of the main amplifier, 10—Oscillating loop signal, 100—Noise cancellation amplifier circuit, 101—Feedback network;

[0062] Figure 3 In the diagram: 311—First bias circuit, 321—Second bias circuit, 331—Third bias circuit, 322—First control circuit, 332—Second control circuit, 310—First transistor, 320—Second transistor, 330—Third transistor, 301—Input node, 302—Internal node, 303—Common output node, 304—First resistor, 305—Second resistor, 306—First capacitor, 307—Quartz crystal, 308—Second capacitor, 315—Third resistor;

[0063] Figure 4 In the middle: 411—Fourth resistor, 413—Fifth resistor, 421—Sixth resistor, 422—Seventh resistor, 431—Eighth resistor, 432—Ninth resistor, 434—Tenth resistor, 412—Third capacitor, 423—Fourth capacitor, 433—Fifth capacitor, 440—Sixth capacitor, 441—Seventh capacitor.

[0064] Figure 9 In the diagram: 910—first inverter, 930—second inverter, 920—amplifier, 911—feedback resistor;

[0065] Figure 10 In the middle: 1002—First inductor;

[0066] Figure 12 In the diagram: 1202—first node, 1203—second node, 1204—eighth capacitor, 1205—ninth capacitor, 1206—second inductor, 1210—bias circuit;

[0067] Figure 13 In the middle: 1301—First external bias circuit, 1302—Second external bias circuit, 1303—First buffer amplifier circuit, 1304—First impedance matching circuit;

[0068] Figure 14 In the circuit diagram: 1401—Third external bias circuit, 1402—Fourth external bias circuit, 1403—Second buffer amplifier circuit, 1404—Second impedance matching circuit. Detailed Implementation

[0069] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may include different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0071] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0072] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0073] The application principle of the present invention will be described in detail below with reference to the accompanying drawings.

[0074] Example 1

[0075] like Figure 2 As shown, this embodiment of the invention provides an oscillator circuit with a noise cancellation structure, including a main amplifier 9, a first slave amplifier branch 1 (i.e., Figure 1 The first amplification branch 1 and the second amplification branch 2 (i.e.) Figure 1 The circuit consists of a primary amplifier 9, a first slave amplifier branch 1, a second slave amplifier branch 2, and a merging circuit 5, forming a noise cancellation amplifier circuit 100. The auxiliary circuit 6, resonator 7, and frequency selection circuit 8 form a feedback network 101. The auxiliary circuit 6 is an optional module, and the circuit design can be customized according to actual needs. The auxiliary circuit 6, resonator 7, and frequency selection circuit 8 can be connected in series in different sequences that can form a closed oscillation loop.

[0076] The main amplifier 9 has two output terminals, referred to as the first output terminal 9a and the second output terminal 9b. The output signal of the first output terminal 9a includes a first oscillation signal component 109a and a first noise component 9an, and the output signal of the second output terminal 9b includes a second oscillation signal component 109b and a second noise component 9bn. The polarity of the output signal of the main amplifier 9 can include two cases: Case A, the first oscillation signal component 109a and the second oscillation signal component 109b are in phase, and the first noise component 9an and the second noise component 9bn are out of phase; Case B, the first oscillation signal component 109a and the second oscillation signal component 109b are out of phase, and the first noise component 9an and the second noise component 9bn are in phase.

[0077] The input terminal 1a of the first slave amplification branch 1 is connected to the first output terminal 9a of the main amplifier 9, and its output terminal 1b is connected to the first input terminal 5a of the merging circuit 5. The first slave amplification branch 1 amplifies the output signal of the first output terminal 9a of the main amplifier, and its output signal includes an amplified first oscillation signal component 109a1 and an amplified first noise component 9an1. The input terminal 2a of the second slave amplification branch 2 is connected to the second output terminal 9b of the main amplifier 9, and its output terminal 2b is connected to the second input terminal 5b of the merging circuit 5. The second slave amplification branch 2 amplifies the output signal of the second output terminal 9b of the main amplifier 9, and its output signal includes an amplified second oscillation signal component 109b2 and an amplified second noise component 9bn2. The polarity of the two slave amplification branches is divided into two cases: Case C, the gain polarity of the first slave amplification branch 1 and the second slave amplification branch 2 is the same; Case D, the gain polarity of the first slave amplification branch 1 and the second slave amplification branch 2 is opposite. The noise cancellation effect is better when the amplitudes of the amplified first noise component 9an1 and the amplified second noise component 9bn2 are equal.

[0078] The merging circuit 5 performs linear algebraic operations on the output signals of the first amplification branch 1 and the second amplification branch 2. Specifically, corresponding to cases A&C and B&D, the merging circuit 5 adds the output signals of the first amplification branch 1 and the second amplification branch 2. Corresponding to cases A&D and B&C, the merging circuit 5 subtracts the output signals of the first amplification branch 1 and the second amplification branch 2, thereby increasing the amplitude of the oscillation signal component and causing the amplified first noise component 9an1 and the amplified second noise component 9bn2 to cancel each other out after merging, thus reducing the amplitude of the noise component.

[0079] In summary, by selecting the polarity relationship between the two output terminals of the main amplifier 9, the gain polarity of the two secondary amplification branches, and the operation method of the merging circuit 5 (algebraic addition or algebraic subtraction), the amplified first oscillation signal component 109a1 and the second oscillation signal component 109b2 are made to have the same synthesis direction at the merging circuit 5, while the amplified first noise component 9an1 and the second noise component 9bn2 are made to have opposite synthesis directions, thus achieving noise cancellation. Theoretically, complete cancellation can be achieved when the amplitudes of the amplified first noise component 9an1 and the amplified second noise component 9bn2 are equal and their polarities are opposite; partial cancellation can be achieved when there is a deviation in their amplitudes or phases.

[0080] The output signal of the merging circuit 5 passes through the auxiliary circuit 6, resonator 7, and frequency selection circuit 8 sequentially or in any other order that enables oscillation, before returning to the input terminal 9g of the main amplifier 9, thus forming a closed oscillation loop. The auxiliary circuit 6 includes, but is not limited to, an amplitude control circuit, a current limiting circuit, and an amplification circuit, and can be specifically configured according to actual needs.

[0081] Example 2

[0082] like Figure 3 As shown, this embodiment of the invention provides an oscillator circuit with a noise cancellation structure. More specifically, this embodiment provides a noise-cancelled Pierce quartz crystal oscillator circuit using BJT devices. The oscillator circuit includes a first transistor 310, a second transistor 320, a third transistor 330, a third resistor 315, a first resistor 304, a second resistor 305, a first bias circuit 311, a second bias circuit 321, a first control circuit 322, a third bias circuit 331, a second control circuit 332, a quartz crystal 307, a first capacitor 306, and a second capacitor 308. Since the first transistor 310, the second transistor 320, and the third transistor 330 in this embodiment all use bipolar junction transistors, the first control circuit 322 is a first emitter circuit used to provide bias voltage and gain adjustment, and the second control circuit 332 is a second emitter circuit used to provide bias voltage and gain adjustment.

[0083] The first transistor 310 and the third resistor 315 constitute the main amplifier 9. The base of the first transistor 310 is connected to the input node 301, and the collector of the first transistor 310 is connected to the internal node 302. The third resistor 315 is connected between the input node 301 and the internal node 302, serving as a feedback resistor to establish DC feedback. The input node 301 corresponds to the input terminal 9g of the main amplifier 9, the internal node 302 corresponds to the first output terminal 9a of the main amplifier 9, and the emitter of the first transistor 310 corresponds to the second output terminal 9b of the main amplifier 9. The noise generated by the first transistor 310 forms corresponding noise components at the internal node 302 and the emitter node of the first transistor 310, respectively, referred to as the first noise component and the second noise component. The first bias circuit 311 is connected to the base of the first transistor 310 and is used to provide the base bias voltage of the first transistor 310; the first regulation circuit 322 is connected between the emitter of the first transistor 310 and the reference ground and is used to provide the emitter bias voltage of the first transistor 310, and affects the gain of the first transistor 310 through current series negative feedback.

[0084] The second transistor 320 forms the first amplification branch 1. The second bias circuit 321 is connected to the base of the second transistor 320 and is used to provide the base bias voltage of the second transistor 320. The emitter of the second transistor 320 is connected to the internal node 302, and the collector of the second transistor 320 is connected to the common output node 303.

[0085] The third transistor 330 constitutes the second amplification branch 2. The third bias circuit 331 is connected to the base of the third transistor 330 to provide a base bias voltage for the third transistor 330. The second control circuit 332 is connected between the emitter of the third transistor 330 and the reference ground to provide an emitter bias voltage for the third transistor 330 and affects the gain of the third transistor 330 through current series negative feedback. The base of the third transistor 330 is connected to the base of the first transistor 310, and the collector of the third transistor 330 is connected to the common output node 303. The first control circuit 322 and the second control circuit 332 may include, but are not limited to, a parallel network of resistors, inductors and capacitors, a parallel network of resistors and capacitors, or any series combination thereof.

[0086] The first resistor 304 serves as a load resistor, connected between the power supply VCC and the common output node 303. The collector currents of the second transistor 320 and the third transistor 330 are superimposed at the common output node 303, and converted into a voltage signal by the equivalent resistance of the common output node 303 relative to AC ground. Therefore, the common output node 303 and its equivalent resistance relative to AC ground constitute the merging circuit 5.

[0087] The second resistor 305 serves as auxiliary circuit 6, connected between the common output node 303 and one end of the quartz crystal 307, used to adjust the excitation power of the quartz crystal 307, which corresponds to the resonator 7. The other end of the quartz crystal 307 is connected to the input node 301, and the first capacitor 306 and the second capacitor 308 are respectively connected between the two ends of the quartz crystal 307 and the reference ground. The quartz crystal 307, the first capacitor 306, and the second capacitor 308 constitute a quartz crystal frequency selection network.

[0088] During operation, the oscillation loop signal 10 is transmitted to the common output node 303 via the paths of the first transistor 310, the second transistor 320, and the third transistor 330, respectively. By setting the operating point, gain, and load of the second transistor 320 and the third transistor 330, the first oscillation signal component and the second oscillation signal component in the two paths are superimposed in phase at the common output node 303, thus increasing their amplitude; at the same time, the first noise component and the second noise component originating from the transistor 310 are superimposed in opposite phase at the common output node 303, thus canceling each other out.

[0089] Figure 4yes Figure 3 The circuit shown is a specific implementation. The oscillator circuit includes a first transistor 310, a second transistor 320, and a third transistor 330; a first resistor 304, a second resistor 305, a third resistor 315, a fourth resistor 411, a fifth resistor 413, a sixth resistor 421, a seventh resistor 422, an eighth resistor 431, a ninth resistor 432, and a tenth resistor 434; a first capacitor 306, a second capacitor 308, a third capacitor 412, a fourth capacitor 423, a fifth capacitor 433, a sixth capacitor 440, and a seventh capacitor 441; and a quartz crystal 307.

[0090] The third resistor 315 is connected between the input node 301 and the internal node 302 as a feedback resistor.

[0091] The first transistor 310 and the third resistor 315 constitute the main amplifier 9;

[0092] The second transistor 320 constitutes the first amplification branch 1;

[0093] The third transistor 330 constitutes the second amplification branch 2;

[0094] The seventh capacitor 441 acts as a coupling capacitor to couple the signal at the base of the first transistor 310 to the base of the third transistor 330.

[0095] The collectors of the second transistor 320 and the third transistor 330 are connected to the common output node 303 (i.e., the current confluence node) and are connected to the power supply VCC through the first resistor 304.

[0096] The sixth resistor 421 is connected between the power supply VCC and the base bias node of the second transistor 320; the seventh resistor 422 is connected between the base of the second transistor 320 and the input node 301; and the fourth resistor 411 is connected between the input node 301 and the reference ground. The fourth capacitor 423, as a bypass capacitor, is connected between the base of the second transistor 320 and the reference ground. The sixth resistor 421, the seventh resistor 422, and the fourth resistor 411 are used to establish the DC operating point required by the first transistor 310 and the second transistor 320; the fourth capacitor 423, as a bypass capacitor, ensures that the base of the second transistor 320 is in a low-impedance AC state near the desired oscillation frequency.

[0097] The first transistor 310 operates in a common-emitter configuration, with its base connected to the input node 301, its collector connected to the internal node 302, and its emitter connected to the reference ground via a first control circuit 322 consisting of a fifth resistor 413 and a third capacitor 412 connected in parallel. The third resistor 315 is connected between the internal node 302 and the input node 301 to form DC feedback, and to feed back the main noise component generated by the first transistor 310 from the internal node 302 to the input node 301 through a voltage divider formed by the fifth resistor 413. This results in a correlated noise voltage response originating from the first transistor 310 at both the input node 301 and the internal node 302, namely, the first noise component and the second noise component.

[0098] The second transistor 320 operates in a common-base configuration, with its emitter connected to the internal node 302 and its collector connected to the common output node 303. The second transistor 320 is used to transmit the signal generated by the first transistor 310 at the internal node 302 to the common output node 303 and to increase the input impedance of the main amplification branch.

[0099] The third transistor 330 operates in a common-emitter configuration. Its base is connected to the base of the first transistor 310 via a seventh capacitor 441 (as a coupling capacitor), and is DC biased by an eighth resistor 431 and a ninth resistor 432. Its emitter is connected to the reference ground via a second control circuit 332 consisting of a tenth resistor 434 and a fifth capacitor 433 connected in parallel. Its collector is connected to the common output node 303. The seventh capacitor 441 is used to transmit the AC component related to the main amplifier noise at the emitter of the first transistor 310, while isolating the DC bias of the first transistor 310 from that of the third transistor 330.

[0100] The first resistor 304 is connected between the power supply VCC and the common output node 303. The output currents of the second transistor 320 and the third transistor 330 are physically superimposed at the common output node 303, thus the common output node 303 constitutes the merging circuit 5. In other embodiments, the merging circuit 5 can also be implemented using an adder, subtractor, transformer, directional coupler, or power combiner, depending on the combination of the amplified first oscillation signal component, the second oscillation signal component, the first noise component, and the second noise component in the first slave amplification branch 1 and the second slave amplification branch 2.

[0101] One end of the quartz crystal 307 is connected to the input node 301 via a sixth capacitor 440 (as a coupling capacitor), and the other end is connected to the common output node 303 via a second resistor 305. A first capacitor 306 (as a load capacitor) and a second capacitor 308 (as a load capacitor) are respectively connected between the two ends of the quartz crystal 307 and the reference ground. The quartz crystal 307, the first capacitor 306, and the second capacitor 308 constitute a Pierce frequency selection network. The sixth capacitor 440 is used to isolate the DC bias of the input node 301. The second resistor 305 is used to adjust the driving power of the quartz crystal 307.

[0102] During operation, the Pierce frequency selection network feeds back the oscillation loop signal to input node 301. This oscillation loop signal is transmitted to the common output node 303 via a first amplification branch 1, which is composed of a main amplifier (first transistor 310) and a second amplification branch 2, which is composed of a seventh capacitor 441 and a third transistor 330. Simultaneously, the oscillation loop signal generates a correlation response (i.e., a second oscillation signal component) at the emitter of the first transistor 310, and is transmitted to the common output node 303 via a second amplification branch 2, which is composed of a seventh capacitor 441 and a third transistor 330.

[0103] The main noise generated inside the first transistor 310 forms correlated noise responses at the internal node 302, emitter, and input node 301. These noise responses are transmitted to the common output node 303 via the branch containing the second transistor 320 and the branch containing the third transistor 330, respectively. By adjusting the gain and phase of the two branches, the two correlated noise signals (i.e., the amplified first and second noise components) are made to have opposite polarities and equal or nearly equal amplitudes at the common output node 303, thereby canceling out the noise generated by the first transistor 310.

[0104] For the oscillation signal selected by the quartz crystal 307, by setting the polarity and phase of the two amplification branches, the polarity of the two oscillation signal components is made the same at the common output node 303. Thus, this embodiment achieves mutual cancellation of correlated noise and preservation or enhancement of the useful oscillation signal, rather than indiscriminately canceling all signals at the common output node 303. Under ideal matching conditions, the correlated noise amplitudes of the two first transistors 310 transmitted from the amplification branches to the common output node 303 are equal or close and have opposite polarities, and the synthesized noise approaches zero. In actual circuits, device process deviations, temperature variations, branch gain errors, and phase errors can generate residual noise, which can be reduced by adjusting the size or bias current of the third transistor 330, the seventh capacitor 441, the third resistor 315, the second control circuit 332, and the output load.

[0105] The second transistor 320, the third transistor 330, and their bias network also generate noise. To reduce the impact of this noise on the cancellation effect, low-noise devices can be selected, the operating current and size of the second transistor 320 and the third transistor 330 can be reasonably set, and the amplification branch should only provide the gain required to cancel the noise, avoiding the introduction of unnecessary noise.

[0106] Example 3

[0107] like Figure 5 As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. The structure of the noise cancellation amplifier circuit in this oscillator circuit differs from that in Embodiment 2. Specifically, it includes a first transistor 310, a third resistor 315, a first bias circuit 311, and a first control circuit 322 forming a main amplifier 9. The first transistor is a bipolar junction transistor (BJT), and therefore the first control circuit 322 is a first emitter circuit. The base of the first transistor 310 is connected to the input node 301 and receives the oscillation loop signal 10. The first bias circuit 311 is connected to the base of the first transistor 310 to provide a base bias voltage for the first transistor 310. The first control circuit 322 is connected between the emitter of the first transistor 310 and a reference ground to provide an emitter bias voltage for the first transistor 310. The third resistor 315 is connected between the input node 301 and the internal node 302 where the collector of the first transistor 310 is located to establish DC feedback and to cause the noise generated by the first transistor 310 to form a correlated noise response between the input node 301 and the internal node 302.

[0108] The second transistor 320 and the second bias circuit 321 constitute the first slave amplification branch 1. The second bias circuit 321 is connected to the base of the second transistor 320 to provide the base bias voltage of the second transistor 320; the emitter of the second transistor 320 is connected to the internal node 302, and the collector of the second transistor 320 is connected to the input terminal 5a of the merging circuit 5. The third transistor 330, the third bias circuit 331, and the second control circuit 332 constitute the second slave amplification branch 2, wherein the third transistor 330 is a bipolar junction transistor, and therefore the second control circuit 332 is the second emitter circuit. The third bias circuit 331 is connected to the base of the third transistor 330 to provide the base bias voltage of the third transistor 330. The second control circuit 332 is connected between the emitter of the third transistor 330 and the reference ground to provide the emitter bias voltage of the third transistor 330 and affects the gain of the third transistor 330 through current series negative feedback. The base of the third transistor 330 is connected to the input node 301, and the collector of the third transistor 330 is connected to the input terminal 5b of the merging circuit 5. The second bias circuit 321, the first bias circuit 311, and the third bias circuit 331 all contain a power supply and a reference ground. The first control circuit 322 and the second control circuit 332 may include, but are not limited to, a parallel network of resistors, inductors, and capacitors, a parallel network of resistors and capacitors, or any series combination thereof.

[0109] The oscillation loop signal 10 is transmitted to the merging circuit 5 via the first slave amplification branch 1, where the first transistor 310 and the second transistor 320 are located, and the second slave amplification branch 2, where the third transistor 330 is located, respectively. The first noise component and the second noise component generated by the first transistor 310 are also transmitted to the merging circuit 5 via the first slave amplification branch 1 and the second slave amplification branch 2, respectively. By setting the operating points established by the first bias circuit 311, the second bias circuit 321, the third bias circuit 331, the first control circuit 322, and the second control circuit 332, as well as the gain and load of the first transistor 320 and the third transistor 330, the two oscillation signal components are superimposed in phase at the merging circuit 5, thus increasing their amplitude, while the related noise components originating from the first transistor 310 are superimposed in opposite phase at the merging circuit 5, thus canceling them out.

[0110] Example 4

[0111] like Figure 6As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. The noise cancellation amplifier circuit is a BJT-based noise cancellation amplifier circuit, specifically comprising a first transistor 310 and a first bias circuit 311 forming a main amplifier 9. The first bias circuit 311 is connected to the base of the first transistor 310 to provide a base bias voltage for the first transistor 310; the oscillation loop signal 10 is connected to the emitter of the first transistor 310. The collector of the first transistor 310 is connected to the base of a second transistor 320.

[0112] The second transistor 320, the second bias circuit 321, and the first control circuit 322 constitute the first amplification branch 1. The second transistor 320 is a bipolar junction transistor (BJT), and therefore the first control circuit 322 is the first emitter circuit. The second bias circuit 321 is connected to the base of the second transistor 320 to provide a base bias voltage. The first control circuit 322 is connected between the emitter of the second transistor 320 and a reference ground to provide an emitter bias voltage and influences the gain of the second transistor 320 through current series negative feedback. The base of the second transistor 320 is connected to the collector of the first transistor 310, and the collector of the second transistor 320 is connected to the input terminal 5a of the merging circuit 5.

[0113] The third transistor 330, the third bias circuit 331, and the second control circuit 332 constitute the second amplification branch 2. The third transistor 330 is a bipolar junction transistor (BJT), and the second control circuit 332 is the second emitter circuit. The third bias circuit 331 is connected to the base of the third transistor 330 to provide a base bias voltage. The second control circuit 332 is connected between the emitter of the third transistor 330 and a reference ground to provide an emitter bias voltage and influences the gain of the third transistor 330 through current series negative feedback. The base of the third transistor 330 is connected to the oscillation loop signal 10 and the emitter of the first transistor 310, and the collector of the third transistor 330 is connected to the input terminal 5b of the merging circuit 5. The first bias circuit 311, the second bias circuit 321, and the third bias circuit 331 all contain a power supply and a reference ground. The first control circuit 322 and the second control circuit 332 may include, but are not limited to, a parallel network of resistors, inductors and capacitors, a parallel network of resistors and capacitors, or any series combination thereof.

[0114] The noise generated by the first transistor 310 forms a correlated noise response at its collector and emitter, and is transmitted to the merging circuit 5 via the first slave amplification branch 1 containing the second transistor 320 and the second slave amplification branch 2 containing the third transistor 330, respectively. By setting the operating points established by the first bias circuit 311, the second bias circuit 321, the third bias circuit 331, the first control circuit 322, and the second control circuit 332, as well as the gain and load of the second transistor 320 and the third transistor 330, the two oscillation signal components are superimposed in phase at the merging circuit 5, thus increasing their amplitude, while the correlated noise component originating from the first transistor 310 is superimposed in opposite phase at the merging circuit 5, thus canceling it out.

[0115] Example 5

[0116] like Figure 7 As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. The noise cancellation amplifier circuit is a noise cancellation amplifier circuit composed of a BJT and a JFET. A first transistor 310 and a first bias circuit 311 constitute the main amplifier 9. The first transistor 310 is a BJT, and the first bias circuit 311 is connected to the base of the first transistor 310 to provide the base bias voltage of the first transistor 310; the oscillation loop signal 10 is connected to the emitter of the first transistor 310. The emitter node of the first transistor 310 corresponds to the input terminal 9g and the output terminal 9b of the main amplifier 9, and the collector node of the first transistor 310 corresponds to the output terminal 9a of the main amplifier 9.

[0117] The second transistor 320, the second bias circuit 321, and the first control circuit 322 constitute the first slave amplification branch 1. The second transistor 320 is a JFET, therefore the first control circuit 322 is the first source circuit. The second bias circuit 321 is connected to the gate of the second transistor 320 to provide the gate bias voltage of the second transistor 320. The first control circuit 322 is connected between the source of the second transistor 320 and the reference ground to provide the source bias voltage of the second transistor 320 and influences the gain of the second transistor 320 through current series negative feedback. The gate of the second transistor 320 is connected to the collector of the first transistor 310, and the drain of the second transistor 320 is connected to the input terminal 5a of the merging circuit 5. The third transistor 330, the third bias circuit 331, and the second control circuit 332 constitute the second slave amplification branch 2. The third transistor 330 is a JFET, therefore the second control circuit 332 is the second source circuit. The third bias circuit 331 is connected to the gate of the third transistor 330 and is used to provide the gate bias voltage of the third transistor 330. The second control circuit 332 is connected between the source of the third transistor 330 and the reference ground and is used to provide the source bias voltage of the third transistor 330, and affects the gain of the third transistor 330 through current series negative feedback. The gate of the third transistor 330 is connected to the oscillation loop signal 10 and the emitter of the first transistor 310, and the drain of the third transistor 330 is connected to the input terminal 5b of the merging circuit 5. The first bias circuit 311, the second bias circuit 321 and the third bias circuit 331 all contain a reference ground. The first regulation circuit 322 and the second control circuit 332 may include, but are not limited to, a parallel network of resistors, inductors and capacitors, a parallel network of resistors and capacitors, or any series combination thereof.

[0118] The noise generated by the first transistor 310 forms a correlated noise response (i.e., a first noise component and a second noise component) at its collector and emitter, and is transmitted to the merging circuit 5 via the first slave amplification branch 1 containing the second transistor 320 and the second slave amplification branch 2 containing the third transistor 330, respectively. By setting the operating point established by the first bias circuit 311, the second bias circuit 321, the first adjustment circuit 322, the third bias circuit 331, and the second control circuit 332, as well as the gain and load of the second transistor 320 and the third transistor 330, the two oscillation signal components are superimposed in phase at the merging circuit 5, thus increasing their amplitude, while the correlated noise component originating from the first transistor 310 is superimposed in opposite phase at the merging circuit 5, thus canceling it out.

[0119] Example 6

[0120] like Figure 8As shown, this embodiment provides an oscillator circuit with a noise cancellation structure, wherein the noise cancellation amplifier circuit is a noise cancellation amplifier circuit composed of MOS transistors. A first transistor 310 and a first bias circuit 311 constitute the main amplifier 9, wherein the first transistor is a MOS transistor. The first bias circuit 311 is connected to the gate of the first transistor 310 and is used to provide the gate bias voltage of the first transistor 310; the oscillation loop signal 10 is connected to the source of the first transistor 310. The drain of the first transistor 310 is connected to the gate of a second transistor 320, wherein the second transistor is a MOS transistor.

[0121] The second transistor 320, the second bias circuit 321, and the first control circuit 322 constitute the first slave amplification branch 1, where the first control circuit 322 is the first source circuit. The second bias circuit 321 is connected to the gate of the second transistor 320 and is used to provide the gate bias voltage of the second transistor 320. The first control circuit 322 is connected between the source of the second transistor 320 and the reference ground and is used to provide the source bias voltage of the second transistor 320, and affects the gain of the second transistor 320 through current series negative feedback. The gate of the second transistor 320 is connected to the drain of the first transistor 310, and the drain of the second transistor 320 is connected to the input terminal 5a of the merging circuit 5. The third transistor 330, the third bias circuit 331, and the second control circuit 332 constitute the second slave amplification branch 2, wherein the third transistor 330 is a MOS transistor, and the second control circuit 332 is the second source circuit. The third bias circuit 331 is connected to the gate of the third transistor 330 and is used to provide the gate bias voltage of the third transistor 330. The second control circuit 332 is connected between the source of the third transistor 330 and the reference ground and is used to provide the source bias voltage of the third transistor 330, and affects the gain of the third transistor 330 through current series negative feedback. The gate of the third transistor 330 is connected to the oscillation loop signal 10 and the source of the first transistor 310, and the drain of the third transistor 330 is connected to the input terminal 5b of the merging circuit 5. The first bias circuit 311, the second bias circuit 321 and the third bias circuit 331 all contain a reference ground. The first regulation circuit 322 and the second control circuit 332 may include, but are not limited to, a parallel network of resistors, inductors and capacitors, a parallel network of resistors and capacitors, or any series combination thereof.

[0122] The noise generated by the first transistor 310 forms a correlated noise response (i.e., a first noise component and a second noise component) at its drain and source, and is transmitted to the merging circuit 5 via the first slave amplification branch 1 containing the second transistor 320 and the second slave amplification branch 2 containing the third transistor 330, respectively. The operating point established by the first bias circuit 311, the second bias circuit 321, the third bias circuit 331, the first adjustment circuit 322, and the second control circuit 332, as well as the gain and load of the second transistor 320 and the third transistor 330, cause the two oscillation signal components to be superimposed in phase at the merging circuit 5, thus increasing their amplitude, and cause the correlated noise component originating from the first transistor 310 to be superimposed in opposite phase at the merging circuit 5, thus canceling it out.

[0123] Figures 5 to 8 The three transistors shown in each figure are not limited to the illustrated device type. The transistors constituting the main amplifier 9, the first slave amplification branch 1, and the second slave amplification branch 2 can independently employ BJTs, JFETs, or MOSFETs. When replacing devices, the base, collector, and emitter of the BJT can correspond to the gate, drain, and source of the JFET or MOSFET with the same control and conduction terminal functions, and the power supply direction, bias voltage, and operational polarity of the merging circuit 5 can be adjusted accordingly based on the device polarity. This invention can be applied as long as it achieves in-phase synthesis of the oscillation signal and out-of-phase cancellation of related noise at the desired oscillation frequency.

[0124] exist Figures 5 to 8 In the illustrated embodiment, the first control circuit (322) and the second control circuit (332) connected to the second terminal (e.g., emitter or source) of the transistor can be flexibly designed according to specific circuit requirements. The first control circuit and the second control circuit can be any one or a combination of bias network, negative feedback / degradation network, AC grounding circuit, resonant frequency selection network or impedance matching network; and can include, but are not limited to, parallel networks of resistors, inductors and capacitors, parallel networks of resistors and capacitors, or any series combination thereof.

[0125] Example 7

[0126] like Figure 9 As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. The noise cancellation amplifier circuit is a noise cancellation amplifier circuit composed of inverters. The first inverter 910 and the feedback resistor 911 constitute the main amplifier 9. The input terminal of the first inverter 910 is connected to the oscillation loop signal 10, and the feedback resistor 911 is connected between the input terminal and the output terminal of the inverter 910 to establish DC feedback and make the noise generated by the first inverter 910 form a correlated noise response at its input and output terminals.

[0127] Amplifier 920 forms the first slave amplification branch 1, with its input connected to the output of the first inverter 910 and its output connected to the input 5a of the merging circuit 5. Second inverter 930 forms the second slave amplification branch 2, with its input connected to the oscillation loop signal 10 and its output connected to the input 5b of the merging circuit 5. The merging circuit 5 combines the signals from inputs 5a and 5b and outputs them from output 5c. By selecting the parameters of the first inverter 910, amplifier 920, second inverter 930, and feedback resistor 911, the two oscillation signals are synthesized in phase at the merging circuit 5, and the two noise components related to the noise of the first inverter 910 are synthesized in phase at the merging circuit 5 to cancel each other out.

[0128] Figure 9 The first inverter 910, amplifier 920, and second inverter 930 can all be constructed by connecting multiple logic units with the same function in parallel. Either the first inverter 910 or the second inverter 930 can be constructed by connecting two or more inverter units whose inputs and outputs are interconnected in parallel. Amplifier 920 is optional and can also be constructed by a non-inverting amplifier circuit or an even number of cascaded inverter units. The number, size, and bias conditions of the parallel devices included in each unit can be set independently to adjust the gain, phase, and noise matching of the corresponding path.

[0129] Example 8

[0130] like Figure 10 As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. The output terminal 5c of the noise cancellation amplifier circuit 100 is connected to the input terminal of the auxiliary circuit 6. The output terminal of the auxiliary circuit 6 is connected to the input terminal 9g of the noise cancellation amplifier circuit 100 via a first inductor 1002. An eighth capacitor 1001 is connected between the input terminal 9g and a reference ground, and a ninth capacitor 1003 is connected between the output terminal of the auxiliary circuit 6 and the reference ground. The first inductor 1002, the eighth capacitor 1001, and the ninth capacitor 1003 constitute an LC frequency selection network and form a closed oscillation loop with the noise cancellation amplifier circuit 100 and the auxiliary circuit 6.

[0131] Example 9

[0132] like Figure 11As shown, this embodiment provides an oscillator circuit with a noise cancellation structure, which is an oscillator circuit composed of a noise cancellation amplifier circuit and a quartz crystal frequency selection network. The output terminal 5c of the noise cancellation amplifier circuit 100 is connected to the input terminal of the auxiliary circuit 6. The output terminal of the auxiliary circuit 6 is connected to the input terminal 9g of the noise cancellation amplifier circuit 100 through a quartz crystal 307. A first capacitor 306 is connected between the input terminal 9g and a reference ground, and a second capacitor 308 is connected between the output terminal of the auxiliary circuit 6 and the reference ground. The quartz crystal 307, the first capacitor 306, and the second capacitor 308 constitute a quartz crystal frequency selection network, forming a closed oscillation loop with the noise cancellation amplifier circuit 100 and the auxiliary circuit 6.

[0133] Example 10

[0134] like Figure 12 As shown, this embodiment provides an oscillator circuit with a noise cancellation structure, which is an oscillator circuit composed of a noise cancellation amplifier circuit, a resonator, and an LC frequency selection network. The input terminal 9g of the noise cancellation amplifier circuit 100 is connected to the second terminal 7b of the resonator 7, and the output terminal 5c is connected to the second node 1203 via the auxiliary circuit 6. The resonator 7 is connected between the first node 1202 and the input terminal 9g of the noise cancellation amplifier circuit 100. The second inductor 1206 is connected between the second node 1203 and the reference ground, the eighth capacitor 1204 is connected between the second node 1203 and the first node 1202, and the ninth capacitor 1205 is connected between the first node 1202 and the reference ground. The second inductor 1206, the eighth capacitor 1204, and the ninth capacitor 1205 constitute an LC frequency selection network, which, together with the resonator 7, the noise cancellation amplifier circuit 100, and the auxiliary circuit 6, forms a closed oscillation loop. The bias circuit 1210 is connected between the common node of port 9g of the noise cancellation amplifier circuit 100 and port 7b of the resonator 7 and the reference ground, and is used to establish the DC operating point of the node where the input terminal 9g is located and the related active devices. The resonator 7 is used to improve the quality factor of the oscillation loop, and the LC frequency selection network is used to achieve frequency selection.

[0135] Example 11

[0136] like Figure 13As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. The oscillator circuit forms an oscillation loop through a noise cancellation amplifier circuit 100, an auxiliary circuit 6, and a frequency selection circuit 8, and outputs the oscillator through a resonator 7, a first buffer amplifier circuit 1303, and a first impedance matching circuit 1304. The output terminal 5c of the noise cancellation amplifier circuit 100 is connected to the first terminal 6a of the auxiliary circuit 6, the second terminal 6b of the auxiliary circuit 6 is connected to the first terminal 8a of the frequency selection circuit 8, and the second terminal 8b of the frequency selection circuit 8 is connected to the input terminal 9g of the noise cancellation amplifier circuit 100, thus forming a closed oscillation loop. The second terminal 7b of the resonator 7 is connected to the input terminal 9g of the noise cancellation amplifier circuit 100, and the first terminal 7a of the resonator 7 is connected to the input terminal 1303a of the first buffer amplifier circuit. The resonator 7 forms an equivalent resonator of the oscillation loop through the load effect of the input stage transistor of the noise cancellation amplifier circuit 100. The first external bias circuit 1301 is connected between the input terminal 9g and the reference ground to establish the DC operating point of the node where the input terminal 9g is located. The second external bias circuit 1302 is connected to the same node where the first terminal 7a of the resonator 7 and the input terminal 1303a of the first buffer amplifier circuit are located, to establish the DC operating point of the node. The first external bias circuit 1301 and the second external bias circuit 1302 preferably adopt a circuit structure with high AC impedance near the oscillation frequency to prevent the oscillation signal from being shunted to ground by the first external bias circuit 1301 or the second external bias circuit 1302. The input terminal 1303a of the first buffer amplifier circuit is connected to the first terminal 7a of the resonator 7, and the output terminal 1303b of the first buffer amplifier circuit is connected to the output terminal of the oscillator circuit via the first impedance matching circuit 1304 (i.e., the output terminal of the first impedance matching circuit 1304 serves as the output terminal of the oscillator circuit). The first buffer amplifier circuit 1303 is used to amplify or buffer the oscillation signal output by the resonator 7 and reduce the pull of the external load on the resonator 7 and the oscillation loop. The first buffer amplifier circuit 1303 preferably adopts a low input impedance circuit structure to reduce the load effect of the first buffer amplifier circuit 1303 on the resonator 7, thereby improving the loaded Q value of the oscillation loop. The second impedance matching circuit 1304 is used to transform the output impedance of the first buffer amplifier circuit 1303 into the impedance required by the external load.

[0137] Example 12

[0138] like Figure 14As shown, this embodiment provides an oscillator circuit with a noise cancellation structure. This embodiment is an oscillator circuit with a noise cancellation structure that samples from the internal nodes of the oscillation loop and outputs through the second buffer amplifier circuit 1403. The output terminal 5c of the noise cancellation amplifier circuit 100 is connected to the first terminal 6a of the auxiliary circuit 6, the second terminal 6b of the auxiliary circuit 6 is connected to the first terminal 8a of the frequency selection circuit 8, and the second terminal 8b of the frequency selection circuit 8 is connected to the input terminal 9g of the noise cancellation amplifier circuit 100, thereby forming a closed oscillation loop. The second terminal 7b of the resonator 7 is connected to the input terminal 9g of the noise cancellation amplifier circuit 100, and the first terminal 7a of the resonator 7 is connected to the reference ground through the fourth bias circuit 1402. The resonator 7 forms the equivalent resonator of the oscillation loop through the load effect of the input stage transistor of the noise cancellation amplifier circuit 100. The third external bias circuit 1401 is connected between the input terminal 9g and the reference ground to establish the DC operating point of the node where the input terminal 9g is located. The third external bias circuit 1401 preferably employs a circuit structure with high AC impedance near the oscillation frequency to prevent the oscillation signal from being shunted to ground by the third external bias circuit 1401. The fourth bias circuit 1402 may be, but is not limited to, a wire or a low input impedance circuit, used to provide a low impedance path for the resonator 7 to connect to the reference ground. The input terminal 1403a of the second buffer amplifier circuit 1403 is connected to the internal node of the oscillation loop between the second terminal 6b of the auxiliary circuit 6 and the first terminal 8a of the frequency selection circuit 8. The output terminal 1403b of the second buffer amplifier circuit 1403 is connected to the output terminal of the oscillator circuit via the second impedance matching circuit 1404. Thus, the oscillation signal can be directly coupled from the internal node of the oscillation loop to the second buffer amplifier circuit 1403, and the second buffer amplifier circuit 1403 provides gain or buffering, while the second impedance matching circuit 1404 provides impedance transformation to reduce the influence of external loads on the oscillation loop. The second buffer amplifier circuit 1403 preferably adopts a low input impedance circuit structure to reduce the load effect of the second buffer amplifier circuit 1403 on the resonator 7 and the oscillation loop, thereby improving the loaded Q value of the oscillation loop. The second impedance matching circuit 1404 is used to transform the output impedance of the second buffer amplifier circuit 1403 into the impedance required by the external load.

[0139] exist Figures 12 to 14 In the illustrated embodiment, the resonator 7 or frequency selection circuit 8 can be a quartz crystal resonator, a metal microwave cavity, a dielectric resonator, a sapphire resonator, a MEMS resonator, a surface acoustic wave resonator, a bulk acoustic wave resonator, or a resonant circuit network composed of more than one inductor and more than one capacitor. The connection order of the noise cancellation amplifier circuit 100, the auxiliary circuit 6, the resonator 7, and the frequency selection circuit 8 can be adjusted according to the specific loop topology. The oscillator circuit of this noise cancellation structure is versatile.

[0140] This invention can be implemented using discrete devices or integrated circuit technology.

[0141] This invention can also be used in conjunction with automatic gain control circuits, amplitude stabilization circuits, or start-up control circuits.

[0142] The common output node in this invention can be a voltage output node or a current confluence node. The confluence circuit 5 includes the intersection point of low-frequency circuit wires, an adder or subtractor, a transformer, a directional coupler, and a power combiner.

[0143] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used to facilitate the description of this invention and to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this invention.

[0144] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An oscillator circuit containing a noise cancellation structure, characterized in that: Includes noise cancellation amplifier circuitry and feedback network; The noise cancellation amplifier circuit includes a main amplifier, a first slave amplifier branch, a second slave amplifier branch, and a merging circuit; The main amplifier has an input terminal, a first output terminal, and a second output terminal. Its input terminal is used to receive an oscillation loop signal, its first output terminal is used to output a first composite signal, and its second output terminal is used to output a second composite signal. The first composite signal includes a first oscillation signal component and a first noise component, and the second composite signal includes a second oscillation signal component and a second noise component. Both the first noise component and the second noise component come from the internal noise of the main amplifier. The merging circuit has a first input terminal, a second input terminal, and an output terminal; The input terminal of the first slave amplifier branch is connected to the first output terminal of the main amplifier, and its output terminal is connected to the first input terminal of the merging circuit; the input terminal of the second slave amplifier branch is connected to the second output terminal of the main amplifier, and its output terminal is connected to the second input terminal of the merging circuit. The merging circuit merges the output signals of the first slave amplification branch and the second slave amplification branch, so that the oscillation signal components in the two output signals are superimposed in phase and the amplitude is enhanced, while the noise components are superimposed in opposite phase and canceled out. The output of the merging circuit is connected to the input of the feedback network, and the output of the feedback network is connected to the input of the main amplifier to form a closed oscillation loop.

2. The oscillator circuit with a noise cancellation structure according to claim 1, characterized in that: The first or second output terminal of the main amplifier is connected to its input terminal.

3. An oscillator circuit with a noise cancellation structure according to claim 1, characterized in that: The merging circuit is a conductor intersection point, an adder, a subtractor, a differential amplifier, a transformer, a directional coupler, or a combiner.

4. An oscillator circuit with a noise cancellation structure according to claim 1, characterized in that: The main amplifier, the first slave amplifier branch, the second slave amplifier branch, and the merging circuit are integrated on the same printed circuit board or integrated circuit substrate.

5. An oscillator circuit with a noise cancellation structure according to claim 1, characterized in that: The main amplifier includes a first transistor and a first bias circuit; the first slave amplifier branch includes a second transistor, a second bias circuit, and a first control circuit; the second slave amplifier branch includes a third transistor, a third bias circuit, and a second control circuit; wherein the first bias circuit, the second bias circuit, and the third bias circuit are used to provide a bias voltage; the first control circuit and the second control circuit are used to provide a bias voltage and adjust the gain. The first transistor, the second transistor, and the third transistor each have a first terminal, a second terminal, and a third terminal. For any one of the first transistor, the second transistor, and the third transistor, when the transistor is a field-effect transistor, the first terminal is the gate, the second terminal is the source, and the third terminal is the drain. In this case, the first control circuit and the second control circuit are respectively the first source circuit and the second source circuit. When the transistor is a bipolar junction transistor, the first terminal is the base, the second terminal is the emitter, and the third terminal is the collector. In this case, the first control circuit and the second control circuit are respectively the first emitter circuit and the second emitter circuit. The first bias circuit is connected to the first terminal of the first transistor, the second bias circuit is connected to the first terminal of the second transistor, the first control circuit is connected between the second terminal of the first transistor and the reference ground, the third bias circuit is connected to the first terminal of the third transistor, and the second control circuit is connected between the second terminal of the third transistor and the reference ground. The first terminal of the first transistor serves as the input terminal of the main amplifier, used to connect the oscillation loop signal; The third terminal of the first transistor serves as the first output terminal of the main amplifier and is connected to the first terminal of the second transistor and its own first terminal, respectively; the first terminal of the first transistor is also connected to the first terminal of the third transistor; the third terminal of the second transistor is connected to the first input terminal of the merging circuit, and the third terminal of the third transistor is connected to the second input terminal of the merging circuit.

6. An oscillator circuit with a noise cancellation structure according to claim 1, characterized in that: The main amplifier includes a first transistor and a first bias circuit; the first slave amplifier branch includes a second transistor, a second bias circuit, and a first control circuit; the second slave amplifier branch includes a third transistor, a third bias circuit, and a second control circuit; wherein the first bias circuit, the second bias circuit, and the third bias circuit are used to provide a bias voltage; the first control circuit and the second control circuit are used to provide a bias voltage and adjust the gain. The first transistor, the second transistor, and the third transistor each have a first terminal, a second terminal, and a third terminal. For any one of the first transistor, the second transistor, and the third transistor, when the transistor is a field-effect transistor, the first terminal is the gate, the second terminal is the source, and the third terminal is the drain. In this case, the first control circuit and the second control circuit are respectively the first source circuit and the second source circuit. When the transistor is a bipolar junction transistor, the first terminal is the base, the second terminal is the emitter, and the third terminal is the collector. In this case, the first control circuit and the second control circuit are respectively the first emitter circuit and the second emitter circuit. The first bias circuit is connected to the first terminal of the first transistor, the second bias circuit is connected to the first terminal of the second transistor, the first control circuit is connected between the second terminal of the second transistor and the reference ground, the third bias circuit is connected to the first terminal of the third transistor, and the second control circuit is connected between the second terminal of the third transistor and the reference ground. The third terminal of the first transistor is connected to the first output terminal of the main amplifier and the first terminal of the second transistor, respectively; the second terminal of the first transistor is connected to the first terminal of the third transistor, serving as the input terminal of the main amplifier, so that the oscillation loop signal enters the first transistor and the third transistor simultaneously, and also serves as one of the noise output terminals of the first transistor, outputting the corresponding noise component to the third transistor; the third terminal of the second transistor is connected to the first input terminal of the merging circuit, and the third terminal of the third transistor is connected to the second input terminal of the merging circuit.

7. An oscillator circuit with a noise cancellation structure according to claim 1, characterized in that: The feedback network includes a frequency selection circuit, an auxiliary circuit, and a resonator; The auxiliary circuit is used to implement a predetermined auxiliary function; The auxiliary circuit, resonator, and frequency selection circuit are connected in series, and the series order can be adjusted arbitrarily.

8. An oscillator circuit with a noise cancellation structure according to claim 7, characterized in that: The resonator is a quartz crystal resonator, a metal microwave cavity, a dielectric resonator, a sapphire resonator, a MEMS resonator, a surface acoustic wave resonator, a bulk acoustic wave resonator, or a resonant circuit network consisting of more than one inductor and more than one capacitor.

9. An oscillator circuit with a noise cancellation structure according to claim 7, characterized in that, The oscillator circuit further includes: a first external bias circuit, a second external bias circuit, a first buffer amplifier circuit, and a first impedance matching circuit; The output of the merging circuit is connected to the input of the frequency selection circuit via the auxiliary circuit, and the output of the frequency selection circuit is connected to the input of the main amplifier to form a closed oscillation loop. The first end of the resonator is connected to the input end of the main amplifier, the second end of the resonator is connected to the input end of the first buffer amplifier circuit, the output end of the first buffer amplifier circuit is connected to the input end of the first impedance matching circuit, and the output end of the first impedance matching circuit serves as the output end of the oscillator circuit. The first external bias circuit is connected between the input terminal of the main amplifier and the reference ground; The second external bias circuit is connected between the second end of the resonator and the reference ground.

10. An oscillator circuit with a noise cancellation structure according to claim 7, characterized in that: The oscillator circuit also includes a third external bias circuit, a fourth external bias circuit, a second buffer amplifier circuit, and a second impedance matching circuit. The output of the merging circuit is connected to the input of the frequency selection circuit via the auxiliary circuit; the output of the frequency selection circuit is connected to the input of the main amplifier to form a closed oscillation loop. The first end of the resonator is connected to the input end of the main amplifier; The third external bias circuit is connected between the first end of the resonator and the reference ground. The second end of the resonator is connected to the reference ground via the fourth external bias circuit; The input terminal of the second buffer amplifier circuit is connected to the internal node of the oscillation loop between the output terminal of the auxiliary circuit and the input terminal of the frequency selection circuit; The output terminal of the second buffer amplifier circuit is connected to the input terminal of the second impedance matching circuit, and the output terminal of the second impedance matching circuit serves as the output terminal of the oscillator circuit.

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