high frequency circuit

Abstract

This disclosure provides a high-frequency circuit capable of selectively disconnecting and connecting a circuit that allows signals with frequencies lower than the operating frequency band to pass to a reference potential terminal. The high-frequency circuit includes: an output terminal; a first transistor having a first terminal, a second terminal, and a control terminal; a first circuit having a resistor and a first capacitor, wherein the resistor and the first capacitor are connected in series between a first node and the reference potential terminal, the first node being located between the second terminal and the output terminal, the reference potential terminal being supplied with a reference potential, the first circuit allowing signals with frequencies lower than the operating frequency band in a high-frequency signal transmitted at the first node to pass to the reference potential terminal; and a switch that disconnects and connects the circuit between the first node and the reference potential terminal via the first circuit.

Description

Technical Field

[0001] This disclosure relates to high-frequency circuits. Background Technology

[0002] In high-frequency circuits, there are known decoupling circuits that are connected to the output terminal of a transistor and have low impedance at low frequencies corresponding to the envelope band of the high-frequency signal (e.g., Patent Document 1).

[0003] Existing technical documents Patent documents Patent Document 1: U.S. Patent Application Publication No. 2005 / 0104679 By setting a circuit that creates a low impedance between the transistor's output terminal and the reference potential at a frequency lower than the operating frequency band, distortion compensation can be achieved. On the other hand, some high-frequency signals in the operating frequency band leak into this circuit, sometimes causing losses. Therefore, from a distortion compensation perspective, decoupling circuits are necessary in broadband modulated wave signals, but they are undesirable in situations where communication capacity is not required, such as in narrowband modulated wave signals. Summary of the Invention

[0004] The purpose of this disclosure is to provide a high-frequency circuit that can selectively disconnect and connect circuits that suppress signals lower than the operating frequency band.

[0005] This disclosure discloses a high-frequency circuit comprising: an output terminal; a first transistor having a first terminal, a second terminal, and a control terminal; a first circuit having a resistor and a first capacitor, wherein the resistor and the first capacitor are connected in series between a first node and a reference potential terminal, the first node being disposed between the second terminal and the output terminal, the reference potential terminal being supplied with a reference potential, the first circuit enabling a signal of a high-frequency signal transmitted at the first node that is lower than the operating frequency band to pass to the reference potential terminal; and a switch for disconnecting and connecting the first node and the reference potential terminal via the path of the first circuit.

[0006] An embodiment of this disclosure is a high-frequency circuit comprising: a substrate; a transistor disposed on the substrate; a lead electrically connected to the transistor; a switch disposed on the substrate, a first terminal of the switch being electrically connected to the lead; and at least one of a resistor or a capacitor disposed on the substrate and electrically connected to a second terminal of the switch.

[0007] Invention Effects According to this disclosure, the disconnection and connection of circuits that suppress signals lower than the operating frequency band can be selected. Attached Figure Description

[0008] Figure 1 This is a block diagram of the high-frequency circuit according to the first embodiment.

[0009] Figure 2 This is a block diagram of the high-frequency circuit according to the second embodiment.

[0010] Figure 3 This is a circuit diagram of the high-frequency circuit of Example 1 of the first embodiment.

[0011] Figure 4 This is a circuit diagram of the high-frequency circuit of Example 1 of the first embodiment.

[0012] Figure 5 This is a top view of the high-frequency circuit of Example 1 of the first embodiment.

[0013] Figure 6 This is a top view of the semiconductor chip in Example 1 of the first embodiment.

[0014] Figure 7 This is a circuit diagram of the high-frequency circuit of Example 2 of the first embodiment.

[0015] Figure 8 This is a top view of the high-frequency circuit of Example 2 of the first embodiment.

[0016] Figure 9 This is a circuit diagram of the high-frequency circuit of Example 1 of the second embodiment.

[0017] Figure 10 This is a top view of the high-frequency circuit of Example 1 of the second embodiment.

[0018] Figure 11 This is a diagram showing S21 relative to the frequency when the switch is turned on and off in Example 1 of the second embodiment.

[0019] Figure 12 This is a circuit diagram of the high-frequency circuit in Example 2 of the second embodiment.

[0020] Figure 13 This is a top view of the high-frequency circuit of Example 2 of the second embodiment.

[0021] Figure 14 This is a circuit diagram of the high-frequency circuit in Example 3 of the second embodiment.

[0022] Figure 15 This is a top view of the high-frequency circuit of Example 3 of the second embodiment.

[0023] Figure 16 This is a top view of the semiconductor chip in Example 3 of the second embodiment.

[0024] Figure 17This is a circuit diagram of the high-frequency circuit in Example 4 of the second embodiment.

[0025] Figure 18 This is a top view of the high-frequency circuit of Example 4 of the second embodiment.

[0026] Figure 19 This is a top view of the high-frequency circuit of Example 5 of the second embodiment.

[0027] Figure 20 This is a top view of the semiconductor chip in Example 5 of the second embodiment.

[0028] Figure 21 This is a top view of the high-frequency circuit of Example 6 of the second embodiment.

[0029] Figure 22 This is a top view of the high-frequency circuit of Example 7 of the second embodiment.

[0030] Figure 23 This is a top view of the semiconductor chip in Example 7 of the second embodiment.

[0031] Figure 24 This is a top view of the high-frequency circuit of Example 8 of the second embodiment.

[0032] Explanation of reference numerals in the attached figures 10: First circuit; 11: Second circuit; 12, 13: Matching circuit; 15: Package; 20: Substrate; 21: Frame; 22, Tout: Output terminal; 23, Tin: Input terminal; 24, Tcont: Control signal terminal; 30, 36: Semiconductor chip; 30A, 36A: Semiconductor substrate; 30B, 30C, 31B, 32B, 33B, 33C, 34B, 35B, 35C, 36B, 36C, 36D, 38B: Electrode; 30E, 36E: Source electrode; 30F, 36F: Drain electrode; 30G, 36G: Gate electrode; 31, 32, 33, 34, 38: Capacitive component; 31A, 32A, 33A, 34A, 38A: Dielectric substrate; 33D: Chip capacitor; 33E: Capacitor; 35 : Resistor component; 35A: Substrate; 35D: Resistor element; 41A, 41B, 42A, 42B, 43, 44, 45, 46, 47, 48A, 48B, 48C: Bonding wires; 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112: High-frequency circuit; C1 (first capacitor), C2 (second capacitor), C3, C11, C21: Capacitors; L1, L2, L3, L4, L11, L12, L21, L22, L31, L32, L33: Inductors; N1 (first node), N2 (second node), N3 (third node): Nodes; Q1 (first transistor), Q2 (second transistor): Transistors; R1: Resistor; SW1: Switch. Detailed Implementation

[0033] [Description of embodiments of this disclosure] First, the implementation plan disclosed herein will be listed for illustration.

[0034] (1) An embodiment of this disclosure is a high-frequency circuit comprising: an output terminal; a first transistor having a first terminal, a second terminal, and a control terminal; a first circuit having a resistor and a first capacitor, wherein the resistor and the first capacitor are connected in series between a first node and a reference potential terminal, the first node being disposed between the second terminal and the output terminal, the reference potential terminal being supplied with a reference potential, the first circuit enabling a signal of a high-frequency signal transmitted at the first node that is lower than the operating frequency band to pass to the reference potential terminal; and a switch for disconnecting and connecting the first node and the reference potential terminal via the path of the first circuit. Thus, the disconnection and connection of the first circuit for suppressing signals lower than the operating frequency band can be selected.

[0035] (2) In (1) above, the switch may also be connected between the first circuit and the reference potential terminal. This makes it easy to generate a control signal for the switch.

[0036] (3) In (1) above, the switch may also be connected between the first node and the first circuit. Thus, the first circuit can be separated from the first node by turning off the switch.

[0037] (4) In any of (1) to (3) above, the high-frequency circuit may also include: a second circuit that reduces the flow of signals with frequencies within the operating frequency band to the first circuit. This reduces the leakage of high-frequency signals from the operating frequency band transmitted at the first node to the first circuit.

[0038] (5) In (4) above, the second circuit may also have an inductor connected in series with the first circuit and the switch between the first node and the reference potential terminal. This reduces the leakage of high-frequency signals in the operating frequency band transmitted at the first node to the first circuit.

[0039] (6) In (4) above, the second circuit may also have a second node located between the first node and the first circuit, which serves as a reference potential at any frequency within the operating frequency band. This reduces the likelihood of high-frequency signals with frequencies within the operating frequency band transmitted at the first node flowing into the first circuit.

[0040] (7) In any of (1) to (6) above, the first circuit may also have a second capacitor connected in parallel with the resistor and the first capacitor between the third node and the reference potential terminal, wherein the third node is located between the resistor and the first capacitor and the first node. This allows the bandwidth of the signal reduced by the first circuit to be widened.

[0041] (8) In any of (1) to (7) above, the switch may be a second transistor having a third terminal, a fourth terminal, and a control terminal, wherein the third terminal and the fourth terminal are located on the path. Thus, a switch can be formed.

[0042] (9) In any of (1) to (8) above, the absolute value of the impedance of the first capacitor at a frequency equivalent to the width of the operating frequency band is less than or equal to 10Ω. Thus, distortion compensation based on DPD can be performed.

[0043] (10) In (8) above, the high-frequency circuit may also include: a substrate, at least the upper surface of which is conductive, the substrate being the reference potential terminal; and a semiconductor chip mounted on the substrate, the semiconductor chip being formed by integrating at least one of the first transistor, the resistor, and the first capacitor, and the second transistor. This enables miniaturization.

[0044] (11) An embodiment of the present disclosure is a high-frequency circuit comprising: a substrate; a transistor disposed on the substrate; a lead electrically connected to the transistor; a switch disposed on the substrate, a first terminal of the switch electrically connected to the lead; and at least one of a resistor or a capacitor disposed on the substrate and electrically connected to a second terminal of the switch. Thus, the disconnection and connection of the lead to the circuit including at least one of the resistor or capacitor can be selected.

[0045] (12) In (11) above, at least the upper surface of the substrate may be conductive, the transistor may have a first terminal, a second terminal, and a first control terminal, the lead may be electrically connected to the second terminal of the transistor, the first end of the resistor may be electrically connected to the second end of the switch, and the capacitor may have a first electrode and a second electrode in which a dielectric substrate is disposed, the first electrode being electrically connected to the substrate and the second electrode being electrically connected to the second end of the resistor. Thus, the disconnection and connection of the lead to the circuit including the resistor and the capacitor can be selected.

[0046] [Details of the embodiments disclosed herein] Hereinafter, specific examples of high-frequency circuits according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but rather, as illustrated by the claims, is intended to include all modifications within the meaning and scope equivalent to the claims.

[0047] (First Implementation) In the following embodiments, a high-frequency amplifier circuit will be used as an example of a high-frequency circuit. The first embodiment is an example in which a switch is connected between the first circuit 10 and the second circuit 11. Figure 1 This is a block diagram of the high-frequency circuit according to the first embodiment. (For example...) Figure 1 As shown, the high-frequency circuit 100 of the first embodiment includes a transistor Q1, a first circuit 10, a second circuit 11, a matching circuit 12, and a matching circuit 13.

[0048] Transistor Q1 (first transistor), for example, is a FET (Field Effect Transistor), having a source S (first terminal), a drain D (second terminal), and a gate G (control terminal). The source S is short-circuited by being electrically connected to a reference potential terminal such as ground. The gate G is electrically connected to the input terminal Tin via matching circuit 13. The drain D is electrically connected to the output terminal Tout via matching circuit 12. A node N1 (first node) located between the drain D and the output terminal Tout is electrically connected to the reference potential terminal via second circuit 11 and first circuit 10.

[0049] Transistor Q1 is, for example, GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0050] Matching circuit 13 matches the impedance from the input terminal Tin to the gate G of transistor Q1. Transistor Q1 amplifies the high-frequency signal Sin input to the input terminal Tin and outputs the amplified high-frequency signal Sout to its drain D. Matching circuit 12 matches the impedance from the drain D of transistor Q1 to the output terminal Tout.

[0051] The first circuit 10 has a resistor R1 and a capacitor C1 (first capacitor) connected in series between node N1 and a reference potential terminal. The first circuit 10 directs a signal in the high-frequency signal Sout flowing through node N1 that is lower than the operating frequency band of the high-frequency circuit 100 to the reference potential terminal. The order of capacitor C1 and resistor R1 can also be reversed. That is, resistor R1 can also be placed between capacitor C1 and the reference potential terminal. Resistor R1 is a damping resistor used to reduce the resonance caused by the capacitor C1 with its large capacitance and the inductor (e.g., an inductor formed by bonding wires, described later).

[0052] The second circuit 11 reduces the flow of signals with frequencies within the operating frequency band in the high-frequency signal Sout transmitted at node N1 to the first circuit 10. In the case where the high-frequency circuit 100 is used as a power amplifier for a mobile communication base station, the center frequency of the operating frequency band is, for example, greater than or equal to 0.5 GHz and less than or equal to 20 GHz, and the width of the operating frequency band is, for example, greater than or equal to 0.1 MHz and less than or equal to 1 GHz.

[0053] A switch SW1 is connected between the second circuit 11 and the first circuit 10. The switch SW1 will disconnect and connect the node N1 and the reference potential terminal through the path of the first circuit 10 based on the control signal Snot.

[0054] The drain bias voltage applied to the drain D of transistor Q1 is supplied from either the second circuit 11 and the switch SW1 or the drain D and the output terminal Tout.

[0055] (Second Implementation) The second embodiment is an example of connecting switch SW1 between the first circuit 10 and the reference potential terminal. Figure 2 This is a block diagram of the high-frequency circuit according to the second embodiment. (For example...) Figure 2 As shown, in the high-frequency circuit 101 of the second embodiment, switch SW1 is connected between the first circuit 10 and the reference potential terminal. Other configurations are the same as in the first embodiment, and descriptions are omitted.

[0056] In both the first and second embodiments, the first circuit 10 is, for example, a VBW (Video Band Width) circuit, which is used to increase the video bandwidth. VBW is used as an indicator of the frequency band of intermodulation distortion. When VBW is small, when the third-order intermodulation distortion (IMD3) of a two-tone signal with a bandwidth comparable to that of the high-frequency circuit 100 is measured, a difference in signal strength occurs between the IMD3 component on the low-frequency side and the IMD3 component on the high-frequency side. When IMD3 is thus asymmetrical, even with distortion compensation based on DPD (Digital Predistortion), the amount of distortion improvement decreases, and sufficient distortion characteristics cannot be obtained. As a cause of this IMD3 asymmetry, a second-order intermodulation distortion (IMD2) component generated in the difference frequency component of the two-tone signal is known. Therefore, by setting the first circuit 10, the video bandwidth increases, and the IMD2 component is suppressed. As a result, the asymmetry of IMD3 is improved, and sufficient distortion compensation can be achieved through DPD.

[0057] When the bandwidths of high-frequency signals Sin and Sout are large, distortion compensation can be easily achieved by setting a VBW circuit. When the bandwidths of high-frequency signals Sin and Sout are small, even if the VBW is small, it is not likely to be a problem, and a VBW circuit may not be used. Thus, there are cases where the characteristics can be improved by setting a VBW circuit or other first circuit 10, and cases where the first circuit 10 may not be set.

[0058] By setting a second circuit 11 between node N1 and the first circuit 10, the leakage of signals within the operating frequency band of the high-frequency signal Sout flowing in node N1 to the first circuit 10, thus reducing losses, is reduced. However, in reality, a portion of the signals within the operating frequency band flows into resistor R1, and through the heating of resistor R1, power is consumed, thus contributing to the losses of high-frequency circuits 100 and 101.

[0059] Therefore, if the characteristics can be improved by setting the first circuit 10, it is ideal to set the first circuit 10. On the other hand, if the improvement in characteristics is not significant even when using the first circuit 10, it is ideal not to set the first circuit 10.

[0060] It should be noted that when high-frequency circuits 100 and 101 are amplifier circuits, the operating frequency band refers to the frequency range between frequencies where the maximum absolute value of S21 is -3dB when the input terminal Tin is set as port 1 and the output terminal Tout is set as port 2. The operating frequency band remains unchanged even if the applications of high-frequency circuits 100 and 101 differ. The bandwidth of the high-frequency signal Sin refers to the bandwidth of the signal input to the input terminal Tin, which varies depending on the application of high-frequency circuits 100 and 101. The bandwidth of the high-frequency signal may be the same as or smaller than the operating frequency band.

[0061] In both the first and second embodiments, a switch SW1 is provided, which connects and disconnects the node N1 and the reference potential terminal via the path of the first circuit 10. Thus, when the switch SW1 is turned on, the first circuit 10 is connected between the node N1 and the reference potential terminal. This allows signals in the high-frequency signal Sout transmitted at node N1 that are lower than the operating frequency band to flow to the reference potential terminal. Therefore, for example, VBW can be increased, making distortion compensation easier to achieve. When the switch SW1 is turned off, the first circuit 10 is disconnected from the node N1 and the reference potential terminal. This reduces the possibility that a portion of the operating frequency band signal in the high-frequency signal Sout transmitted at node N1 is consumed by the resistor R1 of the first circuit 10, thereby increasing the losses of the high-frequency circuits 100 and 101. Thus, the switch SW1 can be turned on or off depending on the intended use of the high-frequency circuits 100 and 101.

[0062] Alternatively, as in the high-frequency circuit 100 of the first embodiment, switch SW1 can be connected between node N1 and the first circuit 10. This allows the second circuit 11 to be completely separated from the first circuit 10 by disconnecting switch SW1.

[0063] Alternatively, as in the high-frequency circuit 101 of the second embodiment, the switch SW1 can be connected between the first circuit 10 and the reference potential terminal. This allows for the easy generation of the control signal voltage for the switch SW1, as described later.

[0064] As in the first and second embodiments, the second circuit 11 reduces the flow of signals with frequencies within the operating frequency band in the high-frequency signal Sout to the first circuit 10. This reduces the leakage of high-frequency signals within the operating frequency band from node N1 to the first circuit 10. Consequently, losses in the high-frequency circuits 100 and 101 can be reduced.

[0065] (Example 1 of the first implementation method) Example 1 of the first embodiment is an example in which switch SW1 is connected between the first circuit 10 and the second circuit 11 and a low-pass matching circuit is used as the matching circuit 12.

[0066] Figure 3 This is a circuit diagram of the high-frequency circuit in Example 1 of the first embodiment. For example... Figure 3 As shown, the first circuit 10 includes capacitor C1, capacitor C2, and resistor R1. Capacitor C2 is shunt connected to node N3 between resistor R1 and transistor Q2.

[0067] Switch SW1 has transistor Q2 (the second transistor). Transistor Q2 is, for example, a FET. Transistor Q2 can also be a bipolar transistor other than a FET. The source S (third terminal) of transistor Q2 is electrically connected to the first circuit 10, and the drain D (fourth terminal) of transistor Q2 is electrically connected to the second circuit 11. The gate G (control terminal) of transistor Q2 is electrically connected to the control signal terminal Tcont. The control signal that turns transistor Q2 on or off ( Figure 1 The control signal Scont is input to the control signal terminal Tcont.

[0068] The second circuit 11 includes an inductor L1. The first terminal of the inductor L1 is electrically connected to node N1, and the second terminal of the inductor L1 is electrically connected to the drain D of transistor Q2. The inductor L1 has high impedance in the operating frequency band.

[0069] Matching circuit 12 is, for example, a low-pass type of a T-type LCL circuit, having inductors L11 and L12 and capacitor C11. Inductors L11 and L12 are connected in series between the drain D of transistor Q1 and the output terminal Tout. Capacitor C11 is shunt connected to node N11 located between inductors L11 and L12.

[0070] Matching circuit 13 is, for example, a T-type LCL circuit, having inductor L21, inductor L22, and capacitor C21. Inductor L21 and inductor L22 are connected in series between the input terminal Tin and the gate G of transistor Q1. Capacitor C21 is shunt connected to node N21 located between inductor L21 and inductor L22. Other configurations are the same as in the first embodiment. Figure 1 Same, explanation omitted.

[0071] In Example 1 of the first embodiment, the first circuit 10 has a node N3 (third node) and a capacitor C2 (second capacitor). Node N3 is located between the resistor R1 and the capacitor C1 and the second circuit 11. The capacitor C2 is connected in parallel with the resistor R1 and the capacitor C1 between node N3 and the reference potential terminal. By making the capacitances of capacitor C1 and capacitor C2 different, the bandwidth of the signal reduced by the first circuit 10 in the high-frequency signal Sout can be widened. The capacitance of capacitor C2 can be set to be less than or equal to 1 / 10 times the capacitance of capacitor C1 or greater than or equal to 10 times the capacitance of capacitor C1, or it can be set to be less than or equal to 1 / 100 times the capacitance of capacitor C1 or greater than or equal to 100 times the capacitance of capacitor C1.

[0072] (Specific example of Example 1 of the first implementation method) A specific example of Example 1 of the first embodiment is an example of providing a high-frequency circuit in the package 15 in the first embodiment. Figure 4 This is a circuit diagram of the high-frequency circuit in Example 1 of the first embodiment. For example... Figure 4 As shown, the first circuit 10 includes inductors L31, L32, and L33. Inductor L31 is connected between node N3 and capacitor C2. Inductor L32 is connected between node N3 and resistor R1. Inductor L33 is connected between resistor R1 and capacitor C1. A drain-source capacitance Cds is connected to the drain D branch of transistor Q1. The drain-source capacitance Cds is equivalent to the source-drain parasitic capacitance of transistor Q1, which is an internal capacitance of transistor Q1, but functions as part of the low-pass matching circuit 12. Other circuit configurations are similar. Figure 3 Same, explanation omitted.

[0073] Figure 5 This is a top view of the high-frequency circuit of Example 1 of the first embodiment. The thickness direction of the substrate 20 is defined as the Z direction, the direction from the input terminal 23 in the frame 21 to the output terminal 22 is defined as the X direction, and the direction orthogonal to the X and Z directions is defined as the Y direction.

[0074] like Figure 5As shown, the high-frequency circuit 103 of Example 1 of the first embodiment includes a package 15, a semiconductor chip 30, a semiconductor chip 36, a capacitive component 31, a capacitive component 32, a capacitive component 33, a capacitive component 34, and a resistive component 35.

[0075] Package 15 has a substrate 20, a frame 21, and a cover (not shown). At least the +Z side of the substrate 20 is conductive. The substrate 20 may be, for example, a copper layer, a molybdenum layer, or a metal plate formed by stacking copper layers. The substrate 20 functions as a reference potential terminal supplied with a reference potential such as ground potential.

[0076] Semiconductor chips 30 and 36, capacitive components 31, 32, 33, and 34, and resistive component 35 are mounted on substrate 20, for example, separated by a conductive bonding layer. A housing 21 is disposed on substrate 20 to surround semiconductor chips 30 and 36, capacitive components 31, 32, 33, 34, and resistive component 35. The housing 21 is, for example, an insulating layer such as ceramic or resin. Input terminals 23, output terminals 22, and control signal terminals 24 are disposed on housing 21. Input terminals 23, output terminals 22, and control signal terminals 24 are, for example, metal layers such as copper or gold. Input terminals 23, output terminals 22, and control signal terminals 24 correspond to input terminal Tin, output terminal Tout, and control signal terminal Tcont, respectively.

[0077] Semiconductor chip 30 includes a semiconductor substrate 30A, electrodes 30B and 30C disposed on the upper surface of the semiconductor substrate 30A, an electrode (not shown) disposed on the lower surface of the semiconductor substrate 30A, and a transistor Q1. Electrodes 30B, 30C, and the electrode on the lower surface of the semiconductor substrate 30A are the gate electrode, drain electrode, and source electrode, respectively, and are electrically connected to the gate (G), drain (D), and source (S) of transistor Q1, respectively. When transistor Q1 is a GaN HEMT, the semiconductor substrate 30A is, for example, a silicon carbide substrate or a sapphire substrate. When transistor Q1 is an LDMOS, the semiconductor substrate 30A is, for example, a silicon substrate. Electrodes 30B and 30C are metal layers such as gold or copper layers.

[0078] Capacitive components 31, 32, 33, and 34 each have a dielectric substrate 31A, a dielectric substrate 32A, a dielectric substrate 33A, and a dielectric substrate 34A, and each has an electrode 31B, an electrode 32B, an electrode 33B, and an electrode under the dielectric substrate. The dielectric substrates 31A, 32A, 33A, and 34A are, for example, an alumina substrate or a barium titanate substrate. The electrodes 31B, 32B, 33B, and 34B are, for example, metal layers such as gold or copper. The dielectric substrate 31A, the electrode 31B disposed therebetween, and the electrode under the dielectric substrate 31A correspond to capacitor C11. The dielectric substrate 32A, the electrode 32B disposed therebetween, and the electrode under the dielectric substrate 32A correspond to capacitor C21. The dielectric substrate 33A, the electrode 33B disposed therebetween, and the electrode under the dielectric substrate 33A correspond to the capacitor C1. The dielectric substrate 34A, the electrode 34B disposed therebetween, and the electrode under the dielectric substrate 34A correspond to the capacitor C2.

[0079] The resistive component 35 includes a substrate 35A, electrodes 35B and 35C, and a resistive element 35D. The substrate 35A is, for example, an insulating substrate such as an alumina substrate or a semiconductor substrate such as a silicon substrate. Electrodes 35B and 35C are metal layers such as gold or copper layers. The resistive element 35D is, for example, a tantalum nitride film. The resistive element 35D forms a resistor R1.

[0080] Figure 6 This is a top view of the semiconductor chip in Example 1 of the first embodiment. (As shown) Figure 6 As shown, the semiconductor chip 36 includes a semiconductor substrate 36A, electrodes 36B, 36C, 36D, and a transistor Q2. Electrodes 36B, 36C, 36D, and transistor Q2 are disposed on the semiconductor substrate 36A. Transistor Q2 has a source electrode 36E, a drain electrode 36F, and a gate electrode 36G. Multiple source electrodes 36E and multiple drain electrodes 36F are alternately disposed. A gate electrode 36G is disposed between one source electrode 36E and one drain electrode 36F. Multiple source electrodes 36E are electrically connected to electrode 36B, multiple drain electrodes 36F are electrically connected to electrode 36C, and multiple gate electrodes 36G are electrically connected to electrode 36D. Transistor Q2 is, for example, a GaN HEMT or other nitride semiconductor transistor, an arsenide semiconductor transistor, or a silicon transistor.

[0081] Return to Figure 5Connection line 41A electrically connects the output terminal Tout to electrode 31B, and connection line 41B electrically connects electrode 31B to electrode 30C. Connection line 42A electrically connects electrode 30B to electrode 32B, and connection line 42B electrically connects electrode 32B to input terminal 23. Connection line 43 electrically connects the output terminal 22 to electrode 36C, connection line 44 electrically connects electrode 36B to electrode 34B, and connection line 45 electrically connects electrode 36B to electrode 35B. Connection line 46 electrically connects electrode 35C to electrode 33B. Connection line 47 electrically connects electrode 36D to control signal terminal 24. Connection lines 41A, 41B, 42A, 42B, 43, 44, 45, 46, and 47 are, for example, fine metal wires such as gold or aluminum wire. Connection lines 41A, 41B, 42A, 42B, 43, 44, 45, and 46 correspond to inductors L12, L11, L22, L21, L1, L31, L32, and L33, respectively.

[0082] Table 1 shows examples of the capacitance values ​​of capacitors C1 and C2 and the resistance values ​​of resistor R1 in the first circuit 10. An example of the inductance of inductor L1 in the second circuit 11 is shown in Table 2. Examples of the inductances of inductors L31, L32, and L33, as well as the capacitances of the drain-source capacitors Cds, are shown in Table 3. Examples of inductors L11 and L12 in matching circuit 12, and capacitor C11 in capacitance are shown in Table 4. Examples of the inductance of inductor L21 and inductor L22 and the capacitance of capacitor C21 in matching circuit 13 are shown in Table 5. (Example 2 of the first implementation) Example 2 of the first embodiment is an example in which switch SW1 is connected between the first circuit 10 and the second circuit 11 and a high-pass matching circuit is used as the matching circuit 12.

[0083] Figure 7 This is a circuit diagram of the high-frequency circuit in Example 2 of the first embodiment. The illustration of the matching circuit 13 is omitted. Figure 7As shown, in the high-frequency circuit 104 of Example 2 of the first embodiment, the second circuit 11 includes an inductor L3 and a capacitor C3. Inductor L3 electrically connects node N1 to node N2, and capacitor C3 electrically connects node N2 to a reference potential terminal. Inductor L2 electrically connects node N1 to the output terminal Tout. Inductor L4 electrically connects node N2 to the drain D of transistor Q2. The second circuit 11, inductor L2, and drain-source capacitor Cds function as a high-pass matching circuit 12. Other configurations are the same as in Example 1 of the first embodiment. Figure 4 Same, explanation omitted.

[0084] Figure 8 This is a top view of the high-frequency circuit in Example 2 of the first embodiment. (As shown) Figure 8 As shown, in the high-frequency circuit 104 of Example 2 of the first embodiment, a capacitive component 38 is provided instead of a capacitive component 31. The capacitive component 38 has a dielectric substrate 38A, an electrode 38B disposed on the dielectric substrate 38A, and an electrode below the dielectric substrate 38A. The materials of the dielectric substrate 38A and the electrode 38B are the same as the material of the capacitive component 31. The dielectric substrate 38A, the electrode 38B disposed therebetween, and the electrode below the dielectric substrate 38A form a capacitor C3.

[0085] Connection lines 48A and 48B are provided instead of connection lines 41A and 41B. Connection line 48A electrically connects electrode 30C to output terminal Tout. Connection line 48B electrically connects electrode 30C to electrode 38B. Connection line 48C is provided instead of connection line 43. Connection line 48C electrically connects electrode 38B to electrode 36C. Connection lines 48A, 48B, and 48C correspond to inductors L2, L3, and L4, respectively. Other configurations are the same as in Example 1 of the first embodiment. Figure 5 Same, explanation omitted.

[0086] Examples of the inductances of inductors L2, L3, and L4, and the capacitance of capacitor C3 in Example 2 of the first embodiment are shown in Table 6. Examples of inductance, capacitance, and resistance values ​​other than those in Table 6 are the same as those in Tables 1 and 3 to 5. Other configurations are the same as those in Example 1 of the first embodiment, and descriptions are omitted. (Example 1 of the second implementation) Example 1 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal and a low-pass matching circuit is used as the matching circuit 12.

[0087] Figure 9 This is a circuit diagram of the high-frequency circuit in Example 1 of the second embodiment. For example... Figure 9 As shown, in the high-frequency circuit 105 of Example 1 of the second embodiment, transistor Q2 is connected between the reference potential terminal and the first circuit 10. The source S and drain D of transistor Q2 are electrically connected to the reference potential terminal and the first circuit 10, respectively. Other configurations are the same as those of Example 1 of the first embodiment. Figure 4 Same, explanation omitted.

[0088] Figure 10 This is a top view of the high-frequency circuit of Example 1 in the second embodiment. For example... Figure 10 As shown, in the high-frequency circuit 105 of Example 1 of the second embodiment, bonding wires 43 and 44 are electrically connected to the electrode 35B of the resistor component 35.

[0089] The capacitive component 33 includes a dielectric substrate 33A, electrodes 33B and 33C, and a discrete chip capacitor 33D. Electrodes 33B and 33C are disposed on the dielectric substrate 33A. The chip capacitor 33D is mounted on electrodes 33B and 33C. The chip capacitor 33D corresponds to capacitor C1.

[0090] Semiconductor chip 36 has electrodes 36C, 36D, and an electrode (not shown) disposed under semiconductor substrate 36A. Electrodes 36C, 36D, and the electrode under semiconductor substrate 36A are electrically connected to the drain D, gate G, and source S of transistor Q2, respectively.

[0091] Examples of inductor, capacitor, and resistor values ​​are the same as in Tables 1 to 5. Other configurations are the same as in Example 1 of the first embodiment, and descriptions are omitted.

[0092] (simulation) In Example 1 of the second embodiment, the throughput characteristics of the first circuit 10 were simulated by turning transistor Q2 on and off. Table 7 shows the capacitances of capacitors C1 and C2, the resistance of resistor R1, and the voltage of transistor Q2. Vgs (on) represents the gate-source voltage of transistor Q2 when switch SW1 is on. Vgs (off) represents the gate-source voltage of transistor Q2 when switch SW1 is off. Figure 11 This is a graph showing S21 relative to frequency when the switch is turned on and off in Example 1 of the second embodiment. The vertical axis represents the absolute value of S21 when the inductor L1 side of the first circuit 10 is set as port 1 and the reference potential terminal is set as port 2. Figure 11As shown, when switch SW1 is turned on, the frequency of S21, which is less than or equal to 1 GHz, decreases compared to when switch SW1 is turned off. Thus, it can be seen that when switch SW1 is turned on, the first circuit 10 allows low-frequency signals (especially those below 500 MHz, which is equivalent to the width of the operating frequency band) to pass through.

[0093] (Example 2 of the second implementation) Example 2 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal and a high-pass matching circuit is used as the matching circuit 12.

[0094] Figure 12 This is a circuit diagram of the high-frequency circuit in Example 2 of the second embodiment. For example... Figure 12 As shown, in the high-frequency circuit 106 of Example 2 of the second embodiment, transistor Q2 is connected between the reference potential terminal and the first circuit 10. The source S and drain D of transistor Q2 are electrically connected to the reference potential terminal and the first circuit 10, respectively. Other configurations are the same as those of Example 2 of the first embodiment. Figure 7 Same, explanation omitted.

[0095] Figure 13 This is a top view of the high-frequency circuit in Example 2 of the second embodiment. (As shown) Figure 13 As shown, in the high-frequency circuit 106 of Example 2 of the second embodiment, bonding wires 48C and 44 are electrically connected to the electrode 35B of the resistive component 35. The capacitive component 33 and the semiconductor chip 36 are connected to the same circuit as in Example 1 of the second embodiment. Figure 10 The capacitive component 33 and the semiconductor chip 36 have the same configuration. Examples of inductor, capacitor, and resistor values ​​are the same as in Tables 1 and 3 to 6 of Example 1 of the first embodiment. Other configurations are the same as in Example 2 of the first embodiment, and descriptions are omitted.

[0096] (Regarding Examples 1 and 2 in the first and second embodiments) In Example 1 of the first embodiment and Example 1 of the second embodiment, the matching circuit 12 is a low-pass type. In this case, the second circuit 11 has an inductor L1 connected in series with the first circuit 10 and the switch SW1 between node N1 and the reference potential terminal. A control signal to turn on the transistor Q2 is applied to the control signal terminal Tcont to turn on the switch SW1. At this time, the inductor L1 becomes a high impedance in the operating frequency band (e.g., above 1 GHz). As a result, the flow of the high-frequency signal Sout in the operating frequency band flowing at node N1 to the first circuit 10 is reduced. On the other hand, the capacitor C1 allows the low-frequency signal flowing at node N1 to pass through the inductor L1 and the first circuit 10 to the reference potential terminal. As a result, the low-frequency signal transmitted at node N1 can be reduced, and the leakage of the high-frequency signal with the operating frequency band transmitted at node N1 to the first circuit 10 can be reduced, thereby reducing the loss of the high-frequency circuit.

[0097] Let the center frequency of the operating frequency band be f0, and let the frequency corresponding to the width of the operating frequency band be Δf. Let the inductance of inductor L1 be L1, and the capacitance of capacitor C1 be C1. At this time, the absolute value of the impedance ZL of inductor L1 at the center frequency f0 is (2π・f0・L1). The absolute value of the impedance ZC of capacitor C1 at the frequency Δf is (1 / (2π・Δf・C1)). Inductor L1 does not allow high-frequency signals of the operating frequency band to pass through, while the first circuit 10 allows signals at frequency Δf to pass through; therefore, ZL is greater than ZC. ZL can be greater than or equal to 10dB of ZC, or it can be greater than or equal to 20dB of ZC.

[0098] In Example 2 of the first embodiment and Example 2 of the second embodiment, a high-pass matching circuit 12 is used. In the matching circuit 12, node N1 becomes a reference potential, such as ground potential, at any frequency within the operating frequency band. Here, switch SW1 and the first circuit 10 are connected between node N2 and the reference potential terminal. That is, the second circuit 11 has a node N2 (second node) located between node N1 and the first circuit 10, which becomes a reference potential at any frequency within the operating frequency band. As a result, the flow of high-frequency signals with frequencies within the operating frequency band transmitted at node N1 to the first circuit 10 can be reduced.

[0099] Alternatively, node N2 can become the reference potential at the center frequency f0 of the operating frequency band. This reduces the leakage of the signal at the center frequency f0 to the reference potential terminal via the first circuit 10.

[0100] In Examples 1 and 2 of the first embodiment, the bias voltage of node N1 is the drain bias voltage. When the high-frequency circuits 103 and 104 are high-output amplifier circuits, the drain bias voltage is, for example, greater than or equal to 50V. To turn transistor Q2 on and off, the gate voltage of transistor Q2 is made to be near the threshold voltage relative to the source voltage of transistor Q2. Therefore, the control signal supplied to the control signal terminal Tcont is approximately 50V. When the drain bias voltage is used to generate the control signal, the on / off state of transistor Q2 affects the drain bias voltage.

[0101] In contrast, in Examples 1 and 2 of the second embodiment, transistor Q2 is DC-disconnected from node N1 via capacitor C1. Therefore, the drain bias voltage is not affected; only a voltage to turn transistor Q2 on and off needs to be applied to the control signal terminal Tcont as a control signal. The control signal voltage can, for example, be in the range of -10V to +10V. Furthermore, the impact of transistor Q2's on / off state on the drain bias voltage can be reduced.

[0102] In Examples 1 and 2 of the first and second embodiments, the absolute value ZC of the impedance of capacitor C1 at a frequency Δf, which is equivalent to the width of the operating frequency band, can be set to less than or equal to 10Ω, less than or equal to 5Ω, or less than or equal to 1Ω. This reduces the signal flowing at frequency Δf at node N1. Therefore, distortion compensation based on DPD can be performed.

[0103] (Example 3 of the second implementation) Example 3 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal, a low-pass matching circuit is used as the matching circuit 12, and transistor Q2 and resistor R1 are located on the same semiconductor chip.

[0104] Figure 14 This is a circuit diagram of the high-frequency circuit in Example 3 of the second embodiment. For example... Figure 14 As shown, in the high-frequency circuit 107 of Example 3 of the second embodiment, a capacitor C1, an inductor L33, and a resistor R1 are connected in series from node N3 between node N3 and the drain D of transistor Q2. Transistor Q2 and resistor R1 are formed on semiconductor chip 36.

[0105] Figure 15 This is a top view of the high-frequency circuit in Example 3 of the second embodiment. (As shown) Figure 15 As shown, the high-frequency circuit 107 of Example 3 in the second embodiment does not include the resistor component 35. The capacitive component 33 has the same configuration as the capacitive component 33 in Example 1 of the second embodiment. The semiconductor chip 36 includes an electrode 35C, an electrode 36D, a transistor Q2, and a resistor R1.

[0106] Connection wires 43 and 44 are electrically connected to electrode 33C of capacitive component 33. Connection wire 46 electrically connects electrode 33B and electrode 35C. Examples of inductance, capacitance, and resistance values ​​are the same as in Tables 1 to 5. Other configurations are the same as in Example 1 of the second embodiment, and descriptions are omitted.

[0107] Figure 16 This is a top view of the semiconductor chip in Example 3 of the second embodiment. (Example:) Figure 16 As shown, an electrode 35C and a resistor 35D are provided on a semiconductor substrate 36A. The resistor 35D, forming resistor R1, is connected between electrodes 36C and 36B. Thus, resistor R1 and transistor Q2 are connected in series between electrodes 35C and 36B. Electrode 36B is electrically connected to the substrate 20 through a via or bonding wire penetrating the semiconductor substrate 36A, thereby being short-circuited. Other configurations are similar to those in Example 1 of the first embodiment. Figure 6 same.

[0108] (Example 4 of the second implementation) Example 4 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal, a high-pass matching circuit is used as the matching circuit 12, and transistor Q2 and resistor R1 are located on the same semiconductor chip.

[0109] Figure 17 This is a circuit diagram of the high-frequency circuit in Example 4 of the second embodiment. For example... Figure 17 As shown, in the high-frequency circuit 108 of Example 4 of the second embodiment, a capacitor C1, an inductor L33, and a resistor R1 are connected in series from node N3 between node N3 and the drain D of transistor Q2. Transistor Q2 and resistor R1 are formed on semiconductor chip 36.

[0110] Figure 18 This is a top view of the high-frequency circuit in Example 4 of the second embodiment. (As shown) Figure 18 As shown, the resistor 35 is not provided in the high-frequency circuit 108 of Example 4 of the second embodiment. The capacitive component 33 and the semiconductor chip 36 have the same configuration as those in Example 3 of the second embodiment. Bonding lines 48C and 44 are electrically connected to the electrode 33C of the capacitive component 33. Examples of inductance, capacitance, and resistance values ​​are the same as in Tables 1 and 3 to 6. Other configurations are the same as in Examples 2 and 3 of the second embodiment, and descriptions are omitted.

[0111] In Examples 3 and 4 of the second embodiment, miniaturization can be achieved by placing the transistor Q2 and resistor R1 on the semiconductor chip 36. Furthermore, when the transistor Q2 is a GaN HEMT, the semiconductor substrate 36A is a substrate with high thermal conductivity, such as a silicon carbide substrate. Therefore, heat dissipation from the resistor R1 can be improved.

[0112] (Example 5 of the second implementation) Example 5 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal, a low-pass matching circuit is used as the matching circuit 12, and transistor Q2, resistor R1 and capacitor C1 are located on the same semiconductor chip.

[0113] Figure 19 This is a top view of the high-frequency circuit in Example 5 of the second embodiment. For example... Figure 19 As shown, in the high-frequency circuit 109 of Example 5 of the second embodiment, the resistor 35 and the capacitor 33 are not provided. The semiconductor chip 36 has an electrode 33C, an electrode 36D, a transistor Q2, a resistor R1, and a capacitor C1.

[0114] Bonding wires 43 and 44 are electrically connected to electrodes 33C of the semiconductor chip 36. Examples of inductance, capacitance, and resistance values ​​are the same as in Tables 1 to 5. Other configurations are the same as in Example 1 of the second embodiment, and descriptions are omitted.

[0115] Figure 20 This is a top view of the semiconductor chip in Example 5 of the second embodiment. (As shown) Figure 20 As shown, an electrode 33C and a capacitor 33E are provided on a semiconductor substrate 36A. A resistor R1 and a capacitor 33E are connected in series between electrodes 36C and 33B. Thus, capacitor C1, resistor R1, and transistor Q2 are connected in series between electrodes 33C and 36B. Other configurations are the same as in Example 3 of the second embodiment. Figure 16 same.

[0116] (Example 6 of the second embodiment) Example 6 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal, a high-pass matching circuit is used as the matching circuit 12, and transistor Q2, resistor R1 and capacitor C1 are located on the same semiconductor chip.

[0117] Figure 21 This is a top view of the high-frequency circuit in Example 6 of the second embodiment. (As shown) Figure 21As shown, in the high-frequency circuit 110 of Example 6 of the second embodiment, the resistor component 35 and the capacitor component 33 are not provided. The semiconductor chip 36 is the same as the semiconductor chip 36 of Example 5 of the second embodiment. Bonding lines 48C and 44 are electrically connected to the electrodes 33C of the semiconductor chip 36. Examples of inductance, capacitance, and resistance values ​​are the same as in Tables 1 and 3 to 6. Other configurations are the same as in Examples 2 and 5 of the second embodiment, and descriptions are omitted.

[0118] In Examples 5 and 6 of the second embodiment, miniaturization can be achieved by incorporating transistor Q2, resistor R1, and capacitor C1 onto semiconductor chip 36. Furthermore, when transistor Q2 is a GaN HEMT, the semiconductor substrate 36A is a substrate with high thermal conductivity, such as a silicon carbide substrate. Therefore, heat dissipation from resistor R1 can be improved.

[0119] Alternatively, as in Examples 3 to 6 of the second embodiment, at least one of the resistor R1, capacitor C1, and capacitor C2 can be integrated into the semiconductor chip 36. Alternatively, at least two of the resistor R1, capacitor C1, and capacitor C2 can be integrated into a chip different from the semiconductor chip 36.

[0120] (Example 7 of the second embodiment) Example 7 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal, a low-pass matching circuit is used as the matching circuit 12, and transistors Q1, Q2 and resistor R1 are located on the same semiconductor chip.

[0121] Figure 22 This is a top view of the high-frequency circuit in Example 7 of the second embodiment. (As shown) Figure 22 As shown, in the high-frequency circuit 111 of Example 7 of the second embodiment, the resistor component 35 and the semiconductor chip 36 are not provided. The semiconductor chip 30 has an electrode 35C, an electrode 36D, a transistor Q2, and a resistor R1. A bonding wire 46 is electrically connected to the electrode 35C of the semiconductor chip 30. Examples of inductance, capacitance, and resistance values ​​are the same as in Tables 1 to 5. Other configurations are the same as in Example 1 of the second embodiment, and descriptions are omitted.

[0122] Figure 23 This is a top view of the semiconductor chip in Example 7 of the second embodiment. (As shown) Figure 23As shown, electrodes 30B and 30C, and a transistor Q1 are provided on a semiconductor substrate 30A. The transistor Q1 has a source electrode 30E, a drain electrode 30F, and a gate electrode 30G. Multiple source electrodes 30E and multiple drain electrodes 30F are alternately arranged. A gate electrode 30G is provided between one source electrode 30E and one drain electrode 30F. Multiple drain electrodes 30F are commonly electrically connected to electrode 30C, and multiple gate electrodes 30G are commonly electrically connected to electrode 30B. Multiple source electrodes 30E are short-circuited by being electrically connected to the substrate 20 via vias penetrating the semiconductor substrate 30A. Other configurations are similar to Example 3 of the second embodiment. Figure 16 same.

[0123] (Example 8 of the second embodiment) Example 8 of the second embodiment is an example in which switch SW1 is connected between the first circuit 10 and the reference potential terminal, a high-pass matching circuit is used as the matching circuit 12, and transistors Q1, Q2 and resistors are located on the same semiconductor chip.

[0124] Figure 24 This is a top view of the high-frequency circuit in Example 8 of the second embodiment. (As shown) Figure 24 As shown, in the high-frequency circuit 112 of Example 8 of the second embodiment, the resistor component 35 and the semiconductor chip 36 are not provided. The semiconductor chip 30 is the same as the semiconductor chip 30 of Example 7 of the second embodiment. The bonding wire 46 is electrically connected to the electrode 35C of the semiconductor chip 30. The examples of inductance, capacitance, and resistance values ​​are the same as those in Tables 1 and 3 to 6. Other configurations are the same as those in Examples 2 and 7 of the second embodiment, and descriptions are omitted.

[0125] In Examples 7 and 8 of the second embodiment, miniaturization can be achieved by incorporating transistors Q1 and Q2 and resistor R1 onto the semiconductor chip 30. Furthermore, when transistor Q1 is a GaN HEMT, the semiconductor substrate 30A is a substrate with high thermal conductivity, such as a silicon carbide substrate. Therefore, heat dissipation from resistor R1 can be improved.

[0126] Alternatively, as in Examples 3 to 8 of the second embodiment, transistor Q2 and at least one of transistor Q1, resistor R1, and capacitor C1 can be integrated into the semiconductor chip. This enables miniaturization.

[0127] As in Examples 1 and 2 of the first embodiment and Examples 1 to 8 of the second embodiment, for example, refer to Figure 5The high-frequency circuit includes a substrate 20, a transistor Q1, an output terminal 22 (lead), a transistor Q2 (switch), a resistor R1, and a capacitor C1. Transistors Q1 and Q2, resistor R1, and capacitor C1 are disposed on the substrate 20. The output terminal 22 is electrically connected to transistor Q1. The electrode 36C of transistor Q2 (the first terminal of the switch) is electrically connected to the output terminal 22. At least one of resistor R1 and capacitor C1 is electrically connected to electrode 36B of transistor Q2 (the second terminal of the switch). Thus, the output terminal 22 can be disconnected from and connected to a first circuit 10 including at least one of resistor R1 or capacitor C1.

[0128] Furthermore, at least the upper surface of the substrate 20 is conductive. The output terminal 22 is electrically connected to the electrode 30C (second terminal) of transistor Q1. The electrode 35B (first terminal) of resistor R1 is electrically connected to the electrode 36B (second terminal of the switch) of transistor Q2. Capacitor C1 has a first electrode in which a dielectric substrate 33A is disposed. Figure 4 The first electrode is electrically connected to the base 20, and the second electrode is electrically connected to the second end of the resistor R1. Thus, the output terminal 22 can be disconnected from and connected to the first circuit 10, which includes the resistor R1 and the capacitor C1.

[0129] It should be considered that the embodiments disclosed herein are illustrative in all respects and are not restrictive. The scope of this disclosure is not indicated by the foregoing meaning, but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A high-frequency circuit, comprising: Output terminals; The first transistor has a first terminal, a second terminal, and a control terminal; The first circuit has a resistor and a first capacitor, wherein... The resistor and the first capacitor are connected in series between the first node and the reference potential terminal. The first node is located between the second terminal and the output terminal. The reference potential terminal is supplied with a reference potential. The first circuit allows a signal in the high-frequency signal transmitted at the first node that is lower than the operating frequency band to pass to the reference potential terminal. as well as The switch will disconnect and connect the first node and the reference potential terminal through the path of the first circuit.

2. The high-frequency circuit according to claim 1, wherein, The switch is connected between the first circuit and the reference potential terminal.

3. The high-frequency circuit according to claim 1, wherein, The switch is connected between the first node and the first circuit.

4. The high-frequency circuit according to any one of claims 1 to 3, comprising: The second circuit reduces the flow of signals with frequencies within the operating frequency band from the high-frequency signal to the first circuit.

5. The high-frequency circuit according to claim 4, wherein, The second circuit has an inductor connected in series with the first circuit and the switch between the first node and the reference potential terminal.

6. The high-frequency circuit according to claim 4, wherein, The second circuit has a second node located between the first node and the first circuit, which serves as a reference potential at any frequency within the operating frequency band.

7. The high-frequency circuit according to any one of claims 1 to 3, wherein, The first circuit has a second capacitor connected in parallel with the resistor and the first capacitor between the third node and the reference potential terminal, wherein the third node is located between the resistor and the first capacitor and the first node.

8. The high-frequency circuit according to any one of claims 1 to 3, wherein, The switch is a second transistor, which has a third terminal, a fourth terminal, and a control terminal, wherein the third terminal and the fourth terminal are located on the path.

9. The high-frequency circuit according to any one of claims 1 to 3, wherein, The absolute value of the impedance of the first capacitor at a frequency comparable to the width of the operating frequency band is less than or equal to 10Ω.

10. The high-frequency circuit according to claim 8, comprising: A substrate, at least its upper surface, is conductive; the substrate is the reference potential terminal; and A semiconductor chip, mounted on the substrate, wherein the semiconductor chip is formed by integrating at least one of the first transistor, the resistor, and the first capacitor, and the second transistor.

11. A high-frequency circuit, comprising: Base; A transistor is disposed on the substrate; Lead wires are electrically connected to the transistor; A switch is disposed on the substrate, and the first end of the switch is electrically connected to the lead wire; as well as At least one of a resistor or a capacitor is disposed on the substrate and electrically connected to the second terminal of the switch.

12. The high-frequency circuit according to claim 11, wherein, At least the upper surface of the substrate is conductive. The transistor has a first terminal, a second terminal, and a first control terminal. The lead is electrically connected to the second terminal of the transistor. The first end of the resistor is electrically connected to the second end of the switch. The capacitor has a first electrode and a second electrode in which a dielectric substrate is disposed, the first electrode being electrically connected to the substrate and the second electrode being electrically connected to a second end of the resistor.

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