Stacked electronic device

Abstract

The electronic device includes a first inductor, a second inductor, and a third inductor. Multiple conductors of the first, second, and third inductors are configured to satisfy at least one of a first condition and a second condition. The first condition is that the orientations of the first and second conductors, and the orientations of the fifth and sixth conductors, are different from the orientations of the third and fourth conductors. The second condition is that the third conductor is positioned in a specific direction at a location different from at least one of the first and fifth conductors, and the fourth conductor is positioned in a specific direction at a location different from at least one of the second and sixth conductors.

Description

Technical Field

[0001] This disclosure relates to a stacked electronic device having a filter comprising multiple inductors. Background Technology

[0002] One type of electronic device used in small mobile communication devices is the bandpass filter. A bandpass filter can be constructed, for example, by connecting a high-pass filter and a low-pass filter in series, wherein the high-pass filter forms an attenuation electrode on the low-frequency side of the passband of the bandpass filter, and the low-pass filter forms an attenuation electrode on the high-frequency side of the passband of the bandpass filter.

[0003] In recent years, the market has demanded miniaturization and space-saving design of small mobile communication devices, which in turn requires miniaturization of the bandpass filters used in these devices. As a suitable bandpass filter for miniaturization, a stacked bandpass filter is known, comprising multiple stacked dielectric layers and multiple conductor layers.

[0004] International Publication No. 2008 / 143071 discloses a stacked bandpass filter, which comprises multiple LC parallel resonators coupled to each other by multiple capacitor electrodes and multiple inductor electrodes. When viewing the loop formed by one inductor electrode and the loop formed by another inductor electrode of the adjacent LC parallel resonators from the arrangement direction of the inductor electrodes, these loops at least partially overlap. The inductors formed by these inductor electrodes are inductively coupled.

[0005] As described in International Publication No. 2008 / 143071, in stacked electronic devices that consist of multiple inductors electromagnetically coupled, miniaturization of the stacked electronic device sometimes results in excessively strong electromagnetic coupling between the multiple inductors. Consequently, the desired characteristics may not be achieved.

[0006] The above problems are not limited to bandpass filters, but also apply to all stacked electronic devices that have filters that include multiple inductors. Summary of the Invention

[0007] (a) Technical problems to be solved One of the objectives of this disclosure is to provide a stacked electronic device that can achieve miniaturization while realizing the desired characteristics.

[0008] (II) Technical Solution A stacked electronic device according to one embodiment of this disclosure includes: a filter comprising a first inductor, a second inductor, and a third inductor; at least one ground terminal connected to a grounding element; and a stack comprising a plurality of stacked dielectric layers for integrating the filter and the at least one ground terminal. The first, second, and third inductors are electrically connected to the at least one ground terminal. When viewed from the stacking direction of the plurality of dielectric layers, the second inductor is disposed between the first and third inductors. The first inductor includes: a first conductor and a second conductor extending in directions parallel to the stacking direction; and a first conductor layer connected to one end of the first conductor and one end of the second conductor. The second inductor includes: a third conductor and a fourth conductor extending in directions parallel to the stacking direction; and a second conductor layer connected to one end of the third conductor and one end of the fourth conductor. The third inductor includes: a fifth conductor and a sixth conductor extending in directions parallel to the stacking direction; and a third conductor layer connected to one end of the fifth conductor and one end of the sixth conductor.

[0009] The first conductor, second conductor, third conductor, fourth conductor, fifth conductor, and sixth conductor are configured to satisfy at least one of a first condition and a second condition. The first condition is that the orientations of the first and second conductors, and the orientations of the fifth and sixth conductors, are different from the orientations of the third and fourth conductors. The second condition is that the third conductor is positioned in a specific direction orthogonal to the stacking direction at a position different from at least one of the first and fifth conductors, and the fourth conductor is positioned in a specific direction at a position different from at least one of the second and sixth conductors. The first inductor and the third inductor are configured such that the region sandwiched between the first and second conductors is not opposite to the region sandwiched between the fifth and sixth conductors.

[0010] (III) Beneficial Effects In a stacked electronic device according to one embodiment of this disclosure, the first conductor, second conductor, third conductor, fourth conductor, fifth conductor, and sixth conductor are configured to satisfy at least one of a first condition and a second condition, and the first inductor and third inductor are configured such that the region sandwiched between the first conductor and the second conductor is not opposite to the region sandwiched between the fifth conductor and the sixth conductor. Thus, according to this disclosure, the stacked electronic device can be miniaturized while achieving the desired characteristics.

[0011] Other objects, features and advantages of this disclosure will become fully apparent from the following description. Attached Figure Description

[0012] Figure 1 This is a circuit diagram illustrating an example of the circuit structure of a stacked electronic device according to a first exemplary embodiment of the present disclosure.

[0013] Figure 2 This is a perspective view showing the appearance of a stacked electronic device according to a first exemplary embodiment of the present disclosure.

[0014] Figure 3 This is an explanatory diagram showing the pattern formation surface of the first dielectric layer of the laminate in a first exemplary embodiment of the present disclosure.

[0015] Figure 4 This is an explanatory diagram showing the patterned surface of the second dielectric layer of the laminate in a first exemplary embodiment of the present disclosure.

[0016] Figure 5 This is an explanatory diagram showing the pattern formation surface of the third dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0017] Figure 6 This is an explanatory diagram showing the pattern formation surface of the fourth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0018] Figure 7 This is an explanatory diagram showing the pattern formation surface of the fifth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0019] Figure 8 This is an explanatory diagram showing the pattern formation surface of the sixth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0020] Figure 9 This is an explanatory diagram showing the pattern formation surface of the seventh dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0021] Figure 10 This is an explanatory diagram showing the pattern formation surface of the eighth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0022] Figure 11 This is an explanatory diagram showing the pattern formation surface of the ninth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0023] Figure 12 This is an explanatory diagram showing the pattern formation surface of the tenth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0024] Figure 13 This is an explanatory diagram showing the pattern formation surfaces of the eleventh to sixteenth dielectric layers of a laminate in a first exemplary embodiment of the present disclosure.

[0025] Figure 14This is an explanatory diagram showing the pattern formation surface of the seventeenth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0026] Figure 15 This is an explanatory diagram showing the side opposite to the patterning surface of the eighteenth dielectric layer of the laminate in the first exemplary embodiment of this disclosure.

[0027] Figure 16 This is a perspective view showing the interior of a laminate in a first exemplary embodiment of the present disclosure.

[0028] Figure 17 This is a perspective view showing a portion of the interior of a laminate in a first exemplary embodiment of the present disclosure.

[0029] Figure 18 This is a three-dimensional view showing the interior of the stack of the stacked electronic device of the first comparative example.

[0030] Figure 19 This is a three-dimensional view showing the interior of the stacked electronic device of the second comparative example.

[0031] Figure 20 This is a three-dimensional view showing the interior of the stacked electronic device of the third comparative example.

[0032] Figure 21 This is a characteristic plot showing the pass-through attenuation characteristics of the filter for the first comparative example model.

[0033] Figure 22 This is a characteristic plot showing the pass-through attenuation characteristics of the filter in the second comparative example model.

[0034] Figure 23 This is a characteristic plot showing the pass-through attenuation characteristics of the filter in the third comparative example model.

[0035] Figure 24 This is a characteristic diagram illustrating the pass-through attenuation characteristics of the filter in the model of the embodiment.

[0036] Figure 25 This is a perspective view showing the interior of a laminate in a second exemplary embodiment of the present disclosure.

[0037] Figure 26 This is a characteristic diagram illustrating an example of the pass-through attenuation characteristics of a filter of a stacked electronic device according to a second exemplary embodiment of the present disclosure.

[0038] Figure 27 This is a perspective view showing the interior of a laminate in a third exemplary embodiment of this disclosure.

[0039] Figure 28This is a characteristic diagram illustrating an example of the pass-through attenuation characteristics of a filter of a stacked electronic device according to a third exemplary embodiment of the present disclosure. Detailed Implementation

[0040] [First Exemplary Implementation] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. First, referring to... Figure 1 The structure of the stacked electronic device (hereinafter simply referred to as electronic device) 1 according to the first exemplary embodiment of the present disclosure will be described. Figure 1 This is a circuit diagram illustrating an exemplary embodiment of electronic device 1. Furthermore, in the following description, the term "in circuit structure" refers to the configuration on the circuit diagram, not the configuration in the physical structure.

[0041] The electronic device 1 in the exemplary embodiment includes a first signal terminal 2, a second signal terminal 3, and a filter 1A disposed between the first signal terminal 2 and the second signal terminal 3 in the circuit structure. The first signal terminal 2 and the second signal terminal 3 are terminals for signal input or output, respectively. That is, when a signal is input to the first signal terminal 2, a signal is output from the second signal terminal 3. When a signal is input to the second signal terminal 3, a signal is output from the first signal terminal 2.

[0042] Filter 1A includes inductors L1, L2, and L3. Inductor L1 corresponds to the "first inductor" in this disclosure. Inductor L2 corresponds to the "second inductor" in this disclosure. Inductor L3 corresponds to the "third inductor" in this disclosure.

[0043] Filter 1A includes a first filter 10, which includes inductors L1 to L3. Filter 1A also includes a second filter 20, which is disposed between the first signal terminal 2 and the first filter 10 in the circuit structure; and a third filter 30, which is disposed between the second signal terminal 3 and the first filter 10 in the circuit structure.

[0044] Filter 1A can be a bandpass filter composed of first to third filters 10, 20, and 30. First filter 10 can be a high-pass filter configured to selectively allow signals with frequencies higher than a specific frequency to pass through. Inductors L1 to L3 can be positioned between the path from the first signal terminal 2 to the second signal terminal 3 and the grounding element in the circuit structure. Second filter 20 and third filter 30 can each be a low-pass filter configured to selectively allow signals with frequencies lower than a specific frequency to pass through.

[0045] Below, refer to Figure 1 Taking the case where filter 1A is a bandpass filter as an example, an example of the circuit structure of electronic device 1 will be explained.

[0046] The first filter 10 includes inductors L1 to L3. The first filter 10 also includes capacitors C11, C12, C13, C14, C15, C16, C17, C18, C19, and C20. Figure 1 In the example shown, the first filter 10 is a high-pass filter.

[0047] The second filter 20 includes an inductor L21 and capacitors C21, C22, and C23. Figure 1 In the example shown, the second filter 20 is a low-pass filter.

[0048] The third filter 30 includes an inductor L31 and capacitors C31, C32, and C33. Figure 1 In the example shown, the third filter 30 is a low-pass filter.

[0049] One end of inductor L21 of the second filter 20 is connected to the first signal terminal 2. Capacitor C21 is connected in parallel with inductor L21. One end of capacitor C22 is connected to one end of inductor L21. One end of capacitor C23 is connected to the other end of inductor L21. The other ends of capacitors C22 and C23 are connected to ground.

[0050] One end of capacitor C11 in the first filter 10 is connected to the other end of inductor L21 in the second filter 20. One end of capacitor C12 is connected to the other end of capacitor C11. One end of capacitor C13 is connected to the other end of capacitor C12. One end of capacitor C14 is connected to the other end of capacitor C13.

[0051] One end of capacitor C15 is connected to the junction of capacitors C11 and C12. One end of inductor L1 is connected to the other end of capacitor C15. The other end of inductor L1 is connected to ground. Capacitor C16 is connected in parallel with inductor L1.

[0052] One end of capacitor C17 is connected to the junction of capacitors C12 and C13. One end of inductor L2 is connected to the other end of capacitor C17. The other end of inductor L2 is connected to ground. Capacitor C18 is connected in parallel with inductor L2.

[0053] One end of capacitor C19 is connected to the junction of capacitors C13 and C14. The other end of inductor L3 is connected to ground. One end of inductor L3 is connected to the other end of capacitor C19. Capacitor C20 is connected in parallel with inductor L3.

[0054] One end of inductor L31 of the third filter 30 is connected to the other end of capacitor C14 of the first filter 10. The other end of inductor L31 is connected to the second signal terminal 3. Capacitor C31 is connected in parallel with respect to inductor L31. One end of capacitor C32 is connected to one end of inductor L31. One end of capacitor C33 is connected to the other end of inductor L31.

[0055] An inductive component can be generated between the other end of inductors L1~L3 and capacitors C22, C23, C32, and C33 and the grounding component. Figure 1 In the figure, reference numeral L11 indicates the aforementioned inductive component.

[0056] Next, refer to Figure 2 The other structures of electronic device 1 will be described. Figure 2 This is a three-dimensional diagram representing electronic device 1.

[0057] The electronic device 1 also includes: at least one ground terminal connected to a grounding element; and a laminate 50 for integrating the filter 1A and the at least one ground terminal. The laminate 50 includes multiple stacked dielectric layers and multiple conductors (multiple conductor layers and multiple vias). For example, low-temperature co-fired ceramic (LTCC) is used as the dielectric material.

[0058] The laminate 50 has: a bottom surface 50A and a top surface 50B located at both ends of the stacking direction T of the plurality of dielectric layers; and four sides 50C to 50F connecting the bottom surface 50A and the top surface 50B. Sides 50C and 50D face opposite sides to each other, and sides 50E and 50F also face opposite sides to each other. Sides 50C to 50F are perpendicular to the bottom surface 50A and the top surface 50B.

[0059] Here, as Figure 2 As shown, the X, Y, and Z directions are defined. The X, Y, and Z directions are orthogonal to each other. In an exemplary embodiment, a direction parallel to the stacking direction T is designated as the Z direction. Furthermore, a direction opposite to the X direction is designated as the -X direction, a direction opposite to the Y direction as the -Y direction, and a direction opposite to the Z direction as the -Z direction. Additionally, the phrase "when viewed from a specific direction (e.g., the stacking direction T)" means observing the object from a separate position along a specific direction or a direction parallel to the specific direction. Furthermore, regarding the constituent elements of electronic device 1, the shape observed from the Z direction is referred to as the "planar shape."

[0060] like Figure 2As shown, bottom surface 50A is located at the end of laminate 50 in the -Z direction. Top surface 50B is located at the end of laminate 50 in the Z direction. Side surface 50C is located at the end of laminate 50 in the -X direction. Side surface 50D is located at the end of laminate 50 in the X direction. Side surface 50E is located at the end of laminate 50 in the -Y direction. Side surface 50F is located at the end of laminate 50 in the Y direction.

[0061] The laminate 50 also includes a plurality of electrodes 111, 112, and 113 disposed on the bottom surface 50A of the laminate 50. The electrodes 111, 112, and 113 are arranged in this order in the X direction.

[0062] Electrode 111 corresponds to the first signal terminal 2. Electrode 113 corresponds to the second signal terminal 3. Electrode 112 is connected to a grounding component. That is, electrode 112 corresponds to at least one grounding terminal. In an exemplary embodiment, at least one grounding terminal is a single grounding terminal. The first signal terminal 2, the second signal terminal 3, and the grounding terminal are disposed on the bottom surface 50A of the laminate 50.

[0063] Next, refer to Figures 3 to 15 An example of the plurality of dielectric layers, plurality of conductor layers, and plurality of vias constituting the laminate 50 will be described. In this example, the laminate 50 includes eighteen dielectric layers stacked together. Hereinafter, these eighteen dielectric layers will be referred to as the first layer to the eighteenth layer from bottom to top. In addition, the first layer to the eighteenth layer will be indicated by reference numerals 51 to 68 in the accompanying drawings.

[0064] exist Figures 3 to 13 In the diagram, multiple circles (a single circle and the inner circle of two double-drawn circles) represent multiple vias. Multiple vias are formed on each of the dielectric layers 51-66. Each via is formed by filling the hole with conductive paste. Figures 3 to 15 In the diagram, the shapes other than the multiple circles representing multiple vias represent multiple dielectric layers, multiple conductor layers, and multiple electrodes. The multiple vias are connected to the electrodes, conductor layers, or other vias, respectively.

[0065] exist Figures 3 to 13 In this drawing, specific vias are labeled with reference numerals. At least a portion of the specific vias constitutes a plurality of columnar conductors, as described later. The connection relationship between each of the specific vias and the conductor layer or other vias is described for the state in which the first to eighteenth dielectric layers 51 to 68 are stacked. Two vias that are adjacent vertically in the stacking direction T among the plurality of vias labeled with the same reference numerals are interconnected.

[0066] Figure 3This indicates the patterning surface of the first dielectric layer 51. Electrodes 111 to 113 are formed on the patterning surface of the dielectric layer 51.

[0067] Figure 4 This indicates the patterned surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the patterned surface of the dielectric layer 52. Additionally, vias labeled T1a, T3, and T5a are formed on the dielectric layer 52. The vias labeled T1a and T3 are connected to the conductor layer 521. The via labeled T5a is connected to the conductor layer 523.

[0068] Figure 5 This indicates the patterned surface of the third dielectric layer 53. Conductor layers 531, 532, and 533 are formed on the patterned surface of the dielectric layer 53. Additionally, vias marked with reference numeral T1a, T3, and T5a are formed on the dielectric layer 53. The via marked with reference numeral T5a is connected to the conductor layer 532.

[0069] Figure 6 This indicates the patterned surface of the fourth dielectric layer 54. Conductor layers 541, 542, and 543 are formed on the patterned surface of the dielectric layer 54. Additionally, vias labeled T1a, T3, T4, and T5a are formed in the dielectric layer 54. The via labeled T4 is connected to the conductor layer 542.

[0070] Figure 7 This indicates the patterned surface of the fifth dielectric layer 55. Conductor layers 551, 552, and 553 are formed on the patterned surface of the dielectric layer 55. Additionally, vias marked with reference numeral T1a, T1b, T3, T4, T5a, and T5b are formed on the dielectric layer 55. The via marked with reference numeral T1b is connected to conductor layer 551. The via marked with reference numeral T5b is connected to conductor layer 553.

[0071] Figure 8This indicates the patterned surface of the sixth dielectric layer 56. Conductor layers 561, 562, 563, and 564 are formed on the patterned surface of the dielectric layer 56. Additionally, vias labeled T1a, T2a, T3, T4, T5a, and T6a are formed on the dielectric layer 56. The via labeled T2a is connected to conductor layer 561. The via labeled T6a is connected to conductor layer 564.

[0072] Figure 9 This indicates the pattern formation surface of the seventh dielectric layer 57. Through-holes marked with reference numeral T1a, T2a, T3, T4, T5a, and T6a are formed in the dielectric layer 57.

[0073] Figure 10 This indicates the patterned surface of the eighth dielectric layer 58. Conductor layers 581, 582, 583, and 584 are formed on the patterned surface of the dielectric layer 58. Additionally, vias marked with reference numeral T1c, T2b, T3, T4, T5c, and T6b are formed on the dielectric layer 58. The via marked T1c is connected to conductor layer 581. The via marked T2b is connected to conductor layer 582. The via marked T5c is connected to conductor layer 583. The via marked T6b is connected to conductor layer 584.

[0074] Figure 11 This indicates the pattern formation surface of the ninth dielectric layer 59. Through-holes marked with reference numeral T1c, reference numeral T2b, reference numeral T3, reference numeral T4, reference numeral T5c, and reference numeral T6b are formed in the dielectric layer 59.

[0075] Figure 12This indicates the pattern forming surface of the tenth dielectric layer 60. Conductor layers 601 and 602 are formed on the pattern forming surface of the dielectric layer 60. In addition, vias marked with reference numeral T1c, T1d, T2b, T2c, T3, T4, T5c, T5d, T6b, and T6c are formed on the dielectric layer 60.

[0076] The through-hole, labeled T1d, connects to a portion near one end of conductor layer 601 along its length. The through-hole, labeled T2c, connects to a portion near the other end of conductor layer 601 along its length. The through-hole, labeled T5d, connects to a portion near one end of conductor layer 602 along its length. The through-hole, labeled T6c, connects to a portion near the other end of conductor layer 602 along its length.

[0077] Figure 13 This refers to the pattern formation surfaces of the eleventh to sixteenth dielectric layers 61-66. Each of the dielectric layers 61-66 has a through-hole marked with reference numeral T1c, reference numeral T1d, reference numeral T2b, reference numeral T2c, reference numeral T3, reference numeral T4, reference numeral T5c, reference numeral T5d, reference numeral T6b, and reference numeral T6c.

[0078] Figure 14 This indicates the patterning surface of the seventeenth dielectric layer 67. Conductor layers 671, 672, 673, 674, 675, 676, and 677 are formed on the patterning surface of the dielectric layer 67.

[0079] A via formed in dielectric layer 66, marked with reference numeral T1d, connects to a portion near one end of conductor layer 671 along its length. A via formed in dielectric layer 66, marked with reference numeral T2b, connects to a portion near the other end of conductor layer 671 along its length. A via formed in dielectric layer 66, marked with reference numeral T1c, connects to a portion near one end of conductor layer 672 along its length. A via formed in dielectric layer 66, marked with reference numeral T2c, connects to a portion near the other end of conductor layer 672 along its length.

[0080] A via formed in dielectric layer 66, marked with reference numeral T3, is connected to a portion near one end of conductor layer 673 along its length. A via formed in dielectric layer 66, marked with reference numeral T4, is connected to a portion near the other end of conductor layer 673 along its length.

[0081] A via formed in dielectric layer 66, marked with reference numeral T5c, connects to a portion near one end of conductor layer 674 along its length. A via formed in dielectric layer 66, marked with reference numeral T6c, connects to a portion near the other end of conductor layer 674 along its length. A via formed in dielectric layer 66, marked with reference numeral T5d, connects to a portion near one end of conductor layer 675 along its length. A via formed in dielectric layer 66, marked with reference numeral T6b, connects to a portion near the other end of conductor layer 675 along its length.

[0082] Figure 15 This indicates the side of the eighteenth dielectric layer 68 opposite to the patterned surface. A mark 681 is formed on this side.

[0083] Figure 2 The stack 50 shown is constructed by stacking the first to eighteenth dielectric layers 51-68 such that the patterned surface of the first dielectric layer 51 becomes the bottom surface 50A of the stack 50, and the surface of the eighteenth dielectric layer 68 opposite to the patterned surface becomes the upper surface 50B of the stack 50. Furthermore, in Figures 3 to 15 The shape and configuration of the multiple conductor layers, multiple electrodes, and multiple vias are shown when viewed from the upper surface 50B side of the laminate 50.

[0084] When stacking the first to eighteenth dielectric layers 51-68, Figures 3 to 13 The multiple vias shown are respectively connected to conductor layers overlapping in the stacking direction T or other vias overlapping in the stacking direction T. Additionally, Figures 3 to 13 The through-hole shown is located inside the electrode or the conductor layer and is connected to the electrode or the conductor layer.

[0085] Figure 16 This refers to the interior of the laminate 50, which consists of the first to eighteenth dielectric layers 51-68. For example... Figure 16 As shown, the following are stacked inside the laminate 50: Figures 3 to 15 Multiple conductor layers and multiple through-holes are shown. Furthermore, in... Figure 16 In the text, mark 681 is omitted.

[0086] Below, on Figure 1 The circuit structure of the electronic device 1 shown is as follows: Figures 3 to 15 The correspondence between the internal constituent elements of the stacked body 50 shown is explained.

[0087] First, the constituent elements of the second filter 20 will be described. The inductor L21 includes a conductor layer 676, a plurality of vias connecting the conductor layer 525 to the conductor layer 676, and a plurality of vias connecting the conductor layer 531 to the conductor layer 676. The conductor layer 525 is connected to the electrode 111 via a via formed in the dielectric layer 51.

[0088] Capacitor C21 includes electrode 111, conductor layer 531, and dielectric layers 51 and 52 between them. Capacitor C22 includes the capacitance between electrode 111 and electrode 112. Capacitor C23 includes electrode 112, conductor layers 524, 531, and 532, and dielectric layers 51 and 52 between them.

[0089] Next, the constituent elements of the first filter 10 will be described. The inductor L1 includes conductor layers 581, 582, 601, 671, 672 and a plurality of vias marked with reference numerals T1a, T1c, T1d, T2a, T2b, and T2c. The via marked with reference numeral T1a formed in the dielectric layer 52 is connected to the electrode 112 via the via formed in the dielectric layer 51 and the conductor layer 521.

[0090] The inductor L2 includes a conductor layer 673 and a plurality of vias marked with reference numerals T3 and T4. The via marked with reference numeral T3 formed in the dielectric layer 52 is connected to the electrode 112 via a via formed in the dielectric layer 51 and the conductor layer 521.

[0091] Inductor L3 includes conductor layers 583, 584, 602, 674, and 675, and multiple vias labeled T5a, T5c, T5d, T6a, T6b, and T6c. The via labeled T5a, formed in dielectric layer 52, is connected to electrode 112 via a via formed in dielectric layer 51 and conductor layer 523.

[0092] Capacitor C11 includes conductor layers 531 and 541 and a dielectric layer 53 between them. Capacitor C12 includes conductor layers 541 and 552 and a dielectric layer 54 between them. Capacitor C13 includes conductor layers 543 and 552 and a dielectric layer 54 between them. Capacitor C14 includes conductor layers 533 and 543 and a dielectric layer 53 between them.

[0093] Capacitor C15 includes conductor layers 541, 551, and 562 and dielectric layers 54 and 55 between them. Capacitor C16 includes the capacitance between conductor layer 551 and a via marked with reference numeral T1a.

[0094] Capacitor C17 includes conductor layers 542 and 552 and a dielectric layer 54 between them. Capacitor C18 includes electrodes 112, conductor layer 542, and dielectric layers 51-53 between them.

[0095] Capacitor C19 includes conductor layers 543, 553, 563 and dielectric layers 54, 55 between them. Capacitor C20 includes the capacitance between conductor layer 553 and a via marked with reference numeral T5a.

[0096] Next, the constituent elements of the third filter 30 will be described. The inductor L31 includes a conductor layer 677, a plurality of vias connecting the conductor layer 533 to the conductor layer 677, and a plurality of vias connecting the conductor layer 522 to the conductor layer 677. The conductor layer 522 is connected to the electrode 113 via a via formed in the dielectric layer 51.

[0097] Capacitor C31 includes electrode 113, conductor layer 533, and dielectric layers 51 and 52 between them. Capacitor C32 includes conductor layers 523 and 533 and dielectric layer 52 between them. Capacitor C33 includes the capacitance between electrode 112 and electrode 113.

[0098] Next, refer to Figures 1 to 17 The structural features of the exemplary embodiments will be described. Figure 17 It is a three-dimensional view showing a portion of the interior of the laminate 50.

[0099] First, the structural features of inductors L1 to L3 will be described. Inductors L1, L2, and L3 are wound around a first axis A1, a second axis A2, and a third axis A3, respectively, which are orthogonal to the stacking direction T. The first axis A1 and the third axis A3 extend in directions parallel to the Y direction. The second axis A2 extends in each direction intersecting the X and Y directions at angles other than 0° and 90°.

[0100] Inductors L1 through L3 are also rectangular or roughly rectangular coils. In rectangular or roughly rectangular coils, regarding the number of turns, when considering the coil as rectangular, one-quarter turns can be counted on each side of the rectangle. Figure 16 and Figure 17 In the example shown, inductors L1 and L3 each have 7 / 4 turns. Inductor L2 has 3 / 4 turns.

[0101] Inductor L1 includes conductor layers 581, 582, 601, 671, and 672, and columnar conductors T1a, T1c, T1d, T2a, T2b, and T2c formed by multiple through-holes labeled T1a, T1c, T1d, T2a, T2b, and T2c. The columnar conductor T1a is a columnar structure formed by connecting multiple through-holes labeled T1a in series. The columnar conductor T1a extends in a direction parallel to the stacking direction T.

[0102] The above description of cylindrical conductor T1a also applies to other cylindrical conductors. The description of other cylindrical conductors is formed by simply replacing the reference numeral T1a in the above description of cylindrical conductor T1a with other reference numerals.

[0103] Pillar conductors T1c, T1d, and T2a are arranged along side surface 50C. Pillar conductors T2b and T2c are arranged in a position that sandwiches pillar conductors T1c, T1d, and T2a between pillar conductors T2b and T2c and side surface 50C. Pillar conductor T1a is arranged between pillar conductors T2b and T2c and side surface 50D.

[0104] Conductor layers 671 and 672 are configured such that the spacing between conductor layers 671 and 672 and the upper surface 50B is smaller than the spacing between conductor layers 671 and 672 and the bottom surface 50A. Conductor layer 601 is positioned to sandwich conductor layers 671 and 672 between conductor layer 601 and the upper surface 50B. Conductor layers 581 and 582 are disposed between conductor layer 601 and the bottom surface 50A in the stacking direction T.

[0105] In inductor L1, cylindrical conductor T2a, conductor layer 581, cylindrical conductor T1c, conductor layer 672, cylindrical conductor T2c, conductor layer 601, cylindrical conductor T1d, conductor layer 671, cylindrical conductor T2b, conductor layer 582, and cylindrical conductor T1a are connected in series in this order. Conductor layer 671 is connected to one end of cylindrical conductor T1d and one end of cylindrical conductor T2b. Conductor layer 672 is connected to one end of cylindrical conductor T1c and one end of cylindrical conductor T2c.

[0106] Conductor layer 601 is connected to the other end of columnar conductor T1d and the other end of columnar conductor T2c. Conductor layer 581 is connected to the other end of columnar conductor T1c and one end of columnar conductor T2a. Conductor layer 582 is connected to the other end of columnar conductor T2b and one end of columnar conductor T1a.

[0107] At least one of the columnar conductors T1c and T1d corresponds to the "first conductor" in this disclosure. At least one of the columnar conductors T2b and T2c corresponds to the "second conductor" in this disclosure. At least one of the conductor layers 601, 671, and 672 corresponds to the "first conductor layer" in this disclosure.

[0108] Inductor L2 includes a conductor layer 673 and columnar conductors T3 and T4 formed by a plurality of through holes labeled T3 and T4 in the attached drawings. The columnar conductor T3 is arranged along side surface 50F. The columnar conductor T4 is arranged along side surface 50E. The conductor layer 673 is configured such that the spacing between the conductor layer 673 and the upper surface 50B is smaller than the spacing between the conductor layer 673 and the bottom surface 50A.

[0109] In inductor L2, cylindrical conductor T4, conductor layer 673, and cylindrical conductor T3 are connected in series in this order. Conductor layer 673 is connected to one end of cylindrical conductor T3 and one end of cylindrical conductor T4.

[0110] The cylindrical conductor T3 corresponds to the "third conductor" in this disclosure. The cylindrical conductor T4 corresponds to the "fourth conductor" in this disclosure. The conductor layer 673 corresponds to the "second conductor layer" in this disclosure.

[0111] Inductor L3 includes conductor layers 583, 584, 602, 674, and 675, and columnar conductors T5a, T5c, T5d, T6a, T6b, and T6c formed by multiple through-holes labeled T5a, T5c, T5d, T6a, T6b, and T6c. The columnar conductors T5c, T5d, and T6a are arranged along side surface 50D. The columnar conductors T6b and T6c are positioned to sandwich the columnar conductors T5c, T5d, and T6a between the columnar conductors T6b and T6c and side surface 50D. The columnar conductor T5a is positioned between the columnar conductors T6b and T6c and side surface 50C.

[0112] Conductor layers 674 and 675 are configured such that the spacing between conductor layers 674 and 675 and the upper surface 50B is smaller than the spacing between conductor layers 674 and 675 and the bottom surface 50A. Conductor layer 602 is positioned to sandwich conductor layers 674 and 675 between conductor layer 602 and the upper surface 50B. Conductor layers 583 and 584 are positioned in the stacking direction T between conductor layer 602 and the bottom surface 50A.

[0113] In inductor L3, cylindrical conductor T6a, conductor layer 583, cylindrical conductor T5c, conductor layer 674, cylindrical conductor T6c, conductor layer 602, cylindrical conductor T5d, conductor layer 675, cylindrical conductor T6b, conductor layer 584, and cylindrical conductor T5a are connected in series in this order. Conductor layer 674 is connected to one end of cylindrical conductor T5c and one end of cylindrical conductor T6c. Conductor layer 675 is connected to one end of cylindrical conductor T5d and one end of cylindrical conductor T6b.

[0114] Conductor layer 602 is connected to the other end of columnar conductor T5d and the other end of columnar conductor T6c. Conductor layer 583 is connected to the other end of columnar conductor T5c and one end of columnar conductor T6a. Conductor layer 584 is connected to the other end of columnar conductor T6b and one end of columnar conductor T5a.

[0115] At least one of the columnar conductors T5c and T5d corresponds to the "fifth conductor" in this disclosure. At least one of the columnar conductors T6b and T6c corresponds to the "sixth conductor" in this disclosure. At least one of the conductor layers 602, 674, and 675 corresponds to the "third conductor layer" in this disclosure.

[0116] Next, the features regarding the configuration of inductors L1 to L3 will be described. Inductors L1 and L3 can be positioned near one diagonal and the other diagonally opposite the planar shape of the laminate 50. Figure 16 and Figure 17 In the example shown, inductor L1 is positioned near a corner where side 50C and side 50F intersect. That is, inductor L1 is positioned such that the distance between inductor L1 and side 50C is smaller than the distance between inductor L1 and side 50D, and the distance between inductor L1 and side 50F is smaller than the distance between inductor L1 and side 50E.

[0117] Inductor L3 is positioned near a corner where side surface 50D intersects with side surface 50E. Specifically, inductor L3 is positioned such that the distance between inductor L3 and side surface 50D is smaller than the distance between inductor L3 and side surface 50C, and the distance between inductor L3 and side surface 50E is smaller than the distance between inductor L3 and side surface 50F.

[0118] Viewed from the stacking direction T, inductor L2 is positioned between inductors L1 and L3.

[0119] The multiple cylindrical conductors of inductors L1 to L3 are configured to satisfy at least one of a first condition and a second condition. The first condition is that the orientation of the first conductor (cylindrical conductors T1c, T1d) and the second conductor (cylindrical conductors T2b, T2c), as well as the orientation of the fifth conductor (cylindrical conductors T5c, T5d) and the sixth conductor (cylindrical conductors T6b, T6c), are different from the orientation of the third conductor (cylindrical conductor T3) and the fourth conductor (cylindrical conductor T4).

[0120] exist Figure 16 and Figure 17In the example shown, cylindrical conductors T3 and T4 are arranged at angles other than 0° and 90° relative to each intersection of the X and Y directions (directions orthogonal to the second axis A2). Hereinafter, this direction will be referred to as the reference direction. The directions in which one of cylindrical conductors T1c and T1d and one of cylindrical conductors T2b and T2c are arranged, as well as the directions in which one of cylindrical conductors T5c and T5d and one of cylindrical conductors T6b and T6c are arranged, are different from the reference direction. For example, the directions in which cylindrical conductors T1c and T2c are arranged, as well as the directions in which cylindrical conductors T5c and T6c are arranged, are parallel to the X direction, which is different from the reference direction. Therefore, in Figure 16 and Figure 17 In the example shown, the multiple cylindrical conductors of inductors L1 to L3 are configured to satisfy the first condition.

[0121] The second condition is that the third conductor, namely the cylindrical conductor T3, is arranged in a specific direction orthogonal to the stacking direction T at a position different from at least one of the first conductors (cylindrical conductors T1c, T1d) and the fifth conductor (cylindrical conductors T5c, T5d), and the fourth conductor, namely the cylindrical conductor T4, is arranged in a specific direction at a position different from at least one of the second conductors (cylindrical conductors T2b, T2c) and the sixth conductor (cylindrical conductors T6b, T6c).

[0122] exist Figure 16 and Figure 17 In the example shown, inductors L1-L3 are arranged along the X direction. A specific direction can be one that intersects the direction in which inductors L1-L3 are arranged. Figure 16 and Figure 17 In the example shown, a specific direction is set to be parallel to the Y direction. The cylindrical conductor T3 is positioned differently from cylindrical conductors T5c and T5d, at least in a direction parallel to the Y direction. The cylindrical conductor T4 is positioned differently from cylindrical conductors T2b and T2c, at least in a direction parallel to the Y direction. Therefore, in Figure 16 and Figure 17 In the example shown, the multiple cylindrical conductors of inductors L1 to L3 are configured to satisfy the second condition.

[0123] Furthermore, inductors L1 and L3 are configured to satisfy a third condition regarding the multiple cylindrical conductors of inductors L1 and L3. Specifically, the region sandwiched between the first conductor (cylindrical conductors T1c and T1d) and the second conductor (cylindrical conductors T2b and T2c) is not opposite to the region sandwiched between the fifth conductor (cylindrical conductors T5c and T5d) and the sixth conductor (cylindrical conductors T6b and T6c). Figure 16 and Figure 17 In the examples shown, these regions are either perpendicular to the Y-direction or perpendicular to a direction slightly inclined relative to the Y-direction. Figure 16 and Figure 17 In the example shown, inductors L1 and L3 are configured to satisfy the third condition.

[0124] The orientation of the first conductor (pillar conductors T1c, T1d) and the second conductor (pillar conductors T2b, T2c) can be the same as the orientation of the fifth conductor (pillar conductors T5c, T5d) and the sixth conductor (pillar conductors T6b, T6c). Figure 16 and Figure 17 In the example shown, the directions in which the cylindrical conductors T1c and T2c are arranged, the directions in which the cylindrical conductors T1d and T2b are arranged, the directions in which the cylindrical conductors T5c and T6c are arranged, and the directions in which the cylindrical conductors T5d and T6b are arranged are all parallel to the X direction.

[0125] Furthermore, a first group comprising the first conductor (pillar conductors T1c, T1d) and the second conductor (pillar conductors T2b, T2c), and a second group comprising the fifth conductor (pillar conductors T5c, T5d) and the sixth conductor (pillar conductors T6b, T6c), are arranged in different positions in a specific direction orthogonal to the stacking direction T. Figure 16 and Figure 17 In the example shown, the first group and the second group are positioned at different locations in a direction parallel to the Y direction.

[0126] Furthermore, the third conductor, namely the cylindrical conductor T3, can be configured such that the distance between the cylindrical conductor T3 and the inductor L1 is smaller than the distance between the cylindrical conductor T3 and the inductor L1. The fourth conductor, namely the cylindrical conductor T4, can be configured such that the distance between the cylindrical conductor T4 and the inductor L3 is smaller than the distance between the cylindrical conductor T4 and the inductor L1. Figure 16 and Figure 17 In the example shown, inductors L1 to L3 are configured to satisfy the above conditions regarding cylindrical conductors T3 and T4.

[0127] Additionally, the second conductor layer, namely conductor layer 673, may include portions extending in each direction intersecting the directions in which the first conductors (pillar conductors T1c, T1d) and the second conductors (pillar conductors T2b, T2c) are arranged, as well as the directions in which the fifth conductors (pillar conductors T5c, T5d) and the sixth conductors (pillar conductors T6b, T6c) are arranged. Figure 16 and Figure 17 In the example shown, conductor layer 673 includes a portion extending in the reference direction.

[0128] Next, the characteristics of the connection relationship between inductors L1 to L3 and at least one ground terminal, namely electrode 112, will be described. The second conductor of inductor L1, namely the columnar conductor T2b, is connected to electrode 112 via conductor layer 582, columnar conductor T1a, conductor layer 521, and two first vias formed in dielectric layer 51. In addition, columnar conductor T2b is connected to electrode 112 without passing through the first conductor layer (conductor layers 601, 671, 672) of inductor L1.

[0129] The third conductor of inductor L2, namely the columnar conductor T3, is connected to the electrode 112 via the conductor layer 521 and two first vias formed in the dielectric layer 51. Alternatively, the columnar conductor T3 is connected to the electrode 112 without passing through the second conductor layer of inductor L2, namely the conductor layer 673.

[0130] The sixth conductor of inductor L3, namely the columnar conductor T6b, is connected to the electrode 112 via conductor layer 584, columnar conductor T5a, conductor layer 523, and the second via formed in dielectric layer 51. Alternatively, the columnar conductor T6b is connected to the electrode 112 without passing through the third conductor layer (conductor layers 602, 674, 675) of inductor L3.

[0131] like Figure 3 As shown, the two first vias connected to conductor layer 521 and the second via connected to conductor layer 523 are connected to electrode 112 at different positions in a direction parallel to the Y direction. Therefore, the cylindrical conductor T2b of inductor L1 and the cylindrical conductor T6b of inductor L3 are substantially electrically connected to electrode 112 at different positions in a direction parallel to the Y direction.

[0132] Furthermore, the methods of electrically connecting two components include connecting the two components via a conductor and connecting the two components via an inductor. On the other hand, methods where a portion of the conductor between the two components is discontinuous, such as connecting the two components via a capacitor, are not included in the methods of electrically connecting the two components.

[0133] The cylindrical conductor T2b of inductor L1 and the cylindrical conductor T3 of inductor L2 are electrically connected to electrode 112 at substantially the same position in a direction parallel to the Y direction. Furthermore, the cylindrical conductor T3 of inductor L2 and the cylindrical conductor T6b of inductor L3 are electrically connected to electrode 112 at substantially different positions in a direction parallel to the Y direction.

[0134] Next, the operation and effects of the electronic device 1 according to the exemplary embodiment will be explained. The electronic device 1 of the exemplary embodiment includes a filter 1A comprising inductors L1 to L3. The characteristics of the filter 1A can be controlled by the inductance and Q value of each of the inductors L1 to L3, and the strength of the electromagnetic coupling between any two of the inductors L1 to L3. However, if the electronic device 1 is miniaturized, the distance between the two inductors becomes smaller. As a result, sometimes the electromagnetic coupling between the two inductors is too strong, and the desired characteristics cannot be achieved.

[0135] One characteristic of filter 1A is the magnitude of its stopband attenuation. When multiple attenuation electrodes are formed in the stopband through inductors L1-L3, if the electromagnetic coupling between two inductors is too strong, the number of attenuation electrodes may decrease, or attenuation electrodes may not be formed at all. As a result, the stopband attenuation may not be sufficiently increased.

[0136] In contrast, in the exemplary embodiment, inductors L1 to L3 are configured to satisfy the aforementioned conditions. Therefore, according to the exemplary embodiment, excessive electromagnetic coupling between the two inductors can be suppressed.

[0137] Next, the effects of the exemplary embodiment will be explained in detail by comparing it with the electronic device 101A of the first comparative example, the electronic device 101B of the second comparative example, and the electronic device 101C of the third comparative example. First, the structures of the electronic devices 101A, 101B, and 101C of the first to third comparative examples will be described. The circuit structures of the electronic devices 101A, 101B, and 101C of the first to third comparative examples are the same as the circuit structure of the electronic device 1 of the exemplary embodiment.

[0138] Figure 18 This is a perspective view showing the interior of the laminated structure of the electronic device 101A of the first comparative example. The electronic device 101A of the first comparative example replaces the inductors L1 to L3 in the exemplary embodiments and includes inductors L101A, L102A, and L103A. Inductor L101A includes columnar conductors T111A and T112A, and a conductor layer 111A connected to one end of columnar conductor T111A and one end of columnar conductor T112A.

[0139] Inductor L102A includes cylindrical conductors T113A and T114A, and a plurality of conductor layers 112A wound on an axis parallel to the stacking direction T. One of the conductor layers 112A is connected to one end of the cylindrical conductor T113A. Another of the conductor layers 112A is connected to one end of the cylindrical conductor T114A. Inductor L102A also includes at least one through-hole connecting two of the conductor layers 112A.

[0140] Inductor L103A includes cylindrical conductors T115A and T116A, and a plurality of conductor layers 113A wound on an axis parallel to the stacking direction T. One of the conductor layers 113A is connected to one end of the cylindrical conductor T115A. Another of the conductor layers 113A is connected to one end of the cylindrical conductor T116A. Inductor L103A also includes at least one through-hole connecting two of the conductor layers 113A.

[0141] In the first comparative example, the cylindrical conductor T113A is positioned at the same location as both cylindrical conductors T112A and T115A in a direction parallel to the Y direction. Therefore, the first comparative example does not satisfy the second condition in the exemplary embodiment. Furthermore, in the first comparative example, the inductors L101A and L103A are configured such that the region sandwiched between cylindrical conductors T111A and T112A is opposite to the region sandwiched between cylindrical conductors T115A and T116A. Therefore, the first comparative example does not satisfy the third condition in the exemplary embodiment.

[0142] Figure 19 This is a perspective view showing the interior of the laminated structure of the electronic device 101B of the second comparative example. The electronic device 101B of the second comparative example replaces the inductors L1-L3 in the exemplary embodiments and includes inductors L101B, L102B, and L103B. Inductor L101B includes columnar conductors T111B and T112B, and a plurality of conductor layers 111B wound on an axis parallel to the lamination direction T. One of the plurality of conductor layers 111B is connected to one end of the columnar conductor T111B. Another of the plurality of conductor layers 111B is connected to one end of the columnar conductor T112B. Inductor L101B also includes at least one through-hole connecting two of the plurality of conductor layers 111B.

[0143] Inductor L102B includes columnar conductors T113B and T114B, and a conductor layer 112B connected to one end of columnar conductors T113B and T114B. The shape and orientation of inductor L102B are the same as those of inductor L2 in the exemplary embodiment.

[0144] Inductor L103B includes cylindrical conductors T115B and T116B, and a plurality of conductor layers 113B wound on an axis parallel to the stacking direction T. One of the conductor layers 113B is connected to one end of the cylindrical conductor T115B. Another of the conductor layers 113B is connected to one end of the cylindrical conductor T116B. Inductor L103B also includes at least one through-hole connecting two of the conductor layers 113B.

[0145] In the second comparative example, the cylindrical conductor T113B is positioned at the same location as cylindrical conductors T112B and T115B in a direction parallel to the Y direction. Furthermore, the cylindrical conductor T114B is positioned at the same location as cylindrical conductors T111B and T116B in a direction parallel to the Y direction. Therefore, the second comparative example does not satisfy the second condition in the exemplary embodiment. Additionally, in the second comparative example, the inductors L101B and L103B are configured such that the region sandwiched between cylindrical conductors T111B and T112B is opposite to the region sandwiched between cylindrical conductors T115B and T116B. Therefore, the second comparative example does not satisfy the third condition in the exemplary embodiment.

[0146] Figure 20 This is a perspective view showing the interior of the laminated structure of the electronic device 101C of the third comparative example. The electronic device 101C of the third comparative example replaces the inductors L1-L3 in the exemplary embodiments and includes inductors L101C, L102C, and L103C. Inductor L101C includes two cylindrical conductors T111C, two cylindrical conductors T112C, and two conductor layers 111C. One side of each conductor layer 111C is connected to one end of one side of each of the cylindrical conductors T111C and one end of one side of each of the cylindrical conductors T112C. The other side of each conductor layer 111C is connected to one end of the other side of each of the cylindrical conductors T111C and one end of each of the cylindrical conductors T112C. Inductor L101C also includes a conductor layer connected to the other end of the other side of each of the cylindrical conductors T111C and one end of each of the cylindrical conductors T112C.

[0147] The shape of inductor L101C is the same as that of inductor L1 in the exemplary embodiment. The orientation of inductor L101C is the same as that of inductor L1 after rotating it 90° about an axis parallel to the stacking direction T.

[0148] Inductor L102C includes cylindrical conductors T113C and T114C, and a plurality of conductor layers 112C wound on an axis parallel to the stacking direction T. One of the conductor layers 112C is connected to one end of the cylindrical conductor T113C. Another of the conductor layers 112C is connected to one end of the cylindrical conductor T114C. Inductor L102C also includes at least one through-hole connecting two of the conductor layers 112C.

[0149] Inductor L103C includes two cylindrical conductors T115C, two cylindrical conductors T116C, and two conductor layers 113C. One end of each conductor layer 113C is connected to one end of one of the two cylindrical conductors T115C and one end of one of the two cylindrical conductors T116C. The other end of each conductor layer 113C is connected to one end of the other cylindrical conductors T115C and one end of the other cylindrical conductor T116C. Inductor L103C also includes a conductor layer connected to the other end of the other cylindrical conductors T115C and one end of one of the cylindrical conductors T116C.

[0150] The shape of inductor L103C is the same as that of inductor L3 in the exemplary embodiment. The orientation of inductor L103C is the same as that of inductor L3 after rotating it 90° about an axis parallel to the stacking direction T.

[0151] In the third comparative example, the cylindrical conductor T113C is positioned in a direction parallel to the Y direction at the same location as the two cylindrical conductors T112C and the two cylindrical conductors T115C. Furthermore, the cylindrical conductor T114C is positioned in a direction parallel to the Y direction at the same location as one of the two cylindrical conductors T111C and one of the two cylindrical conductors T116C. Therefore, the third comparative example does not satisfy the second condition in the exemplary embodiment. Additionally, in the third comparative example, the inductors L101C and L103C are configured such that the region sandwiched between the two cylindrical conductors T111C and the two cylindrical conductors T112C is opposite to the region sandwiched between the two cylindrical conductors T115C and the two cylindrical conductors T116C. Therefore, the third comparative example does not satisfy the third condition in the exemplary embodiment.

[0152] Next, the characteristics of the models of the first to third comparative examples and the model of the embodiment will be explained. The model of the first comparative example is the model of electronic device 101A of the first comparative example. The model of the second comparative example is the model of electronic device 101B of the second comparative example. The model of the third comparative example is the model of electronic device 101C of the third comparative example. The model of the embodiment is the model of electronic device 1 of the exemplary embodiment. Here, the pass-through attenuation characteristics of the filter 1A (bandpass filter) of each of the models of the first to third comparative examples and the model of the embodiment are obtained by simulation.

[0153] In the model of the embodiment, electronic device 1 is designed such that three attenuation electrodes are formed in the stopband of filter 1A by inductors L1 to L3. In the model of the first comparative example, electronic device 101A of the first comparative example is designed the same as electronic device 1, except for the shape and arrangement of inductors L101A to L103A. In the model of the second comparative example, electronic device 101B of the second comparative example is designed the same as electronic device 1, except for the shape and arrangement of inductors L101B to L103B. In the model of the third comparative example, electronic device 101C of the third comparative example is designed the same as electronic device 1, except for the shape and arrangement of inductors L101C to L103C.

[0154] Figure 21 This is a characteristic diagram showing the pass-through attenuation characteristics of filter 1A of the model representing the first comparative example. Figure 22 This is a characteristic diagram showing the pass-through attenuation characteristics of filter 1A of the model representing the second comparative example. Figure 23 This is a characteristic diagram showing the pass-through attenuation characteristics of filter 1A in the model of the third comparative example. Figure 24 This is a characteristic diagram of the attenuation characteristics of filter 1A in the model representing the embodiment. Figures 21 to 24 In the diagram, the horizontal axis represents frequency, and the vertical axis represents attenuation.

[0155] like Figure 24 As shown, in the model of this embodiment, three attenuation electrodes are formed in the stopband on the low-frequency side of the passband. Figure 24 In the diagram, the arrow labeled 91a indicates the attenuator with the highest frequency among the three attenuators, namely the attenuator formed by inductor L2. The arrow labeled 91c indicates the attenuator with the lowest frequency among the three attenuators, namely the attenuator formed by inductor L1. The arrow labeled 91b indicates the attenuator formed by inductor L3.

[0156] like Figures 21 to 23 As shown, in the models of the first to third comparative examples, there is only one attenuation electrode in the stopband formed on the low-frequency side of the passband. In the models of the first to third comparative examples, compared to the case where multiple attenuation electrodes are formed in the stopband on the low-frequency side of the passband, the absolute value of the attenuation of the stopband on the low-frequency side of the passband is smaller. One reason for the reduction in the number of attenuation electrodes in the stopband formed on the low-frequency side of the passband is that the electromagnetic coupling between multiple inductors forming multiple attenuation electrodes in the stopband on the low-frequency side of the passband is too strong. In the models of the first to third comparative examples, the electromagnetic coupling between multiple inductors can be considered too strong.

[0157] from Figures 21 to 24As can be understood from the attenuation characteristics shown, according to the exemplary embodiment, excessive electromagnetic coupling between the two inductors can be suppressed. Therefore, according to the exemplary embodiment, the electronic device 1 can be miniaturized while achieving the desired characteristics.

[0158] Furthermore, although not illustrated, in the electronic device 101 of the third comparative example, when an inductor with the same structure as inductor L111C or inductor L113C is used instead of inductor L112C, the first condition is not met. In this case, the electromagnetic coupling between the multiple inductors is enhanced compared to the model of the third comparative example. Therefore, in this case, similar to the model of the third comparative example, the absolute value of the attenuation of the stopband on the low-frequency side of the passband becomes smaller.

[0159] Furthermore, in the exemplary embodiment, inductors L1, L2, and L3 are wound around a first axis A1, a second axis A2, and a third axis A3, respectively, which are orthogonal to the stacking direction T. According to the exemplary embodiment, by arranging inductors L1-L3 in a manner that satisfies the aforementioned conditions, the area of ​​the opening (the region surrounded by the conductor) of each inductor L1-L3 can be increased. As a result, according to the exemplary embodiment, the Q value of each inductor L1-L3 can be increased.

[0160] Furthermore, in the exemplary embodiment, the inductor L2 forms the highest frequency attenuation electrode in the stopband on the low-frequency side of the passband, i.e., the attenuation electrode closest to the passband. In the exemplary embodiment, the area of ​​the opening of inductor L2 is set to be larger than the area of ​​the openings of inductors L1 and L3 respectively. Therefore, according to the exemplary embodiment, the insertion loss in the passband can be reduced.

[0161] [Second Exemplary Implementation] Next, a second exemplary embodiment of this disclosure will be described. First, referring to... Figure 25 The differences between the structure of the electronic device 1 in the exemplary embodiment and the first exemplary embodiment will be described. Figure 25 This is a perspective view showing the interior of the stack 50 in an exemplary embodiment.

[0162] In an exemplary embodiment, inductor L1 replaces conductor layers 671 and 672 in the first exemplary embodiment and includes conductor layers 1661 and 1671 wound on an axis A4 parallel to the stacking direction T. Conductor layers 1661 and 1671 are positioned at different locations in the stacking direction T. Conductor layer 1661 is connected to one end of columnar conductor T2b. Conductor layer 1671 is connected to one end of columnar conductor T1d. Inductor L1 also includes a through-hole connecting conductor layers 1661 and 1671. In an exemplary embodiment, conductor layers 581 and 601 and columnar conductors T1c, T2a, and T2c are not provided in inductor L1.

[0163] In an exemplary embodiment, inductor L3 replaces conductor layers 674 and 675 in the first exemplary embodiment and includes conductor layers 1664 and 1674 wound on an axis A5 parallel to the stacking direction T. Conductor layers 1664 and 1674 are positioned at different locations in the stacking direction T. Conductor layer 1664 is connected to one end of the cylindrical conductor T6b. Conductor layer 1674 is connected to one end of the cylindrical conductor T5d. Inductor L3 also includes a through-hole connecting conductor layers 1664 and 1674. In an exemplary embodiment, conductor layers 583 and 603 and cylindrical conductors T5c, T6a, and T6c are not provided in inductor L3.

[0164] Next, an example of the characteristics of the electronic device 1 in the exemplary embodiment will be described. Figure 26 This refers to filter 1A in an exemplary embodiment (see reference). Figure 1 The characteristic plot of the attenuation characteristic. Figure 26 In the diagram, the horizontal axis represents frequency, and the vertical axis represents attenuation. For example... Figure 26 As shown, similar to the model of the embodiment described in the first exemplary embodiment, three attenuation poles are formed in the stopband on the low-frequency side of the passband. Figure 26 In the diagram, the arrow labeled 91a indicates the attenuator with the highest frequency among the three attenuators, namely the attenuator formed by inductor L2. The arrow labeled 91c indicates the attenuator with the lowest frequency among the three attenuators, namely the attenuator formed by inductor L1. The arrow labeled 91b indicates the attenuator formed by inductor L3.

[0165] Additionally, in an exemplary embodiment, electrode 112 corresponds to a ground terminal.

[0166] The cylindrical conductor T2b of inductor L1, the cylindrical conductor T3 of inductor L2, and the cylindrical conductor T6b of inductor L3 are connected to electrode 112.

[0167] Other structures, functions, and effects in the exemplary embodiments are the same as in the first exemplary embodiment.

[0168] [Third Exemplary Implementation] Next, a third exemplary embodiment of this disclosure will be described. First, referring to... Figure 27 The differences between the structure of the electronic device 1 in the exemplary embodiment and the first exemplary embodiment will be described. Figure 27 This is a perspective view showing the interior of the stack 50 in an exemplary embodiment.

[0169] In an exemplary embodiment, inductor L2 replaces conductor layer 673 in the first exemplary embodiment and includes conductor layers 1653, 1663, and 1673 wound on an axis A6 parallel to the stacking direction T. Conductor layers 1653, 1663, and 1673 are positioned at different locations in the stacking direction T. Conductor layer 1653 is connected to one end of pillar conductor T4. Conductor layer 1673 is connected to one end of pillar conductor T3. Inductor L2 also includes a plurality of through-holes connecting two of the conductor layers 1653, 1663, and 1673.

[0170] Furthermore, in this exemplary embodiment, the number of grounding terminals differs from that in the first exemplary embodiment. Specifically, in this exemplary embodiment, the laminate 50 replaces electrode 112 and includes electrodes 114 and 115. Electrode 114 corresponds to the "first grounding terminal" in this disclosure. Electrode 115 corresponds to the "second grounding terminal" in this disclosure.

[0171] The cylindrical conductor T2b of inductor L1 and the cylindrical conductor T3 of inductor L2 are electrically connected to electrode 114. The cylindrical conductor T6b of inductor L3 is electrically connected to electrode 115.

[0172] Next, an example of the characteristics of the electronic device 1 in the exemplary embodiment will be described. Figure 28 This refers to filter 1A in an exemplary embodiment (see reference). Figure 1 The characteristic plot of the attenuation characteristic. Figure 28 In the diagram, the horizontal axis represents frequency, and the vertical axis represents attenuation. For example... Figure 28 As shown, similar to the model of the embodiment described in the first exemplary embodiment, three attenuation poles are formed in the stopband on the low-frequency side of the passband. Figure 28 In the diagram, the arrow labeled 91a indicates the attenuator with the highest frequency among the three attenuators, namely the attenuator formed by inductor L2. The arrow labeled 91c indicates the attenuator with the lowest frequency among the three attenuators, namely the attenuator formed by inductor L1. The arrow labeled 91b indicates the attenuator formed by inductor L3.

[0173] Other structures, functions, and effects in the exemplary embodiments are the same as in the first exemplary embodiment.

[0174] Furthermore, this disclosure is not limited to the exemplary embodiments described above, and various modifications are possible. For example, the shape and configuration of each of the inductors L1 to L3 are arbitrary as long as the conditions of the claims are met.

[0175] Alternatively, at least one grounding terminal may be a first grounding terminal, a second grounding terminal, and a third grounding terminal. In this case, inductor L1 may be electrically connected to the first grounding terminal, inductor L2 may be electrically connected to the second grounding terminal, and inductor L3 may be electrically connected to the third grounding terminal.

[0176] in addition, Figure 1 The inductance component L11 shown can be included in the laminate 50 or in the mounting substrate on which the electronic device 1 is mounted.

[0177] As described above, a stacked electronic device according to one embodiment of the present disclosure includes: a filter comprising a first inductor, a second inductor, and a third inductor; at least one ground terminal connected to a grounding element; and a stack comprising a plurality of stacked dielectric layers for integrating the filter and the at least one ground terminal. The first, second, and third inductors are electrically connected to the at least one ground terminal. When viewed from the stacking direction of the plurality of dielectric layers, the second inductor is disposed between the first and third inductors. The first inductor includes: a first conductor and a second conductor extending in directions parallel to the stacking direction; and a first conductor layer connected to one end of the first conductor and one end of the second conductor. The second inductor includes: a third conductor and a fourth conductor extending in directions parallel to the stacking direction; and a second conductor layer connected to one end of the third conductor and one end of the fourth conductor. The third inductor includes: a fifth conductor and a sixth conductor extending in directions parallel to the stacking direction; and a third conductor layer connected to one end of the fifth conductor and one end of the sixth conductor.

[0178] The first conductor, second conductor, third conductor, fourth conductor, fifth conductor, and sixth conductor are configured to satisfy at least one of a first condition and a second condition. The first condition is that the orientations of the first and second conductors, and the orientations of the fifth and sixth conductors, are different from the orientations of the third and fourth conductors. The second condition is that the third conductor is positioned in a specific direction orthogonal to the stacking direction at a position different from at least one of the first and fifth conductors, and the fourth conductor is positioned in a specific direction at a position different from at least one of the second and sixth conductors. The first inductor and the third inductor are configured such that the region sandwiched between the first and second conductors is not opposite to the region sandwiched between the fifth and sixth conductors.

[0179] In a stacked electronic device according to one embodiment of this disclosure, the orientation of the first and second conductors can be the same as the orientation of the fifth and sixth conductors. A first group including the first and second conductors and a second group including the fifth and sixth conductors can be arranged in different positions in specific directions.

[0180] Furthermore, in a stacked electronic device according to one embodiment of this disclosure, the third conductor may be configured such that the distance between the third conductor and the first inductor is smaller than the distance between the third conductor and the third inductor. The fourth conductor may be configured such that the distance between the fourth conductor and the third inductor is smaller than the distance between the fourth conductor and the first inductor.

[0181] Additionally, in a stacked electronic device according to one embodiment of this disclosure, the second conductor layer may include a portion extending in each direction intersecting the directions of the first and second conductors and the directions of the fifth and sixth conductors.

[0182] Furthermore, in one embodiment of the stacked electronic device disclosed herein, at least one ground terminal may be a single ground terminal. The second conductor and the sixth conductor may be electrically connected to a ground terminal at different locations in a specific direction.

[0183] Furthermore, in one embodiment of the stacked electronic device disclosed herein, at least one ground terminal may be a first ground terminal and a second ground terminal. A second conductor may be electrically connected to the first ground terminal. A sixth conductor may be electrically connected to the second ground terminal.

[0184] In addition, in a stacked electronic device according to one embodiment of the present disclosure, the first inductor, the second inductor and the third inductor can be wound around an axis orthogonal to the stacking direction.

[0185] In addition, in one embodiment of the stacked electronic device disclosed herein, one of the first conductor layer, the third conductor layer, and the second conductor layer may be wound around an axis parallel to the stacking direction, while the other of the first conductor layer, the third conductor layer, and the second conductor layer may not be wound around an axis parallel to the stacking direction.

[0186] Furthermore, in one embodiment of the stacked electronic device disclosed herein, the filter may include a high-pass filter, which includes a first inductor, a second inductor, and a third inductor, and is configured to selectively allow signals with frequencies higher than a specific frequency to pass through. The first, second, and third inductors may form multiple attenuation electrodes in the frequency region lower than the specific frequency in the filter's pass-through attenuation characteristics. The second inductor may form the attenuation electrode with the highest frequency among the multiple attenuation electrodes.

[0187] Based on the foregoing description, it is evident that various methods and variations of this disclosure can be implemented. Therefore, within the scope equivalent to the claims, this disclosure may also be implemented in ways other than the exemplary embodiments described above.

Claims

1. A stacked electronic device, characterized in that, have: The filter includes a first inductor, a second inductor, and a third inductor; At least one grounding terminal, which is connected to a grounding element; and A laminate comprising multiple stacked dielectric layers for integrating the filter and the at least one ground terminal. The first inductor, the second inductor, and the third inductor are electrically connected to the at least one ground terminal. Viewed from the stacking direction of the plurality of dielectric layers, the second inductor is disposed between the first inductor and the third inductor. The first inductor includes: a first conductor and a second conductor extending in directions parallel to the stacking direction; and a first conductor layer connected to one end of the first conductor and one end of the second conductor. The second inductor includes: a third conductor and a fourth conductor extending in directions parallel to the stacking direction; and a second conductor layer connected to one end of the third conductor and one end of the fourth conductor. The third inductor includes: a fifth conductor and a sixth conductor extending in directions parallel to the stacking direction; and a third conductor layer connected to one end of the fifth conductor and one end of the sixth conductor. The first conductor, the second conductor, the third conductor, the fourth conductor, the fifth conductor, and the sixth conductor are configured to satisfy at least one of the first and second conditions. The first condition is that the orientations of the first and second conductors, and the orientations of the fifth and sixth conductors, are different from the orientations of the third and fourth conductors. The second condition is that the third conductor is positioned in a specific direction orthogonal to the stacking direction at a position different from at least one of the first conductor and the fifth conductor, and the fourth conductor is positioned in the specific direction at a position different from at least one of the second conductor and the sixth conductor. The first inductor and the third inductor are configured such that the region sandwiched between the first conductor and the second conductor is not opposite to the region sandwiched between the fifth conductor and the sixth conductor.

2. The stacked electronic device according to claim 1, characterized in that, The first conductor and the second conductor are arranged in the same direction as the fifth conductor and the sixth conductor.

3. The stacked electronic device according to claim 2, characterized in that, A first group comprising the first conductor and the second conductor and a second group comprising the fifth conductor and the sixth conductor are arranged in different positions in the specific direction.

4. The stacked electronic device according to claim 1, characterized in that, The third conductor is configured such that the distance between the third conductor and the first inductor is smaller than the distance between the third conductor and the third inductor. The fourth conductor is configured such that the distance between the fourth conductor and the third inductor is smaller than the distance between the fourth conductor and the first inductor.

5. The stacked electronic device according to claim 1, characterized in that, The second conductor layer includes a portion extending in a direction that intersects with the directions in which the first conductor and the second conductor are arranged, as well as the directions in which the fifth conductor and the sixth conductor are arranged.

6. The stacked electronic device according to claim 1, characterized in that, The at least one grounding terminal is a single grounding terminal. The second conductor and the sixth conductor are electrically connected to a grounding terminal at different locations in the specific direction.

7. The stacked electronic device according to claim 1, characterized in that, The at least one grounding terminal is a first grounding terminal and a second grounding terminal. The second conductor is electrically connected to the first grounding terminal. The sixth conductor is electrically connected to the second grounding terminal.

8. The stacked electronic device according to claim 1, characterized in that, The first inductor, the second inductor, and the third inductor are each wound around an axis orthogonal to the stacking direction.

9. The stacked electronic device according to claim 1, characterized in that, The first conductor layer and the third conductor layer are wound around one of the second conductor layers with an axis parallel to the stacking direction as the center, while the other of the first conductor layer and the third conductor layer is not wound on an axis parallel to the stacking direction.

10. The stacked electronic device according to claim 1, characterized in that, The filter includes a high-pass filter, which comprises the first inductor, the second inductor, and the third inductor, and is configured to selectively allow signals of frequencies higher than a specific frequency to pass through.

11. The stacked electronic device according to claim 10, characterized in that, The first inductor, the second inductor, and the third inductor form multiple attenuation electrodes in the pass-through attenuation characteristics of the filter in a frequency region lower than the specific frequency. The second inductor forms the highest frequency attenuation electrode among the plurality of attenuation electrodes.

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