Inductance simulator module and power over bus system

Abstract

This invention provides an inductor simulator module and a Power over Bus system. A high-side clamping circuit clamps the Vds voltage drop of the high-side NLDMOS transistor to a first fixed value, simulating a large-value on-chip inductor. A high-side compensation network ensures the stability of the entire high-side clamping circuit loop. Correspondingly, a low-side clamping circuit clamps the Vds voltage drop of the low-side NLDMOS transistor to a second fixed value, simulating a large-value on-chip inductor. A low-side compensation network also ensures the stability of the entire low-side clamping circuit loop. Thus, the inductor simulator module of this invention can simulate two separate inductors in a Power over Bus system, realizing the function of a differential inductor. Furthermore, compared to PMOS transistors, the transistors used in this invention to simulate inductors are all NLDMOS transistors, which can further reduce the active inductor architecture area of ​​NLDMOS transistors, making it suitable for high-current Power over Bus systems.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an inductor simulator module and a Power over BUS system. Background Technology

[0002] Power over Bus (BUS) is an innovative industrial communication and power supply technology that transmits power and data simultaneously through the same pair of wires, significantly simplifying the complexity of traditional wiring.

[0003] Figure 1 This is a schematic diagram of a Power over Bus system. (See attached diagram) Figure 1 This paper illustrates a Power over BUS differential signal transmission system, including a first bus BUS+, a second bus BUS-, a first working module A, a second working module B, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a first discrete inductor L1, and a second discrete inductor L2. The first working module A draws power from the power supply VP via the first bus BUS+. The arrangement of the fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, and eighth capacitor C8 enables a communication connection between the first working module A and the second working module B through capacitive coupling, thereby facilitating signal transmission.

[0004] In a Power over Bus system, power and signal transmission can be achieved simultaneously on the same bus, such as... Figure 1 The diagram shows the power path and the signal path. To achieve power transmission, inductors (i.e., the first discrete inductor L1 and the second discrete inductor L2) must be used between the bus (first bus BUS+ and second bus BUS-) and the power supply side (first working module A and second working module B) to achieve a high impedance state of the bus during signal transmission, allowing the signal to be transmitted between the first working module A and the second working module B with almost no loss.

[0005] However, the large area of ​​the first discrete inductor L1 and the second discrete inductor L2 is not conducive to system integration. Although there are currently solutions to achieve larger on-chip inductors by controlling the Vds voltage drop of the PMOS transistor, this solution can only simulate single-ended discrete inductors and is not suitable for power over bus systems with differential signal transmission. In addition, for high-current applications, the active inductor architecture based on the PMOS transistor also has a large area, which is not conducive to further improving the integration of the on-chip system. Summary of the Invention

[0006] This invention provides an inductor simulator module and a Power over BUS system. The inductor simulator module can simulate the discrete inductors in the Power over BUS system, thereby reducing the inductor area and improving the system integration.

[0007] According to one aspect of the present invention, the present invention provides an inductor simulator module, which includes a high-side inductor simulator and a low-side inductor simulator.

[0008] The high-side inductor simulator includes a high-side clamping circuit, a high-side compensation network, and a high-side NLDMOS transistor. The drain of the high-side NLDMOS transistor is connected to a power supply, and the source of the high-side NLDMOS transistor is connected to the first bus of the Power over BUS system. The high-side clamping circuit connects the drain and source of the high-side NLDMOS transistor to clamp the Vds of the high-side NLDMOS transistor to a first fixed value, so that the high-side NLDMOS transistor always operates in the saturation region. The high-side compensation network connects the gate and source of the high-side NLDMOS transistor to provide zero-point compensation to the high-side NLDMOS transistor. The Vds of the high-side NLDMOS transistor is the drain-source voltage drop of the high-side NLDMOS transistor.

[0009] The low-side inductor simulator includes a low-side clamping circuit, a low-side compensation network, and a low-side NLDMOS transistor. The drain of the low-side NLDMOS transistor is connected to the second bus of the Power over BUS system, and the source of the low-side NLDMOS transistor is grounded. The low-side clamping circuit connects the drain and source of the low-side NLDMOS transistor to clamp the Vds of the low-side NLDMOS transistor to a second fixed value, so that the low-side NLDMOS transistor always operates in the saturation region. The low-side compensation network connects the gate and source of the low-side NLDMOS transistor to provide zero-point compensation to the low-side NLDMOS transistor. The Vds of the low-side NLDMOS transistor is the drain-source voltage drop of the low-side NLDMOS transistor.

[0010] Optionally, the high-side clamping circuit includes the zeroth to second PMOS transistors, the zeroth to third NMOS transistors, a high-side voltage clamping unit, and the first to sixth current sources;

[0011] The source of the zeroth PMOS transistor, the source of the first PMOS transistor, and the source of the second PMOS transistor are all connected to a first voltage. The drain and gate of the zeroth PMOS transistor are connected together with the gate of the first PMOS transistor. The drain of the first PMOS transistor is connected to a second voltage through the sixth current source. The gate and drain of the second PMOS transistor are connected together. The drain of the zeroth NMOS transistor is connected to the first voltage through the first current source. The source of the zeroth NMOS transistor is connected to the second voltage through the third current source. The gate and drain of the zeroth NMOS transistor are connected together. The gate of the first NMOS transistor is connected to the gate of the zeroth NMOS transistor. The drain of the MOS transistor is connected to the drain of the zeroth PMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are both connected to the second voltage through the fourth current source. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor. The gate of the second NMOS transistor is connected to the gate and drain of the third NMOS transistor. The drain of the third NMOS transistor is connected to the first voltage through the second current source. The source of the third NMOS transistor is connected to the second voltage through the fifth current source. The gate of the high-side NLDMOS transistor is connected to the drain of the first PMOS transistor. The source of the high-side NLDMOS transistor is connected to the source of the third NMOS transistor through the first resistor.

[0012] One end of the high-side voltage clamping unit is connected to the source of the zeroth NMOS transistor, and the other end of the high-side voltage clamping unit is connected to the drain of the high-side NLDMOS transistor. The clamping voltage output by the high-side voltage clamping unit is the first fixed value.

[0013] Optionally, the high-side voltage clamping unit includes a seventh current source and a first clamping resistor. One end of the seventh current source is connected to the source of the zeroth NMOS transistor and one end of the first clamping resistor. The other end of the seventh current source is connected to the second voltage, and the other end of the first clamping resistor is connected to the drain of the high-side NLDMOS transistor.

[0014] Optionally, the high-side compensation network includes a first capacitor, a second capacitor, and a second resistor. The two ends of the second capacitor are respectively connected to the gate and source of the high-side NLDMOS transistor. The branch formed by the second resistor and the first capacitor in series is connected in parallel with the second capacitor.

[0015] Optionally, the low-side clamping circuit includes the fourth to sixth PMOS transistors, the fifth NMOS transistor, the sixth NMOS transistor, the eighth current source, the ninth current source, and a low-side voltage clamping unit;

[0016] The sources of the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to a third voltage. The drain and gate of the fourth PMOS transistor are connected. The drain, gate, and gate of the fifth PMOS transistor are connected together. The drain of the sixth PMOS transistor is grounded through the ninth current source. The drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor. The sources of the fifth and sixth NMOS transistors are both grounded through the eighth current source. The drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor. The drain of the low-side NLDMOS transistor is connected to the gate of the sixth NMOS transistor through a third resistor. The gate of the low-side NLDMOS transistor is connected to the drain of the sixth PMOS transistor.

[0017] One end of the low-side voltage clamping unit is connected to the third voltage, the other end of the low-side voltage clamping unit is grounded, the output terminal of the low-side voltage clamping unit is connected to the gate of the fifth NMOS transistor, and the clamping voltage output by the low-side voltage clamping unit is the second fixed value.

[0018] Optionally, the low-side voltage clamping unit includes a tenth current source and a second clamping resistor. The first terminal of the tenth current source is connected to the third voltage, the second terminal of the tenth current source is grounded through the second clamping resistor, and the second terminal of the tenth current source is connected to the gate of the fifth NMOS transistor.

[0019] Optionally, the low-side compensation network includes a third capacitor, a fourth capacitor, and a fourth resistor. The two ends of the fourth capacitor are respectively connected to the gate and source of the low-side NLDMOS transistor. The branch formed by the fourth resistor and the third capacitor connected in series is connected in parallel with the fourth capacitor.

[0020] Optionally, the first fixed value is greater than half the amplitude of the signal on the first bus and the sum of Vdsat of the high-side NLDMOS transistor, and the second fixed value is greater than half the amplitude of the signal on the second bus and the sum of Vdsat of the low-side NLDMOS transistor.

[0021] According to another aspect of the present invention, the present invention also provides a Power over BUS system, comprising:

[0022] The inductor simulator module as described above;

[0023] First working module;

[0024] Second working module;

[0025] A first bus, the first end of which is connected to the source of the high-side NLDMOS transistor, and the second end of which is connected to the first working module;

[0026] The second bus has a first end connected to the first working module and a second end connected to the drain of the low-side NLDMOS transistor.

[0027] A capacitive coupling unit is provided, which connects the first bus, the second bus, the first working module, and the second working module. The capacitive coupling unit communicates between the first working module and the second working module through capacitive coupling.

[0028] Optionally, the capacitive coupling unit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor. The first working module is connected to the second bus through the fifth capacitor, the first working module is connected to the first bus through the sixth capacitor, the second working module is connected to the first bus through the seventh capacitor, and the second working module is connected to the second bus through the eighth capacitor.

[0029] The inductor simulator module described above clamps the Vds voltage drop of the high-side NLDMOS transistor to a first fixed value through a high-side clamping circuit, simulating on-chip inductors with larger inductance values. The high-side compensation network ensures the stability of the entire high-side clamping circuit loop. Correspondingly, the low-side clamping circuit clamps the Vds voltage drop of the low-side NLDMOS transistor to a second fixed value, simulating on-chip inductors with larger inductance values. The low-side compensation network ensures the stability of the entire low-side clamping circuit loop. Thus, the inductor simulator module of this invention can simulate two separate inductors in a Power over Bus system, realizing the function of a differential inductor. Considering that the impedance of a PMOS transistor is greater than that of an NMOS transistor of the same area, the transistors used in this invention to simulate inductors are all NLDMOS transistors, rather than PMOS transistors, which can further reduce the active inductor architecture area of ​​the NLDMOS transistor, making it suitable for high-current Power over Bus systems. In addition, the inductor simulator module of the present invention is also fully compatible with single-ended signal transmission systems. It can use either a high-side inductor simulator or a low-side inductor simulator to simulate inductance. The inductor simulator proposed in this invention can reduce on-chip capacitance while ensuring good transient response, thus saving chip area.

[0030] It should be noted that the Power over BUS system includes the inductor simulator module, and therefore also has the technical effects brought by the inductor simulator module, which will not be repeated here. Attached Figure Description

[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0032] Figure 1 This is a schematic diagram of a Power over Bus system;

[0033] Figure 2 This is a schematic diagram of a high-side inductor simulator of an inductor simulator module according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of a low-side inductor simulator of an inductor simulator module according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of a Power over BUS system according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0037] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] This invention illustratively provides an inductor simulator module for a Power over Bus system. The inductor simulator module includes a high-side inductor simulator and a low-side inductor simulator. The high-side inductor simulator simulates an on-chip inductor with a relatively large inductance value, and the low-side inductor simulator also simulates an on-chip inductor with a relatively large inductance value. The on-chip inductors simulated by the high-side and low-side inductor simulators are then applied to the Power over Bus system to achieve the function of a differential inductor. The high-side and low-side inductor simulators of this invention will be described in detail below.

[0039] Figure 2 This is a schematic diagram of a high-side inductor simulator according to an embodiment of the present invention. (See attached diagram.) Figure 2The high-side inductor simulator includes a high-side clamping circuit 11, a high-side compensation network 12, and a high-side NLDMOS transistor Q1. The drain of the high-side NLDMOS transistor Q1 is connected to the power supply VP, and the source of the high-side NLDMOS transistor Q1 serves as the BP terminal, connected to the first bus BUS+ of the Power over BUS system. The high-side clamping circuit 11 connects the drain and source of the high-side NLDMOS transistor Q1 to clamp the Vds of the high-side NLDMOS transistor Q1 to a first fixed value, ensuring that the high-side NLDMOS transistor Q1 always operates in the saturation region and achieves optimal inductor simulation performance. The high-side compensation network 12 connects the gate and source of the high-side NLDMOS transistor Q1 to provide zero-point compensation to the high-side NLDMOS transistor Q1. Thus, by clamping the Vds voltage drop of the high-side NLDMOS transistor Q1 to a first fixed value through the high-side clamping circuit 11, a larger on-chip inductance value can be simulated, ensuring that the Vds voltage drop of the high-side NLDMOS transistor Q1 is greater than the signal jitter on the bus, and ensuring that a sufficiently large current can still be provided to the bus during signal jitter. The gate of the high-side NLDMOS transistor Q1 is the dominant pole of the entire high-side clamping circuit 11 loop, and the high-side compensation network 12 provides zero-point compensation here to ensure the stability of the entire high-side clamping circuit 11 loop.

[0040] In one embodiment, the first fixed value is greater than half the amplitude of the signal on the first bus BUS+ and the sum of Vdsat (saturation drain-source voltage) of the high-side NLDMOS transistor Q1. This ensures that the high-side NLDMOS transistor Q1 remains in the saturation region during signal transmission, thereby achieving optimal inductor analog performance and still transmitting a sufficiently large current to the bus even during signal jitter. For example, for a signal with an amplitude of 3Vpp on the bus, the Vds voltage drop of the high-side NLDMOS transistor Q1 needs to be greater than (1.5Vpp + Vdsat). For instance, if Vpp is 1V and Vdsat is 500mV, the high-side clamping circuit 11 needs to clamp the Vds voltage drop of the high-side NLDMOS transistor Q1 to a value greater than 2V.

[0041] In one embodiment, the high-side clamping circuit 11 includes a zeroth to a second PMOS transistor, a zeroth to a third NMOS transistor, a high-side voltage clamping unit, and a first to a sixth current source. The source of the zeroth PMOS transistor PM0, the source of the first PMOS transistor PM1, and the source of the second PMOS transistor PM2 are all connected to a first voltage Vc1. The drain and gate of the zeroth PMOS transistor PM0 and the gate of the first PMOS transistor PM1 are connected together. The drain of the first PMOS transistor is connected to a second voltage Vc2 through the sixth current source IS6. The gate and drain of the second PMOS transistor PM2 are connected together. The drain of the zeroth NMOS transistor NM0 is connected to the first voltage Vc1 through the first current source IS1. The source of the zeroth NMOS transistor NM0 is connected to the second voltage Vc2 through the third current source IS3. The gate and drain of the zeroth NMOS transistor NM0 are connected together. The first NMOS transistor NM1... The gate of the first NMOS transistor NM1 is connected to the gate of the zeroth NMOS transistor NM0. The drain of the first NMOS transistor NM1 is connected to the drain of the zeroth PMOS transistor PM0. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are both connected to the second voltage Vc2 through the fourth current source IS4. The drain of the second NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2. The gate of the second NMOS transistor NM2 is connected to the gate and drain of the third NMOS transistor NM3. The drain of the third NMOS transistor NM3 is connected to the first voltage Vc1 through the second current source IS2. The source of the third NMOS transistor NM3 is connected to the second voltage Vc2 through the fifth current source IS5. The gate of the high-side NLDMOS transistor Q1 is connected to the drain of the first PMOS transistor PM1. The source of the high-side NLDMOS transistor Q1 is connected to the source of the third NMOS transistor NM3 through the first resistor R1. One end of the high-side voltage clamping unit is connected to the source of the zeroth NMOS transistor NM0, and the other end of the high-side voltage clamping unit is connected to the drain of the high-side NLDMOS transistor Q1. The clamping voltage output by the high-side voltage clamping unit is the first fixed value.

[0042] It should be noted that the first voltage Vc1 is preferably provided by a charge pump to ensure a sufficiently large voltage margin. Furthermore, the active architecture of the aforementioned high-side inductor simulator does not have high requirements for the driving capability and response capability of the charge pump; therefore, the charge pump in this application will not occupy a large chip area compared to the high-side NLDMOS transistor Q1. The second voltage Vc2 is a floating source voltage, less than the power supply voltage VP and also less than the first voltage Vc1; for example, the second voltage Vc2 is -5V. The dimensions of the zeroth NMOS transistor NM0 and the third NMOS transistor NM3 are equal. The constant currents provided by the first current source IS1, the second current source IS2, the third current source IS3, the fifth current source IS5, and the sixth current source IS6 are all I0, while the constant current provided by the fourth current source IS4 is 2I0. Figure 2 The demonstrated Rg1 is the gate resistance of the high-side NLDMOS transistor Q1.

[0043] Thus, when the loop of the high-side clamping circuit 11 is stable, the differential pair input voltages formed by the first NMOS transistor NM1 and the second NMOS transistor NM2 are clamped to be consistent. The dimensions of the zeroth NMOS transistor NM0 and the third NMOS transistor NM3 are equal, and the current flowing through them is equal. Therefore, the source voltage of the zeroth NMOS transistor NM0 is equal to the source voltage of the third NMOS transistor NM3, that is, Va equals Vb. The clamping voltage output by the high-side voltage clamping unit is defined as Vx. Then Va = VP - Vx, therefore Vb = VP - Vx. Since Vb is equal to the voltage at the BP terminal, the source voltage of the high-side NLDMOS transistor Q1 is equal to Vb, and the Vds of the high-side NLDMOS transistor Q1 is Vp - Vb = Vx.

[0044] In one embodiment, the high-side voltage clamping unit includes a seventh current source IS7 and a first clamping resistor Rx. One end of the seventh current source IS7 is connected to the source of the zeroth NMOS transistor NM0 and one end of the first clamping resistor Rx. The other end of the seventh current source IS7 is connected to the second voltage Vc2, and the other end of the first clamping resistor Rx is connected to the drain of the high-side NLDMOS transistor Q1. The constant current provided by the seventh current source IS7 is I1. Thus, Vx = I1 * Rx.

[0045] In one embodiment, the high-side compensation network 12 includes a first capacitor C1, a second capacitor C2, and a second resistor R2. The two ends of the second capacitor C2 are respectively connected to the gate and source of the high-side NLDMOS transistor Q1. The branch formed by the second resistor R2 and the first capacitor C1 connected in series is connected in parallel with the second capacitor C2.

[0046] Figure 3 This is a schematic diagram of a low-side inductor simulator according to an embodiment of the present invention. (See attached diagram.) Figure 3The low-side inductor simulator includes a low-side clamping circuit 21, a low-side compensation network 22, and a low-side NLDMOS transistor Q2. The drain of the low-side NLDMOS transistor Q2 is connected to the second bus BUS- of the Power over BUS system as the BN terminal, and the source of the low-side NLDMOS transistor Q2 is grounded. The low-side clamping circuit 21 is connected to the drain and source of the low-side NLDMOS transistor Q2 to clamp the Vds of the low-side NLDMOS transistor Q2 to a second fixed value, so that the low-side NLDMOS transistor Q2 always operates in the saturation region and obtains the best inductor simulation performance. The low-side compensation network 22 is connected to the gate and source of the low-side NLDMOS transistor Q2 to provide zero-point compensation to the low-side NLDMOS transistor Q2. Thus, by clamping the Vds voltage drop of the low-side NLDMOS transistor Q2 to a second fixed value through the low-side clamping circuit 21, a larger on-chip inductance value can be simulated, ensuring that the Vds voltage drop of the low-side NLDMOS transistor Q2 is greater than the signal jitter on the bus, and ensuring that a sufficiently large current can still be provided to the bus during signal jitter. The gate of the low-side NLDMOS transistor Q2 is the dominant pole of the entire low-side clamping circuit 21 loop, and the low-side compensation network 22 provides zero-point compensation here to ensure the stability of the entire low-side clamping circuit 21 loop. Understandably, Figure 3 The “GND” symbol indicates grounding.

[0047] In one embodiment, the second fixed value is greater than the sum of half the amplitude of the signal on the second bus BUS- and the Vdsat of the low-side NLDMOS transistor Q2. This can be understood by referring to the description of the first fixed value in the high-side inductor simulator, and will not be repeated here.

[0048] In one embodiment, the low-side clamping circuit 21 includes a fourth to sixth PMOS transistor, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, an eighth current source IS8, a ninth current source IS9, and a low-side voltage clamping unit 210; the sources of the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 are all connected to a third voltage Vreg; the drain and gate of the fourth PMOS transistor PM4 are connected; the drain, gate, and gate of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected together; the fourth PMOS transistor PM4... The drain of the sixth PMOS transistor PM6 is grounded through the ninth current source IS9. The drain of the fifth NMOS transistor NM5 is connected to the drain of the fourth PMOS transistor PM4. The sources of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are both grounded through the eighth current source IS8. The drain of the sixth NMOS transistor NM6 is connected to the drain of the fifth PMOS transistor PM5. The drain of the low-side NLDMOS transistor Q2 is connected to the gate of the sixth NMOS transistor NM6 through the third resistor R3. The gate of the low-side NLDMOS transistor Q2 is connected to the drain of the sixth PMOS transistor PM6. One end of the low-side voltage clamping unit 210 is connected to the third voltage Vreg, and the other end of the low-side voltage clamping unit 210 is grounded. The output of the low-side voltage clamping unit 210 is connected to the gate of the fifth NMOS transistor NM5, and the clamping voltage output by the low-side voltage clamping unit 210 is the second fixed value. It should be noted that the constant current provided by the eighth current source IS8 is 2I0, and the constant current provided by the ninth current source IS9 is I0. Figure 3 The demonstrated Rg2 is the gate resistor of the low-side NLDMOS transistor Q2. The third voltage Vreg can be provided by the chip's internal power supply VP, for example, 5V.

[0049] Thus, when the loop of the low-side clamping circuit 21 is stable, the differential pair input voltages formed by the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are clamped to be the same, and the gate voltage of the fifth NMOS transistor NM5 is equal to the gate voltage of the sixth NMOS transistor NM6. The clamping voltage output by the low-side voltage clamping unit 210 is defined as Vy, then the gate voltage of the fifth NMOS transistor NM5 is Vy, and the voltage at the BN terminal is Vy. Therefore, the Vds of the low-side NLDMOS transistor Q2 is Vy - 0 = Vy.

[0050] In one embodiment, the low-side voltage clamping unit 210 includes a tenth current source IS10 and a second clamping resistor Ry. The first terminal of the tenth current source IS10 is connected to the third voltage Vreg, and the second terminal of the tenth current source IS10 is grounded through the second clamping resistor Ry. The second terminal of the tenth current source IS10 is connected to the gate of the fifth NMOS transistor NM5. The constant current provided by the tenth current source IS10 is I0. Thus, Vy = I0 * Ry.

[0051] In one embodiment, the low-side compensation network 22 includes a third capacitor C3, a fourth capacitor C4, and a fourth resistor R4. The two ends of the fourth capacitor C4 are respectively connected to the gate and source of the low-side NLDMOS transistor Q2. The branch formed by the third resistor R3 and the third capacitor C3 connected in series is connected in parallel with the fourth capacitor C4.

[0052] It should be noted that in actual design, the bandwidth of the high-side inductor simulator and the low-side inductor simulator must be much smaller than the signal rate to ensure that the inductor simulator does not respond when the signal jitters. That is, when the signal jitters, the DC gate-source voltage (DC Vgs) of the NLDMOS does not change much, thus ensuring that the NLDMOS current does not change abruptly, approximating the characteristics of an inductor.

[0053] Figure 4 This is a schematic diagram of a Power over BUS system according to an embodiment of the present invention. Based on the aforementioned inductor simulator module, this embodiment of the present invention provides a Power over BUS system, the system including the aforementioned inductor simulator module, a first working module A, a second working module B, a first bus BUS+, a second bus BUS-, and a capacitive coupling unit. The first end of the first bus BUS+ is connected to the source of the high-side NLDMOS transistor Q1, the second end of the first bus BUS+ is connected to the first working module A, the first end of the second bus BUS- is connected to the first working module A, and the second end of the second bus BUS- is connected to the drain of the low-side NLDMOS transistor Q2. The capacitive coupling unit connects the first bus BUS+, the second bus BUS-, the first working module A, and the second working module B, and the capacitive coupling unit communicates between the first working module A and the second working module B through capacitive coupling.

[0054] For example, the first working module A is the air conditioner wired controller, and the second working module B is the air conditioner indoor unit.

[0055] Furthermore, the Power over BUS system also includes an MCU, which is communicatively connected to the second working module B and interacts with it. The second working module B and the MCU are connected to an external bus BUS_C for obtaining power.

[0056] In one embodiment, the capacitive coupling unit includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. The first working module A is connected to the second bus BUS- through the fifth capacitor C5, the first working module A is connected to the first bus BUS+ through the sixth capacitor C6, the second working module B is connected to the first bus BUS+ through the seventh capacitor C7, and the second working module B is connected to the second bus BUS- through the eighth capacitor C8.

[0057] In summary, the inductor simulator module of this invention clamps the Vds voltage drop of the high-side NLDMOS transistor to a first fixed value through a high-side clamping circuit, enabling the simulation of on-chip inductors with larger inductance values. The high-side compensation network ensures the stability of the entire high-side clamping circuit loop. Correspondingly, the low-side clamping circuit clamps the Vds voltage drop of the low-side NLDMOS transistor to a second fixed value, enabling the simulation of on-chip inductors with larger inductance values. The low-side compensation network also ensures the stability of the entire low-side clamping circuit loop. Thus, the inductor simulator module of this invention can simulate two separate inductors in a Power over Bus system, realizing the function of a differential inductor. Considering that the impedance of a PMOS transistor is greater than that of an NMOS transistor of the same area, the transistors used in this invention to simulate inductors are all NLDMOS transistors, rather than PMOS transistors, which can further reduce the active inductor architecture area of ​​the NLDMOS transistor, making it suitable for high-current Power over Bus systems. In addition, the inductor simulator module of the present invention is also fully compatible with single-ended signal transmission systems. It can use either a high-side inductor simulator or a low-side inductor simulator to simulate inductance. The inductor simulator proposed in this invention can reduce on-chip capacitance while ensuring good transient response, thus saving chip area.

[0058] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. An inductor simulator module, applied in a Power over Bus system, characterized in that, The inductor simulator module includes a high-side inductor simulator and a low-side inductor simulator; The high-side inductor simulator includes a high-side clamping circuit, a high-side compensation network, and a high-side NLDMOS transistor. The drain of the high-side NLDMOS transistor is connected to a power supply, and the source of the high-side NLDMOS transistor is connected to the first bus of the Power over BUS system. The high-side clamping circuit connects the drain and source of the high-side NLDMOS transistor to clamp the Vds of the high-side NLDMOS transistor to a first fixed value, so that the high-side NLDMOS transistor always operates in the saturation region. The high-side compensation network connects the gate and source of the high-side NLDMOS transistor to provide zero-point compensation to the high-side NLDMOS transistor. The Vds of the high-side NLDMOS transistor is the drain-source voltage drop of the high-side NLDMOS transistor. The low-side inductor simulator includes a low-side clamping circuit, a low-side compensation network, and a low-side NLDMOS transistor. The drain of the low-side NLDMOS transistor is connected to the second bus of the Power over BUS system, and the source of the low-side NLDMOS transistor is grounded. The low-side clamping circuit connects the drain and source of the low-side NLDMOS transistor to clamp the Vds of the low-side NLDMOS transistor to a second fixed value, so that the low-side NLDMOS transistor always operates in the saturation region. The low-side compensation network connects the gate and source of the low-side NLDMOS transistor to provide zero-point compensation to the low-side NLDMOS transistor. The Vds of the low-side NLDMOS transistor is the drain-source voltage drop of the low-side NLDMOS transistor.

2. The inductor simulator module according to claim 1, characterized in that, The high-side clamping circuit includes the zeroth to second PMOS transistors, the zeroth to third NMOS transistors, a high-side voltage clamping unit, and the first to sixth current sources; The source of the zeroth PMOS transistor, the source of the first PMOS transistor, and the source of the second PMOS transistor are all connected to a first voltage. The drain and gate of the zeroth PMOS transistor are connected together with the gate of the first PMOS transistor. The drain of the first PMOS transistor is connected to a second voltage through the sixth current source. The gate and drain of the second PMOS transistor are connected together. The drain of the zeroth NMOS transistor is connected to the first voltage through the first current source. The source of the zeroth NMOS transistor is connected to the second voltage through the third current source. The gate and drain of the zeroth NMOS transistor are connected together. The gate of the first NMOS transistor is connected to the gate of the zeroth NMOS transistor. The drain of the MOS transistor is connected to the drain of the zeroth PMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are both connected to the second voltage through the fourth current source. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor. The gate of the second NMOS transistor is connected to the gate and drain of the third NMOS transistor. The drain of the third NMOS transistor is connected to the first voltage through the second current source. The source of the third NMOS transistor is connected to the second voltage through the fifth current source. The gate of the high-side NLDMOS transistor is connected to the drain of the first PMOS transistor. The source of the high-side NLDMOS transistor is connected to the source of the third NMOS transistor through the first resistor. One end of the high-side voltage clamping unit is connected to the source of the zeroth NMOS transistor, and the other end of the high-side voltage clamping unit is connected to the drain of the high-side NLDMOS transistor. The clamping voltage output by the high-side voltage clamping unit is the first fixed value.

3. The inductor simulator module according to claim 2, characterized in that, The high-side voltage clamping unit includes a seventh current source and a first clamping resistor. One end of the seventh current source is connected to the source of the zeroth NMOS transistor and one end of the first clamping resistor. The other end of the seventh current source is connected to the second voltage. The other end of the first clamping resistor is connected to the drain of the high-side NLDMOS transistor.

4. The inductor simulator module according to claim 1, characterized in that, The high-side compensation network includes a first capacitor, a second capacitor, and a second resistor. The two ends of the second capacitor are respectively connected to the gate and source of the high-side NLDMOS transistor. The branch formed by the second resistor and the first capacitor in series is connected in parallel with the second capacitor.

5. The inductor simulator module according to claim 1, characterized in that, The low-side clamping circuit includes the fourth to sixth PMOS transistors, the fifth NMOS transistor, the sixth NMOS transistor, the eighth current source, the ninth current source, and a low-side voltage clamping unit; The sources of the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to a third voltage. The drain and gate of the fourth PMOS transistor are connected. The drain, gate, and gate of the fifth PMOS transistor are connected together. The drain of the sixth PMOS transistor is grounded through the ninth current source. The drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor. The sources of the fifth and sixth NMOS transistors are both grounded through the eighth current source. The drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor. The drain of the low-side NLDMOS transistor is connected to the gate of the sixth NMOS transistor through a third resistor. The gate of the low-side NLDMOS transistor is connected to the drain of the sixth PMOS transistor. One end of the low-side voltage clamping unit is connected to the third voltage, the other end of the low-side voltage clamping unit is grounded, the output terminal of the low-side voltage clamping unit is connected to the gate of the fifth NMOS transistor, and the clamping voltage output by the low-side voltage clamping unit is the second fixed value.

6. The inductor simulator module according to claim 5, characterized in that, The low-side voltage clamping unit includes a tenth current source and a second clamping resistor. The first end of the tenth current source is connected to the third voltage, and the second end of the tenth current source is grounded through the second clamping resistor. The second end of the tenth current source is connected to the gate of the fifth NMOS transistor.

7. The inductor simulator module according to claim 1, characterized in that, The low-side compensation network includes a third capacitor, a fourth capacitor, and a fourth resistor. The two ends of the fourth capacitor are connected to the gate and source of the low-side NLDMOS transistor, respectively. The branch formed by the fourth resistor and the third capacitor connected in series is connected in parallel with the fourth capacitor.

8. The inductor simulator module according to claim 1, characterized in that, The first fixed value is greater than half the amplitude of the signal on the first bus and the sum of Vdsat of the high-side NLDMOS transistor; the second fixed value is greater than half the amplitude of the signal on the second bus and the sum of Vdsat of the low-side NLDMOS transistor; the Vdsat of the high-side NLDMOS transistor is the saturation drain-source voltage of the high-side NLDMOS transistor, and the Vdsat of the low-side NLDMOS transistor is the saturation drain-source voltage of the low-side NLDMOS transistor.

9. A Power over Bus system, characterized in that, include: The inductor simulator module according to any one of claims 1-8; First working module; Second working module; A first bus, the first end of which is connected to the source of the high-side NLDMOS transistor, and the second end of which is connected to the first working module; The second bus has a first end connected to the first working module and a second end connected to the drain of the low-side NLDMOS transistor. A capacitive coupling unit is provided, which connects the first bus, the second bus, the first working module, and the second working module. The capacitive coupling unit communicates between the first working module and the second working module through capacitive coupling.

10. The Power over BUS system according to claim 9, characterized in that, The capacitive coupling unit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor. The first working module is connected to the second bus through the fifth capacitor, the first working module is connected to the first bus through the sixth capacitor, the second working module is connected to the first bus through the seventh capacitor, and the second working module is connected to the second bus through the eighth capacitor.

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