Duty cycle correction circuit

Abstract

The duty cycle correction circuit includes a duty cycle adjustment circuit and a duty cycle control circuit. The duty cycle adjustment circuit generates multiple duty cycle correction clock signals by adjusting the phase of multiple external clock signals according to multiple codes. The duty cycle control circuit controls a first correction operation that finds and fixes the optimal value of a first code among the multiple codes, and a second correction operation that finds and fixes the optimal value of a second code among the multiple codes. The duty cycle control circuit is configured to change the first code in basic units within a first adjustable range and change the second code by the maximum value within a second adjustable range in each of the multiple cycles executing the first correction operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0040207, filed on March 28, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure generally relate to a semiconductor circuit, and more specifically, to a duty cycle correction circuit. Background Technology

[0004] In clock-based semiconductor circuits (such as semiconductor memories and the central processing unit (CPU) or graphics processing unit (GPU) that controls them), precise control of the clock signal's duty cycle is crucial. For example, in semiconductor memory, data is input and output at the rising and falling edges of the clock signal. If the duty cycle is not exactly 50%, a timing deviation occurs between the rising and falling edges, causing data to fail to be input or output correctly at the expected timing. Here, a 50% duty cycle means that the duration of the "high" level period and the "low" level period of the clock signal are equal. Therefore, in various clock-based semiconductor circuits, it is essential to use a duty cycle correction circuit to correct the clock signal's duty cycle. A duty cycle correction circuit includes a first delay circuit and a second delay circuit, with the first delay circuit controlled according to a first code and the second delay circuit controlled according to a second code. The duty cycle correction circuit performs duty cycle correction by adjusting the values ​​of the first and second codes based on the phase difference between the two signals output by the second delay circuit.

[0005] Figure 1 An example of code changes during duty cycle correction operations according to existing technology is shown. In this example, the first code is adjusted to "2" and the second code is adjusted to "4", thus successfully adjusting the clock signal duty cycle to 50% within an acceptable error range. Here, "2" and "4" refer to the step size, not the code value. The first code is based on a binary encoding method, with a different value for each step; while the second code is based on a Gray code method, with a different value for each step. The Gray code method increases or decreases the number of bits with a value of "1" (binary) or "0" (binary) by 1 for each step increase or decrease.

[0006] Reference Figure 1Traditional duty cycle correction circuits operate by fixing the first code at "0" and gradually incrementing the second code from "0". When the second code reaches its maximum step size of "8", the first code increments by one step, and the second code decrements by one step. The duty cycle correction operation is accomplished by detecting the "bang-bang" state between the first and second codes. When the time for changing the code by one step is defined as one cycle, detecting the bang-bang state of the second code, specifically the repetition of "4" and "5", requires 24 cycles. The problem with existing technology is the increased time required to lock the time or complete the duty cycle correction. Summary of the Invention

[0007] In one embodiment, a duty cycle correction circuit may include: a duty cycle adjustment circuit configured to adjust the phase of a plurality of external clock signals according to a plurality of codes to generate a plurality of duty cycle correction clock signals; and a duty cycle control circuit configured to control a first correction operation that finds and fixes an optimal value of a first code among the plurality of codes and a second correction operation that finds and fixes an optimal value of a second code among the plurality of codes. The duty cycle control circuit is configured to change the first code in basic units within a first adjustable range and change the second code by a maximum value within a second adjustable range in each of a plurality of cycles in which the first correction operation is performed.

[0008] In an embodiment, a duty cycle correction circuit may include: a duty cycle adjustment circuit configured to adjust the phase of a plurality of external clock signals according to a plurality of codes to generate a plurality of duty cycle correction clock signals; a duty cycle detection circuit configured to generate a plurality of duty cycle detection signals according to the plurality of duty cycle correction clock signals; a code adjustment clock generation circuit configured to generate a plurality of code adjustment clock signals for changing a second code among the plurality of codes by a maximum value within an adjustable range in each of a plurality of cycles in a first segment, the first segment including a time frame from the start time of adjustment of a first code among the plurality of codes to the time of adjustment of the first code to activate a first code adjustment completion signal; a multiplexer configured to selectively output a plurality of code adjustment clock signals and a plurality of duty cycle detection valid signals according to the first code adjustment completion signal; a first code adjustment circuit configured to change a first code according to the plurality of duty cycle detection valid signals and configured to generate a first code minimum detection signal and a first code maximum detection signal according to the first code; and a second code adjustment circuit configured to change a second code according to the output of the multiplexer. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating an example of code changes during duty cycle correction operations based on existing technology.

[0010] Figure 2This is a diagram illustrating the configuration of a duty cycle correction circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram illustrating the configuration of the first adjustment circuit.

[0012] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram illustrating the configuration of the second adjustment circuit.

[0013] Figure 5 This is a diagram illustrating a method for modifying second code according to an embodiment of the present disclosure.

[0014] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram illustrating the configuration of the duty cycle control circuit.

[0015] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6 The code in the diagram shows the detailed configuration of the clock generation circuit.

[0016] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 7 A diagram showing the detailed configuration of the shifting units in the diagram.

[0017] Figure 9 It is used to describe embodiments according to this disclosure. Figure 7 The code in the diagram adjusts the timing of the clock generation circuit.

[0018] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 6 The diagram shows the detailed configuration of the circuit.

[0019] Figure 11 It is used to describe embodiments according to this disclosure. Figure 10 The timing diagram for determining the operation of the circuit.

[0020] Figure 12 This illustrates an embodiment according to the present disclosure. Figure 6 The code value in the diagram determines the detailed configuration of the circuit.

[0021] Figures 13 to 18 This is a timing diagram used to describe the duty cycle correction operation of a duty cycle correction circuit according to an embodiment of the present disclosure.

[0022] Figure 19 This is a diagram illustrating an example of code changes during duty cycle correction operation according to an embodiment of the present disclosure. Detailed Implementation

[0023] Various embodiments of this disclosure can reduce the time required for duty cycle correction, thereby ensuring timing margin and improving the resolution of duty cycle correction.

[0024] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0025] Figure 2 This is a diagram illustrating the configuration of a duty cycle correction circuit 100 according to an embodiment of the present disclosure.

[0026] Reference Figure 2 The duty cycle correction circuit 100 may include a duty cycle adjustment circuit 101, a phase divider circuit 102, a duty cycle detection circuit 103, and a duty cycle control circuit 104.

[0027] Duty cycle adjustment circuit 101 can receive multiple external clock signals RE-C and RE-N, as well as multiple codes CC. <m:0>、CF <n:0>、NC <m:0>and NF <n:0>It can output multiple duty cycle correction clock signals RE-C-DCC and RE-N-DCC. The duty cycle adjustment circuit 101 may include a first duty cycle adjustment circuit 101A and a second duty cycle adjustment circuit 101B.

[0028] Multiple external clock signals RE-C and RE-N may include a first external clock signal RE-C and a second external clock signal RE-N.

[0029] Multiple code CC <m:0>、CF <n:0>、NC <m:0>and NF <n:0>It can be classified as the first code set CC related to the phase correction of the first external clock signal RE-C. <m:0>and CF <n:0>And the second code set NC related to the phase correction of the second external clock signal RE-N. <m:0>and NF <n:0>And it can be selectively adjusted. In the first code set CC <m:0>and CF <n:0>In the middle, CC <m:0>Called the first code, CF <n:0>This is called the second code. In the second code set NC <m:0>and NF <n:0>In China, NC <m:0>It is called the third code, NF <n:0>This is called the fourth code. During duty cycle correction operation, the first code set CC can be selected based on the operating conditions. <m:0>and CF <n:0>and the second code set NC <m:0>and NF <n:0>One of them. Although, in order to distinguish, NC <m:0>and NF <n:0>They are called the third and fourth codes, but if the second code set NC is chosen... <m:0>and NF <n:0>The third code NC is used for phase correction of the second external clock signal RE-N. <m:0>With the first code CC <m:0>Correspondingly, the fourth code NF is used. <n:0>With the second code CF <n:0>Use accordingly.

[0030] First code CC <m:0>Second Code CF <n:0>It can be used for phase adjustment in the first duty cycle adjustment circuit 101A. Third code NC <m:0>and the fourth code NF <n:0>It can be used for phase adjustment of the second duty cycle adjustment circuit 101B. The multiple duty cycle correction clock signals RE-C-DCC and RE-N-DCC may include the first duty cycle correction clock signal RE-C-DCC and the second duty cycle correction clock signal RE-N-DCC.

[0031] The first duty cycle adjustment circuit 101A can receive the first external clock signal RE-C and the first code CC. <m:0>Second Code CF <n:0>It can also output the first duty cycle correction clock signal RE-C-DCC.

[0032] The second duty cycle adjustment circuit 101B can receive the second external clock signal RE-N and the third code NC. <m:0>and the fourth code NF <n:0>It can also output a second duty cycle correction clock signal RE-N-DCC.

[0033] The first duty cycle adjustment circuit 101A may include a first adjustment circuit 200 and a second adjustment circuit 300. The first adjustment circuit 200 may delay the first external clock signal RE-C and the first code CC. <m:0>The corresponding time is used to generate the first clock signal FCK and the second clock signal SCK. The second adjustment circuit 300 can adjust according to the second code CF. <n:0>A first clock signal FCK and a second clock signal SCK are mixed in a predetermined ratio to generate a first duty cycle corrected clock signal RE-C-DCC. The term "predetermined" as used herein for parameters (such as predetermined timing, time, or voltage levels) indicates that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but not before the parameter is used in the process or algorithm.

[0034] The second duty cycle adjustment circuit 101B can be configured similarly to the first duty cycle adjustment circuit 101A.

[0035] The phase divider circuit 102 can receive a first duty cycle corrected clock signal RE-C-DCC and a second duty cycle corrected clock signal RE-N-DCC, and can output multi-phase clock signals ICK, IBCK, QCK, and QBCK. The phase divider circuit 102 can divide the phases of the first duty cycle corrected clock signal RE-C-DCC and the second duty cycle corrected clock signal RE-N-DCC to generate multi-phase clock signals ICK, IBCK, QCK, and QBCK.

[0036] The duty cycle detection circuit 103 can receive multi-phase clock signals ICK, IBCK, QCK, and QBCK, and can output multiple duty cycle detection signals DCD-OUTP and DCD-OUTN. The duty cycle detection circuit 103 can detect the phase difference between the multi-phase clock signals ICK, IBCK, QCK, and QBCK to generate multiple duty cycle detection signals DCD-OUTP and DCD-OUTN. The multiple duty cycle detection signals DCD-OUTP and DCD-OUTN may include a first duty cycle detection signal DCD-OUTP and a second duty cycle detection signal DCD-OUTN.

[0037] The duty cycle detection circuit 103 can output a signal obtained by adding the phase difference between QCK and IBCK and the phase difference between QBCK and ICK as a first duty cycle detection signal DCD-OUTP, and can output a signal obtained by adding the phase difference between ICK and QCK and the phase difference between IBCK and QBCK as a second duty cycle detection signal DCD-OUTN.

[0038] The duty cycle control circuit 104 can receive multiple control signals CTRLS and multiple duty cycle detection signals DCD-OUTP and DCD-OUTN, and can output multiple codes CC. <m:0>、CF <n:0>、NC <m:0>and NF <n:0>For example, multiple control signals CTRLS can be generated by a system (such as a semiconductor memory device or a memory controller for controlling a semiconductor memory device) including a duty cycle correction circuit 100 according to an embodiment of the present disclosure based on an external command or an internally determined sequence, and can be provided to the duty cycle correction circuit 100.

[0039] Duty cycle control circuit 104 can adjust multiple codes CC based on multiple duty cycle detection signals DCD-OUTP and DCD-OUTN. <m:0>、CF <n:0>、NC <m:0>and NF <n:0>The value of .

[0040] Adjust multiple codes CC based on multiple duty cycle detection signals DCD-OUTP and DCD-OUTN. <m:0>、CF <n:0>、NC <m:0>and NF <n:0>The operation of the duty cycle, i.e., the duty cycle correction operation, can include a first correction operation and a second correction operation. The duty cycle correction operation can be performed within a predetermined segment (hereinafter referred to as a segment) according to the operating specifications of the system including the duty cycle correction circuit 100. The entire segment for performing the duty cycle correction operation can include a first segment for the first correction operation and a second segment for the second correction operation. The first correction operation may include finding the first code CC. <m:0>and third code NC <m:0>The optimal value. The second correction operation may include finding the second code CF. <n:0>and the fourth code NF <n:0>The optimal value. Each of the first and second segments can include multiple cycles.

[0041] Duty cycle control circuit 104 can detect multiple CC codes. <m:0>、CF <n:0>、NC <m:0>and NF <n:0>Does a bang-bang state occur in the code, and can multiple code CCs be stopped when a bang-bang state is detected? <m:0>、CF <n:0>、NC <m:0>and NF <n:0>.

[0042] The duty cycle control circuit 104 can selectively control the first duty cycle adjustment circuit 101A and the second duty cycle adjustment circuit 101B. When the first duty cycle adjustment circuit 101A is selected, the duty cycle control circuit 104 can adjust the first code CC based on multiple duty cycle detection signals DCD-OUTP and DCD-OUTN. <m:0>Second Code CF <n:0>When the second duty cycle adjustment circuit 101B is selected, the duty cycle control circuit 104 can adjust the third code NC based on the duty cycle detection signals DCD-OUTP and DCD-OUTN. <m:0>and the fourth code NF <n:0>.

[0043] Since the operation of the duty cycle control circuit 104 in controlling the first duty cycle adjustment circuit 101A and the second duty cycle adjustment circuit 101B is similar, the control operation based on the first duty cycle adjustment circuit 101A will be described below.

[0044] The duty cycle control circuit 104 can change the first code CC in basic units within an adjustable range (e.g., a first adjustable range) during each cycle of the first segment. <m:0>And change the second code CF by the maximum value within the adjustable range (e.g., the second adjustable range). <n:0>To detect the first code CC <m:0>The bang-bang state is completed and the first correction operation is finished. Furthermore, the duty cycle control circuit 104 can fix the first code CC. <m:0>Furthermore, the second code CF is adjusted in basic units for each cycle of the second segment. <n:0>To detect the second code CF <n:0>The bang-bang state is completed and the second correction operation is finished.

[0045] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram showing the detailed configuration of the first adjustment circuit 200.

[0046] In the following description, the duty cycle correction circuit 100 is configured to cause multiple codes CC <m:0>、CF <n:0>、NC <m:0>and NF <n:0>Examples where m is 3 and n is 7.

[0047] Reference Figure 3 The first adjustment circuit 200 may include a delay control signal generation circuit 210 and a delay circuit 220.

[0048] The delay control signal generation circuit 210 can receive the first code CC<3:0> and can output multiple delay control signals F<2:1>, S<2:1>, and M<1:0>. The delay control signal generation circuit 210 may include multiple logic gates 211 to 216. The first logic gate 211 can output signals generated by controlling the first code CC<3:0>. <2> and the first code CC <3> The result obtained by performing a NOR operation is used as the delay control signal F. <1> The second logic gate 212 can output a delay control signal F. <1> The result obtained by inversion is used as the delay control signal F. <2> The third logic gate 213 can output the first code CC. <3> The result obtained by inversion is used as the delay control signal S. <1> The fourth logic gate 214 can output a delay control signal S. <1> The result obtained by inversion is used as the delay control signal S. <2> The fifth logic gate 215 can output the code CC through the first code. <2> and the first code CC <1> The result obtained by performing an XOR operation is used as the delay control signal M. <0> The sixth logic gate 216 can output the code CC through the first code. <0> and the first code CC <1> The result obtained by performing the XOR operation is used as the delay control signal M. <1> .

[0049] Delay circuit 220 can delay the first external clock signal RE-C by a time corresponding to a plurality of delay control signals F<2:1>, S<2:1>, and M<1:0> to generate a first clock signal FCK and a second clock signal SCK. Delay circuit 220 may include a first delay line 230, a second delay line 240, a first phase mixing circuit MX1 250, and a second phase mixing circuit MX2 260. First delay line 230 can delay the first external clock signal RE-C by a time corresponding to the plurality of delay control signals F<2:1> and can output the result. First delay line 230 can be configured with a plurality of logic gates (e.g., a plurality of NAND gates), and the delay time of the first external clock signal RE-C can be adjusted by changing the number of NAND gates through which the first external clock signal RE-C passes according to the plurality of delay control signals F<2:1>. Second delay line 240 can delay the first external clock signal RE-C by a time corresponding to the plurality of delay control signals S<2:1> and can output the result. The first phase mixing circuit 250 can output the outputs of the first delay line 230 and the second delay line 240 according to the delay control signal M. <0> The result is obtained by mixing in a predetermined ratio. The second phase mixing circuit 260 can output the result by mixing the outputs of the first delay line 230 and the second delay line 240 according to the delay control signal M. <1> The result obtained by mixing in a certain proportion is used as the first clock signal FCK and the second clock signal SCK.

[0050] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram showing the detailed configuration of the second adjustment circuit 300.

[0051] Reference Figure 4 The second adjustment circuit 300 may include an inverter circuit 301, multiple preamplifier circuits 310, 320, 330 and 340, and a main circuit 350.

[0052] Inverter circuit 301 can invert the first clock signal FCK, the second clock signal SCK, and the second code CF<7:0> to generate an inverted first clock signal FCKB, an inverted second clock signal SCKB, and an inverted second code CFB<7:0>. Inverter circuit 301 may include multiple inverters.

[0053] Multiple preamplifier circuits 310, 320, 330 and 340 can selectively output one of the inverted first clock signal FCKB and the inverted second clock signal SCKB according to the second code CF<7:0> and the inverted second code CFB<7:0>.

[0054] The first preamplifier circuit 310 can selectively output one of the inverted first clock signal FCKB and the inverted second clock signal SCKB according to the second codes CF0, CF4 and the inverted second codes CFB0, CFB4. The first preamplifier circuit 310 may include multiple logic gates 311 to 314. The outputs of the multiple logic gates 311 to 314 can be connected together to the first node ND1.

[0055] The second preamplifier circuit 320 can selectively output one of the inverted first clock signal FCKB and the inverted second clock signal SCKB according to the second codes CF1, CF5 and the inverted second codes CFB1, CFB5. The second preamplifier circuit 320 may include multiple logic gates 321 to 324. The outputs of the multiple logic gates 321 to 324 can be connected together to the second node ND2.

[0056] The third preamplifier circuit 330 can selectively output one of the inverted first clock signal FCKB and the inverted second clock signal SCKB based on the second codes CF2, CF6 and the inverted second codes CFB2, CFB6. The third preamplifier circuit 330 may include multiple logic gates 331 to 334. The outputs of the multiple logic gates 331 to 334 can be connected together to the third node ND3.

[0057] The fourth preamplifier circuit 340 can selectively output one of the inverted first clock signal FCKB and the inverted second clock signal SCKB based on the second codes CF3, CF7 and the inverted second codes CFB3, CFB7. The fourth preamplifier circuit 340 may include multiple logic gates 341 to 344. The outputs of the multiple logic gates 341 to 344 can be connected together to the fourth node ND4.

[0058] Since multiple preamplifier circuits 310, 320, 330, and 340 are similarly configured and operated, the configuration and operation of one preamplifier circuit (e.g., the first preamplifier circuit 310), representing the other preamplifier circuits, will be described. When the second code CF0 is at a logic high level, the first logic gate 311 can invert the first clock signal FCKB and output the result to the first node ND1. When the second code CF4 is at a logic low level, the second logic gate 312 can invert the second clock signal SCKB and output the result to the first node ND1. When the second code CF4 is at a logic high level, the third logic gate 313 can invert the first clock signal FCKB and output the result to the first node ND1. When the second code CF0 is at a logic low level, the fourth logic gate 314 can invert the second clock signal SCKB and output the result to the first node ND1.

[0059] The main circuit 350 can output a first duty cycle correction clock signal RE-C-DCC as the result of mixing the phases of signals output from multiple preamplifier circuits 310, 320, 330, and 340 (applied to the first to fourth nodes ND1 to ND4). The main circuit 350 may include multiple logic gates 351 to 356. The first logic gate 351 inverts the signal at the first node ND1 and outputs the result to the fifth node ND5. The second logic gate 352 inverts the signal at the second node ND2 and outputs the result to the sixth node ND6. The third logic gate 353 inverts the signal at the third node ND3 and outputs the result to the fifth node ND5. The fourth logic gate 354 inverts the signal at the fourth node ND4 and outputs the result to the sixth node ND6. The fifth logic gate 355 inverts the signal at the fifth node ND5 and outputs the result to the seventh node ND7. The sixth logic gate 356 inverts the signal at the sixth node ND6 and outputs the result to the seventh node ND7. The first duty cycle correction clock signal RE-C-DCC can be output through the seventh node ND7.

[0060] Figure 5 This is a diagram illustrating a method for modifying second code according to an embodiment of the present disclosure.

[0061] Reference Figure 5 This illustrates an example where the second code CF<7:0> is divided into "0" to "8". The configuration method of the second code CF<7:0> may vary depending on the code control method, circuit design method, etc. "0" to "8" represent the stages of the second code CF<7:0>, not decimal values. The second code CF<7:0> can have different values ​​in each stage according to the Gray code method. The Gray code method is a method where the number of bits with a value of "1" (binary) or "0" (binary) increases or decreases by 1 as the stage increases or decreases. For example, in the second code CF<7:0>, all bits in stage "0" can be set to "1", and when adjusting to stage "1", the CF<7:0> remains "1" while the other bits remain "1". <0> It can be changed to "0"; when adjusted to level "2", keep "1" in other bits and CF <0> CF with "0" <1> The level "1" can be changed to "0". As the level changes in the manner described above, the number of bits with a value of "1" can decrease, while the number of bits with a value of "0" can increase. Note that this example is provided for a specific explanation, and the following implementation is also possible: In level "0", all bits are initially set to "0", and as the level changes, the number of bits with a value of "0" decreases, while the number of bits with a value of "1" increases.

[0062] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 2 A detailed diagram showing the configuration of the duty cycle control circuit 104.

[0063] Reference Figure 6 The duty cycle control circuit 104 may include a code adjustment clock generation circuit 401, a first multiplexer MUX1 402, a first code adjustment circuit 403, a second code adjustment circuit 404, a second multiplexer MUX2 405, a completion determination circuit 406, a code value determination circuit 407, and a selection circuit 408. The duty cycle control circuit 104 may further include a timing control signal generation circuit 409. The timing control signal generation circuit 409 can generate multiple timing control signals TNCK-STT, DCD-VLD, CCHG-CT, CCHG-FT, and DCC-STT related to the operating timing of the duty cycle control circuit 104.

[0064] Figure 6 This is merely an example of the duty cycle control circuit 104 including a timing control signal generation circuit 409. In a system that includes a duty cycle correction circuit 100 but not the duty cycle correction circuit 100 itself, multiple timing control signals TNCK-STT, DCD-VLD, CCHG-CT, CCHG-FT and DCC-STT can be generated and provided to the duty cycle correction circuit 100.

[0065] The code adjustment clock generation circuit 401 can generate multiple code adjustment clock signals CCK-EV and CCK-OD to change the second code CF<7:0> by the maximum value within an adjustable range during each cycle of the first segment from the start time of the first code CC<3:0> to the activation time of the first code adjustment completion signal CCAL-DNE.

[0066] The code adjustment clock generation circuit 401 can also generate multiple code adjustment clock signals CCK-EV and CCK-OD to change the fourth code NF<7:0> by the maximum value within the adjustable range during each cycle of the first segment from the start time of adjustment of the third code NC<3:0> to the activation time of the first code adjustment completion signal CCAL-DNE.

[0067] The duty cycle correction circuit 100 can perform duty cycle correction operations by switching between the first code sets CC<3:0> and CF<7:0> and the second code sets NC<3:0> and NF<7:0>. The operation of the reference code value determination circuit 407, selection circuit 408, first code adjustment circuit 403, and second code adjustment circuit 404 will be described in detail later. Therefore, the code adjustment clock generation circuit 401 can receive the first code CC. <0> and third code NC <0> And selectively use one of them.

[0068] The code adjustment clock generation circuit 401 can receive the clock adjustment start signal TNCK-STT, the code set change signal CHN-SEL, and the first code CC. <0> and third code NC <0> The system includes the currently selected code, the first code increment limit detection signal CILMT, the first duty cycle detection valid signal DCD-OUTP-VLD, the first code adjustment complete signal CCAL-DNE, and the reset signal RSTB. It can also output multiple code adjustment clock signals CCK-EV and CCK-OD. These multiple code adjustment clock signals CCK-EV and CCK-OD can include the first adjustment clock signal CCK-EV and the second adjustment clock signal CCK-OD.

[0069] The first multiplexer 402 can receive multiple code adjustment clock signals CCK-EV and CCK-OD, a first duty cycle detection valid signal DCD-OUTP-VLD, a second duty cycle detection valid signal DCD-OUTN-VLD, and a first code adjustment complete signal CCAL-DNE. It can also output multiple code adjustment clock signals CCK-EV and CCK-OD, or output the first duty cycle detection valid signal DCD-OUTP-VLD and the second duty cycle detection valid signal DCD-OUTN-VLD.

[0070] The first multiplexer 402 can selectively output multiple code adjustment clock signals CCK-EV and CCK-OD or multiple duty cycle detection valid signals DCD-OUTP-VLD and DCD-OUTN-VLD based on the first code adjustment completion signal CCAL-DNE.

[0071] The first multiplexer 402 can output a first adjustment clock signal CCK-EV and a second adjustment clock signal CCK-OD when the first code adjustment completion signal CCAL-DNE is deactivated, and can output a first duty cycle detection valid signal DCD-OUTP-VLD and a second duty cycle detection valid signal DCD-OUTN-VLD when the first code adjustment completion signal CCAL-DNE is activated.

[0072] The first code adjustment circuit 403 can receive the first duty cycle detection valid signal DCD-OUTP-VLD, the second duty cycle detection valid signal DCD-OUTN-VLD, the second code minimum / maximum detection signal FMNX, the code change timing signal CCHG, the code set selection signal SEL-RECN, and the code set change signal CHN-SEL, and can output the first code minimum detection signal CMIN, the first code maximum detection signal CMAX, the first code CC<3:0>, and the third code NC<3:0>.

[0073] The first code adjustment circuit 403 can activate the first code minimum detection signal CMIN to a logic high level when the first code CC<3:0> and the third code NC<3:0> are at the minimum level, and can activate the first code maximum detection signal CMAX to a logic high level when the first code CC<3:0> and the third code NC<3:0> are at the maximum level.

[0074] When the code change timing signal CCHG is activated, the first code adjustment circuit 403 can increase or decrease the code selected between the first code CC<3:0> and the third code NC<3:0> based on the first duty cycle detection valid signal DCD-OUTP-VLD and the second duty cycle detection valid signal DCD-OUTN-VLD.

[0075] When the second code minimum / maximum detection signal FMNX and the code change timing signal CCHG are activated, the first code adjustment circuit 403 can increase or decrease the selected code between the first code CC<3:0> and the third code NC<3:0> according to the first duty cycle detection valid signal DCD-OUTP-VLD and the second duty cycle detection valid signal DCD-OUTN-VLD.

[0076] When the second code minimum / maximum detection signal FMNX and the code change timing signal CCHG are activated, and the first duty cycle detection valid signal DCD-OUTP-VLD is at a logic high level, the first code adjustment circuit 403 can add the code selected between the first code CC<3:0> and the third code NC<3:0>.

[0077] When the second duty cycle detection valid signal DCD-OUTN-VLD is at a logic high level, and the second code adjustment circuit 403 is activated with the second code minimum / maximum detection signal FMNX and the code change timing signal CCHG, the first code adjustment circuit 403 can reduce the code selection between the first code CC<3:0> and the third code NC<3:0>.

[0078] When the code set selection signal SEL-RECN is at a logic high level, the first code adjustment circuit 403 can output the third code NC<3:0> as the initial value and adjust the first code CC<3:0>. When the code set selection signal SEL-RECN is at a second logic level (e.g., logic low level), the first code adjustment circuit 403 can output the first code CC<3:0> as the initial value and adjust the third code NC<3:0>.

[0079] The first code adjustment circuit 403 can prevent changes to the first code CC<3:0> and the third code NC<3:0> based on the second code minimum / maximum detection signal FMNX and the code set change signal CHN-SEL. When the second code minimum / maximum detection signal FMNX is deactivated, the first code adjustment circuit 403 can prevent changes to the first code CC<3:0> and the third code NC<3:0>. When the code set change signal CHN-SEL is activated, the first code adjustment circuit 403 can prevent changes to the first code CC<3:0> and the third code NC<3:0>.

[0080] The second code adjustment circuit 404 can receive the output of the first multiplexer 402, the second code minimum / maximum detection signal FMNX and the code set selection signal SEL-RECN, and can output the second code CF<7:0> and the fourth code NF<7:0>.

[0081] The second code adjustment circuit 404 can increase or decrease the code selected between the second code CF<7:0> and the fourth code NF<7:0> based on the output of the first multiplexer 402.

[0082] When the code set selection signal SEL-RECN is at a logic high level, the second code adjustment circuit 404 can output the fourth code NF<7:0> as the initial value and adjust the second code CF<7:0>. When the code set selection signal SEL-RECN is at a logic low level, the second code adjustment circuit 404 can output the second code CF<7:0> as the initial value and adjust the fourth code NF<7:0>.

[0083] The second multiplexer 405 can receive the first timing change signal CCHG-CT, the second timing change signal CCHG-FT, and the first code adjustment completion signal CCAL-DNE, and can output the code timing change signal CCHG.

[0084] When the first code adjustment completion signal CCAL-DNE is deactivated, the second multiplexer 405 can output the first timing change signal CCHG-CT as the code change timing signal CCHG. When the first code adjustment completion signal CCAL-DNE is activated, the second multiplexer 405 can output the second timing change signal CCHG-FT as the code change timing signal CCHG.

[0085] The completion determination circuit 406 can receive the first duty cycle detection signal DCD-OUTP, the second duty cycle detection signal DCD-OUTN, the duty cycle adjustment start signal DCC-STT, the first code increment limit detection signal CILMT, and the second code minimum / maximum detection signal FMNX, and can output the first code adjustment completion signal CCAL-DNE and the duty cycle adjustment completion signal DCC-DNE.

[0086] When the first code adjustment completion signal CCAL-DNE is deactivated to a logic low level, the completion determination circuit 406 can detect the bang-bang state of the first code CC<3:0> and the third code NC<3:0> based on the first duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN, and activate the first code adjustment completion signal CCAL-DNE to a logic high level. The activation of the first code adjustment completion signal CCAL-DNE indicates that the adjustment of the first code CC<3:0> and the third code NC<3:0> has been completed.

[0087] When the first code adjustment completion signal CCAL-DNE is deactivated, if the first duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN do not detect the bang-bang state of the first code CC<3:0> and the third code NC<3:0>, then the completion determination circuit 406 can keep the first code adjustment completion signal CCAL-DNE at a logic low level.

[0088] When the first code increment limit detection signal CILMT is activated, that is, when the currently adjusted code between the first code CC<3:0> and the third code NC<3:0> cannot be adjusted further, the completion determination circuit 406 can activate the first code adjustment completion signal CCAL-DNE.

[0089] When the first code adjustment completion signal CCAL-DNE is activated, the completion determination circuit 406 can activate the duty cycle adjustment completion signal DCC-DNE to a logic high level by detecting the bang-bang state of the second code CF<7:0> and the fourth code NF<7:0> according to the first duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN.

[0090] When the first code adjustment completion signal CCAL-DNE is activated, and the second duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN do not detect the bang-bang state of the second code CF<7:0> and the fourth code NF<7:0>, the completion determination circuit 406 can deactivate the duty cycle adjustment completion signal DCC-DNE to a logic low level.

[0091] When a predetermined time has elapsed by counting the effective segment signal DCD-VLD, the completion determination circuit 406 can activate the duty cycle adjustment completion signal DCC-DNE.

[0092] When both the first code increment limit detection signal CILMT and the second code minimum / maximum detection signal FMNX are activated, i.e., when further code adjustment cannot be performed, the completion determination circuit 406 can activate the duty cycle adjustment completion signal DCC-DNE.

[0093] The code value determination circuit 407 can receive the valid segment signal DCD-VLD, the duty cycle detection signals DCD-OUTP and DCD-OUTN, the first code minimum detection signal CMIN, the first code maximum detection signal CMAX, and the least significant bit CC of the first and third codes. <0> / NC <0> It can also output the most significant bit and least significant bit CF<7,0> / NF<7,0> of the second and fourth codes, and can output the first code increment limit detection signal CILMT, the second code minimum / maximum detection signal FMNX, the first duty cycle detection valid signal DCD-OUTP-VLD, the second duty cycle detection valid signal DCD-OUTN-VLD, and the code set change signal CHN-SEL.

[0094] The code value determination circuit 407 can generate and output a first duty cycle detection valid signal DCD-OUTP-VLD and a second duty cycle detection valid signal DCD-OUTN-VLD based on the duty cycle detection signals DCD-OUTP and DCD-OUTN corresponding to the valid segment signal DCD-VLD.

[0095] The code value determination circuit 407 can be based on the first code minimum detection signal CMIN, the first code maximum detection signal CMAX, and the least significant bit CC of the first and third codes. <0> / NC <0> The most significant bit and least significant bit of the second and fourth codes CF<7,0> / NF<7,0>, the first duty cycle detection valid signal DCD-OUTP-VLD and the second duty cycle detection valid signal DCD-OUTN-VLD generate the first code increment limit detection signal CILMT, the second code minimum / maximum detection signal FMNX and the code set change signal CHN-SEL.

[0096] The code value determination circuit 407 can determine that the first code CC<3:0> and the third code NC<3:0> are in the minimum level based on the first code minimum detection signal CMIN, and can determine that the first code CC<3:0> and the third code NC<3:0> are in the maximum level based on the first code maximum detection signal CMAX. The code value determination circuit 407 can also determine whether the second code CF<7:0> and the fourth code NF<7:0> are in the minimum or maximum level based on the most significant bit CF<7,0> / NF<7,0> of the second code and the least significant bit CF<7,0> / NF<7,0> of the fourth code.

[0097] When multiple codes CC<3:0>, CF<7:0>, NC<3:0> and NF<7:0> are all at the minimum level and the second duty cycle detection valid signal DCD-OUTN-VLD is at a high level, the code value determination circuit 407 can activate the code set change signal CHN-SEL to a logic high level.

[0098] When the first code maximum detection signal CMAX is activated and the first duty cycle detection valid signal DCD-OUTP-VLD is at a high level, the code value determination circuit 407 can activate the first code increment limit detection signal CILMT to a logic high level.

[0099] When the least significant bit of the first code CC<3:0> is low, the second code CF<7:0> and the fourth code NF<7:0> are at their minimum level, and the second duty cycle detection valid signal DCD-OUTN-VLD is high, the code value determination circuit 407 can activate the second code minimum / maximum detection signal FMNX to a logic high level. When the least significant bit of the first code CC<3:0> is high, the second code CF<7:0> and the fourth code NF<7:0> are at their maximum level, and the second duty cycle detection valid signal DCD-OUTN-VLD is high, the code value determination circuit 407 can activate the second code minimum / maximum detection signal FMNX to a logic high level. When the least significant bit of the first code CC<3:0> is low, the second code CF<7:0> and the fourth code NF<7:0> are at their maximum level, and the first duty cycle detection valid signal DCD-OUTN-VLD is high, the code value determination circuit 407 can activate the second code minimum / maximum detection signal FMNX to a logic high level. When the least significant bit of the first code CC<3:0> is high, the second code CF<7:0> and the fourth code NF<7:0> are at the minimum level, and the first duty cycle detection valid signal DCD-OUTP-VLD is high, the code value determination circuit 407 can activate the second code minimum / maximum detection signal FMNX to a logic high level.

[0100] Selection circuit 408 can receive code set change signal CHN-SEL and output code set selection signal SEL-RECN. When code set change signal CHN-SEL is activated, selection circuit 408 can output code set selection signal SEL-RECN with a logic level opposite to the previous logic level.

[0101] The timing control signal generation circuit 409 can receive multiple control signals CTRLS and a duty cycle adjustment completion signal DCC-DNE, and can output multiple timing control signals TNCK-STT, DCD-VLD, CCHG-CT, CCHG-FT, and DCC-STT. The multiple control signals CTRLS may include signals related to the start and end operations of the duty cycle correction circuit 100.

[0102] The timing control signal generation circuit 409 can generate multiple timing control signals TNCK-STT, DCD-VLD, CCHG-CT, CCHG-FT and DCC-STT according to multiple cycles in the entire segment where the duty cycle correction operation is performed.

[0103] The timing control signal generation circuit 409 can initialize multiple timing control signals TNCK-STT, DCD-VLD, CCHG-CT, CCHG-FT, and DCC-STT based on the duty cycle adjustment completion signal DCC-DNE. These multiple timing control signals TNCK-STT, DCD-VLD, CCHG-CT, CCHG-FT, and DCC-STT may include a clock adjustment start signal TNCK-STT, a valid segment signal DCD-VLD, a first timing change signal CCHG-CT, a second timing change signal CCHG-FT, and a duty cycle adjustment start signal DCC-STT.

[0104] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6 The code in the diagram shows the detailed configuration of the clock generation circuit 401.

[0105] Reference Figure 7 The code adjustment clock generation circuit 401 may include a source clock generation circuit 410, a shift circuit 430, and an adjustment clock generation circuit 470.

[0106] The source clock generation circuit 410 can receive the first external clock signal RE-C, the source clock generation start signal TNCK-STT, the first code increment limit detection signal CILMT, multiple adjustment clock segment signals CK-STTB and CKXB, the code set change signal CHN-SEL, and the first code adjustment completion signal CCAL-DNE, and can output the source clock signal TNCK.

[0107] The source clock generation circuit 410 can divide the first external clock signal RE-C to generate multiple divided clock signals CKEV and CKOD, and can output the pulse corresponding to the segment determined by the multiple adjustment clock segment signals CK-STTB and CKXB among the pulses of the multiple divided clock signals CKEV and CKOD as the source clock signal TNCK.

[0108] The source clock generation circuit 410 may include multiple frequency divider circuits 411 and 415 and multiple logic gates 412 to 414 and 416 to 422. The first frequency divider circuit 411 divides the first external clock signal RE-C by two to generate the external clock divided signal CKDIV. The first logic gate 412 outputs the result obtained by performing an AND operation on the source clock generation start signal TNCK-STT, the second adjustment clock segment signal CKXB, the inverted first code increment limit detection signal CILMT, the inverted code set change signal CHN-SEL, and the inverted first code adjustment completion signal CCAL-DNE. The second logic gate 413 outputs the result obtained by performing an AND operation on the external clock divided signal CKDIV and the output of the first logic gate 412. The third logic gate 414 inverts the output of the second logic gate 413 and outputs it. The second frequency divider circuit 415 divides the output of the second logic gate 413 by two and outputs the result. The fourth logic gate 416 inverts and outputs the output of the second frequency divider circuit 415. The fifth logic gate 417 inverts and outputs the output of the fourth logic gate 416. The sixth logic gate 418 outputs the result obtained by performing an AND operation between the output of the third logic gate 414 and the output of the fifth logic gate 417, which serves as the even-numbered frequency divider clock signal CKEV among the multiple frequency divider clock signals CKEV and CKOD. The seventh logic gate 419 outputs the result obtained by performing an AND operation between the output of the third logic gate 414 and the output of the fourth logic gate 416, which serves as the odd-numbered frequency divider clock signal CKOD among the multiple frequency divider clock signals CKEV and CKOD. The eighth logic gate 420 outputs the result obtained by performing an OR operation between the outputs of the sixth logic gate 418 and the seventh logic gate 419. The ninth logic gate 421 outputs the result obtained by performing a NOR operation between the output of the eighth logic gate 420 and the first adjustment clock segment signal CK-STTB. The tenth logic gate 422 can output the result obtained by performing an AND operation on the output of the ninth logic gate 421 and the second adjustment clock segment signal CKXB, as the source clock signal TNCK. Multiple frequency divider circuits 411 and 415 can initialize their outputs according to the reset signal RSTB.

[0109] The source clock generation circuit 410 generates the source clock signal TNCK only when the first code increment limit detection signal CILMT, the code set change signal CHN-SEL, and the first code adjustment completion signal CCAL-DNE are all disabled. It can also prevent the generation of the source clock signal TNCK when any one of the first code increment limit detection signal CILMT, the code set change signal CHN-SEL, and the first code adjustment completion signal CCAL-DNE is activated.

[0110] The shift circuit 430 can receive multiple divided clock signals CKEV and CKOD, and can output multiple adjusted clock segment signals CK-STTB and CKXB. The shift circuit 430 can shift the power supply level VCCD according to the multiple divided clock signals CKEV and CKOD to generate multiple adjusted clock segment signals CK-STTB and CKXB. The multiple divided clock signals CKEV and CKOD can include even-numbered divided clock signals CKEV and odd-numbered divided clock signals CKOD.

[0111] The shift circuit 430 may include a flip-flop 440 and multiple shift units 451 to 459. The flip-flop 440 can latch the power supply level VCCD according to an even-numbered divided clock signal CKEV to generate a shift start signal CK-STT. The multiple shift units 451 to 459 can shift the shift start signal CK-STT according to multiple divided clock signals CKEV and CKOD to generate multiple adjusted clock segment signals CK-STTB and CKXB. Among the multiple shift units 451 to 459, even-numbered shift units 452, 454, 456, and 458 can shift and output the input signal according to the even-numbered divided clock signal CKEV; odd-numbered shift units 451, 453, 455, 457, and 459 can shift and output the input signal according to the odd-numbered divided clock signal CKOD. Among the multiple shift units 451 to 459, the first shift unit 451 can output an inverted signal as the first adjustment clock segment signal CK-STTB. The second to eighth shift units 452 to 458 can shift and output the output of the previous shift unit according to multiple frequency-divided clock signals CKEV and CKOD. The ninth shift unit 459 can output the inverted signal of the output of the eighth shift unit 458 as the second adjustment clock segment signal CKXB.

[0112] The clock generation circuit 470 can receive the source clock signal TNCK, the least significant bit CC of the first code CC<3:0> and the third code NC<3:0>. <0> / NC <0> The inverted least significant bit (CCB) is generated by inverting the least significant bit. <0> / NCB <0> It also includes the first duty cycle detection valid signal DCD-OUTP-VLD, and can output multiple code adjustment clock signals CCK-EV and CCK-OD.

[0113] The adjustment clock generation circuit 470 can generate multiple code adjustment clock signals CCK-EV and CCK-OD based on the source clock signal TNCK. The adjustment clock generation circuit 470 can determine the least significant bit CC of the first code CC<3:0> and the third code NC<3:0>. <0> / NC <0> And the first duty cycle detection valid signal DCD-OUTP-VLD, selects and outputs one of multiple code adjustment clock signals CCK-EV and CCK-OD and can block the output of the other.

[0114] The clock generation circuit 470 may include a multiplexer 471 and multiple logic gates 472 to 474. The multiplexer 471 can select and output the least significant bit CC based on the valid signal DCD-OUTP-VLD detected according to a first duty cycle. <0> / NC <0> and the least significant bit (CCB) of the inverted phase <0> / NCB <0> One of them. For example, assuming the first code set CC<3:0> and CF<7:0> are selected, the multiplexer 471 can select and output the least significant bit CC. <0> and the least significant bit (CCB) of the inverted phase <0> One of the following is the first logic gate 472, which inverts and outputs the output of the multiplexer 471. The second logic gate 473 outputs the result obtained by performing an AND operation on the source clock signal TNCK and the output of the first logic gate 472, as the first adjustment clock signal CCK-EV. The third logic gate 474 outputs the result obtained by performing an AND operation on the source clock signal TNCK and the output of the multiplexer 471, as the second adjustment clock signal CCK-OD. When the generation of the source clock signal TNCK is blocked, the adjustment clock generation circuit 470 can prevent the generation of multiple code adjustment clock signals CCK-EV and CCK-OD.

[0115] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 7 A diagram showing the detailed configuration of the shift unit 451 in the diagram.

[0116] Reference Figure 8 The shift unit 451 may include logic gates 501 and 502, and transistors 503 and 504. The first logic gate 501 inverts the logic level of the inverting output terminal OUTB and applies the result to the output terminal OUT. The second logic gate 502 applies the result obtained by performing a NOR operation on the logic level of the output terminal OUT and the logic level of the reset terminal RST to the inverting output terminal OUTB. Transistors 503 and 504 may be connected between the inverting output terminal OUTB and the ground terminal, and may operate according to the signals from the clock terminal CK and the input terminal IN, respectively.

[0117] Figure 9 It is used to describe embodiments according to this disclosure. Figure 7 The code in the diagram adjusts the timing of the operation of the clock generation circuit 401.

[0118] Reference Figure 9 The code adjustment clock generation circuit 401 can divide the first external clock signal RE-C to generate an external clock frequency division signal CKDIV. The external clock frequency division signal CKDIV has a period time 1tCK corresponding to the two period times 2tCK of the first external clock signal RE-C.

[0119] When the source clock generation start signal TNCK-STT is activated, multiple frequency division clock signals CKEV and CKOD can be generated.

[0120] When the shift start signal CK-STT is activated, the first adjustment clock segment signal CK-STTB can be converted to a low level after one cycle based on the external clock divider signal CKDIV, while the second adjustment clock segment signal CKXB can remain at a high level.

[0121] At this time, when the least significant bit CC <0> When the first duty cycle detection valid signal DCD-OUTP-VLD is at logic low level "0", the first adjustment clock signal CCK-EV can be generated based on multiple frequency division clock signals CKEV and CKOD. Although Figure 9 It is not shown in the diagram, but the second adjustment clock signal CCK-OD can be kept in a low-level invalid state.

[0122] Starting from the time point when the shift start signal CK-STT is activated, the second adjustment clock segment signal CKXB can be switched to a low level after a predetermined time based on multiple frequency division clock signals CKEV and CKOD has elapsed.

[0123] When the second adjustment clock segment signal CKXB goes low, the first adjustment clock signal CCK-EV can be initialized to low.

[0124] The first adjustment clock signal CCK-EV, which has eight pulses, can be generated (e.g., within a time frame) from the time point when the first adjustment clock segment signal CK-STTB transitions to a low level (i.e., from that time point onwards) to the time point when the second adjustment clock segment signal CKXB transitions to a low level (i.e., from that time point onwards).

[0125] On the other hand, when the least significant bit CC <0> When the logic level is low and the first duty cycle detection valid signal DCD-OUTP-VLD is high, a second adjustment clock signal CCK-OD with eight pulses can be generated in the segment from the time point when the first adjustment clock segment signal CK-STTB turns low to the time point when the second adjustment clock segment signal CKXB turns low, while the first adjustment clock signal CCK-EV remains in a low-level invalid state.

[0126] When the reset signal RSTB goes low, the shift start signal CK-STT, the first adjustment clock segment signal CK-STTB, and the second adjustment clock segment signal CKXB can be initialized.

[0127] The foregoing Figure 5 The description illustrates an example where the second code CF<7:0> is configured to be at levels 0 through 8. In each cycle of the first segment, eight adjustments are required to change the second code CF<7:0> from a predetermined level, i.e., from the lowest level "0" to the highest level "8" or vice versa. Therefore, the above description is based on an example where the code adjustment clock generation circuit 401 is configured to generate a first adjustment clock signal CCK-EV and a second adjustment clock signal CCK-OD (each signal having eight pulses).

[0128] Figure 10 This illustrates an embodiment according to the present disclosure. Figure 6 A diagram showing the detailed configuration of the completion determination circuit 406.

[0129] Reference Figure 10 The determination circuit 406 may include a counter 610, a bang-bang detection circuit 620, a first signal generation circuit 630, a second signal generation circuit 640, a third signal generation circuit 650, and a decoder 660.

[0130] Counter 610 can count the valid segment signal DCD-VLD and output the counting result signal CNTOUT. The duty cycle correction operation should be performed within the time specified in the operating specifications. The counting result signal CNTOUT can be activated to a logic high level for the specified time to indicate the time limit for the duty cycle correction operation.

[0131] The bang-bang detection circuit 620 can receive a first duty cycle detection signal DCD-OUTP, a second duty cycle detection signal DCD-OUTN, and a bang-bang reset signal BB-RSTB, and can output a bang-bang detection signal BB-DNE. When the first duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN are generated alternately at logic high levels, the bang-bang detection circuit 620 can activate the bang-bang detection signal BB-DNE to a logic high level.

[0132] The first signal generation circuit 630 can receive the bang-bang detection signal BB-DNE, the first code adjustment completion signal CCAL-DNE, the first code increment limit detection signal CILMT, and the valid segment signal DCD-VLD, and can output the first code adjustment completion signal CCAL-DNE. When any one of the bang-bang detection signal BB-DNE, the first code adjustment completion signal CCAL-DNE, and the first code increment limit detection signal CILMT is activated after the valid segment signal DCD-VLD is deactivated, the first signal generation circuit 630 can keep the first code adjustment completion signal CCAL-DNE in an active state.

[0133] The first signal generation circuit 630 may include multiple logic gates 631 and 632 and a flip-flop 633. The first logic gate 631 can output the result obtained by performing an OR operation on the bang-bang detection signal BB-DNE, the first code adjustment completion signal CCAL-DNE, and the first code increment limit detection signal CILMT. The logic gate 632 can invert the valid segment signal DCD-VLD and output the inverted valid segment signal DCD-VLDB. The flip-flop 633 can output the output of logic gate 631 at the time when the inverted valid segment signal DCD-VLDB transitions to a logic high level, serving as the first code adjustment completion signal CCAL-DNE.

[0134] The second signal generation circuit 640 can receive the first code adjustment completion signal CCAL-DNE and the duty cycle adjustment start signal DCC-STT, and can output a bang-bang reset signal BB-RSTB. The second signal generation circuit 640 can generate the bang-bang reset signal BB-RSTB in response to the activation of the first code adjustment completion signal CCAL-DNE.

[0135] The second signal generation circuit 640 may include a delay circuit 641 and multiple logic gates 642 to 644. The delay circuit 641 can delay the first code adjustment completion signal CCAL-DNE by a predetermined time and output the result. Logic gate 642 can invert the output of the delay circuit 641. Logic gate 643 can output the result obtained by performing a NAND operation on the output of logic gate 642 and the first code adjustment completion signal CCAL-DNE. Logic gate 644 can output the result obtained by performing an AND operation on the output of logic gate 643 and the duty cycle adjustment start signal DCC-STT, as a bang-bang reset signal BB-RSTB.

[0136] The third signal generation circuit 650 can receive the bang-bang detection signal BB-DNE, the inverted active segment signal DCD-VLDB, the first code adjustment completion signal CCAL-DNE, the code adjustment limit detection signal CFMNX, and the count result signal CNTOUT, and can output the duty cycle adjustment completion signal DCC-DNE. When the first code adjustment completion signal CCAL-DNE is activated, and any one of the bang-bang detection signal BB-DNE, the code adjustment limit detection signal CFMNX, and the count result signal CNTOUT is activated, the third signal generation circuit 650 can activate the duty cycle adjustment completion signal DCC-DNE.

[0137] The third signal generation circuit 650 may include a flip-flop 651 and a logic gate 652. The flip-flop 651 can latch the bang-bang detection signal BB-DNE and output the result as the second code adjustment completion signal FCAL-DNE when the inverted active segment signal DCD-VLDB is at a logic high level. The flip-flop 651 can initialize the second code adjustment completion signal FCAL-DNE to a logic low level when the first code adjustment completion signal CCAL-DNE is disabled. The logic gate 652 can output the result obtained by performing an OR operation on the second code adjustment completion signal FCAL-DNE, the code adjustment limit detection signal CFMNX, and the count result signal CNTOUT, as the duty cycle adjustment completion signal DCC-DNE.

[0138] Decoder 660 can decode the first code increment limit detection signal CILMT and the second code minimum / maximum detection signal FMNX, and can output the code adjustment limit detection signal CFMNX. When both the first code increment limit detection signal CILMT and the second code minimum / maximum detection signal FMNX are activated, decoder 660 can activate the code adjustment limit detection signal CFMNX. Activation of the code adjustment limit detection signal CFMNX indicates that the first code CC<3:0>, the third code NC<3:0>, the second code CF<7:0>, and the fourth code NF<7:0> can no longer be adjusted.

[0139] Figure 11 It is used to describe embodiments according to this disclosure. Figure 10 The timing diagram for determining the operation of circuit 406 in the middle.

[0140] Reference Figure 11 When the first duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN are generated alternately at logic high levels in two cycles, the bang-bang detection signal BB-DNE can be activated to a logic high level. The activation of the bang-bang detection signal BB-DNE indicates that the adjustment of the first code CC<3:0> and the third code NC<3:0> has been completed.

[0141] After the bang-bang detection signal BB-DNE is activated to a logic high level, when the inverted active segment signal DCD-VLDB is converted to a logic high level, the first code adjustment completion signal CCAL-DNE can be activated to a logic high level.

[0142] When the first code adjustment completion signal CCAL-DNE is activated, the bang-bang reset signal BB-RSTB can be activated to a logic low level. Therefore, the bang-bang detection signal BB-DNE can be deactivated to a logic low level.

[0143] After the bang-bang detection signal BB-DNE is deactivated, it can be reactivated to a logic high level based on the first duty cycle detection signal DCD-OUTP and the second duty cycle detection signal DCD-OUTN. The reactivation of the bang-bang detection signal BB-DNE indicates that the adjustment of the second code CF<7:0> and the fourth code NF<7:0> has been completed.

[0144] After the bang-bang detection signal BB-DNE is activated to a logic high level, when the inverted active segment signal DCD-VLDB is converted to a logic high level, the second code adjustment completion signal FCAL-DNE can be activated to a logic high level.

[0145] When the second code adjustment completion signal FCAL-DNE is activated, the duty cycle adjustment completion signal DCC-DNE can be activated to a logic high level, indicating that the duty cycle correction operation has been completed.

[0146] Figure 12 This illustrates an embodiment according to the present disclosure. Figure 6 A diagram showing the detailed configuration of the code value determination circuit 407.

[0147] Reference Figure 12 The code value determination circuit 407 may include a first signal generation logic circuit 710 and a second signal generation logic circuit 720.

[0148] The first signal generation logic circuit 710 can receive the valid segment signal DCD-VLD, the first duty cycle detection signal DCD-OUTP, and the second duty cycle detection signal DCD-OUTN, and can output the first duty cycle detection valid signal DCD-OUTP-VLD and the second duty cycle detection valid signal DCD-OUTN-VLD. The first signal generation logic circuit 710 can output the result obtained by performing an AND operation on the first duty cycle detection signal DCD-OUTP and the valid segment signal DCD-VLD as the first duty cycle detection valid signal DCD-OUTP-VLD, and can also output the result obtained by performing an AND operation on the second duty cycle detection signal DCD-OUTN and the valid segment signal DCD-VLD as the second duty cycle detection valid signal DCD-OUTN-VLD.

[0149] The second signal generation logic circuit 720 can receive the first duty cycle detection valid signal DCD-OUTP-VLD, the second duty cycle detection valid signal DCD-OUTN-VLD, and the least significant bit CC of the first code and the third code. <0> / NC <0> The most significant bit and least significant bit CF<7,0> / NF<7,0> of each of the second and fourth codes, the first code minimum detection signal CMIN and the first code maximum detection signal CMAX, and can output the first code increment limit detection signal CILMT, the second code minimum / maximum detection signal FMNX and the code set change signal CHN-SEL.

[0150] The second signal generation logic circuit 720 can determine that the first code CC<3:0> and the third code NC<3:0> are at the minimum level based on the first code minimum detection signal CMIN, and can determine that the first code CC<3:0> and the third code NC<3:0> are at the maximum level based on the first code maximum detection signal CMAX. The second signal generation logic circuit 720 can determine whether the second code CF<7:0> and the fourth code NF<7:0> are at the minimum or maximum level based on the most significant bit and least significant bit CF<7,0> / NF<7,0> of the second and fourth codes, respectively.

[0151] When multiple codes CC<3:0>, CF<7:0>, NC<3:0> and NF<7:0> are all at the minimum level and the second duty cycle detection valid signal DCD-OUTN-VLD is at a high level, the second signal generation logic circuit 720 can activate the code set change signal CHN-SEL to a logic high level.

[0152] When the first code maximum detection signal CMAX is activated and the first duty cycle detection valid signal DCD-OUTP-VLD is at a logic high level, the second signal generation logic circuit 720 can activate the first code increment limit detection signal CILMT to a logic high level.

[0153] When the least significant bit of the first code CC<3:0> is low, the second code CF<7:0> and the fourth code NF<7:0> are at their minimum level, and the second duty cycle detection valid signal DCD-OUTN-VLD is high, the second signal generation logic circuit 720 can activate the second code minimum / maximum detection signal FMNX to a logic high level. When the least significant bit of the first code CC<3:0> is high, the second code CF<7:0> and the fourth code NF<7:0> are at their maximum level, and the second duty cycle detection valid signal DCD-OUTN-VLD is high, the second signal generation logic circuit 720 can activate the second code minimum / maximum detection signal FMNX to a logic high level. When the least significant bit of the first code CC<3:0> is low, the second code CF<7:0> and the fourth code NF<7:0> are at their maximum level, and the first duty cycle detection valid signal DCD-OUTN-VLD is high, the second signal generation logic circuit 720 can activate the second code minimum / maximum detection signal FMNX to a logic high level. When the least significant bit of the first code CC<3:0> is high, the second code CF<7:0> and the fourth code NF<7:0> are at the minimum level, and the first duty cycle detection valid signal DCD-OUTP-VLD is high, the second signal generation logic circuit 720 can activate the second code minimum / maximum detection signal FMNX to a logic high level.

[0154] Figures 13 to 18 This is a timing diagram used to describe the duty cycle correction operation of the duty cycle correction circuit 100 according to an embodiment of the present disclosure. Figures 13 to 18 The duty cycle correction operation based on the first code adjustment completion signal CCAL-DNE, the first code increment limit detection signal CILMT, the second code minimum / maximum detection signal FMNX, and the code set change signal CHN-SEL under different state conditions is described.

[0155] Reference Figure 13 This will describe the duty cycle correction operation when CCAL-DNE=0, CILMT=0, FMNX=0 and CHN-SEL=0.

[0156] With the first code set CC<3:0> and CF<7:0> selected, no code set change occurs because the code set change signal CHN-SEL is "0". Since the first code adjustment completion signal CCAL-DNE is "0", the optimization of the first code CC<3:0> is not yet complete. Because both the first code increment limit detection signal CILMT and the second code minimum / maximum detection signal FMNX are "0", the first code CC<3:0> and the second code CF<7:0> can be adjusted. Assume that at the activation point of the valid segment signal DCD-VLD, both the first code CC<3:0> and the second code CF<7:0> are "0".

[0157] During the active segment of the valid segment signal DCD-VLD, a first duty cycle detection valid signal DCD-OUTP-VLD can be generated at a logic high level. The active segment of the valid segment signal DCD-VLD corresponds to one of a plurality of cycles of the duty cycle correction operation segment.

[0158] Since the second code CF<7:0> is in an adjustable state, the source clock generation start signal TNCK-STT can be activated first, and then the first timing change signal CCHG-CT can be activated after a predetermined timing margin.

[0159] When the source clock generation start signal TNCK-STT is activated, the first adjustment clock signal CCK-EV is generated, and the second code CF<7:0> is adjusted to "8" by changing the maximum value according to the first adjustment clock signal CCK-EV.

[0160] Since the first duty cycle detection valid signal DCD-OUTP-VLD is at a logic high level, the first code CC<3:0> is incremented to "1" according to the activated first change timing signal CCHG-CT.

[0161] After the first code CC<3:0> is adjusted to "1", the valid segment signal DCD-VLD and the first duty cycle detection valid signal DCD-OUTP-VLD are initialized by the reset signal RSTB.

[0162] Reference Figure 14 This will describe the duty cycle correction operation when CCAL-DNE=0, CILMT=0, FMNX=1 and CHN-SEL=0.

[0163] Since the code set selection signal SEL-RECN is "0", the first code set CC<3:0> and CF<7:0> are selected. Since the first code adjustment completion signal CCAL-DNE is "0", the optimization of the first code CC<3:0> is not yet complete. Since the first code increment limit detection signal CILMT is "0", the first code CC<3:0> is in an adjustable state, while the second code minimum / maximum detection signal FMNX is "1", indicating that the second code CF<7:0> is in an unadjustable state. Assume that at the activation point of the effective segment signal DCD-VLD, the first code CC<3:0> is "1" and the second code CF<7:0> is "8".

[0164] Within the active segment of the valid segment signal DCD-VLD, a first duty cycle detection valid signal DCD-OUTP-VLD can be generated by a logic low level. The active segment of the valid segment signal DCD-VLD corresponds to one of the multiple cycles included in the duty cycle correction operation segment.

[0165] Since the second code CF<7:0> is in an unadjustable state, the first change timing signal CCHG-CT is activated first, and then the source clock generation start signal TNCK-STT is activated after a predetermined timing margin.

[0166] Since the first duty cycle detection valid signal DCD-OUTP-VLD is at a logic low level, the first code CC<3:0> decreases to "0" according to the activated first change timing signal CCHG-CT.

[0167] When the source clock generation start signal TNCK-STT is activated, the first adjustment clock signal CCK-EV is generated, and the second code CF<7:0> is adjusted to "0" by changing the maximum value according to the first adjustment clock signal CCK-EV.

[0168] After the first code CC<3:0> is adjusted to "0", the valid segment signal DCD-VLD and the first duty cycle detection valid signal DCD-OUTP-VLD are initialized by the reset signal RSTB.

[0169] For reference Figure 13 and 14 According to the embodiments of this disclosure, in each cycle included in the duty cycle correction operation, the second code CF<7:0> is changed by the maximum value within the adjustable range, thereby reducing the time required to complete the adjustment of the first code CC<3:0>.

[0170] Reference Figure 15 This section describes the duty cycle correction operation when CCAL-DNE=0, CILMT=0, FMNX=1, and CHN-SEL=1.

[0171] Since the first code adjustment completion signal CCAL-DNE is "0", the optimization of the first code CC<3:0> is not yet complete. Since the first code increment limit detection signal CILMT is "0", the first code CC<3:0> is in an adjustable state. Since the second code minimum / maximum detection signal FMNX is "1", the second code CF<7:0> is in an unadjustable state. Assume that at the activation point of the valid segment signal DCD-VLD, both the first code CC<3:0> and the second code CF<7:0> are "0", and during the active segment of the valid segment signal DCD-VLD, a second duty cycle detection valid signal DCD-OUTN-VLD is generated with a logic high level.

[0172] When the code set selection signal SEL-RECN is at a logic high level, the duty cycle correction operation is performed by adjusting the first code CC<3:0> and the second code CF<7:0> provided to the first duty cycle adjustment circuit 101A.

[0173] When the second duty cycle detection valid signal DCD-OUTN-VLD goes high, the first code CC<3:0> needs to be de-escalated. However, since both the first code CC<3:0> and the second code CF<7:0> are already set to "0", the phase of the first external clock signal RE-C cannot be adjusted by the first duty cycle adjustment circuit 101A. Instead, the phase of the second external clock signal RE-N must be adjusted by the second duty cycle adjustment circuit 101B. Therefore, the code set change signal CHN-SEL is converted to a high logic level, and consequently, the code set selection signal SEL-RECN is converted to a different logic level, such as a low logic level.

[0174] Since the second code minimum / maximum detection signal FMNX is "1", indicating that the second code CF<7:0> is in an unadjustable state, the first change timing signal CCHG-CT is activated first, and then after a predetermined timing margin, the source clock generation start signal TNCK-STT is activated.

[0175] Although the first timing change signal CCHG-CT and the source clock generation start signal TNCK-STT are activated, the generation of the first adjustment clock signal CCK-EV and the adjustment of the first code CC<3:0> are prevented because the code set change signal CHN-SEL is converted to a logic high level.

[0176] The valid segment signal DCD-VLD and the second duty cycle detection valid signal DCD-OUTN-VLD are initialized by the reset signal RSTB.

[0177] Reference Figure 16 This will describe the duty cycle correction operation when CCAL-DNE=1, CILMT=0, FMNX=0 and CHN-SEL=0.

[0178] Since the first code adjustment completion signal CCAL-DNE is "1", the optimal value of the first code CC<3:0> has been found. Since both the first code increment limit detection signal CILMT and the second code minimum / maximum detection signal FMNX are "0", the first code CC<3:0> and the second code CF<7:0> are in an adjustable state. Assume that at the activation point of the valid segment signal DCD-VLD, the first code CC<3:0> is "0" and the second code CF<7:0> is "2", and during the active segment of the valid segment signal DCD-VLD, the first duty cycle detection valid signal DCD-OUTP-VLD is generated with a logic high level.

[0179] Since the first code adjustment completion signal CCAL-DNE is "1", the second change timing signal CCHG-FT and the source clock generation start signal TNCK-STT can be activated at the same timing.

[0180] Although the second timing change signal CCHG-FT and the source clock generation start signal TNCK-STT are activated, the generation of the first adjustment clock signal CCK-EV is prevented because the first code adjustment completion signal CCAL-DNE is "1", and the change of the first code CC<3:0> is also prevented because the second code minimum / maximum detection signal FMNX is "0".

[0181] On the other hand, since the first code adjustment completion signal CCAL-DNE is "1", the second code adjustment circuit 404 increases the second code CF<7:0> to "3" according to the first duty cycle detection valid signal DCD-OUTP-VLD which is at a logic high level.

[0182] Reference Figure 17 This will describe the duty cycle correction operation when CCAL-DNE=1, CILMT=0, FMNX=1 and CHN-SEL=0.

[0183] Since the first code adjustment completion signal CCAL-DNE is "1", the optimal value of the first code CC<3:0> has been found. Since the first code increment limit detection signal CILMT is "0", the first code CC<3:0> is adjustable. However, since the second code minimum / maximum detection signal FMNX is "1", the second code CF<7:0> is not adjustable. Assume that at the activation point of the valid segment signal DCD-VLD, the first code CC<3:0> is "0", the second code CF<7:0> is "8", and during the active segment of the valid segment signal DCD-VLD, the first duty cycle detection valid signal DCD-OUTP-VLD is generated with a logic high level.

[0184] Although the first code adjustment completion signal CCAL-DNE is "1", the second code minimum / maximum detection signal FMNX is also "1". Therefore, regardless of the first duty cycle detection valid signal DCD-OUTP-VLD, the second code adjustment circuit 404 will keep the second code CF<7:0> as "8".

[0185] Since the first code adjustment completion signal CCAL-DNE is "1", the second change timing signal CCHG-FT and the source clock generation start signal TNCK-STT can be activated at the same timing.

[0186] Although the source clock generation start signal TNCK-STT is activated, the generation of the first adjustment clock signal CCK-EV is prevented because the first code adjustment completion signal CCAL-DNE is "1".

[0187] Since the second code minimum / maximum detection signal FMNX is "1", the first code adjustment circuit 403 changes the first code CC<3:0> to "1" according to the second change timing signal CCHG-FT.

[0188] When the first code CC<3:0> changes to "1", the second code minimum / maximum detection signal FMNX changes to "0".

[0189] When the second code minimum / maximum detection signal FMNX is converted to "0", the second code adjustment circuit 404 changes the second code CF<7:0> to "7" so that the duty cycle correction operation can continue.

[0190] Reference Figure 18 This section describes the duty cycle correction operation for the cases of CCAL-DNE=1, CILMT=0, FMNX=1, and CHN-SEL=1.

[0191] Since the first code adjustment completion signal CCAL-DNE is "1", the optimal value of the first code CC<3:0> has been found. Although the first code increment limit detection signal CILMT is "0", indicating that the first code CC<3:0> is adjustable, the second code minimum / maximum detection signal FMNX is "1", indicating that the second code CF<7:0> is not adjustable. Assume that at the activation point of the valid segment signal DCD-VLD, both the first code CC<3:0> and the second code CF<7:0> are "0", and during the active segment of the valid segment signal DCD-VLD, the first duty cycle detection valid signal DCD-OUTP-VLD is generated with a logic high level.

[0192] Because the code set change signal CHN-SEL is at a logic high level, the generation of the first adjustment clock signal CCK-EV and the change of the first code CC<3:0> are prevented.

[0193] When the code set change signal CHN-SEL transitions to logic high, the second code minimum / maximum detection signal FMNX transitions to "0".

[0194] When the second code minimum / maximum detection signal FMNX is converted to "0", the second code adjustment circuit 404 changes the second code CF<7:0> to "1", so that the duty cycle correction operation can continue.

[0195] Since the first code adjustment completion signal CCAL-DNE is "1", the second change timing signal CCHG-FT and the source clock generation start signal TNCK-STT can be activated at the same timing.

[0196] Although the source clock generation start signal TNCK-STT is activated, the generation of the first adjustment clock signal CCK-EV is prevented because the first code adjustment completion signal CCAL-DNE is "1".

[0197] Although the second timing change signal CCHG-FT is activated, the change of the first code CC<3:0> is blocked because the code set change signal CHN-SEL is at a logic high level.

[0198] Figure 19 This is a diagram illustrating an example of code changes during duty cycle correction operation according to an embodiment of the present disclosure. Figure 19 An example of duty cycle correction is shown by adjusting the first code CC<3:0> to "2" and the second code CF<7:0> to "4".

[0199] Reference Figure 19 In each cycle included in the duty cycle correction operation, the second code CF<7:0> is changed by a maximum value of "8" within the adjustable range, and the first code CC<3:0> is changed in basic units. By detecting the bang-bang state of the first code CC<3:0> and the second code CF<7:0> using this method, the duty cycle correction operation can be completed within 15 cycles. Therefore, compared with the reference... Figure 1 Compared to existing technologies, the time required for duty cycle correction operations can be reduced. The above embodiments are merely examples of the second code CF<7:0> being configured with levels from "0" to "8". When the number of levels of the second code CF<7:0> is increased to improve the resolution of the duty cycle correction operation, the time required for the duty cycle correction operation can be further significantly reduced compared to existing technologies.

[0200] Concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to the description provided. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A duty cycle correction circuit, comprising: The duty cycle adjustment circuit adjusts the phase of multiple external clock signals according to multiple codes to generate multiple duty cycle correction clock signals; as well as The duty cycle control circuit controls a first correction operation to find and fix the optimal value of a first code among the plurality of codes, and a second correction operation to find and fix the optimal value of a second code among the plurality of codes. In each of the plurality of cycles in which the duty cycle control circuit performs the first correction operation, the first code is changed in basic units within a first adjustable range, and the second code is changed in maximum values ​​within a second adjustable range.

2. The duty cycle correction circuit according to claim 1, wherein, The duty cycle adjustment circuit includes: A first duty cycle adjustment circuit adjusts the phase of a first external clock signal among the plurality of external clock signals according to the first code and the second code to generate a first duty cycle correction clock signal among the plurality of duty cycle correction clock signals; and The second duty cycle adjustment circuit adjusts the phase of the second external clock signal among the multiple external clock signals according to the third and fourth codes among the multiple codes, so as to generate the second duty cycle correction clock signal among the multiple duty cycle correction clock signals.

3. The duty cycle correction circuit according to claim 2, wherein, The first duty cycle adjustment circuit includes: A first adjustment circuit delays the first external clock signal by a time corresponding to the first code to generate a first clock signal and a second clock signal; and The second adjustment circuit mixes the first clock signal and the second clock signal at a predetermined ratio according to the second code to generate the first duty cycle correction clock signal.

4. The duty cycle correction circuit according to claim 2, further comprising: The phase divider circuit generates a multi-phase clock signal by dividing the phases of the first duty cycle correction clock signal and the second duty cycle correction clock signal.

5. The duty cycle correction circuit according to claim 4, further comprising: The duty cycle detection circuit detects the phase difference of the multi-phase clock signal to generate multiple duty cycle detection signals, and provides the multiple duty cycle detection signals to the duty cycle control circuit.

6. The duty cycle correction circuit according to claim 1, wherein, When the second code is in an adjustable state during the execution of the first correction operation, the duty cycle control circuit changes the second code by the maximum value within the second adjustable range, and then changes the first code by the basic unit within the first adjustable range.

7. The duty cycle correction circuit according to claim 6, wherein, When the second code is in an unadjustable state during the execution of the first correction operation, the duty cycle control circuit changes the first code in basic units within the first adjustable range, and then changes the second code in the maximum value within the second adjustable range.

8. The duty cycle correction circuit according to claim 1, wherein, In each of the multiple cycles of performing the second correction operation, the duty cycle control circuit changes the second code in basic units within the second adjustable range.

9. The duty cycle correction circuit according to claim 2, wherein, The duty cycle control circuit selectively controls the first duty cycle adjustment circuit and the second duty cycle adjustment circuit. When the first duty cycle adjustment circuit is selected, the first code and the second code are adjusted. When the second duty cycle adjustment circuit is selected, the third code and the fourth code are adjusted.

10. A duty cycle correction circuit, comprising: The duty cycle adjustment circuit adjusts the phase of multiple external clock signals according to multiple codes to generate multiple duty cycle correction clock signals; The duty cycle detection circuit generates multiple duty cycle detection signals based on the multiple duty cycle correction clock signals; A code adjustment clock generation circuit generates multiple code adjustment clock signals to change a second code among the multiple codes by a maximum value within an adjustable range in each of the multiple cycles in a first segment. The first segment includes a time frame from the start time of adjustment of the first code among the multiple codes to the time when the adjustment of the first code is completed to activate the first code adjustment completion signal. The multiplexer selectively outputs multiple code adjustment clock signals and multiple duty cycle detection valid signals based on the first code adjustment completion signal; The first code adjustment circuit changes the first code according to the plurality of duty cycle detection valid signals, and generates a first code minimum detection signal and a first code maximum detection signal according to the first code; as well as The second code adjustment circuit changes the second code according to the output of the multiplexer.

11. The duty cycle correction circuit according to claim 10, further comprising: The circuit completes the determination process by detecting the bang-bang state of the first code based on the multiple duty cycle detection signals and activating the first code adjustment completion signal.

12. The duty cycle correction circuit according to claim 10, wherein, Multiple duty cycle detection signals corresponding to the valid segment signals are output as the multiple valid duty cycle detection signals, and The duty cycle correction circuit further includes: a code value determination circuit, which generates a first code increment limit detection signal, a second code minimum / maximum detection signal, and a code set change signal based on the first code minimum detection signal, the first code maximum detection signal, the plurality of duty cycle detection valid signals, and at least one of the most significant bit and least significant bit of each of the plurality of codes.

13. The duty cycle correction circuit according to claim 12, wherein, The code value determination circuit activates the code set change signal when the first code and the second code are at the minimum level and the second duty cycle detection valid signal among the plurality of duty cycle detection valid signals is at the first logic level.

14. The duty cycle correction circuit according to claim 12, wherein, The code value determination circuit activates the first code increment limit detection signal when the first code is at its maximum level and the first duty cycle detection valid signal among the plurality of duty cycle detection valid signals is at a first logic level.

15. The duty cycle correction circuit according to claim 12, wherein, The code value determination circuit activates the second code minimum / maximum detection signal under at least one of the following conditions: a) When the least significant bit of the first code is at the second logic level, the second code is at the minimum level, and the second duty cycle detection valid signal among the plurality of duty cycle detection valid signals is at the first logic level; b) When the least significant bit is at the second logic level, the second code is at the maximum level, and the second duty cycle detection valid signal is at the first logic level; c) When the least significant bit is at the second logic level, the second code is at the maximum level, and the first duty cycle detection valid signal among the plurality of duty cycle detection valid signals is at the first logic level; as well as d) When the least significant bit is at the first logic level, the second code is at the minimum level, and the first duty cycle detection valid signal is at the first logic level.

16. The duty cycle correction circuit according to claim 12, wherein, The code adjustment clock generation circuit prevents the generation of the plurality of code adjustment clock signals when any one of the first code increment limit detection signal, the code set change signal, and the first code adjustment completion signal is activated.

17. The duty cycle correction circuit according to claim 10, wherein, The multiplexer outputs the plurality of code adjustment clock signals when the first code adjustment completion signal is in an inactive state, and outputs the plurality of duty cycle detection valid signals when the first code adjustment completion signal is in an active state.

18. The duty cycle correction circuit according to claim 12, wherein, When the second code minimum / maximum detection signal is in an inactive state, the first code adjustment circuit prevents the first code from changing.

19. The duty cycle correction circuit according to claim 12, wherein, When the code set change signal is activated, the first code adjustment circuit prevents the change of the first code.

20. The duty cycle correction circuit according to claim 10, wherein, The duty cycle adjustment circuit includes: A first duty cycle adjustment circuit adjusts the phase of a first external clock signal among the plurality of external clock signals according to the first code and the second code to generate a first duty cycle correction clock signal among the plurality of duty cycle correction clock signals; and The second duty cycle adjustment circuit adjusts the phase of the second external clock signal among the multiple external clock signals according to the third and fourth codes among the multiple codes, so as to generate the second duty cycle correction clock signal among the multiple duty cycle correction clock signals.

21. The duty cycle correction circuit according to claim 20, wherein, The first duty cycle adjustment circuit includes: A first adjustment circuit delays the first external clock signal by a time corresponding to the first code to generate a first clock signal and a second clock signal; and The second adjustment circuit mixes the first clock signal and the second clock signal at a predetermined ratio according to the second code to generate the first duty cycle correction clock signal.

22. The duty cycle correction circuit according to claim 10, wherein, The code adjustment clock generation circuit includes: The source clock generation circuit divides one of the plurality of external clock signals to generate a plurality of frequency-divided clock signals, and outputs a pulse from the plurality of frequency-divided clock signals that corresponds to a segment determined by a plurality of adjustment clock segment signals as the source clock signal. A shift circuit shifts a first logic level according to the plurality of frequency-divided clock signals to generate the plurality of adjusted clock segment signals; and The clock generation circuit adjusts the clock signals according to the source clock signal, selects one of the multiple code adjustment clock signals based on the least significant bit of the first code and one of the multiple duty cycle detection valid signals, and outputs the selected one of the multiple code adjustment clock signals while preventing the output of the remaining code adjustment clock signals.

23. The duty cycle correction circuit according to claim 12, wherein, The completion determination circuit further includes: A counter is used to count the effective segment signals to generate a counting result signal; The bang-bang detection circuit generates a bang-bang detection signal based on the bang-bang reset signal and the plurality of duty cycle detection signals. The first signal generation circuit, after the effective segment signal is deactivated, activates the first code adjustment completion signal when any one of the bang-bang detection signal, the first code adjustment completion signal, and the first code increment limit detection signal is activated; and The second signal generation circuit generates the bang-bang reset signal by adjusting the activation of the signal according to the first code.

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