A clock circuit, a PCB board and a controller

Abstract

The application discloses a clock circuit, a PCB and a controller, comprising a delay chain unit, a switch unit, a bootstrap capacitor C1, a threshold detection unit and a dynamic body bias unit, the enable end of the delay chain unit and the first enable end of the switch unit are connected with an external input clock end respectively, the output end of the delay chain unit is connected with the second enable end of the switch unit, the two ends of the bootstrap capacitor C1 are connected with the input end of the threshold detection unit through the switch unit, and the output end of the threshold detection unit is connected with the input end of the dynamic body bias unit; the pre-charge signal provided by the delay chain unit cooperates with the original clock signal, thereby ensuring the accuracy of the charge and discharge timing sequence of the bootstrap capacitor C1; the threshold detection unit provides feedback basis for the dynamic body bias unit according to the output state of the bootstrap capacitor C1, so that the dynamic body bias unit can dynamically adjust the body bias voltage, so that the circuit can maintain good driving capability under low power supply voltage, which is helpful to reduce the dynamic power consumption and inhibit the increase of the leakage current.

Description

Technical Field

[0001] This invention relates to the field of clock circuit technology, and in particular to a clock circuit, PCB board and controller. Background Technology

[0002] Traditional clock buffer trees are typically driven by multi-stage inverter chains, with the final stage being a large-size CMOS inverter. However, to suppress jitter, the gate oxide of the final-stage inverter is usually thick, or low-threshold devices are used with increased channel area. Power optimization methods are limited to clock gating using complementary shorting switches or CMOS transmission gates. When the load capacitance is fixed, dynamic power consumption can be reduced by lowering the supply voltage. However, this results in an excessively high proportion of dynamic power consumption and increased leakage current. It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a clock circuit that, through the pre-charge signal provided by the delay chain unit and the original clock signal, combined with the real-time monitoring of the output state of the bootstrap capacitor by the threshold detection unit and the feedback adjustment of the body bias voltage by the dynamic body bias unit, helps to reduce dynamic power consumption and suppress leakage current growth.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A clock circuit includes a delay chain unit, a switching unit, a bootstrap capacitor C1, a threshold detection unit, and a dynamic body bias unit. The enable terminals of the delay chain unit and the first enable terminal of the switching unit are connected to an external input clock terminal. The output terminal of the delay chain unit is connected to the second enable terminal of the switching unit. The two ends of the bootstrap capacitor C1 are connected to the input terminal of the threshold detection unit through the switching unit. The output terminal of the threshold detection unit is connected to the input terminal of the dynamic body bias unit. The delay chain unit sends a pre-charge signal to the switching unit based on the original clock signal. The switching unit adjusts the charging and discharging state of the bootstrap capacitor C1 based on the pre-charge signal and the original clock signal. The threshold detection unit detects whether the output signal of the bootstrap capacitor C1 is in the flip transition region and sends a continuous body bias enable signal to the dynamic body bias unit based on the detection state. The dynamic body bias unit continuously generates a reverse body bias voltage based on the body bias enable signal.

[0005] In the clock circuit, the delay chain unit includes a first inverting part, a second inverting part, and a third inverting part connected in series. The input terminal of the first inverting part is connected to an external input clock terminal, and the output terminal of the third inverting part is connected to the second enable terminal of the switching unit.

[0006] In the clock circuit, the first inverting section includes a first field-effect transistor (FET) M1 and a second FET M2; the second inverting section includes a third FET M3 and a fourth FET M4; the third inverting section includes a fifth FET M5 and a sixth FET M6; the gates of the first FET M1 and the second FET M2 are connected to an external clock input terminal; the sources of the first FET M1, the third FET M3, and the fifth FET M5 are connected to an external power supply terminal; the sources of the second FET M2, the fourth FET M4, and the sixth FET M6 are grounded; and the drain of the first FET M1 is connected to the second FET M6. The drain of M2 is connected, and the connection node between the drains of the first field-effect transistor M1 and the second field-effect transistor M2 is connected to the gates of the third field-effect transistor M3 and the fourth field-effect transistor M4. The drain of the third field-effect transistor M3 is connected to the drain of the fourth field-effect transistor M4, and the connection node between the drains of the third field-effect transistor M3 and the fourth field-effect transistor M4 is connected to the gates of the fifth field-effect transistor M5 and the sixth field-effect transistor M6. The drain of the fifth field-effect transistor M5 is connected to the drain of the sixth field-effect transistor M6, and the connection node between the drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 is connected to the second enable terminal of the switching unit.

[0007] In the clock circuit, the switching unit includes a first switching section and a second switching section. The enable terminal of the first switching section is connected to the connection node of the drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6. The first input terminal of the first switching section is connected to an external power supply terminal, and the second input terminal of the first switching section is grounded. The output terminal of the first switching section is connected to both ends of the bootstrap capacitor C1. The enable terminal of the second switching section is connected to an external clock input terminal. The first input terminal of the second switching section is connected to an external power supply terminal, and the second input terminal of the second switching section is grounded. The output terminal of the second switching section is connected to both ends of the bootstrap capacitor C1 and the input terminal of the threshold detection unit.

[0008] In the clock circuit, the first switching section includes a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, and a tenth field-effect transistor (FET) M10; the second switching section includes an eleventh field-effect transistor (FET) M11 and a twelfth field-effect transistor (FET) M12; the sources of the seventh FET M7, the ninth FET M9, and the eleventh FET M11 are connected to an external power supply terminal, the sources of the eighth FET M8, the tenth FET M10, and the twelfth FET M12 are grounded, the gates of the seventh FET M7 and the eighth FET M8 are connected to the connection node of the drains of the fifth FET M5 and the sixth FET M6, and the seventh FET M7... The drain of transistor M7 is connected to the drain of the eighth field-effect transistor M8, and the connection node of the drains of the seventh field-effect transistor M7 and the eighth field-effect transistor M8 is connected to the gate and drain of the ninth field-effect transistor M9, the gate and drain of the tenth field-effect transistor M10, and the two ends of the bootstrap capacitor C1. The gate of the eleventh field-effect transistor M11 is connected to the gate of the twelfth field-effect transistor M12 and the external input clock terminal. The drain of the eleventh field-effect transistor M11 is connected to the drain of the twelfth field-effect transistor M12, and the connection node of the drains of the eleventh field-effect transistor M11 and the twelfth field-effect transistor M12 is connected to the two ends of the bootstrap capacitor C1 and the input terminal of the threshold detection unit.

[0009] In the clock circuit, the threshold detection unit includes a first Schmitt trigger SMT1, a second Schmitt trigger SMT2, and a fourth inverting section. The input terminals of the first Schmitt trigger SMT1 and the second Schmitt trigger SMT2 are respectively connected to the connection node of the drain of the eleventh field-effect transistor M11 and the twelfth field-effect transistor M12. The output terminal of the first Schmitt trigger SMT1 is connected to the enable terminal of the fourth inverting section. The output terminal of the fourth inverting section is connected to the enable terminal of the dynamic body bias unit. The first input terminal of the fourth inverting section is connected to the first input terminal of the dynamic body bias unit. The second input terminal of the fourth inverting section and the output terminal of the second Schmitt trigger SMT2 are respectively connected to the second input terminal of the dynamic body bias unit.

[0010] In the clock circuit, the fourth inverting section includes a thirteenth field-effect transistor (FET) M13 and a fourteenth field-effect transistor (FET) M14. The gate of the thirteenth FET M13 is connected to the gate of the fourteenth FET M14. The connection node of the gates of the thirteenth FET M13 and the fourteenth FET M14 is connected to the output terminal of the first Schmitt trigger SMT1. The source of the thirteenth FET M13 is connected to the first input terminal of the dynamic body bias unit. The source of the fourteenth FET M14 is connected to the second input terminal of the dynamic body bias unit. The drain of the thirteenth FET M13 is connected to the drain of the fourteenth FET M14. The connection node of the drains of the thirteenth FET M13 and the fourteenth FET M14 is connected to the enable terminal of the dynamic body bias unit.

[0011] In the clock circuit, the dynamic body bias unit includes a first charge pump, a second charge pump, a fifteenth field-effect transistor M15, and a sixteenth field-effect transistor M16. The input terminals of the first charge pump and the second charge pump are connected to an external power supply terminal. The output terminal of the first charge pump is connected to the source of the thirteenth field-effect transistor M13 and the fifteenth field-effect transistor M15. The output terminal of the second charge pump is connected to the output terminal of the second Schmitt trigger, the source of the fourteenth field-effect transistor M14, and the source of the sixteenth field-effect transistor M16. The gates of the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 are connected to the connection node of the drains of the thirteenth field-effect transistor M13 and the fourteenth field-effect transistor M14. The drain of the fifteenth field-effect transistor M15 is connected to the drain of the sixteenth field-effect transistor M16.

[0012] This application also provides a PCB board printed with the clock circuit described above.

[0013] This application also provides a controller that uses the clock circuit described above for operation control.

[0014] Beneficial effects: This invention provides a clock circuit where the pre-charge signal provided by the delay chain unit works in conjunction with the original clock signal to ensure the accuracy of the charging and discharging timing of the bootstrap capacitor C1. A threshold detection unit monitors the output state of the bootstrap capacitor C1 in real time, providing a feedback basis for the dynamic body bias unit. The dynamic body bias unit dynamically adjusts the body bias voltage based on the feedback results, enabling the circuit to maintain good driving capability even under low power supply voltage conditions. This also helps reduce dynamic power consumption and suppress leakage current growth, thereby optimizing the jitter characteristics of the clock signal to a certain extent and enhancing the timing stability of the circuit under various process corners. Attached Figure Description Figure 1A circuit block diagram of the clock circuit provided by the present invention; Figure 2 The circuit structure diagram of the clock circuit provided by the present invention.

[0015] Explanation of key component symbols: 1-Delay chain unit, 2-Switch unit, 3-Threshold detection unit, 4-Dynamic volume bias unit. Detailed Implementation

[0016] This invention provides a clock circuit, a PCB board, and a controller. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0017] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0018] Please see Figures 1 to 2This invention provides a clock circuit comprising a delay chain unit 1, a switching unit 2, a bootstrap capacitor C1, a threshold detection unit 3, and a dynamic body bias unit 4. The enable terminal of the delay chain unit 1 is connected to an external input clock terminal to receive the original clock signal. After delaying the original clock signal, the delay chain unit 1 sends a pre-charge signal from its output terminal to the control terminal of the switching unit 2. The switching unit 2 has two control terminals: one directly connected to the external input clock terminal to receive the original clock signal, and the other receiving the pre-charge signal from the delay chain unit 1. The output terminal of the switching unit 2 is connected to both ends of the bootstrap capacitor C1 and the input terminal of the threshold detection unit 3. The switching unit 2 is configured to respond to a logical combination of the original clock signal and the pre-charge signal by switching internal path connections to adjust the charging and discharging state of the bootstrap capacitor C1, thereby generating a clock signal with increased swing at the output terminal of the bootstrap capacitor C1. The bootstrap capacitor C1, as a charge storage and transfer element, is connected across the output nodes of the switching unit 2. Under the control of switching unit 2, bootstrap capacitor C1 performs pre-charging and charge transfer operations at different stages of the clock cycle, thereby achieving potential bootstrapping of the output node and enhancing its driving capability for subsequent circuits. The input of threshold detection unit 3 is connected to the output of bootstrap capacitor C1 to monitor the voltage level of the output signal in real time. Threshold detection unit 3 is configured to identify whether the output signal is in a voltage transition region. When a signal is detected entering this transition region, threshold detection unit 3 sends a continuous body bias enable signal to dynamic body bias unit 4. This detection mechanism utilizes the transient characteristics of the signal to accurately capture changes in the clock edge. The input of dynamic body bias unit 4 is connected to the output of threshold detection unit 3 to receive the body bias enable signal. In response to this signal, dynamic body bias unit 4 continuously generates a reverse body bias voltage. This reverse body bias voltage is applied to the substrate of the key transistor in the clock circuit, optimizing the switching speed and leakage current characteristics of the circuit by dynamically adjusting the threshold voltage of the transistor.

[0019] During operation, after the original clock signal is input, it undergoes multi-stage processing by delay chain unit 1 to generate a pre-charge signal with a certain phase lag characteristic. This pre-charge signal, together with the original clock signal, acts on switching unit 2, driving the control logic within switching unit 2 to periodically manage the charging and discharging of the bootstrap capacitor according to a specific timing relationship. Within the preset phase interval of the clock signal, switching unit 2 responds to the pre-charge signal, establishing a charging path for the bootstrap capacitor to store charge. In subsequent phase intervals, switching unit 2 responds to changes in the original clock signal, reconstructing the connection relationship of the bootstrap capacitor, enabling it to output a clock signal with a higher amplitude than the conventional supply voltage during discharge, thereby enhancing the overall driving capability of the circuit. Simultaneously, threshold detection unit 3 monitors the voltage state at the output terminal of the bootstrap capacitor in real time. Since the bootstrap capacitor inevitably experiences a voltage reversal transition region during charging and discharging, threshold detection unit 3 utilizes its unique hysteresis characteristics to accurately capture the signal characteristics of this transition region and perform signal shaping. When a specific voltage reversal state is detected, threshold detection unit 3 immediately outputs a corresponding volume bias enable signal to dynamic volume bias unit 4. Upon receiving the signal, the dynamic body bias unit 4 activates its internal charge pump circuit, generating and outputting a reverse body bias voltage. This reverse body bias voltage is fed back to the substrate of the key transistor inside the circuit, adjusting its switching characteristics and conduction current by changing the transistor's threshold voltage.

[0020] In this embodiment, the pre-charge signal provided by delay chain unit 1, in conjunction with the original clock signal, ensures the accuracy of the charging and discharging timing of bootstrap capacitor C1. The threshold detection unit 3's real-time monitoring of the output state of bootstrap capacitor C1 provides feedback to the dynamic body bias unit 4. The dynamic body bias unit 4 dynamically adjusts the body bias voltage based on the feedback result, enabling the circuit to maintain good driving capability even at low power supply voltages. This also helps reduce dynamic power consumption and suppress the increase in leakage current, thereby improving the jitter characteristics of the clock signal to a certain extent and enhancing the timing stability of the circuit under various process corners.

[0021] Delay chain unit 1 serves as the front end for receiving the original clock signal, and its enable terminal is connected to the external input clock terminal. Specifically, delay chain unit 1 can be composed of multiple inverters connected in series, for example, it can include a first inverter section, a second inverter section, and a third inverter section connected in series. Each inverter section can be composed of a pair of complementary metal-oxide-semiconductor field-effect transistors. Taking the first inverter section as an example, it includes a first field-effect transistor M1 and a second field-effect transistor M2, with their gates connected as the input terminal and their drains connected as the output terminal. The second inverter section includes a third field-effect transistor M3 and a fourth field-effect transistor M4, and the third inverter section includes a fifth field-effect transistor M5 and a sixth field-effect transistor M6. The sources of the first field-effect transistor M1, the third field-effect transistor M3, and the fifth field-effect transistor M5 are all connected to the external power supply terminal, while the sources of the second field-effect transistor M2, the fourth field-effect transistor M4, and the sixth field-effect transistor M6 are grounded. This multi-stage cascaded structure can shape and delay the input clock, and output a precharge signal from the output terminal of the third inverter section to the switching unit 2.

[0022] The first enable terminal of switching unit 2 is directly connected to the external input clock terminal, while the second enable terminal is connected to the output terminal of delay chain unit 1. Switching unit 2 can be internally divided into a first switching section and a second switching section. The first switching section is mainly responsible for responding to the pre-charge signal of delay chain unit 1 and controlling the charging circuit of bootstrap capacitor C1; the second switching section responds to the original clock signal and controls the discharging and output circuit of bootstrap capacitor C1. Specifically, the first switching section may include a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, and a tenth field-effect transistor M10. The seventh and eighth field-effect transistors M7 and M8 constitute the first-stage switch, whose gates are controlled by the pre-charge signal, and whose drain connections further control the conduction and cutoff of the ninth and tenth field-effect transistors M9 and M10, thereby achieving potential control across the bootstrap capacitor C1. The second switching section may include an eleventh field-effect transistor M11 and a twelfth field-effect transistor M12, both of whose gates are connected to the original clock signal, serving as the main switch to control the output of bootstrap capacitor C1. With this dual-switch control, the circuit can precisely operate the bootstrap capacitor C1 at different clock phases.

[0023] The bootstrap capacitor C1 is connected to the output node of switching unit 2. During different phases of the clock signal, switching unit 2 changes the connection of bootstrap capacitor C1. For example, during the pre-charge phase, one end of bootstrap capacitor C1 is pulled high to the supply voltage, while the other end is grounded through the switch to complete the pre-charge. During the evaluation phase, the pre-charged charge is transferred, allowing the output node voltage to exceed the supply voltage, thus achieving the bootstrap effect. This helps improve the switching speed of subsequent driver stages.

[0024] Switching unit 2 can be divided into two stages during operation: During the pre-charge phase of the clock signal, the pre-charge signal output by delay chain unit 1 reaches a specific level. At this time, the control path in switching unit 2 that responds to the pre-charge signal is activated. Specifically, the pre-charge signal is applied to the gates of the seventh field-effect transistor M7 and the eighth field-effect transistor M8, causing the seventh field-effect transistor M7 to turn on and the eighth field-effect transistor M8 to turn off. The conduction of the seventh field-effect transistor M7 pulls the gates of the ninth field-effect transistor M9 and the tenth field-effect transistor M10 to a high potential, thereby controlling the ninth field-effect transistor M9 to turn off and the tenth field-effect transistor M10 to turn on. In this state, one end of the bootstrap capacitor C1 is connected to the external power supply through the conducting seventh field-effect transistor M7 for charging, and the other end is grounded through the conducting tenth field-effect transistor M10, completing the storage of the pre-charge charge. At the same time, the path in switching unit 2 that responds to the original clock signal is in the off state, that is, the eleventh field-effect transistor M11 and the twelfth field-effect transistor M12 remain off under the control of the original clock signal, thereby isolating the bootstrap capacitor C1 from the subsequent load and preventing charge leakage.

[0025] When the circuit enters the evaluation phase, the original clock signal flips, activating the control path in switching unit 2 that responds to the original clock signal. At this time, the original clock signal is applied to the gates of the eleventh field-effect transistor M11 and the twelfth field-effect transistor M12, causing M11 to turn off and M12 to turn on. Simultaneously, the precharge signal output from delay chain unit 1 also flips, causing M7 to turn off and M8 to turn on. The turn-on of M8 pulls down the gate potentials of M9 and M10, causing M9 to turn on and M10 to turn off. Under this connection, the bootstrap capacitor C1 is no longer directly connected to the power supply and ground, but is connected to the output node through the conducting M9 and M12. Since the bootstrap capacitor C1 has stored charge during the pre-charge phase, the voltage difference across the bootstrap capacitor C1 remains constant as the output node potential changes with the clock signal, thereby raising the output node potential to a level exceeding the external supply voltage and achieving bootstrap voltage boost.

[0026] By utilizing the time difference between the precharge signal and the original clock signal, the precharge phase and the evaluation phase are separated, effectively preventing a DC path between the power supply and ground, and helping to reduce short-circuit power consumption. Simultaneously, the over-supply voltage output generated by the bootstrap capacitor C1 during the evaluation phase enhances the drive capability of the output node, accelerates the switching speed of subsequent circuits, and thus improves the edge characteristics of the clock signal to some extent. Furthermore, this structure allows the circuit to maintain stable performance at lower supply voltages, helping to alleviate the problem of increased leakage current in low-voltage designs and improving the timing stability of the circuit in low-power modes.

[0027] The input terminal of threshold detection unit 3 is connected to the output terminal of bootstrap capacitor C1. To capture the switching state of the bootstrap capacitor's output voltage, threshold detection unit 3 can employ a Schmitt trigger structure. Specifically, it can include a first Schmitt trigger SMT1 and a second Schmitt trigger SMT2. The input terminals of these two Schmitt triggers are connected in parallel to the output node of bootstrap capacitor C1. Due to the hysteresis characteristic of the Schmitt trigger, it can effectively filter out glitches and noise in the switching transition region, improving anti-interference capability. The output terminal of the first Schmitt trigger SMT1 is connected to the enable terminal of the fourth inverting section, which can be composed of a thirteenth field-effect transistor M13 and a fourteenth field-effect transistor M14. The gates of the thirteenth and fourteenth field-effect transistors M13 and M14 are connected and receive the signal from the first Schmitt trigger SMT1. Their sources are respectively connected to different input terminals of the dynamic body bias unit 4, and their drains are connected together as the output terminal of the fourth inverting section, connected to the enable terminal of the dynamic body bias unit 4. The output terminal of the second Schmitt trigger SMT2 is directly connected to the other input terminal of the dynamic body bias unit 4. With this configuration, the threshold detection unit 3 can generate a corresponding body bias enable signal based on the voltage state of the bootstrap capacitor C1.

[0028] The dynamic body bias unit 4 dynamically generates a reverse body bias voltage based on the signal from the threshold detection unit 3. This unit may include a first charge pump, a second charge pump, and a fifteenth field-effect transistor (FET) M15 and a sixteenth field-effect transistor (FET) M16. The inputs of both the first and second charge pumps are connected to an external power supply to convert the power supply voltage to generate the desired body bias voltage. The output of the first charge pump is connected to the source of the fifteenth FET M15 and the aforementioned thirteenth FET M13; the output of the second charge pump is connected to the source of the sixteenth FET M16 and the fourteenth FET M14. The gates of the fifteenth and sixteenth FETs M15 are connected and controlled by the output signal of the fourth inverting section. When the circuit detects that the clock signal is in a specific flip-flop range, the dynamic body bias unit 4 is activated, the charge pumps begin operating, and a body bias voltage higher than the power supply voltage or lower than ground is generated and applied to the substrate of the critical transistor.

[0029] To ensure stable operation of the circuit under different process angles and temperatures, this invention also incorporates a feedback adjustment mechanism. The reverse body bias voltage generated by the dynamic body bias unit 4 is not constant but dynamically adjusted based on the monitoring results of the bootstrap capacitor C1 by the threshold detection unit 3. For example, when a slower rising or falling edge of the output signal is detected, the pulse width output by the threshold detection unit 3 changes, thereby adjusting the on-time or output amplitude of the charge pump in the dynamic body bias unit 4. This alters the voltage applied to the MOS transistor substrate, adjusting its threshold voltage and ultimately optimizing circuit performance. This dynamic adjustment helps reduce performance fluctuations caused by process variations to some extent, and also helps reduce the increase in leakage current caused by a decrease in power supply voltage.

[0030] During operation, when the external input clock signal is low, delay chain unit 1 outputs a high level, controlling the first switch to turn on and pre-charging the bootstrap capacitor C1. At this time, the second switch is off, and the output node is isolated. When the external input clock signal jumps to a high level, the second switch turns on, releasing the charge stored in the bootstrap capacitor C1, causing the voltage of the output node to rise, forming a bootstrap. Simultaneously, threshold detection unit 3 monitors the voltage change of the output node in real time. When the voltage crosses the threshold point of the Schmitt trigger, the output states of the first Schmitt trigger SMT1 and the second Schmitt trigger SMT2 flip, controlling the fifteenth field-effect transistor M15 and the sixteenth field-effect transistor M16 in the dynamic body bias unit 4 through the fourth inverting unit. This causes the first and second charge pumps to begin pumping charge into the corresponding nodes, generating a reverse body bias voltage. This reverse body bias voltage acts on key transistors in the clock buffer path, adjusting their conduction capability and switching speed, thereby helping to improve the jitter characteristics of the clock signal and reduce the overall circuit's dynamic power consumption.

[0031] In summary, by introducing a delay chain, switching unit 2, and bootstrap capacitor, combined with threshold detection and dynamic body bias technology, this clock circuit can adapt to different load conditions. By dynamically adjusting the body bias voltage, it alleviates to some extent the problems of increased leakage current and excessive dynamic power consumption under low voltage design.

[0032] This application also provides a PCB board printed with the clock circuit described above.

[0033] This application also provides a controller that uses the clock circuit described above for operation control.

[0034] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A clock circuit, characterized in that, The system includes a delay chain unit, a switching unit, a bootstrap capacitor C1, a threshold detection unit, and a dynamic body bias unit. The enable terminals of the delay chain unit and the first enable terminal of the switching unit are connected to an external input clock. The output terminal of the delay chain unit is connected to the second enable terminal of the switching unit. The two ends of the bootstrap capacitor C1 are connected to the input terminal of the threshold detection unit through the switching unit. The output terminal of the threshold detection unit is connected to the input terminal of the dynamic body bias unit. The delay chain unit sends a pre-charge signal to the switching unit based on the original clock signal. The switching unit adjusts the charging and discharging state of the bootstrap capacitor C1 based on the pre-charge signal and the original clock signal. The threshold detection unit detects whether the output signal of the bootstrap capacitor C1 is in the flip transition region and sends a continuous body bias enable signal to the dynamic body bias unit based on the detection state. The dynamic body bias unit continuously generates a reverse body bias voltage based on the body bias enable signal.

2. The clock circuit according to claim 1, characterized in that, The delay chain unit includes a first inverting section, a second inverting section, and a third inverting section connected in series. The input terminal of the first inverting section is connected to an external input clock terminal, and the output terminal of the third inverting section is connected to the second enable terminal of the switching unit.

3. The clock circuit according to claim 2, characterized in that, The first inverting section includes a first field-effect transistor M1 and a second field-effect transistor M2; the second inverting section includes a third field-effect transistor M3 and a fourth field-effect transistor M4; the third inverting section includes a fifth field-effect transistor M5 and a sixth field-effect transistor M6; the gates of the first field-effect transistor M1 and the second field-effect transistor M2 are connected to an external input clock terminal; the sources of the first field-effect transistor M1, the third field-effect transistor M3, and the fifth field-effect transistor M5 are connected to an external power supply terminal; the sources of the second field-effect transistor M2, the fourth field-effect transistor M4, and the sixth field-effect transistor M6 are grounded; the drain of the first field-effect transistor M1 and the drain of the second field-effect transistor M2 are connected to each other. The connection is made such that the drain of the first field-effect transistor M1 and the drain of the second field-effect transistor M2 are connected to the gate of the third field-effect transistor M3 and the fourth field-effect transistor M4, the drain of the third field-effect transistor M3 is connected to the drain of the fourth field-effect transistor M4, the drain of the third field-effect transistor M3 and the fourth field-effect transistor M4 are connected to the gate of the fifth field-effect transistor M5 and the sixth field-effect transistor M6, the drain of the fifth field-effect transistor M5 is connected to the drain of the sixth field-effect transistor M6, and the drain of the fifth field-effect transistor M5 and the sixth field-effect transistor M6 is connected to the second enable terminal of the switching unit.

4. The clock circuit according to claim 3, characterized in that, The switching unit includes a first switching section and a second switching section. The enable terminal of the first switching section is connected to the connection node of the drains of the fifth field-effect transistor M5 and the sixth field-effect transistor M6. The first input terminal of the first switching section is connected to an external power supply terminal, and the second input terminal of the first switching section is grounded. The output terminal of the first switching section is connected to both ends of the bootstrap capacitor C1. The enable terminal of the second switching section is connected to an external input clock terminal. The first input terminal of the second switching section is connected to an external power supply terminal, and the second input terminal of the second switching section is grounded. The output terminal of the second switching section is connected to both ends of the bootstrap capacitor C1 and the input terminal of the threshold detection unit.

5. The clock circuit according to claim 4, characterized in that, The first switching section includes a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, and a tenth field-effect transistor (FET) M10; the second switching section includes an eleventh field-effect transistor (FET) M11 and a twelfth field-effect transistor (FET) M12; the sources of the seventh FET M7, the ninth FET M9, and the eleventh FET M11 are connected to an external power supply terminal; the sources of the eighth FET M8, the tenth FET M10, and the twelfth FET M12 are grounded; the gates of the seventh FET M7 and the eighth FET M8 are connected to the connection node of the drains of the fifth FET M5 and the sixth FET M6; the drain of the seventh FET M7... The drain of the seventh field-effect transistor M7 is connected to the drain of the eighth field-effect transistor M8, and the connection node between the drains of the seventh field-effect transistor M7 and the eighth field-effect transistor M8 is connected to the gate and drain of the ninth field-effect transistor M9, the gate and drain of the tenth field-effect transistor M10, and the two ends of the bootstrap capacitor C1. The gate of the eleventh field-effect transistor M11 is connected to the gate of the twelfth field-effect transistor M12 and the external input clock terminal. The drain of the eleventh field-effect transistor M11 is connected to the drain of the twelfth field-effect transistor M12, and the connection node between the drains of the eleventh field-effect transistor M11 and the twelfth field-effect transistor M12 is connected to the two ends of the bootstrap capacitor C1 and the input terminal of the threshold detection unit.

6. The clock circuit according to claim 5, characterized in that, The threshold detection unit includes a first Schmitt trigger SMT1, a second Schmitt trigger SMT2, and a fourth inverting section. The input terminals of the first Schmitt trigger SMT1 and the second Schmitt trigger SMT2 are respectively connected to the connection node of the drain of the eleventh field-effect transistor M11 and the twelfth field-effect transistor M12. The output terminal of the first Schmitt trigger SMT1 is connected to the enable terminal of the fourth inverting section. The output terminal of the fourth inverting section is connected to the enable terminal of the dynamic volume bias unit. The first input terminal of the fourth inverting section is connected to the first input terminal of the dynamic volume bias unit. The second input terminal of the fourth inverting section and the output terminal of the second Schmitt trigger SMT2 are respectively connected to the second input terminal of the dynamic volume bias unit.

7. The clock circuit according to claim 6, characterized in that, The fourth inverting section includes a thirteenth field-effect transistor (FET) M13 and a fourteenth field-effect transistor (FET) M14. The gate of the thirteenth FET M13 is connected to the gate of the fourteenth FET M14. The connection node of the gates of the thirteenth FET M13 and the fourteenth FET M14 is connected to the output terminal of the first Schmitt trigger SMT1. The source of the thirteenth FET M13 is connected to the first input terminal of the dynamic body bias unit. The source of the fourteenth FET M14 is connected to the second input terminal of the dynamic body bias unit. The drain of the thirteenth FET M13 is connected to the drain of the fourteenth FET M14. The connection node of the drains of the thirteenth FET M13 and the fourteenth FET M14 is connected to the enable terminal of the dynamic body bias unit.

8. The clock circuit according to claim 7, characterized in that, The dynamic body bias unit includes a first charge pump, a second charge pump, a fifteenth field-effect transistor (FET) M15, and a sixteenth field-effect transistor (FET) M16. The input terminals of the first and second charge pumps are connected to an external power supply. The output terminal of the first charge pump is connected to the source terminals of the thirteenth FET M13 and the fifteenth FET M15. The output terminal of the second charge pump is connected to the output terminal of the second Schmitt trigger, the source terminal of the fourteenth FET M14, and the source terminal of the sixteenth FET M16. The gate terminals of the fifteenth FET M15 and the sixteenth FET M16 are connected to the connection node of the drain terminals of the thirteenth FET M13 and the fourteenth FET M14. The drain terminal of the fifteenth FET M15 is connected to the drain terminal of the sixteenth FET M16.

9. A PCB board, characterized in that, The PCB board is printed with a clock circuit as described in any one of claims 1-8.

10. A controller, characterized in that, The controller employs a clock circuit as described in any one of claims 1-8.

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