Second pulse signal jitter detection method and device and electronic equipment

Abstract

The application discloses a PPS signal jitter detection method and device and electronic equipment; the method comprises the following steps: acquiring a reference PPS signal and a measured PPS signal; in the case that a first rising edge of the reference PPS signal is detected, a current first count value corresponding to the time when the first rising edge arrives is latched, and a current second count value corresponding to the measured PPS signal is latched; the number of real-time clock cycles between the rising edges of the reference PPS signal is acquired, and a target cycle number in the number of real-time clock cycles is intercepted as a judgment threshold; in the case that a first difference between the current first count value and the current second count value is greater than the judgment threshold, a second difference between the number of real-time clock cycles and the first difference is used to determine a jitter detection result. The technical scheme can avoid calculating a large error difference, flexibly cope with the possible cross-second jump of the PPS signal, and improve the jitter detection effect.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to a method, apparatus and electronic device for detecting jitter in a second pulse signal. Background Technology

[0002] In distributed systems, the Pulse Per Second (PPS) signal is often used as a time reference. For example, base stations use the PPS signal output by the Global Navigation Satellite System (GNSS) (i.e., the reference PPS signal) for air interface time calibration. However, due to transmission link noise, crystal oscillator aging, and ambient temperature variations, locally generated PPS signals or the PPS signals being compared often exhibit jitter. Therefore, it is necessary to detect the jitter between the measured PPS signal and the reference PPS signal.

[0003] Currently, the main method for jitter detection in PPS signals is the dedicated Time-to-Digital Converter (TDC) chip method, which uses a high-precision TDC chip to measure the time interval. However, high-precision TDC chips are relatively expensive and cannot flexibly handle the potential cross-second jumps in PPS signals (i.e., when the phase difference between the measured PPS signal and the reference PPS signal is close to 1 second, simple subtraction will yield a huge erroneous difference instead of the actual tiny jitter), resulting in poor jitter detection performance. Summary of the Invention

[0004] This application provides a method, apparatus, electronic device, and readable storage medium for jitter detection based on second pulse signals. The jitter detection calculation process can be fully implemented using digital logic, without the need for external dedicated chips. It is easy to implement in a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC), reducing detection costs. At the same time, a portion of the real-time clock cycles between the rising edges of the reference second pulse signal is introduced as a judgment threshold. If the first difference between the current first count value and the current second count value is greater than the judgment threshold, the first difference is not used as the jitter detection result. Instead, the jitter detection result is determined based on the second difference between the real-time clock cycles and the first difference. Even if the phase difference between the measured PPS signal and the reference PPS signal is close to 1 second, it can avoid calculating a huge difference that may lead to errors, so as to flexibly deal with possible cross-second jumps in the PPS signal and improve the jitter detection effect.

[0005] In a first aspect, embodiments of this application provide a method for detecting jitter in a second pulse signal, including: Acquire the reference second pulse signal and the measured second pulse signal; Upon detecting the first rising edge of the reference second pulse signal, the current first count value corresponding to the arrival time of the first rising edge is latched, and the current second count value corresponding to the measured second pulse signal is latched. Obtain the number of real-time clock cycles between the rising edges of the reference second pulse signal, and extract the target number of cycles from the real-time clock cycle count as the judgment threshold; If the first difference between the current first count value and the current second count value is greater than the determination threshold, the jitter detection result is determined based on the second difference between the real-time clock cycle number and the first difference.

[0006] Optionally, obtaining the number of real-time clock cycles between the rising edges of the reference second pulse signal includes: Determine the previous first rising edge corresponding to the first rising edge currently detected by the reference second pulse signal; Obtain the historical first count value corresponding to the arrival time of the previous first rising edge that has been latched; The difference between the current first count value and the historical first count value is determined as the number of real-time clock cycles between the rising edges of the reference second pulse signal; Wherein, the number of real-time clock cycles is the number of local high-frequency clock cycles actually occupied by one complete cycle of the reference second pulse signal.

[0007] Optionally, before latching the current first count value corresponding to the arrival time of the first rising edge, the method further includes: The reference second pulse signal and the measured second pulse signal are synchronized to the same local high-frequency clock so that the data transition edges of the reference second pulse signal and the measured second pulse signal are aligned with the rising edge of the local high-frequency clock; the same local high-frequency clock is generated by a local crystal oscillator and has a fixed frequency; The detection process of the first rising edge of the reference second pulse signal includes: The first rising edge of the reference second pulse signal is detected according to the synchronized local high-frequency clock; The latching of the current second count value corresponding to the measured second pulse signal includes: The second rising edge of the measured second pulse signal is detected based on the synchronized local high-frequency clock. Latch the current second count value corresponding to the arrival time of the current second rising edge.

[0008] Optionally, the first count value is obtained by continuously accumulating the period of the reference second pulse signal from zero using the local high-frequency clock as the counting pulse and a first counter; the second count value is obtained by continuously accumulating the period of the measured second pulse signal from zero using the local high-frequency clock as the counting pulse and a second counter; wherein neither the first counter nor the second counter returns to zero.

[0009] Optionally, determining the jitter detection result based on the second difference between the number of real-time clock cycles and the first difference includes: Multiple first rising edges of the reference second pulse signal are detected, and a second difference between the number of real-time clock cycles corresponding to each first rising edge and the first difference is calculated. The multiple second differences are smoothed to obtain a smoothing result, and the smoothing result is determined as the jitter detection result.

[0010] Optionally, the smoothing process for the plurality of second differences to obtain a smoothing result includes: Multiple second differences are sequentially stored into a shift register sequence of a preset depth; wherein, each time a new second difference is stored in the shift register sequence, the earliest stored second difference is discarded, so as to ensure that the shift register sequence always contains the number of most recently generated second differences corresponding to the preset depth. Calculate the arithmetic mean of the number of second differences currently stored in the shift register sequence corresponding to the preset depth, and determine the arithmetic mean as the smoothing result.

[0011] Optionally, the step of extracting the target number of cycles from the real-time clock cycle count as the determination threshold includes: Half of the real-time clock cycles are taken as the judgment threshold; The method further includes: If the first difference between the current first count value and the current second count value is less than or equal to the determination threshold, the first difference is determined as the jitter detection result.

[0012] Secondly, embodiments of this application provide a second pulse signal jitter detection device, comprising: The acquisition unit is used to acquire the reference second pulse signal and the measured second pulse signal; A latching unit is used to latch the current first count value corresponding to the arrival time of the first rising edge when the first rising edge of the reference second pulse signal is detected, and to latch the current second count value corresponding to the measured second pulse signal. The interception unit is used to obtain the number of real-time clock cycles between the rising edges of the reference second pulse signal, and intercept the target number of cycles from the number of real-time clock cycles as a judgment threshold. The determining unit is configured to determine a jitter detection result based on a second difference between the number of real-time clock cycles and the first difference when the first difference between the current first count value and the current second count value is greater than the determination threshold.

[0013] Thirdly, embodiments of this application provide an electronic device, which includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the method described in the first aspect.

[0014] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the method described in the first aspect.

[0015] In this embodiment, the periods of the reference second pulse signal and the measured second pulse signal are first continuously counted to obtain a first count value corresponding to the reference second pulse signal and a second count value corresponding to the measured second pulse signal. Each time the first rising edge of the reference second pulse signal is detected, the current first count value corresponding to the arrival time of the first rising edge of the reference second pulse signal is latched, and the current second count value corresponding to the measured second pulse signal is latched. A portion of the real-time clock cycles between the rising edges of the reference second pulse signal is extracted as a judgment threshold. If the first difference between the current first count value and the current second count value is greater than the judgment threshold, the jitter detection result is determined based on the second difference between the real-time clock cycles and the first difference.

[0016] The jitter detection calculation process can be fully implemented using digital logic, without the need for external dedicated chips. It is easy to implement in a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), reducing detection costs. At the same time, a portion of the real-time clock cycles between the rising edges of the reference second pulse signal is introduced as a judgment threshold. If the first difference between the current first count value and the current second count value is greater than the judgment threshold, the first difference is not used as the jitter detection result. Instead, the jitter detection result is determined based on the second difference between the real-time clock cycles and the first difference. Even if the phase difference between the measured PPS signal and the reference PPS signal is close to 1 second, it can avoid calculating a huge difference that may lead to errors. This allows for flexible handling of possible cross-second transitions in the PPS signal and improves the jitter detection effect. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a second pulse signal calibration scenario in related technologies; Figure 2 This is a schematic flowchart of a second pulse signal jitter detection method according to an embodiment of this application; Figure 3 A flowchart illustrating a specific implementation process for obtaining the number of real-time clock cycles provided in this application embodiment; Figure 4 A flowchart illustrating a specific implementation process for determining jitter detection results, provided in an embodiment of this application; Figure 5 A flowchart illustrating a specific implementation process for obtaining a smoothing result, provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a second pulse signal jitter detection device according to an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0021] The second pulse signal jitter detection method, apparatus, electronic device, and readable storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0022] Please see Figure 1 First, we will provide an exemplary introduction to the second pulse signal calibration scenario in related technologies: like Figure 1 As shown, Figure 1This diagram illustrates a pulse-per-second (PPS) signal calibration scenario in related technologies. In distributed systems, the Pulse Per Second (PPS) signal is often used as a time reference. For example, base stations use the PPS signal output by the Global Navigation Satellite System (GNSS) (i.e., the reference PPS signal) for air interface time calibration. However, due to transmission link noise, crystal oscillator aging, and environmental temperature variations, locally generated PPS signals or the PPS signals being compared often exhibit jitter. Therefore, it is necessary to detect the jitter between the measured PPS signal and the reference PPS signal.

[0023] Currently, the main method for jitter detection in PPS signals is the dedicated Time-to-Digital Converter (TDC) chip method, which uses a high-precision TDC chip to measure the time interval. However, high-precision TDC chips are expensive and cannot flexibly handle the potential cross-second jumps in the PPS signal (i.e., when the phase difference between the measured PPS signal and the reference PPS signal is close to 1 second, simple subtraction will yield a huge erroneous difference instead of the actual tiny jitter), resulting in poor jitter detection performance. Another related technology uses a fixed-parameter counting method for jitter detection. This method uses a fixed-frequency clock inside the FPGA to count the PPS periods. However, the fixed-parameter counting method assumes that the local clock frequency is absolutely accurate (e.g., precisely 250MHz). In practical applications, local crystal oscillators have errors at the ppm level and temperature drift. Once the local clock frequency deviates, the measured 1-second scale itself becomes incorrect, leading to a large systematic error in the calculated jitter value.

[0024] It is worth noting that the above description of the second pulse signal calibration scenario in the relevant technology is only an exemplary demonstration. In practical applications, other types of second pulse signal calibration scenarios may exist, and no specific limitations are made for them.

[0025] To address the aforementioned problems, this application provides a method for detecting jitter in a pulse-per-second (PPS) signal. This method avoids calculating large, erroneous differences, flexibly responding to potential cross-second jumps in the PPS signal and improving jitter detection performance. Figure 2 As shown, Figure 2 This is a flowchart illustrating a second pulse signal jitter detection method according to an embodiment of this application. The method includes the following steps: S201. Obtain the reference second pulse signal and the measured second pulse signal.

[0026] The reference second pulse signal can refer to a standard second pulse signal used as a time reference. In some embodiments, the reference second pulse signal can typically be generated by a high-precision clock source, such as a 1PPS signal output by a GNSS receiver, with a nominal period of 1 second, to provide a stable time reference.

[0027] The measured second pulse signal can refer to the second pulse signal whose jitter needs to be detected. In some embodiments, the measured second pulse signal can be a PPS signal generated by local crystal oscillator frequency division, or a PPS signal after transmission link. Its period should theoretically be 1 second, but due to the influence of various interference factors, the measured second pulse signal may have edge offset. It can be understood that the phase difference between the measured second pulse signal and the reference second pulse signal reflects the degree of jitter of the measured signal.

[0028] Optionally, the method of obtaining the reference second pulse signal may include: directly acquiring the externally input PPS signal, i.e., the reference second pulse signal, through the general-purpose input / output pins of the FPGA.

[0029] Optionally, the method of obtaining the measured second pulse signal may include: obtaining the locally generated PPS signal from the internal clock divider module of the base station.

[0030] S202. When the first rising edge of the reference second pulse signal is detected, latch the current first count value corresponding to the arrival time of the first rising edge, and latch the current second count value corresponding to the measured second pulse signal.

[0031] The first rising edge can refer to the moment when the reference second pulse signal jumps from a low level to a high level, which marks the beginning of a new second cycle.

[0032] The first count value can refer to the current count value obtained by continuously counting the period of the reference second pulse signal. In some embodiments, the first count value can be the local high-frequency clock as the counting pulse, which starts to accumulate after the system starts up and does not return to zero with the change of the PPS signal period.

[0033] The second count value can refer to the current count value obtained by continuously counting the period of the measured second pulse signal. In some embodiments, the second count value can be continuously accumulated using a local high-frequency clock as the counting pulse.

[0034] Latching refers to saving the current count value of a counter to a register at a specific trigger point so that the difference in count values ​​can be calculated later. Latching operations are atomic, ensuring that the saved value strictly corresponds to the trigger point.

[0035] Optionally, the detection method for the first rising edge of the reference second pulse signal may include: first synchronizing the reference second pulse signal and the measured second pulse signal to the same local high-frequency clock generated by the local crystal oscillator with a fixed frequency, so that the data transition edges of the reference second pulse signal and the measured second pulse signal are aligned with the rising edge of the local high-frequency clock, and then detecting the first rising edge of the reference second pulse signal according to the synchronized local high-frequency clock.

[0036] Synchronization can refer to aligning the level changes of the asynchronous input PPS signal with the rising edge of the local high-frequency clock by using a register-based timing mechanism, thereby eliminating the risk of metastability.

[0037] A local crystal oscillator can refer to a quartz crystal resonator mounted on a circuit board that, in conjunction with an oscillation circuit, generates a stable square wave clock signal.

[0038] The same local high-frequency clock can refer to the operating clock of the entire system, which is generated by the local crystal oscillator and has a fixed frequency. In some embodiments, all counters, registers, and logic operations can run under this local high-frequency clock domain. However, since the externally input PPS signal (reference PPS signal) is asynchronous with the local high-frequency clock, direct sampling may lead to metastability, so two- or three-stage register synchronization processing may be required.

[0039] A data transition edge refers to the extremely brief physical transition process of a digital logic signal between a low level (such as logic 0) and a high level (such as logic 1). A data transition edge is not a continuous level state, but a momentary state switch.

[0040] A rising edge can be a specific form of a data transition edge, which can refer to the instant when a digital signal transitions from logic 0 (low level) to logic 1 (high level).

[0041] In some embodiments, synchronizing the reference second pulse signal and the measured second pulse signal to the same local high-frequency clock generated by a local crystal oscillator with a fixed frequency, so that the data transition edges of both the reference second pulse signal and the measured second pulse signal are aligned with the rising edge of the local high-frequency clock, may include: synchronizing the reference second pulse signal and the measured second pulse signal using two-stage flip-flops respectively. In this case, the data input of the first-stage flip-flop is connected to the asynchronous PPS signal (either the reference second pulse signal or the measured second pulse signal), and its clock input is connected to the local high-frequency clock. The data input of the second-stage flip-flop is connected to the output of the first-stage flip-flop, and its clock input is also connected to the local high-frequency clock. After synchronization by the two-stage flip-flops, the data transition edge of the output synchronized PPS signal (either the reference second pulse signal or the measured second pulse signal) is aligned with the rising edge of the local high-frequency clock, and the metastability probability is extremely low. In other embodiments, the two synchronized PPS signals can be denoted as synchronized reference PPS and synchronized measured PPS, respectively, and can be used for subsequent rising edge detection and counter latching.

[0042] In some embodiments, detecting the first rising edge of the reference second pulse signal based on the synchronized local high-frequency clock may include: comparing the value of the current clock cycle of the synchronized reference PPS signal with the value of the previous clock cycle based on the synchronized local high-frequency clock, and determining that a rising edge (i.e., the first rising edge) of the reference second pulse signal has been detected when the value of the current clock cycle is high and the value of the previous clock cycle is low.

[0043] It should be noted that, corresponding to the first rising edge, the rising edge of the measured second pulse signal can be referred to as the second rising edge.

[0044] In other embodiments, the method of detecting the second rising edge of the measured second pulse signal based on the synchronized local high-frequency clock may include: determining the second rising edge of the measured second pulse signal by comparing the current value of the synchronized measured PPS signal with the level of the delay value based on the synchronized local high-frequency clock.

[0045] Understandably, the detection of the second rising edge is used to determine the edge position of the PPS signal under test, but the trigger time for latching the second count value is still the first rising edge of the reference PPS, not the second rising edge of the PPS under test.

[0046] Optionally, the method of latching the current first count value corresponding to the arrival time of the first rising edge may include: connecting the enable terminal of the first latch register to the detection pulse of the first rising edge, connecting the data input terminal of the first latch register to the output of the first counter, and latching the current output first count value of the first counter into the first latch register when the detection pulse of the first rising edge is valid.

[0047] Optionally, the method of latching the current second count value corresponding to the measured second pulse signal may include: connecting the enable terminal of the second latch register to the detection pulse of the first rising edge, connecting the data input terminal of the second latch register to the output of the second counter, and storing the current output second count value of the second counter into the second latch register at the next rising edge of the clock when the detection pulse of the first rising edge is valid.

[0048] Understandably, during the latching process described above, when the first rising edge of the reference second pulse signal is detected, the latching operation is immediately triggered, latching the current value of the first counter into the first latch register, and simultaneously latching the current value of the second counter into the second latch register.

[0049] In some embodiments, the first count value is obtained by continuously accumulating the period of the reference second pulse signal from zero using a first counter, with the local high-frequency clock as the counting pulse; the second count value is obtained by continuously accumulating the period of the measured second pulse signal from zero using a second counter, with the local high-frequency clock as the counting pulse; wherein neither the first counter nor the second counter returns to zero.

[0050] The counting pulse can be a local high-frequency clock signal that drives the state of the internal register of the counter to flip (e.g., increment by 1).

[0051] The period can refer to the duration of the reference second pulse signal or the measured second pulse signal, and its standard value can be 1 second.

[0052] Optionally, using a local high-frequency clock as the counting pulse and employing a first counter to continuously accumulate the period of the reference second pulse signal starting from zero can include: using a counter with a reset value of 0 as the first counter, which increments its count value by 1 on each rising edge of the reference second pulse signal, without returning to zero during the counting process, so that the difference between the latch values ​​corresponding to two adjacent rising edges is exactly equal to the number of clock cycles between the two latches. In some embodiments, the first counter can be a 32-bit unsigned incrementing counter that automatically returns to zero and continues continuous accumulation only after counting to the power of 32 minus 1.

[0053] Optionally, using a local high-frequency clock as the counting pulse and employing a second counter to continuously accumulate the period of the measured second pulse signal starting from zero can include: using a counter with a reset value of 0 as the second counter, which increments its count value by 1 on the rising edge of each measured second pulse signal, without returning to zero during the counting process. In some embodiments, the first counter can be a 32-bit unsigned incrementing counter that automatically returns to zero and continues continuous accumulation only after counting to the power of 32 minus 1.

[0054] S203. Obtain the number of real-time clock cycles between the rising edges of the reference second pulse signal, and extract the target number of real-time clock cycles as the judgment threshold.

[0055] The real-time clock cycle count refers to the actual number of local high-frequency clock cycles that occur between two consecutive rising edges of the reference second pulse signal. The real-time clock cycle count reflects the actual length of one complete cycle of the reference second pulse signal; it is a dynamic value obtained through actual measurement, rather than a pre-set fixed parameter.

[0056] The target number of cycles can refer to a portion of the real-time clock cycle count, which can be used as a threshold value to determine whether the phase difference crosses the whole second boundary.

[0057] The decision threshold can refer to a threshold used to compare the magnitude of the first difference.

[0058] In one embodiment, a specific implementation process for obtaining the number of real-time clock cycles between the rising edges of a reference second pulse signal is described. Please refer to [reference needed]. Figure 3 , Figure 3 This is a flowchart illustrating a specific implementation process for obtaining the number of real-time clock cycles, as provided in an embodiment of this application. Figure 3 As shown, the specific implementation steps for obtaining the number of real-time clock cycles are as follows: S2031. Determine the previous first rising edge corresponding to the first rising edge currently detected by the reference second pulse signal.

[0059] The previous first rising edge can refer to the most recent rising edge of the reference second pulse signal detected before the currently detected first rising edge.

[0060] Optionally, the method for determining the previous first rising edge corresponding to the currently detected first rising edge of the reference second pulse signal may include: pre-maintaining a rising edge event queue or history register, and saving the relevant information of the current rising edge (i.e., the new first rising edge) each time a new first rising edge is detected, while retaining the relevant information of the previous rising edge as a record of the previous first rising edge. Then, the previous first rising edge corresponding to the currently detected first rising edge can be determined by the information retained in the rising edge event queue or history register.

[0061] S2032. Obtain the historical first count value corresponding to the arrival time of the previous first rising edge that has been latched.

[0062] The first historical count value refers to the count value output by the first counter latched at the time of the arrival of the previous first rising edge. This count value has been stored in the aforementioned rising edge event queue or history register.

[0063] Optionally, the method of obtaining the historical first count value corresponding to the arrival time of the previous first rising edge may include: reading and determining the historical first count value corresponding to the previous first rising edge from the aforementioned pre-maintained rising edge event queue or history register.

[0064] S2033. The difference between the current first count value and the historical first count value is determined as the number of real-time clock cycles between the rising edges of the reference second pulse signal.

[0065] The real-time clock cycle number is the number of local high-frequency clock cycles actually occupied by one complete cycle of the reference second pulse signal.

[0066] Optionally, determining the difference between the current first count value and the historical first count value as the number of real-time clock cycles between the rising edges of the reference second pulse signal can include: using a 32-bit unsigned subtractor to calculate the difference between the current first count value and the historical first count value, and determining the calculation result as the number of local high-frequency clock cycles actually occupied by one complete cycle of the reference second pulse signal, i.e., the number of real-time clock cycles. In some embodiments, considering that when calculating the difference between the current first count value and the historical first count value, since the first counter is a 32-bit free counter, there may be a counter overflow and return to zero, it is necessary to use an unsigned subtractor to perform modulo operations. Specifically, the current first count value is subtracted from the historical first count value. If the result is non-negative, it is directly used as the difference; if the result is negative (indicating that the first counter overflowed between two rising edges), 2 to the power of 32 is added to obtain the correct unsigned difference.

[0067] Optionally, the method of selecting a target number of cycles from the real-time clock cycles as the determination threshold may include selecting half of the real-time clock cycles as the determination threshold. In some embodiments, if the first difference between the current first count value and the current second count value is less than or equal to the determination threshold, the first difference between the current first count value and the current second count value can be directly determined as the jitter detection result.

[0068] Here, half a cycle can refer to the value obtained by dividing the real-time clock cycle number by 2. In some embodiments, half a cycle can correspond to the clock cycle number of half a PPS cycle. Since the phase difference of the second pulse signal has circular symmetry, half a cycle can be the dividing point that distinguishes between the short arc and the long arc of the circle. When the phase difference is less than half a cycle, the direct difference between the current first count value and the current second count value is the short arc; when the phase difference is greater than half a cycle, the short arc is the second difference obtained by subtracting the direct difference (first difference) from the complete cycle.

[0069] In some embodiments, using half of the real-time clock cycle count as the determination threshold may include setting the determination threshold to the right by shifting the real-time clock cycle count by one bit, i.e., dividing the real-time clock cycle count by 2 and rounding down. In other embodiments, the real-time clock cycle count can be updated each time the reference PPS rises, so the determination threshold is also dynamically updated, always following the current actual cycle length.

[0070] When the first difference is less than or equal to half a cycle, it means that the phase difference between the rising edge of the reference PPS and the rising edge of the measured PPS belongs to a short arc of a circle. That is, the direct difference (first difference) is the actual jitter size, and there is no need to compensate. In this case, the first difference can be directly output as the jitter detection result.

[0071] S204. If the first difference between the current first count value and the current second count value is greater than the judgment threshold, the jitter detection result is determined based on the second difference between the real-time clock cycle number and the first difference.

[0072] The first difference can refer to the difference between the currently latched first count value and the second count value, that is, the absolute value of the first count value minus the second count value. This difference can represent the original clock cycle difference between the rising edge of the reference PPS and the rising edge of the measured PPS.

[0073] The second difference can be the difference obtained by subtracting the first difference from the number of real-time clock cycles. This difference can represent the short arc length of the phase difference on a circle, i.e., the actual minute jitter. In some embodiments, since the second pulse signal is periodic, the phase difference of the second pulse signal is actually a circumferential quantity, with a value range between 0 and a complete cycle. Therefore, when the original difference between two rising edges is greater than half a complete cycle, it means that the actual phase difference should be calculated in the opposite direction, i.e., by subtracting the original difference from the complete cycle, to obtain the true minute jitter.

[0074] When the first difference is greater than half a complete cycle, it means that the direct difference between the two rising edges (the first difference) belongs to the long arc of the circle. The actual small jitter should be calculated from the opposite direction, that is, the first difference is subtracted from the complete cycle (the number of real-time clock cycles). The second difference is the length of the short arc of the circle, that is, the actual jitter size.

[0075] In one embodiment, when the comparison result shows that the first difference is greater than the decision threshold, the second difference is obtained by subtracting the first difference from the number of real-time clock cycles. The multiplexer selects the second difference as the output. The subtraction operation uses 32-bit unsigned subtraction. Since the first difference is less than the number of real-time clock cycles (theoretically, the phase difference does not exceed one complete cycle), the result is positive. The output second difference, also in clock cycles, is sent to the smoothing module.

[0076] In some embodiments, when determining whether the first difference between the current first count value and the current second count value is greater than a determination threshold, a 32-bit unsigned comparator can be used to compare the first difference with the determination threshold. For example, the first difference can be the unsigned difference between the current first count value and the second count value, with a value range of 0 to 2^32 minus 1, while the determination threshold is approximately 125000000. The comparison result between the first difference and the determination threshold can be divided into two cases: the first difference is greater than the determination threshold, or the first difference is less than or equal to the determination threshold.

[0077] In one embodiment, a specific implementation process for determining jitter detection results based on a second difference between the number of real-time clock cycles and a first difference is described. Please refer to [reference needed]. Figure 4 , Figure 4 This is a flowchart illustrating a specific implementation process for determining jitter detection results, provided as an embodiment of this application. Figure 4 As shown, the specific implementation steps for determining the jitter detection result are as follows: S2041. Detect multiple first rising edges of the reference second pulse signal, and calculate the second difference between the number of real-time clock cycles corresponding to each first rising edge and the first difference.

[0078] Here, multiple first rising edges can refer to several consecutively detected rising edges of reference PPS, with each rising edge corresponding to one jitter detection calculation. In some embodiments, for the first rising edge of each reference PPS, the corresponding first difference is calculated according to the method in the above embodiment, and a decision threshold is used to determine whether to take the first difference or the second difference as the original jitter value. That is, when the first difference is greater than the decision threshold, the original jitter value is the second difference (i.e., the number of real-time clock cycles minus the first difference); when the first difference is less than or equal to the decision threshold, the original jitter value is the first difference.

[0079] Optionally, the method for calculating the second difference between the number of real-time clock cycles corresponding to each first rising edge and the first difference may include: performing the jitter calculation in the above embodiment once for each reference PPS rising edge detected (i.e., once per second) to obtain a second difference (assuming that the first difference between each first count value and the corresponding second count value is greater than the judgment threshold), and obtaining N second differences after continuously detecting N rising edges to form a second difference sequence.

[0080] S2042. Smooth the multiple second differences to obtain the smoothing result, and determine the smoothing result as the jitter detection result.

[0081] Smoothing can refer to filtering the original jitter value sequence (second difference sequence) to eliminate transient spikes and random noise, thereby obtaining a stable jitter estimate. It can be understood that each element in the second difference sequence corresponds to the jitter measurement result within one second. However, due to transient factors such as electromagnetic interference and power supply noise, some measurements may exhibit spikes, deviating from the true jitter level, thus requiring smoothing processing.

[0082] The smoothing result can be a stable jitter value after filtering, which can more accurately reflect the long-term jitter level and quality trend of the clock source.

[0083] Optionally, the method of smoothing multiple second differences to obtain a smoothed result and determining the smoothed result as the jitter detection result may include: using a sliding window averaging method to smooth multiple second differences to obtain a smoothed result, and determining the smoothed result as the jitter detection result. In some embodiments, a window of depth N can be maintained. Each time a new original jitter value is obtained, it is added to the window, while the oldest value in the window is removed. Then, the arithmetic mean of all values ​​in the window is calculated as the smoothed result. In other embodiments, the window depth N can be set according to application requirements. For example, N is equal to 64, 128, or 256, corresponding to an average time window of 64 seconds, 128 seconds, or 256 seconds, respectively.

[0084] In one embodiment, a specific implementation process for smoothing multiple second differences to obtain a smoothed result is described. Please refer to [reference needed]. Figure 5 , Figure 5 This is a flowchart illustrating a specific implementation process for obtaining a smoothing result, as provided in an embodiment of this application. Figure 5 As shown, the specific implementation steps to obtain the smoothing result are as follows: S20421. Store multiple second differences sequentially into a shift register sequence of preset depth.

[0085] In this process, each time a new second difference is stored in the shift register sequence, the oldest stored second difference is discarded, so as to ensure that the shift register sequence always contains the number of most recently generated second differences corresponding to the preset depth.

[0086] A shift register sequence can refer to a storage structure consisting of multiple cascaded registers, where each register stores a second difference (the original jitter value).

[0087] The preset depth can refer to the number of registers in the shift register sequence, which can be denoted as N, for example, N equals 256. In some embodiments, each time a new second difference is stored in the shift register sequence, the values ​​in all registers can be shifted one bit in the output direction in sequence, and the earliest stored second difference is removed from the end of the sequence and discarded, thereby ensuring that the sequence always contains the most recently generated N (preset depth) second differences.

[0088] S20422. Calculate the arithmetic mean of the number of second differences currently stored in the shift register sequence corresponding to the preset depth, and determine the arithmetic mean as the smoothing result.

[0089] The arithmetic mean can be the sum of all N values ​​in the shift register sequence divided by N. In some embodiments, since the sum register already maintains the sum within the window in real time, the arithmetic mean calculation only requires dividing the sum by N. The division operation can be implemented by shifting (when N is a power of 2). For example, when N equals 256, shifting the sum right by 8 bits yields the average value, without the need for a complex divider.

[0090] Optionally, the method of calculating the arithmetic mean of the number of second differences currently stored in the shift register sequence corresponding to a preset depth and determining the arithmetic mean as the smoothing result may include: calculating the arithmetic mean of N second differences using a pre-maintained first-in-first-out shift register sequence of depth N, an accumulator register, and a divider, and determining the calculated arithmetic mean as the smoothing result.

[0091] In some embodiments, the method of calculating the arithmetic mean of N second differences using a pre-maintained first-in-first-out shift register sequence of depth N, an accumulator register, and a divider, and determining the calculated arithmetic mean as the smoothing result, may include: whenever a new jitter data point (second difference) arrives, the first-in-first-out shift register sequence writes the new jitter data point to the tail of the queue, while simultaneously removing and discarding the oldest historical jitter data point stored at the head of the queue, so as to keep the first-in-first-out shift register sequence always storing the N most recently generated unsmoothed original jitter data points; the accumulator register synchronously performs an accumulation update operation, that is, adding the new jitter data point and subtracting the discarded historical jitter data point to the current accumulation sum, thereby updating the accumulation sum in real time; the divider divides the updated accumulation sum by the aforementioned preset depth N, and outputs the resulting quotient as the smoothing result after sliding window smoothing.

[0092] For example, when N equals 256, the average value is equal to the sum right-shifted by 8 bits, i.e., taking the high 24 bits of the sum (assuming the sum is 32 bits). This calculation can be completed within one clock cycle after the rising edge of each reference PPS. The output average value is the smoothed jitter detection result. Simultaneously, the current raw jitter value (the latest second difference) can also be output as a real-time indicator for scenarios requiring rapid response. The two indicators are output in parallel, reflecting short-term real-time jitter and long-term average jitter respectively.

[0093] In this embodiment, the periods of the reference second pulse signal and the measured second pulse signal are first continuously counted to obtain a first count value corresponding to the reference second pulse signal and a second count value corresponding to the measured second pulse signal. Each time the first rising edge of the reference second pulse signal is detected, the current first count value corresponding to the arrival time of the first rising edge of the reference second pulse signal is latched, and the current second count value corresponding to the measured second pulse signal is latched. A portion of the real-time clock cycles between the rising edges of the reference second pulse signal is extracted as a judgment threshold. If the first difference between the current first count value and the current second count value is greater than the judgment threshold, the jitter detection result is determined based on the second difference between the real-time clock cycles and the first difference.

[0094] The jitter detection calculation process can be fully implemented using digital logic, without the need for external dedicated chips. It is easy to implement in a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), reducing detection costs. At the same time, a portion of the real-time clock cycles between the rising edges of the reference second pulse signal is introduced as a judgment threshold. If the first difference between the current first count value and the current second count value is greater than the judgment threshold, the first difference is not used as the jitter detection result. Instead, the jitter detection result is determined based on the second difference between the real-time clock cycles and the first difference. Even if the phase difference between the measured PPS signal and the reference PPS signal is close to 1 second, it can avoid calculating a huge difference that may lead to errors. This allows for flexible handling of possible cross-second transitions in the PPS signal and improves the jitter detection effect.

[0095] Corresponding to the above method embodiments, this application also provides a second pulse signal jitter detection device, such as... Figure 6 As shown, Figure 6 This is a schematic diagram of a second pulse signal jitter detection device according to an embodiment of this application. The device includes: Acquisition unit 601 is used to acquire the reference second pulse signal and the measured second pulse signal; The latch unit 602 is used to latch the current first count value corresponding to the arrival time of the first rising edge when the first rising edge of the reference second pulse signal is detected, and to latch the current second count value corresponding to the measured second pulse signal. The interception unit 603 is used to obtain the number of real-time clock cycles between the rising edges of the reference second pulse signal, and intercept the target number of real-time clock cycles as the judgment threshold. The determining unit 604 is used to determine the jitter detection result based on the second difference between the real-time clock cycle number and the first difference when the first difference between the current first count value and the current second count value is greater than the determination threshold.

[0096] Optionally, the interception unit 603 is specifically used to determine the previous first rising edge corresponding to the currently detected first rising edge of the reference second pulse signal; obtain the historical first count value corresponding to the arrival time of the latched previous first rising edge; and determine the difference between the current first count value and the historical first count value as the number of real-time clock cycles between rising edges of the reference second pulse signal; wherein, the number of real-time clock cycles is the number of local high-frequency clock cycles actually occupied by one complete cycle of the reference second pulse signal.

[0097] Optionally, the latch unit 602 is further configured to synchronize the reference second pulse signal and the measured second pulse signal to the same local high-frequency clock, so that the data transition edges of the reference second pulse signal and the measured second pulse signal are aligned with the rising edge of the local high-frequency clock; the same local high-frequency clock is generated by a local crystal oscillator and has a fixed frequency; the latch unit 602 is specifically configured to detect the first rising edge of the reference second pulse signal according to the synchronized local high-frequency clock; detect the current second rising edge of the measured second pulse signal according to the synchronized local high-frequency clock; and latch the current second count value corresponding to the arrival time of the current second rising edge.

[0098] Optionally, the first count value is obtained by continuously accumulating the period of the reference second pulse signal from zero using the local high-frequency clock as the counting pulse and the first counter; the second count value is obtained by continuously accumulating the period of the measured second pulse signal from zero using the local high-frequency clock as the counting pulse and the second counter; wherein neither the first counter nor the second counter returns to zero.

[0099] Optionally, the determining unit 604 is specifically used to detect multiple first rising edges of the reference second pulse signal, and calculate the second difference between the number of real-time clock cycles corresponding to each first rising edge and the first difference; perform smoothing processing on multiple second differences to obtain a smoothing processing result, and determine the smoothing processing result as the jitter detection result.

[0100] Optionally, the determining unit 604 is specifically used to store multiple second differences sequentially into a shift register sequence of a preset depth; wherein, each time a new second difference is stored in the shift register sequence, the earliest stored second difference is discarded, so as to keep the shift register sequence always containing the number of second differences corresponding to the preset depth that have been generated most recently; the arithmetic mean of the number of second differences currently stored in the shift register sequence that correspond to the preset depth is calculated, and the arithmetic mean is determined as the smoothing result.

[0101] Optionally, the interception unit 603 is specifically used to intercept half of the real-time clock cycle count as a judgment threshold; the determination unit 604 is also used to determine the first difference as the jitter detection result if the first difference between the current first count value and the current second count value is less than or equal to the judgment threshold.

[0102] like Figure 7 As shown, this application embodiment also provides an electronic device, including a processor 701, a memory 702, and a program or instructions stored in the memory 702 and executable on the processor 701. When the program or instructions are executed by the processor 701, they implement the various processes of the above-described second pulse signal jitter detection method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0103] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described second pulse signal jitter detection method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0104] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0105] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0106] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0107] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0108] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the claims.

Claims

1. A method for detecting jitter in a second pulse signal, characterized in that, include: Acquire the reference second pulse signal and the measured second pulse signal; Upon detecting the first rising edge of the reference second pulse signal, the current first count value corresponding to the arrival time of the first rising edge is latched, and the current second count value corresponding to the measured second pulse signal is latched. Obtain the number of real-time clock cycles between the rising edges of the reference second pulse signal, and extract the target number of cycles from the real-time clock cycle count as the judgment threshold; If the first difference between the current first count value and the current second count value is greater than the determination threshold, the jitter detection result is determined based on the second difference between the real-time clock cycle number and the first difference.

2. The method according to claim 1, characterized in that, The step of obtaining the number of real-time clock cycles between the rising edges of the reference second pulse signal includes: Determine the previous first rising edge corresponding to the first rising edge currently detected by the reference second pulse signal; Obtain the historical first count value corresponding to the arrival time of the previous first rising edge that has been latched; The difference between the current first count value and the historical first count value is determined as the number of real-time clock cycles between the rising edges of the reference second pulse signal; Wherein, the number of real-time clock cycles is the number of local high-frequency clock cycles actually occupied by one complete cycle of the reference second pulse signal.

3. The method according to claim 1, characterized in that, Before latching the current first count value corresponding to the arrival time of the first rising edge, the method further includes: The reference second pulse signal and the measured second pulse signal are synchronized to the same local high-frequency clock so that the data transition edges of the reference second pulse signal and the measured second pulse signal are aligned with the rising edge of the local high-frequency clock; the same local high-frequency clock is generated by a local crystal oscillator and has a fixed frequency; The detection process of the first rising edge of the reference second pulse signal includes: The first rising edge of the reference second pulse signal is detected according to the synchronized local high-frequency clock; The latching of the current second count value corresponding to the measured second pulse signal includes: The second rising edge of the measured second pulse signal is detected based on the synchronized local high-frequency clock. Latch the current second count value corresponding to the arrival time of the current second rising edge.

4. The method according to claim 3, characterized in that, The first count value is obtained by continuously accumulating the period of the reference second pulse signal from zero using the local high-frequency clock as the counting pulse and a first counter; the second count value is obtained by continuously accumulating the period of the measured second pulse signal from zero using the local high-frequency clock as the counting pulse and a second counter; wherein neither the first counter nor the second counter returns to zero.

5. The method according to any one of claims 1 to 4, characterized in that, The jitter detection result is determined based on the second difference between the number of real-time clock cycles and the first difference: Multiple first rising edges of the reference second pulse signal are detected, and a second difference between the number of real-time clock cycles corresponding to each first rising edge and the first difference is calculated. The multiple second differences are smoothed to obtain a smoothing result, and the smoothing result is determined as the jitter detection result.

6. The method according to claim 5, characterized in that, The smoothing process for the plurality of second differences to obtain a smoothing result includes: Multiple second differences are sequentially stored into a shift register sequence of a preset depth; wherein, each time a new second difference is stored in the shift register sequence, the earliest stored second difference is discarded, so as to ensure that the shift register sequence always contains the number of most recently generated second differences corresponding to the preset depth. Calculate the arithmetic mean of the number of second differences currently stored in the shift register sequence corresponding to the preset depth, and determine the arithmetic mean as the smoothing result.

7. The method according to any one of claims 1 to 4, characterized in that, The step of extracting the target number of real-time clock cycles as the determination threshold includes: Half of the real-time clock cycles are taken as the judgment threshold; The method further includes: If the first difference between the current first count value and the current second count value is less than or equal to the determination threshold, the first difference is determined as the jitter detection result.

8. A device for detecting jitter in a second pulse signal, characterized in that, include: The acquisition unit is used to acquire the reference second pulse signal and the measured second pulse signal; A latching unit is used to latch the current first count value corresponding to the arrival time of the first rising edge when the first rising edge of the reference second pulse signal is detected, and to latch the current second count value corresponding to the measured second pulse signal. The interception unit is used to obtain the number of real-time clock cycles between the rising edges of the reference second pulse signal, and intercept the target number of cycles from the number of real-time clock cycles as a judgment threshold. The determining unit is configured to determine a jitter detection result based on a second difference between the number of real-time clock cycles and the first difference when the first difference between the current first count value and the current second count value is greater than the determination threshold.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the second pulse signal jitter detection method as described in any one of claims 1-7.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the second pulse signal jitter detection method as described in any one of claims 1-7.

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