Semiconductor device

Abstract

Embodiments of the present invention provide a semiconductor device capable of reducing the memory capacity of a gate driver. The semiconductor device of the embodiment includes: a first table including a plurality of driving modes; a controller including the first table; and driver circuitry. The driver circuitry includes: a second table including a first mode and a second mode; a control circuit; a generation circuit for generating drive pulses; and a drive circuitry for driving a switching element. During the timing of turning the switching element on or off, if the change in a first information of the switching element is less than a first threshold, the control circuit generates a correction value, and the generation circuit generates drive pulses based on the first mode and the correction value. If the change in the first information is greater than or equal to the first threshold, the control circuit replaces the first mode with the second mode, and the generation circuit generates drive pulses based on the replaced first mode.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-049750 (filed on March 25, 2025). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] Semiconductor devices are known that include a gate driver that drives the switching element (hereinafter also referred to as "power switch") used in power devices. In such semiconductor devices, when the gate driver drives the power switch quickly, the switching losses decrease and the overall efficiency increases. However, a large surge (ringing) is generated. The surge becomes a cause of noise. On the other hand, when the gate driver drives the power switch slowly, the surge is reduced. However, the switching losses increase and the overall efficiency decreases. Thus, there is a trade-off between reducing surge and reducing switching losses.

[0005] In recent years, active gate control technology has emerged as a technique for controlling power switches via gate drivers. This is not simply turning the power switch on or off, but rather changing the strength of the drive during on-time. For example, a specific waveform is generated to improve the aforementioned trade-off between the power switch's gate drive mode, and the power switch is driven based on this waveform. This technique can improve the previously trade-off relationship between surge and switching losses, achieving a balance between reducing surge and reducing switching losses. However, to cope with variations in load current flowing through the load in a system containing power devices, the power supply voltage supplied to the power switch, and the temperature of the power devices, more drive modes are needed, increasing memory capacity. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device capable of reducing the memory capacity of the gate driver.

[0007] The semiconductor device of the embodiment includes: a first meter including multiple driving modes; a controller including the first meter; and a driver circuit. The driver circuit includes: a second meter, a control circuit, a generation circuit, and a driver circuit. The second meter includes at least a first mode and a second mode from the multiple driving modes of the first meter. The generation circuit generates a driving pulse based on the first mode. The driver circuit drives a switching element by a voltage or current based on the first mode at a timing based on the driving pulse. At a timing when the switching element is turned on or off, if the change in a first information of the switching element is less than a first threshold, the control circuit generates a correction value. The generation circuit generates a driving pulse based on the first mode and the correction value. If the change in the first information of the switching element is greater than or equal to the first threshold, the control circuit replaces the first mode with the second mode. The generation circuit generates a driving pulse based on the replaced first mode. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example of the hardware configuration of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a timing diagram illustrating an example of the operation of a switching element within a system containing power devices in a comparative example semiconductor device when normal gate control is used to turn on the switching element.

[0010] Figure 3 This is a timing diagram illustrating an example of the operation of a switching element in a system containing a power device in the semiconductor device of the first embodiment when the switching element is turned on by active gate control.

[0011] Figure 4 This is a timing diagram illustrating an example of the operation in a comparative example semiconductor device when the switching element in a system containing power devices is turned off by normal gate control.

[0012] Figure 5 This is a timing diagram illustrating an example of the operation of the semiconductor device in the first embodiment when the switching element in the system containing the power device is turned off by active gate control.

[0013] Figure 6 This is a diagram illustrating an example of the timing of the supply of a braking voltage corresponding to the drain current when the switching element is turned on by the active gate control of the semiconductor device of the first embodiment.

[0014] Figure 7 This is a diagram illustrating an example of the timing of the supply of a braking voltage corresponding to the drain current when the switching element is turned off by active gate control of the semiconductor device of the first embodiment.

[0015] Figure 8This is a diagram illustrating an example of the timing of the supply of a braking voltage corresponding to the drain voltage when the switching element is turned on by the active gate control of the semiconductor device of the first embodiment.

[0016] Figure 9 This is a diagram illustrating an example of the timing of the supply of a braking voltage corresponding to the drain voltage when the switching element is turned off by active gate control of the semiconductor device of the first embodiment.

[0017] Figure 10 This diagram illustrates an example of the timing of the supply of a braking voltage corresponding to temperature when the switching element is turned on by the active gate control of the semiconductor device of the first embodiment.

[0018] Figure 11 This is a diagram illustrating an example of the timing of the supply of a braking voltage corresponding to temperature when the switching element is turned off by active gate control of the semiconductor device of the first embodiment.

[0019] Figure 12 This is a conceptual diagram illustrating an example of a lookup table used in a semiconductor device according to the first embodiment.

[0020] Figure 13 This is a conceptual diagram illustrating an example of a lookup table stored in the memory within the gate driver of the semiconductor device included in the first embodiment.

[0021] Figure 14 This is a block diagram illustrating an example of the functional configuration of the control circuit within the gate driver of the semiconductor device included in the first embodiment.

[0022] Figure 15 This is a diagram illustrating an example of the configuration of a lookup table within the gate driver of the semiconductor device included in the first embodiment.

[0023] Figure 16 This is a circuit diagram illustrating an example of the configuration of the generation circuit within the gate driver of the semiconductor device included in the first embodiment.

[0024] Figure 17 This is a diagram illustrating an example of the waveform of a drive pulse generated by a generation circuit within a gate driver included in the semiconductor device of the first embodiment.

[0025] Figure 18 This is a flowchart illustrating an example of the active gate control operation of the semiconductor device according to the first embodiment.

[0026] Figure 19 This is a flowchart illustrating an example of the active gate control operation of the semiconductor device according to the first embodiment.

[0027] Figure 20 This is a flowchart illustrating an example of the active gate control operation of the semiconductor device according to the first embodiment.

[0028] Figure 21 This is a flowchart illustrating an example of the active gate control operation of the semiconductor device according to the first embodiment.

[0029] Figure 22 This is a diagram illustrating an example of the configuration of a lookup table within the gate driver of the semiconductor device included in the second embodiment.

[0030] Figure 23 This is a diagram illustrating an example of the configuration of a lookup table within the gate driver of the semiconductor device included in the third embodiment.

[0031] Figure 24 This is a circuit diagram illustrating an example of the configuration of the generation circuit within the gate driver of the semiconductor device included in the third embodiment.

[0032] Figure 25 This is a diagram illustrating an example of the waveform of a drive pulse generated by a generation circuit within a gate driver included in the semiconductor device of the third embodiment.

[0033] Figure 26 This is a diagram illustrating an example of the waveform of a drive pulse generated by a generation circuit within a gate driver included in the semiconductor device of the third embodiment.

[0034] Figure 27 This is a diagram illustrating an example of the waveform of a drive pulse generated by a generation circuit within a gate driver included in the semiconductor device of the third embodiment. Detailed Implementation

[0035] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, sometimes the same reference numerals are used to denote constituent elements having substantially the same function and structure, and repeated descriptions are omitted. When elements having the same structure are specifically distinguished from each other, sometimes different characters or numbers are appended to the end of the same reference numeral. Furthermore, descriptions of a particular embodiment, unless explicitly or obviously excluded, are also applicable to descriptions of other embodiments.

[0036] 1. First Implementation Method

[0037] The semiconductor device of the first embodiment will be described. Hereinafter, a semiconductor device including a gate driver for driving a power switch will be described as an example. The semiconductor device of this embodiment is used, for example, in driving power switches used in vehicle traction inverters and the like.

[0038] 1.1 Composition

[0039] 1.1.1 Hardware Configuration of Semiconductor Devices

[0040] use Figure 1 The hardware configuration of the semiconductor device 1 according to the first embodiment will be described. Figure 1 This is a block diagram illustrating an example of the hardware configuration of the semiconductor device 1 according to this embodiment.

[0041] Semiconductor device 1 is a device that controls the switching element (power switch) 41 within system 4, which contains power devices. Hereinafter, system 4, which contains power devices, will also be referred to as "system 4". Semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. Semiconductor device 1 is connected to system 4 via a bus.

[0042] Semiconductor device 1, based on an active gate controlled driving mode, supplies a driving voltage Vdv to switching element 41, thereby controlling the on and off states of switching element 41. Figure 1 The diagram illustrates a case where the switching element 41 is controlled by voltage (voltage-driven). The switching element 41 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Examples of MOSFETs used as switching elements 41 include silicon carbide (SiC) MOSFETs. Figure 1 In this example, switching element 41 is an n-channel MOSFET. Switching element 41 constitutes an inverter circuit within system 4, which contains power devices. One end of switching element 41 or the other end is connected to a load (not shown) within system 4, which contains power devices. The load is, for example, a motor.

[0043] Additionally, semiconductor device 1 obtains from system 4 the values ​​of the drain current Id of switching element 41, the drain-source voltage Vds (hereinafter referred to as "drain voltage Vds") of switching element 41, and the temperature Temp of system 4 (switching element 41). The drain current Id is, for example, equivalent to the current flowing through the load in system 4 (load current). The drain voltage Vds is, for example, equivalent to the power supply voltage supplied to system 4 (switching element 41). The temperature Temp is, for example, detected by a temperature sensor (not shown) within system 4. Semiconductor device 1 maintains or changes the drive mode for controlling the on and off of switching element 41 based on the drain current Id, drain voltage Vds, and temperature Temp. Hereinafter, the values ​​of drain current Id, drain voltage Vds, and temperature Temp will also be collectively referred to as "System Information INF".

[0044] like Figure 1As shown, the semiconductor device 1 includes, for example, an MCU (Micro Controller Unit) 2 and a gate driver 3. Hereinafter, the MCU 2 will also be referred to as "controller 2". The gate driver 3 will also be referred to as "driver circuit 3".

[0045] MCU2 is a device that controls gate driver 3. MCU2 is connected to gate driver 3 via a bus. MCU2 includes, for example, a processor 21, a memory 22, and a communication interface (I / F) circuit 23.

[0046] Processor 21 is, for example, a CPU (Central Processing Unit). Processor 21 performs various control processes. Processor 21 performs, for example, drive mode transmission processing and drive indication processing. Drive mode transmission processing is the process of obtaining one or more drive modes from a lookup table (LUT) described later based on system information INF received from system 4 via gate driver 3, and sending the obtained drive modes to gate driver 3. Drive indication processing is the process of sending a clock signal and a PWM (Pulse Width Modulation) signal indicating the on or off state of switching element 41 to gate driver 3. Hereinafter, the clock signal will be referred to as "signal CLK". The PWM signal will be referred to as "signal PWM".

[0047] The memory 22 includes, for example, ROM (Read Only Memory) and RAM (Random Access Memory). The ROM stores, for example, programs for enabling the processor 21 to execute various control processes, including drive mode transfer processing and drive instruction processing. Additionally, the ROM stores lookup tables (LUTs). The RAM is used as the working area of ​​the processor 21. The RAM temporarily stores, for example, the programs executed by the processor 21 and data generated during the execution of these processes.

[0048] The communication interface circuit 23 is responsible for communication between the MCU2 and the gate driver 3. The communication interface circuit 23 sends signals such as CLK and PWM, as well as data such as one or more drive modes, to the gate driver 3. The communication interface circuit 23 also receives system information such as INF from the gate driver 3.

[0049] Gate driver 3 is a device that drives switching element 41. Gate driver 3 is connected to system 4 via a bus. Gate driver 3 includes, for example, control circuitry 31, memory 32, communication interface (I / F) circuitry 33, generation circuitry 34, and drive circuitry 35.

[0050] Control circuit 31 is a circuit that performs various control processes. Control circuit 31 may be, for example, a CPU, MPU (Microprocessing Unit), GPU (Graphics Processing Unit), or FPGA (Field Programmable Gate Array). Control circuit 31 performs, for example, system information acquisition processing, drive mode loading processing, system information determination processing, drive mode correction processing, and drive mode switching processing. System information acquisition processing involves obtaining system information INF from system 4. Drive mode loading processing involves receiving one or more drive modes from MCU2 and loading the received drive modes into memory 32. System information determination processing involves determining whether there are changes in drain current Id, drain voltage Vds, and temperature Temp obtained from system 4. Drive mode correction processing involves correcting the drive mode. Drive mode switching processing involves switching the drive mode. Details regarding system information acquisition processing, drive mode loading processing, system information determination processing, drive mode correction processing, and drive mode switching processing will be described later.

[0051] The memory 32 includes, for example, ROM and RAM. The ROM stores, for example, programs for causing the control circuit 31 to perform various control processes, including system information acquisition processing, drive mode loading processing, system information determination processing, drive mode correction processing, and drive mode switching processing. The RAM is used as the operating area of ​​the control circuit 31. The RAM temporarily stores, for example, the programs executed by the control circuit 31 and data during the execution of the aforementioned processes. The drive mode loaded through the drive mode loading process is stored in the RAM.

[0052] The communication interface circuit 33 is responsible for communication between the gate driver 3 and the MCU2, and between the gate driver 3 and the system 4. The communication interface circuit 33 sends system information INF and other data to the MCU2. The communication interface circuit 33 receives signals such as CLK and PWM, as well as one or more drive modes, from the MCU2. Additionally, the communication interface circuit 33 supplies the drive voltage Vdv to the system 4. The communication interface circuit 33 receives system information INF from the system 4.

[0053] The generation circuit 34 generates drive pulses (waveforms) based on the drive patterns stored in the RAM within the memory 32. The drive pulses control the timing of supplying the drive voltage Vdv to the gate of the switching element 41.

[0054] The drive circuit 35 is a circuit that drives the switching element 41 by voltage based on the drive mode stored in RAM within the memory 32, based on the timing of the drive pulse.

[0055] 1.1.2 Lookup Table LUT

[0056] The lookup table (LUT) will be explained. The lookup table (LUT) is a table that stores the drive modes for active gate control. Active gate control will be explained first below.

[0057] (Active gate control)

[0058] Active gate control is illustrated by comparing it with normal gate control.

[0059] Figure 2 This is a timing diagram illustrating an example of the operation of the switching element 41 when it is turned on by normal gate control in a comparative example semiconductor device. Figure 2 The diagram shows the changes in drain current Id and drain voltage Vds under normal gate control with a drive voltage Vdv. Drain current Id is represented by a solid line, and drain voltage Vds is represented by a dashed line.

[0060] Before time t11, switching element 41 is in the off state. The drive voltage Vdv is voltage Vdv1. Voltage Vdv1 is the voltage that turns off switching element 41 (e.g., 0V). The drain current Id is, for example, 0A. The drain voltage Vds is, for example, a voltage higher than 0V and is the power supply voltage provided to the power switch.

[0061] At time t11, switching element 41 is turned on. Specifically, a voltage Vdv2 is supplied (applied) to the gate of switching element 41. Voltage Vdv2 is the voltage that turns on switching element 41 (e.g., a voltage higher than voltage Vdv1). As a result, the gate-source voltage Vgs (hereinafter referred to as "gate voltage Vgs") of switching element 41 rises. Furthermore, the gate typically has a parasitic resistance (not shown), and immediately after the application of voltage Vdv2, the gate voltage Vgs and voltage Vdv2 are not the same voltage, but gradually approach the same level.

[0062] At time t12, if the gate voltage Vgs becomes higher than the threshold voltage Vth of the switching element 41, the drain current Id begins to flow through the switching element 41. As the drain current Id increases, the drain voltage Vds begins to decrease.

[0063] At time t13, a large surge in drain current Id occurs. Subsequently, the surge in drain current Id decreases as the drain voltage Vds decreases, eventually converging. The drain voltage Vds also eventually converges.

[0064] Figure 3 This is a timing diagram illustrating an example of the operation of the switching element 41 in the semiconductor device 1 when it is turned on by active gate control. Figure 3This represents the changes in drain current Id and drain voltage Vds when active gate control is applied to the drive voltage Vdv. The drain current Id is represented by a solid line, and the drain voltage Vds is represented by a dashed line.

[0065] Before time t21, switching element 41 is in the off state. The drive voltage Vdv is voltage Vdv1. Voltage Vdv1 is the voltage that turns off switching element 41 (e.g., 0V). The drain current Id is, for example, 0A. The drain voltage Vds is, for example, a voltage higher than 0V.

[0066] At time t21, switching element 41 is turned on. Specifically, a voltage Vdv2 is supplied to the gate of switching element 41. Voltage Vdv2 is the voltage that turns on switching element 41 (e.g., a voltage higher than voltage Vdv1). As a result, the gate voltage Vgs of switching element 41 increases.

[0067] At time t22, if the gate voltage Vgs becomes higher than the threshold voltage Vth of the switching element 41, the drain current Id begins to flow through the switching element 41. As the drain current Id increases, the drain voltage Vds begins to decrease.

[0068] At time t23, in order to suppress the generation of large surges that will occur after time t23, a voltage Vdv3 is supplied to the gate of switching element 41. Voltage Vdv3 is the voltage that turns on switching element 41 (e.g., a voltage higher than voltage Vdv1 and lower than voltage Vdv2). As a result, the gate voltage Vgs of switching element 41 decreases. The period (length) from time t22 to time t23 is longer than... Figure 2 The period from time t12 to time t13 shown is short. That is, a voltage Vdv3 is supplied to the gate of switching element 41 before the surge of drain current Id is generated. As a result, after time t23, a surge of drain current Id is generated, but the surge is smaller. Thereafter, the surge of drain current Id decreases as the drain voltage Vds decreases. The lower the voltage Vdv3, the smaller the surge.

[0069] At time t24, to suppress the increase in conduction losses, a voltage Vdv2 is supplied to the gate of switching element 41. As a result, the gate voltage Vgs of switching element 41 increases, and the conduction losses decrease. Furthermore, while the gate voltage Vgs increases due to the supply of voltage Vdv2, the surge generated after time t23 is small. Therefore, the surge in drain current Id decreases as the drain voltage Vds decreases, eventually converging. The drain voltage Vds also eventually converges. The longer the period from time t23 to time t24, the smaller the surge.

[0070] Figure 4 This is a timing diagram illustrating an example of the operation of the switching element 41 in a comparative example semiconductor device when it is turned off by normal gate control. Figure 4 The diagram shows the changes in drain current Id and drain voltage Vds under normal gate control with a drive voltage Vdv. Drain current Id is represented by a dashed line, and drain voltage Vds is represented by a solid line.

[0071] Before time t31, switching element 41 is in the ON state. The drive voltage Vdv is voltage Vdv4. Voltage Vdv4 is the voltage that turns on switching element 41 (e.g., a voltage higher than 0V). The drain current Id is, for example, a current higher than 0A. The drain voltage Vds is, for example, 0V.

[0072] At time t31, switching element 41 is turned off. Specifically, a voltage Vdv5 is supplied to the gate of switching element 41. Voltage Vdv5 is the voltage that turns off switching element 41 (e.g., a voltage lower than voltage Vdv4). As a result, the gate-source voltage Vgs of switching element 41 decreases.

[0073] At time t32, the drain voltage Vds begins to rise. Afterwards, the drain current Id begins to decrease.

[0074] At time t33, a large surge in drain voltage Vds occurs. Subsequently, the surge in drain voltage Vds decreases as drain current Id decreases, eventually converging. Drain current Id also eventually converges.

[0075] Figure 5 This is a timing diagram illustrating an example of the operation of the switching element 41 in the semiconductor device 1 when it is turned off by active gate control. Figure 5 This represents the changes in drain current Id and drain voltage Vds when active gate control is applied to the drive voltage Vdv. The drain current Id is represented by a dashed line, and the drain voltage Vds is represented by a solid line.

[0076] Before time t41, switching element 41 is in the ON state. The drive voltage Vdv is voltage Vdv4. Voltage Vdv4 is the voltage that turns on switching element 41 (e.g., a voltage higher than 0V). The drain current Id is, for example, a current higher than 0A. The drain voltage Vds is, for example, 0V.

[0077] At time t41, switching element 41 is turned on. Specifically, a voltage Vdv5 is supplied to the gate of switching element 41. Voltage Vdv5 is a voltage that turns off switching element 41 (e.g., a voltage lower than voltage Vdv4). As a result, the gate voltage Vgs of switching element 41 decreases.

[0078] At time t42, the drain voltage Vds begins to rise. Afterwards, the drain current Id begins to decrease.

[0079] At time t43, to suppress the generation of large surges that will occur after time t43, a voltage Vdv6 is supplied to the gate of switching element 41. Voltage Vdv6 is the voltage that turns off switching element 41 (e.g., a voltage higher than voltage Vdv5 and lower than voltage Vdv4). As a result, the gate voltage Vgs of switching element 41 rises. The period (length) from time t42 to time t43 is longer than... Figure 4 The period from time t32 to time t33 is short. That is, a voltage Vdv6 is supplied to the gate of switching element 41 before the surge of drain voltage Vds is generated. Therefore, after time t43, a surge of drain voltage Vds is generated, but the surge is smaller. Thereafter, the surge of drain voltage Vds decreases as the drain current Id decreases. The higher the voltage Vdv6, the smaller the surge.

[0080] At time t44, to suppress the increase in switching losses, a voltage Vdv5 is supplied to the gate of switching element 41. This reduces the gate voltage Vgs of switching element 41, thus decreasing the switching losses. Furthermore, while the gate voltage Vgs decreases due to the supply of voltage Vdv5, the surge generated after time t43 is small. Therefore, the surge in drain voltage Vds decreases as drain current Id decreases, eventually converging. Drain current Id also eventually converges. The longer the period from time t43 to time t44, the smaller the surge.

[0081] like Figure 3 and Figure 5 As shown, Figure 3 The waveform of the driving voltage Vdv during the period from time t21 to time t24 is used to make Figure 5 The waveform of the driving voltage Vdv during the period from time t41 to time 44 is the inverted waveform.

[0082] Hereinafter, the voltage supplied to the gate of the switching element 41 for turning on or off will be referred to as "first drive voltage V1". The period for supplying the first drive voltage V1 will be referred to as "first drive period T1". The voltage supplied to the gate of the switching element 41 to suppress the generation of large surges will be referred to as "braking voltage Vb". The period for supplying the braking voltage Vb will be referred to as "braking period Tb". The voltage supplied to the gate of the switching element 41 after the braking period Tb to suppress the increase of conduction loss or switching loss will be referred to as "second drive voltage V2".

[0083] When the switching element 41 is turned on, such as Figure 3 As shown, the first driving voltage V1 is voltage Vdv2. The first driving period T1 is from time t21 to time t23. The braking voltage Vb is voltage Vdv3. The braking period Tb is from time t23 to time t24. The second driving voltage V2 is voltage Vdv2.

[0084] When the switching element 41 is turned off, such as Figure 5 As shown, the first driving voltage V1 is voltage Vdv5. The first driving period T1 is from time t41 to time t43. The braking voltage Vb is voltage Vdv6. The braking period Tb is from time t43 to time t44. The second driving voltage V2 is voltage Vdv5.

[0085] The second driving voltage V2 can also be different from the first driving voltage V1. That is, the second driving voltage V2 can be a voltage higher than the first driving voltage V1, or a voltage lower than the first driving voltage V1.

[0086] Thus, in active gate control, the first drive voltage V1, the first drive period T1, the braking voltage Vb, the braking period Tb, and the second drive voltage V2 are set.

[0087] In addition, the first driving voltage V1, the first driving period T1, the braking voltage Vb, the braking period Tb and the second driving voltage V2 are determined based on the drain current Id, the drain voltage Vds and the temperature Temp of the switching element 41.

[0088] Figure 6 This is a diagram illustrating an example of the timing of the supply of the braking voltage Vb corresponding to the drain current Id when the switching element 41 is turned on by the active gate control of the semiconductor device 1. Figure 6 An example of the waveform of the drain current Id is shown in a semiconductor device of the comparative example when the switching element 41 is turned on by normal gate control. Figure 6 The three waveforms shown correspond to the cases where the drain current Id is low, high, and in between.

[0089] like Figure 6 As shown, the higher the drain current Id, the later the timing of the drain current Id surge. Furthermore, the higher the drain current Id, the larger the drain current Id surge. Therefore, when the switching element 41 is turned on by the active gate control of semiconductor device 1, as... Figure 6 As indicated by the middle arrow, it is preferable to supply the braking voltage Vb before a surge occurs, based on the value of the drain current Id. For example, the higher the drain current Id, the later the timing of supplying the braking voltage Vb.

[0090] Figure 7 This is a diagram illustrating an example of the timing of the supply of the braking voltage Vb corresponding to the drain current Id when the switching element 41 is turned off by the active gate control of the semiconductor device 1. Figure 7An example of the drain current Id and drain voltage Vds waveforms is shown in the semiconductor device of the comparative example when the switching element 41 is turned off by normal gate control. The drain current Id is represented by a dashed line, and the drain voltage Vds is represented by a solid line. Figure 7 The waveforms shown by the three dashed lines correspond to the low drain current Id, the high drain current, and a value in between. Figure 7 The waveform with the smallest surge in drain voltage Vds among the three solid lines shown corresponds to the case of low drain current Id, while the waveform with the largest surge in drain voltage Vds corresponds to the case of high drain current Id. The remaining waveforms correspond to values ​​between the low and high drain current Id values.

[0091] like Figure 7 As shown, the higher the drain current Id, the earlier the timing of the drain voltage Vds surge. Furthermore, the higher the drain current Id, the larger the drain voltage Vds surge. Therefore, when the switching element 41 is turned off by the active gate control of semiconductor device 1, as... Figure 7 As indicated by the middle arrow, it is preferable to supply the braking voltage Vb before the surge in drain voltage Vds is generated, based on the value of the drain current Id. For example, the higher the drain current Id, the earlier the timing of supplying the braking voltage Vb.

[0092] Figure 8 This is a diagram illustrating an example of the timing of the supply of the braking voltage Vb corresponding to the drain voltage Vds when the switching element 41 is turned on by the active gate control of the semiconductor device 1. Figure 8 An example of the drain current Id and drain voltage Vds waveforms is shown in the semiconductor device of the comparative example when the switching element 41 is turned on by normal gate control. The drain current Id is represented by a solid line, and the drain voltage Vds is represented by a dashed line. Figure 8 The waveforms shown by the three dashed lines correspond to the low drain voltage Vds, the high drain voltage, and a value in between. Figure 8 The waveform with the smallest drain current Id surge among the three solid lines shown corresponds to the case where the drain voltage Vds is low, while the waveform with the largest drain current Id surge corresponds to the case where the drain voltage Vds is high. The remaining waveforms correspond to values ​​between the low and high drain voltage Vds values.

[0093] like Figure 8 As shown, the higher the drain voltage Vds, the earlier the timing of the drain current Id surge. Furthermore, the higher the drain voltage Vds, the larger the drain current Id surge. Therefore, in the active gate control of semiconductor device 1, as... Figure 8As indicated by the middle arrow, it is preferable to apply a braking voltage Vb before the surge that generates the drain current Id, based on the value of the drain voltage Vds. For example, the higher the drain voltage Vds, the earlier the timing of supplying the braking voltage Vb.

[0094] Figure 9 This is a diagram illustrating an example of the timing of the supply of the braking voltage Vb corresponding to the drain voltage Vds when the switching element 41 is turned off by the active gate control of the semiconductor device 1. Figure 9 An example of the waveform of the drain voltage Vds is shown in a semiconductor device of the comparative example when the switching element 41 is turned off by normal gate control. Figure 9 The three waveforms shown correspond to the low drain voltage Vds, the high drain voltage, and a value in between.

[0095] like Figure 9 As shown, the higher the drain voltage Vds, the later the timing of the drain voltage Vds surge. Furthermore, the higher the drain voltage Vds, the larger the drain voltage Vds surge. Therefore, when the switching element 41 is turned off by the active gate control of semiconductor device 1, as... Figure 9 As indicated by the middle arrow, it is preferable to supply the braking voltage Vb before a surge occurs, based on the value of the drain voltage Vds. For example, the higher the drain voltage Vds, the later the timing of supplying the braking voltage Vb.

[0096] Figure 10 This is a diagram illustrating an example of the timing of the supply of the braking voltage Vb, which corresponds to the temperature Temp, when the active gate of the semiconductor device 1 controls the switching element 41 to turn on. Figure 10 An example of the waveform of the drain current Id is shown in a semiconductor device of the comparative example when the switching element 41 is turned on by normal gate control. Figure 10 The waveform with a smaller surge in drain current Id corresponds to a lower temperature (Temp), while the waveform with a larger surge in drain current Id corresponds to a higher temperature (Temp).

[0097] like Figure 10 As shown, the higher the temperature (Temp), the earlier the timing of the drain current Id surge. Furthermore, the higher the temperature (Temp), the larger the drain current Id surge. Therefore, in the active gate control of semiconductor device 1, as... Figure 10 As indicated by the arrow, it is preferable to supply the braking voltage Vb before the surge of drain current Id occurs, based on the temperature Temp. For example, the higher the temperature Temp, the earlier the timing of supplying the braking voltage Vb.

[0098] Figure 11This is a diagram illustrating an example of the timing of the supply of braking voltage Vb corresponding to temperature Temp when the switching element 41 is turned off by active gate control of semiconductor device 1. Figure 11 An example of the drain voltage Vds waveform is shown in a comparative example semiconductor device when the switching element 41 is turned off by normal gate control. Figure 11 In the two waveforms shown, the waveform with a smaller surge in drain voltage Vds corresponds to the case of high temperature Temp, while the waveform with a larger surge in drain voltage Vds corresponds to the case of low temperature Temp.

[0099] like Figure 11 As shown, the higher the temperature (Temp), the later the timing of the drain voltage Vds surge. Furthermore, the higher the temperature (Temp), the smaller the drain voltage Vds surge. Therefore, when the switching element 41 is turned off by active gate control of semiconductor device 1, preferably, as... Figure 11 As indicated by the arrow, the braking voltage Vb is supplied before the surge in drain voltage Vds occurs, based on the temperature Temp. For example, the higher the temperature Temp, the later the timing of supplying the braking voltage Vb.

[0100] Based on the above, in the active gate control of semiconductor device 1, a drive mode Pa is prepared that corresponds to changes in the environment of the switching element 41, i.e., changes in system information INF (changes in drain current Id, drain voltage Vds, and temperature Temp). Drive mode Pa is based on a combination of drain current Id, drain voltage Vds, and temperature Temp. Furthermore, drive mode Pa includes a parameter PM1 corresponding to the first drive voltage V1, a parameter PM2 corresponding to the first drive period T1, a parameter PM3 corresponding to the braking voltage Vb, a parameter PM4 corresponding to the braking period Tb, and a parameter PM5 corresponding to the second drive voltage V2. Parameters PM1 to PM5 are determined based on drain current Id, drain voltage Vds, and temperature Temp. In other words, parameters PM1 to PM5 are appropriate parameters corresponding to drain current Id, drain voltage Vds, and temperature Temp. In this embodiment, in order to switch the drive mode Pa suitable for active gate control according to the aforementioned environmental changes, a lookup table (LUT) is used to store information about drive mode Pa.

[0101] (Lookup table)

[0102] Figure 12This is a conceptual diagram illustrating an example of a lookup table (LUT) used in the semiconductor device 1 of this embodiment. In this embodiment, as the drive mode Pa when the switching element 41 is on, 64 drive modes Pa1 are prepared, consisting of combinations of 4 drain currents Id, 4 drain voltages Vds, and 4 temperatures Temp. Furthermore, as the drive mode Pa when the switching element 41 is off, 64 drive modes Pa2 are prepared, consisting of combinations of 4 drain currents Id, 4 drain voltages Vds, and 4 temperatures Temp. That is, the lookup table (LUT) includes 64 drive modes Pa1 and 64 drive modes Pa2.

[0103] Hereinafter, the 64 driving modes Pa1 are represented as "driving mode Pa1(i, j, k)" and the 64 driving modes Pa2 are represented as "driving mode Pa2(i, j, k)" (i, j, and k are integers greater than 0 and less than 3). Without distinguishing between driving modes Pa1(i, j, k) and Pa2(i, j, k), they are represented as "driving mode Pa(i, j, k)".

[0104] The value of i corresponds to the drain current Id. A larger value of i indicates a higher drain current Id in drive mode Pa. The drain current Id corresponding to drive mode Pa(i+1, j, k) is higher than that corresponding to drive mode Pa(i, j, k). The drain current Id corresponding to drive mode Pa(i-1, j, k) is lower than that corresponding to drive mode Pa(i, j, k).

[0105] j corresponds to the drain voltage Vds. The larger the value of j, the higher the drain voltage Vds of the driving mode Pa. The drain voltage Vds corresponding to driving mode Pa(i,j+1,k) is higher than that corresponding to driving mode Pa(i,j,k). The drain voltage Vds corresponding to driving mode Pa(i,j-1,k) is lower than that corresponding to driving mode Pa(i,j,k).

[0106] k corresponds to temperature Temp. The larger the value of k, the higher the temperature Temp of the driving mode Pa. The temperature Temp corresponding to driving mode Pa(i,j,k+1) is higher than the temperature Temp corresponding to driving mode Pa(i,j,k). The temperature Temp corresponding to driving mode Pa(i,j,k-1) is lower than the temperature Temp corresponding to driving mode Pa(i,j,k).

[0107] Furthermore, the number of drain current Id, drain voltage Vds, and temperature Temp used for drive modes Pa1(i,j,k) and Pa2(i,j,k) can be less than four, and can be three or more. Drive modes Pa1(i,j,k) and Pa2(i,j,k) respectively include the five parameters PM1 to PM5 mentioned above.

[0108] The drain current Id changes according to the motor's rotation. The motor's rotation changes frequently. Therefore, the drain current Id changes rapidly. On the other hand, the drain voltage Vds and temperature Temp change slowly. The drain current Id, drain voltage Vds, and temperature Temp exhibit these changing characteristics. Furthermore, the timing of the braking voltage Vb can be predicted based on the changes in drain current Id, drain voltage Vds, and temperature Temp.

[0109] Based on the above, and taking into account the characteristics of the changes in drain current Id, drain voltage Vds, and temperature Temp, 64 drive modes Pa1 and 64 drive modes Pa2 are prepared.

[0110] For example, a lookup table (LUT) is loaded from the ROM in memory 22 into RAM in MCU2 immediately after the power to semiconductor device 1 is turned on.

[0111] When the switching element 41 is turned on or off, and the drive mode Pa is loaded from the RAM in memory 22 to the RAM in memory 32 each time, the communication between MCU2 and gate driver 3 takes time and sometimes cannot handle active gate control.

[0112] Furthermore, in order to cope with various anticipated changes in system information INF before the switching element 41 is turned on or off, if more drive modes Pa are preloaded from the RAM in memory 22 to the RAM in memory 32, the capacity of memory 32 increases, leading to increased costs. In this case, the proprietary area of ​​gate driver 3 becomes larger, and gate driver 3 may not be able to be accommodated within semiconductor device 1.

[0113] Hereinafter, the driving mode Pa corresponding to the current system information INF will be described as "current mode Pac(ic, jc, kc)". Current mode Pac is the driving mode Pa anticipated based on the current system information INF. When the switching element 41 is turned on or off, the drain current Id, drain voltage Vds, and temperature Temp do not change drastically. Therefore, for example, when the switching element 41 is turned on or off and the drain current Id changes, the driving mode Pa changes from the current mode Pac to a driving mode Pa that increases or decreases the value of i by 1. That is, the driving mode Pa changes to driving mode Pa(ic+1, jc, kc) or driving mode Pa(ic-1, jc, kc). When the switching element 41 is turned on or off and the drain voltage Vds changes, the driving mode Pa changes from the current mode Pac to a driving mode Pa that increases or decreases the value of j by 1. That is, the driving mode Pa changes to driving mode Pa(ic, jc+1, kc) or driving mode Pa(ic, jc-1, kc). When the switching element 41 is turned on or off, or when the temperature Temp changes, the drive mode Pa changes from the current mode Pac to a drive mode Pa that increases or decreases the value of k by 1. That is, the drive mode Pa changes to drive mode Pa(ic, jc, kc+1) or drive mode Pa(ic, jc, kc-1).

[0114] Furthermore, when the system information INF changes little, the appropriate drive mode Pa becomes similar to the current mode Pac. Therefore, even without switching the current mode Pac, appropriate active gate control corresponding to the change in system information INF can be achieved by changing the supply timing of the braking voltage Vb based on the current mode Pac. On the other hand, when the system information INF changes significantly, the appropriate drive mode Pa becomes dissimilar to the current mode Pac. Therefore, without switching the current mode Pac, appropriate active gate control corresponding to the change in system information INF may not be possible.

[0115] Based on the above, in this embodiment, the current mode Pac(ic, jc, kc), drive mode Pa(ic±1, jc, kc), drive mode Pa(ic, jc±1, kc), and drive mode Pa(ic, jc, kc±1) from all drive modes Pa contained in the lookup table LUT are loaded from memory 22 into memory 32. The current mode Pac is the drive mode that the MCU2 anticipates will change at the timing when the switching element 41 is turned on or off, based on the system information INF. Hereinafter, drive modes Pa(ic±1, jc, kc), drive mode Pa(ic, jc±1, kc), and drive mode Pa(ic, jc, kc±1) will also be described as "the 6 drive modes Pa adjacent to the current mode Pac". The drive mode Pa(ic±1, jc, kc) is the drive mode corresponding to the increase or decrease of the drain current Id from the current mode Pac. The driving mode Pa(ic, jc±1, kc) is the driving mode corresponding to the increase or decrease of the drain voltage Vds from the current mode Pac. The driving mode Pa(ic, jc, kc±1) is the driving mode corresponding to the increase or decrease of the temperature Temp from the current mode Pac. The lookup table LUT containing the seven driving modes Pa loaded into memory 32 is denoted as "lookup table LUTg". That is, lookup table LUTg is stored in memory 32.

[0116] Figure 13 This is a conceptual diagram representing an example of a lookup table (LUTg) stored in memory 32. For example... Figure 13 As shown, the lookup table LUTg contains the current mode Pac(ic, jc, kc), the driving mode Pa(ic±1, jc, kc), the driving mode Pa(ic, jc±1, kc), and the driving mode Pa(ic, jc, kc±1). These driving modes Pa are loaded into the memory 32, for example, immediately after the power to the semiconductor device 1 is turned on, and after the switching element 41 is turned on or off.

[0117] 1.1.3 Functional Composition of Control Circuit

[0118] use Figure 14 The functional configuration of the control circuit 31 within the gate driver 3 will be explained. Figure 14 This is a block diagram illustrating an example of the functional configuration of the control circuit 31. Figure 14 Also shown are the lookup table LUTg, generation circuit 34, and drive circuit 35 within MCU2, system 4, and gate driver 3.

[0119] like Figure 14As shown, the control circuit 31 includes an acquisition unit 301, a loading unit 302, a determination unit 303, a correction unit 304, and a switching unit 305 as functional blocks. That is, the control circuit 31 functions as the acquisition unit 301, the loading unit 302, the determination unit 303, the correction unit 304, and the switching unit 305.

[0120] (Acquisition Section 301)

[0121] The acquisition unit 301 performs system information acquisition processing. For example, the acquisition unit 301 acquires system information INF (the value of drain current Id, the value of drain voltage Vds, and the value of temperature Temp) from system 4.

[0122] (Loading section 302)

[0123] The loading unit 302 performs drive mode loading processing. For example, the loading unit 302 receives system information INF from the acquisition unit 301. The loading unit 302 sends the received system information INF to the processor 21 within the MCU2. When the processor 21 receives the system information INF, the processor 21 retrieves the current mode Pac corresponding to the system information INF (current system information INF) and the six drive modes Pa adjacent to the current mode Pac from the lookup table LUT. For example, after the power supply to the semiconductor device 1 is immediately turned on and after the switching element 41 is turned off (after reaching a stable state), 64 drive modes Pa1 are retrieved from the lookup table LUT; after the switching element 41 is turned on (after reaching a stable state), 64 drive modes Pa2 are retrieved from the lookup table LUT. The processor 21 sends these retrieved drive modes Pa to the loading unit 302. When a drive mode Pa is received, the loading unit 302 updates the drive mode Pa in the lookup table LUTg.

[0124] (Judgment Section 303)

[0125] The determination unit 303 performs system information determination processing. For example, the determination unit 303 receives system information INF from the acquisition unit 301. The determination unit 303 determines whether the system information INF has changed. If the system information INF has not changed, the value indicating no correction to the supply timing (=0) is sent to the generation circuit 34 as the correction value Vam for the braking voltage Vb supply timing. If the change in the system information INF is small, the category of the changed information (drain current Id, drain voltage Vds, or temperature Temp) CL and the change amount Δ are sent to the correction unit 304. If the change in the system information INF is large, the category of the changed information CL and the change amount Δ are sent to the switching unit 305.

[0126] (Revision 304)

[0127] The correction unit 304 performs drive mode correction processing. For example, if the correction unit 304 receives the category CL and the change amount Δ from the determination unit 303, it generates a correction value Vam for the timing of the braking voltage Vb supply. The correction unit 304 sends the generated correction value Vam to the generation circuit 34.

[0128] For example, when switching element 41 is turned on and drain current Id increases (the change ΔId > 0), such as Figure 6 As shown, this generates a timing delay for the surge in drain current Id. Therefore, when the drain current Id increases, the correction unit 304 generates a positive correction value Vam to delay the timing of the braking voltage Vb supply. When the switching element 41 is turned on and the drain current Id decreases (change ΔId < 0), as... Figure 6 As shown, the timing of the surge that generates the drain current Id is advanced. Therefore, when the drain current Id decreases, the correction unit 304 generates a negative correction value Vam to advance the timing of the braking voltage Vb supply. On the other hand, when the switching element 41 is turned off and the drain current Id increases, as... Figure 7 As shown, the timing of the surge that generates the drain voltage Vds is advanced. Therefore, when the drain current Id increases, the correction unit 304 generates a negative correction value Vam to advance the timing of the braking voltage Vb supply. When the switching element 41 is turned off and the drain current Id decreases, as... Figure 7 As shown, this represents the timing delay of the surge that generates the drain voltage Vds. Therefore, when the drain current Id decreases, the correction unit 304 generates a positive correction value Vam to delay the timing of the braking voltage Vb supply. The correction value Vam is generated based on the change ΔId.

[0129] When switching element 41 is turned on and drain voltage Vds rises (the change ΔVds > 0), such as Figure 8 As shown, the timing of the surge that generates the drain current Id is advanced. Therefore, when the drain voltage Vds rises, the correction unit 304 generates a negative correction value Vam to advance the timing of the braking voltage Vb supply. When the switching element 41 is turned on and the drain voltage Vds decreases (change ΔVds < 0), as Figure 8 As shown, the timing delay of the surge that generates the drain current Id is calculated. Therefore, when the drain voltage Vds decreases, the correction unit 304 generates a positive correction value Vam to delay the timing of the braking voltage Vb supply. On the other hand, when the switching element 41 is turned off and the drain voltage Vds rises, as... Figure 9 As shown, this generates a timing delay for the surge in drain voltage Vds. Therefore, when the drain voltage Vds rises, the correction unit 304 generates a positive correction value Vam to delay the timing of the braking voltage Vb supply. When the switching element 41 is turned off and the drain voltage Vds falls, as... Figure 9 As shown, the timing of the surge that generates the drain voltage Vds becomes earlier. Therefore, when the drain voltage Vds decreases, in order to advance the timing of the braking voltage Vb supply, the correction unit 304 generates a negative correction value Vam. The correction value Vam is generated based on the change ΔVds.

[0130] When the switching element 41 is turned on and the temperature Temp rises (the change ΔTemp > 0), such as Figure 10 As shown, the timing of the surge that generates the drain current Id is advanced. Therefore, when the temperature Temp rises, in order to advance the timing of the supply of the braking voltage Vb, the correction unit 304 generates a negative correction value Vam. When the switching element 41 is turned on and the temperature Temp decreases (the change ΔTemp < 0), as Figure 10 As shown, the timing delay of the surge that generates the drain current Id is explained. Therefore, when the temperature Temp decreases, the correction unit 304 generates a positive correction value Vam to delay the timing of the braking voltage Vb supply. On the other hand, when the switching element 41 is turned off and the temperature Temp rises, as... Figure 11 As shown, this results in a timing delay for the surge that generates the drain voltage Vds. Therefore, when the temperature Temp rises, the correction unit 304 generates a positive correction value Vam to delay the timing of the braking voltage Vb supply. When the switching element 41 is turned off and the temperature Temp decreases, as... Figure 11 As shown, the timing of the surge that generates the drain voltage Vds becomes earlier. Therefore, when the temperature Temp decreases, in order to advance the timing of the braking voltage Vb supply, the correction unit 304 generates a negative correction value Vam. The correction value Vam is generated based on the change in ΔTemp.

[0131] (Switching unit 305)

[0132] The switching unit 305 performs a drive mode switching process. For example, when the switching unit 305 receives the category CL and change amount Δ from the determination unit 303, it determines one of the six drive modes Pa adjacent to the current mode Pac that will be switched to the current mode Pac (hereinafter referred to as "switching mode Pas"). The switching unit 305 sends the switching mode Pas determined as the lookup table LUTg and switches the current mode Pac in the lookup table LUTg to the switching mode Pas. That is, the current mode Pac is replaced by the switching mode Pas. Hereinafter, the replaced current mode Pac is also referred to as "replaced current mode Pacr". As a result, the memory 32 stores the current mode Pac and the five drive modes Pa adjacent to the current mode Pac.

[0133] For example, when the switching element 41 is turned on or off and the drain current Id increases (change ΔId > 0), the switching unit 305 determines the driving mode Pa(ic+1, jc, kc) as the switching mode Pas. The current mode Pac switches from driving mode Pa(ic, jc, kc) to driving mode Pa(ic+1, jc, kc). When the switching element 41 is turned on or off and the drain current Id decreases (change ΔId < 0), the switching unit 305 determines the driving mode Pa(ic-1, jc, kc) as the switching mode Pas. The current mode Pac switches from driving mode Pa(ic, jc, kc) to driving mode Pa(ic-1, jc, kc).

[0134] When the switching element 41 is turned on or off and the drain voltage Vds increases (change ΔVds > 0), the switching unit 305 determines the driving mode Pa(ic, jc+1, kc) as the switching mode Pas. The current mode Pac switches from driving mode Pa(ic, jc, kc) to driving mode Pa(ic, jc+1, kc). When the switching element 41 is turned on or off and the drain voltage Vds decreases (change ΔVds < 0), the switching unit 305 determines the driving mode Pa(ic, jc-1, kc) as the switching mode Pas. The current mode Pac switches from driving mode Pa(ic, jc, kc) to driving mode Pa(ic, jc-1, kc).

[0135] When the switching element 41 is turned on or off and the temperature Temp rises (change ΔTemp > 0), the switching unit 305 determines the driving mode Pa(ic, jc, kc+1) as the switching mode Pas. The current mode Pac switches from driving mode Pa(ic, jc, kc) to driving mode Pa(ic, jc, kc+1). When the switching element 41 is turned on or off and the temperature Temp decreases (change ΔTemp < 0), the switching unit 305 determines the driving mode Pa(ic, jc, kc-1) as the switching mode Pas. The current mode Pac switches from driving mode Pa(ic, jc, kc) to driving mode Pa(ic, jc, kc-1).

[0136] In addition, the switching unit 305 sends a value indicating no correction of the supply timing (=0) as the correction value Vam of the braking voltage Vb supply timing to the generation circuit 34.

[0137] The generation circuit 34 retrieves the parameter PM2 corresponding to the first driving period T1 of the current mode Pac and the parameter PM4 corresponding to the braking period Tb from the lookup table LUTg. Additionally, the generation circuit 34 receives a correction value Vam from the determination unit 303, the correction unit 304, or the switching unit 305. The generation circuit 34 generates a driving pulse Pu based on the parameters PM2 and PM4 of the current mode Pac and the correction value Vam. For example, if the correction value Vam (=0) is received from the determination unit 303, the generation circuit 34 generates the driving pulse Pu based on the parameters PM2 and PM4 of the current mode Pac. If the correction value Vam (≠0) is received from the correction unit 304, the generation circuit 34 generates the driving pulse Pu based on the parameters PM2 and PM4 of the current mode Pac and the correction value Vam. The correction value Vam is added to the parameter PM2 corresponding to the first driving period T1. Upon receiving a correction value Vam (=0) from the switching unit 305, the generation circuit 34 generates a drive pulse Pu based on the parameters PM2 and PM4 of the replaced current mode Pacr. The generation circuit 34 sends the generated drive pulse Pu to the current mode Pac in the lookup table LUTg.

[0138] Based on the timing of the drive pulse Pu, the current mode Pac in the lookup table LUTg is sent to the drive circuit 35, along with parameters PM1 corresponding to the first drive voltage V1, PM3 corresponding to the braking voltage Vb, and PM5 corresponding to the second drive voltage V2. Parameters PM1, PM3, and PM5 are stored in a register (not shown) within the drive circuit 35 and, after being converted into voltages, are supplied to the switching element 41 as the drive voltage Vdv.

[0139] 1.1.4 Structure of the LUTg lookup table

[0140] use Figure 15 The structure of the lookup table LUTg is explained. Figure 15 This is a diagram illustrating an example of the structure of a lookup table LUTg. Figure 15 Only the current mode Pac is shown among the seven drive modes Pa in the lookup table LUTg. The other drive modes Pa in the lookup table LUTg also have the same structure as the current mode Pac. Additionally, Figure 15 The control circuit 31, the generation circuit 34, and the drive circuit 35 are also shown.

[0141] like Figure 15 As shown, the current mode Pac includes registers RG1 to RG5.

[0142] Registers RG1 through RG3 are numbered sequentially from right to left on the page. Register RG1 stores parameter PM1 corresponding to the first driving voltage V1. Register RG2 stores parameter PM3 corresponding to the braking voltage Vb. Register RG3 stores parameter PM5 corresponding to the second driving voltage V2. Parameters PM1, PM3, and PM5 represent the values ​​of the driving force. The driving force, for example, takes values ​​from 0 to 63. When the driving force takes values ​​from 0 to 63, each of registers RG1 through RG3 includes, for example, six flip-flops. As an example of setting the driving force for registers RG1 through RG3, for instance, register RG1 is set to "60", register RG2 is set to "4", and register RG3 is set to "60". Registers RG1 through RG3 constitute the shift register SR.

[0143] Register RG4 stores parameter PM2 corresponding to the first driving period T1. Register RG5 stores parameter PM4 corresponding to the braking period Tb. Parameters PM2 and PM4 represent values ​​indicating the voltage supply period. The voltage supply period, for example, takes a value from 0 to 31. When the voltage supply period takes a value from 0 to 31, registers RG4 and RG5 each contain, for example, 5 flip-flops. As an example of setting the voltage supply period for registers RG4 and RG5 respectively, register RG4 is set to "6" and register RG5 is set to "4".

[0144] The generation circuit 34 receives signals CLK and PWM from MCU2. The generation circuit 34 obtains parameters PM2 and PM4 from the current mode Pac. The generation circuit 34 receives a correction value Vam from the control circuit 31. Based on the signals CLK and PWM, parameters PM2 and PM4, and the correction value Vam, the generation circuit 34 generates a drive pulse Pu. The generation circuit 34 sends the generated drive pulse Pu to the shift register SR of the current mode Pac.

[0145] The shift register SR shifts the values ​​stored in registers RG1 to RG3 respectively during the rising pulse of drive pulse Pu, and outputs parameter PM from register RG1 to drive circuit 35. First, parameter PM1 is output from register RG1 to drive circuit 35. Next, parameter PM3 is output from register RG1 to drive circuit 35. Then, parameter PM5 is output from register RG1 to drive circuit 35.

[0146] 1.1.5 Structure of the Generating Circuit

[0147] use Figure 16 The configuration of the generation circuit 34 will be explained. Figure 16 This is a circuit diagram illustrating an example of the configuration of the generating circuit 34.

[0148] like Figure 16As shown, the generation circuit 34 includes a multiplexer (MUX) 51, an adder 52, counters 53 and 54, and a waveform shaping circuit 55.

[0149] The MUX51 is a circuit that selects one of counters 53 and 54 based on the signal Sg1 output from counter 53, and outputs the input signal CLK to the selected counter.

[0150] Adder 52 is a circuit that adds the correction value Vam to the parameter PM2 and outputs the result as the sum Vad to counter 53. Since the correction value Vam can be any one of negative, 0, or positive, the sum Vad can be any one of the following: a value smaller than the parameter PM2, a value equal to the parameter PM2, or a value larger than the parameter PM2.

[0151] Counter 53 receives signal CLK from MUX 51 and determines whether the count value Cnt of signal CLK reaches the sum value Vad received from adder 52. If the count value Cnt has not reached the sum value Vad, counter 53 outputs a first value (e.g., "0") as signal Sg1. If the count value Cnt reaches the sum value Vad, counter 53 outputs a second value (e.g., "1") as signal Sg1.

[0152] Counter 54 is a circuit that receives signal CLK from MUX51 and determines whether the count value Cnt of signal CLK has reached the value of parameter PM4. Counter 54 does not output signal Sg2 if the count value Cnt has not reached the value of parameter PM4. Counter 54 outputs signal Sg2 if the count value Cnt has reached the value of parameter PM4.

[0153] The waveform shaping circuit 55 generates a drive pulse Pu based on signals PWM, Sg1, or Sg2, shapes the waveform of the generated drive pulse Pu, and outputs it. The waveform shaping circuit 55 generates and outputs the drive pulse Pu at the timing of the rise or fall of the signal PWM. The waveform shaping circuit 55 generates and outputs the drive pulse Pu upon receiving a signal Sg1 representing a second value. The waveform shaping circuit 55 generates and outputs the drive pulse Pu upon receiving a signal Sg2.

[0154] Figure 17 This is a diagram showing an example of the waveform of the drive pulse Pu generated by the generation circuit 34. Figure 17 This represents the waveform when the switching element 41 is turned on.

[0155] At time t51, signals PWM and CLK rise. Consequently, waveform shaping circuit 55 generates and outputs drive pulse Pu. Furthermore, when switching element 41 is off, signal PWM falls at time t51. Waveform shaping circuit 55 generates and outputs drive pulse Pu in the same manner as when switching element 41 is on.

[0156] During the period from time t51 to time t52, the count value Cnt of signal CLK has not reached the sum value Vad, so counter 53 outputs signal Sg1 representing the first value. Therefore, MUX51 selects counter 53.

[0157] At time t52, when the count value Cnt of signal CLK reaches the sum value Vad, counter 53 outputs signal Sg1 representing the second value. Consequently, waveform shaping circuit 55 generates and outputs drive pulse Pu. The period from time t51 to time t52 corresponds to parameter PM2. That is, at time t52, the first drive period T1 ends. Furthermore, when switching element 41 is off, at time t52, when both switching element 41 and waveform shaping circuit 55 are on, drive pulse Pu is generated and output in the same manner.

[0158] During the period from time t52 to time t53, the count value Cnt of signal CLK reaches the sum value Vad, therefore counter 53 outputs signal Sg1 representing the second value. Therefore, MUX 51 selects counter 54. Conversely, during the period from time t52 to time t53, the count value Cnt of signal CLK does not reach the value of parameter PM4, therefore counter 54 does not output signal Sg2.

[0159] At time t53, when the count value Cnt of signal CLK reaches the value of parameter PM4, counter 54 outputs signal Sg2. Consequently, waveform shaping circuit 55 generates and outputs drive pulse Pu. The period from time t52 to time t53 corresponds to parameter PM4. That is, at time t53, the braking period Tb ends. Furthermore, when switching element 41 is off, at time t53, when both switching element 41 and waveform shaping circuit 55 are on, drive pulse Pu is generated and output in the same manner.

[0160] 1.2 Active gate control operation

[0161] The active gate control operation of the semiconductor device 1 according to the first embodiment will be described. Figures 18-21 This is a flowchart illustrating an example of active gate control operation. The following explanation will focus on the case where switch element 41 is turned on. The same applies to the case where switch element 41 is turned off. In the following explanation, "on" is replaced with "off" when switch element 41 is turned off.

[0162] For example, when the switching element 41 is turned on, when the signal PWM rises, the acquisition unit 301 acquires system information INF from the system 4 (S101) and sends the acquired system information INF to the determination unit 303.

[0163] Next, the determination unit 303 receives system information INF from the acquisition unit 301 and determines whether the system information INF (any one of drain current Id, drain voltage Vds, and temperature Temp) has changed (S102).

[0164] If the system information INF is determined to be unchanged (S102_No), the determination unit 303 generates a correction value Vam (=0) for the timing of the braking voltage Vb supply as described above (S103), and sends the generated correction value Vam to the generation circuit 34.

[0165] Next, the generation circuit 34 receives the correction value Vam from the determination unit 303, and generates a drive pulse Pu based on the parameters PM2 and PM4 of the current mode Pac and the correction value Vam (S111). The generation circuit 34 sends the generated drive pulse Pu to the current mode Pac. During the rising timing of the drive pulse Pu, the parameters PM1, PM3, or PM5 of the current mode Pac are output to the drive circuit 35.

[0166] Next, the drive circuit 35 receives parameters PM1, PM3, or PM5 of the current mode Pac at the timing of the rise of the drive pulse Pu, and supplies the drive voltage Vdv corresponding to the parameters PM1, PM3, or PM5 to the switching element 41 (S112). Specifically, after converting the parameters PM1, PM3, or PM5 into voltages, the drive circuit 35 supplies the converted voltages as the drive voltage Vdv to the switching element 41. The waveform of the drive voltage Vdv supplied to the switching element 41 is, for example, as shown below. Figure 3 As shown. Furthermore, when the switching element 41 is turned off, the waveform of the drive voltage Vdv supplied to the switching element 41 is, for example, as shown below. Figure 5 As shown.

[0167] If the system information INF is determined to have changed (S102_Yes), the determination unit 303 determines whether the drain current Id has changed (S104). If the drain current Id is determined to have changed (S104_Yes), the determination unit 303 determines whether the change in drain current Id ΔId is less than the threshold TH1 (S105). If the change in ΔId is determined to be less than the threshold TH1 (S105_Yes), the correction unit 304 generates a correction value Vam (≠0) for the braking voltage Vb supply timing as described above (S121), and sends the generated correction value Vam to the generation circuit 34. Next, steps S111 and S112 are executed. If the change in ΔId is determined to be greater than or equal to the threshold TH1 (S105_No), the switching unit 305 switches the current mode Pac as described above (S131). Next, as described above, the switching unit 305 generates a correction value Vam (=0) for the timing of the braking voltage Vb supply (S132), and sends the generated correction value Vam to the generation circuit 34. Then, steps S111 and S112 are executed.

[0168] If it is determined that the drain current Id has not changed (S104_No), the determination unit 303 determines whether the drain voltage Vds has changed (S106). If it is determined that the drain voltage Vds has changed (S106_Yes), the determination unit 303 determines whether the change in drain voltage Vds ΔVds is less than the threshold TH2 (S107). If it is determined that the change ΔVds is less than the threshold TH2 (S107_Yes), as described above, the correction unit 304 generates a correction value Vam (≠0) for the braking voltage Vb supply timing (S121) and sends the generated correction value Vam to the generation circuit 34. Next, steps S111 and S112 are executed. If it is determined that the change ΔVds is greater than or equal to the threshold TH2 (S107_No), the switching unit 305 switches the current mode Pac as described above (S131). Next, as described above, the switching unit 305 generates a correction value Vam (=0) for the timing of the braking voltage Vb supply (S132), and sends the generated correction value Vam to the generation circuit 34. Then, steps S111 and S112 are executed.

[0169] If the drain voltage Vds is determined to be unchanged (S106_No), the determination unit 303 determines whether the change in temperature Temp, ΔTemp, is less than the threshold TH3 (S108). If the change in temperature, ΔTemp, is less than the threshold TH3 (S108_Yes), as described above, the correction unit 304 generates a correction value Vam (≠0) for the supply timing of the braking voltage Vb (S121) and sends the generated correction value Vam to the generation circuit 34. Then, steps S111 and S112 are executed. If the change in temperature, ΔTemp, is greater than or equal to the threshold TH3 (S108_No), the switching unit 305 switches the current mode Pac as described above (S131). Then, as described above, the switching unit 305 generates a correction value Vam (=0) for the supply timing of the braking voltage Vb (S132) and sends the generated correction value Vam to the generation circuit 34. Then, steps S111 and S112 are executed.

[0170] Furthermore, the threshold values ​​TH1 to TH3 depend on the characteristics of the switching element 41. Additionally, the threshold values ​​TH1 to TH3 also depend on the specifications of system 4, such as noise tolerance, withstand voltage, and efficiency. Therefore, these factors are considered when determining the threshold values ​​TH1 to TH3.

[0171] After the switching element 41 is turned on and reaches a stable state, the loading unit 302, in order to handle the situation where the switching element 41 is turned off, retrieves the current mode Pac corresponding to the system information INF and the 6 adjacent driving modes Pa from the 64 driving modes Pa2 in the lookup table LUT. Furthermore, when the switching element 41 is turned off, after the switching element 41 is turned on and reaches a stable state, the loading unit 302, in order to handle the situation where the switching element 41 is turned on, retrieves the current mode Pac corresponding to the system information INF and the 6 adjacent driving modes Pa from the 64 driving modes Pa1 in the lookup table LUT.

[0172] 1.3 Effects of this implementation method

[0173] The semiconductor device 1 in this embodiment includes a lookup table (LUT), an MCU 2, and a gate driver 3.

[0174] The lookup table (LUT) contains multiple drive modes Pa corresponding to changes in the system information INF of the switching element 41. Drive mode Pa is based on a combination of drain current Id, drain voltage Vds, and temperature Temp. Additionally, drive mode Pa includes a parameter PM1 corresponding to the first drive voltage V1, a parameter PM2 corresponding to the first drive period T1, a parameter PM3 corresponding to the braking voltage Vb, a parameter PM4 corresponding to the braking period Tb, and a parameter PM5 corresponding to the second drive voltage V2.

[0175] MCU2 stores a lookup table (LUT).

[0176] Gate driver 3 stores the current mode Pac among multiple drive modes Pa containing lookup tables (LUTs), and the lookup tables LUTg of the six drive modes Pa adjacent to the current mode Pac. The lookup tables LUTg are loaded from MCU2 into memory 32 within gate driver 3.

[0177] Additionally, the gate driver 3 includes a control circuit 31, a generation circuit 34, and a drive circuit 35. The generation circuit 34 generates a drive pulse Pu based on the current mode Pac. The drive circuit 35 drives the switching element 41 by a voltage based on the current mode Pac, at a timing based on the drive pulse Pu.

[0178] As described above, when the system information INF changes little, the appropriate driving mode Pa becomes a mode similar to the current mode Pac. Conversely, when the system information INF changes significantly, the appropriate driving mode Pa becomes a mode dissimilar to the current mode Pac.

[0179] Therefore, in this embodiment, when the system information INF of the switching element 41 changes by a amount Δ less than a threshold during the timing of the switching element 41 being turned on or off, the control circuit 31 generates a braking voltage Vb to supply a timing correction value Vam, and the generation circuit 34 generates a drive pulse Pu based on the current mode Pac and the correction value Vam. On the other hand, when the change in the system information INF of the switching element is greater than or equal to the threshold, the control circuit 31 replaces the current mode Pac with a drive mode Pa adjacent to the current mode Pac, and the generation circuit 34 generates a drive pulse Pu based on the replaced current mode Pacr.

[0180] That is, when the system information INF changes little, the current mode Pac is not switched, and the switching element 41 is driven by adjusting the timing of the braking voltage Vb supply to the current mode Pac. On the other hand, when the system information INF changes significantly, the current mode Pac is switched, and the switching element 41 is driven by the switched current mode Pac. As a result, the number of drive modes Pa stored in the lookup table LUTg of the memory 32 can be reduced. Therefore, according to this embodiment, the capacity of the memory 32 of the gate driver 3 can be reduced.

[0181] Furthermore, the parameters PM1 to PM5 included in the drive mode Pa of the lookup table LUT are appropriate parameters corresponding to the drain current Id, drain voltage Vds, and temperature Temp. Therefore, by using the lookup table LUTg loaded from the lookup table LUT for active gate control, it is possible to reduce surges and reduce conduction or switching losses.

[0182] 2. Second Implementation Method

[0183] The semiconductor device according to the second embodiment will be described. In the semiconductor device 1 of the second embodiment, the configuration of the lookup table LUTg differs from that of the first embodiment. Hereinafter, the differences from the first embodiment will be explained.

[0184] 2.1 Structure of the lookup table LUTg

[0185] use Figure 22 The configuration of the lookup table LUTg of the semiconductor device 1 in the second embodiment will be described. Figure 22 This is a diagram illustrating an example of the configuration of the lookup table LUTg of the semiconductor device 1 in this embodiment. Figure 22 Only the current mode Pac is shown among the seven drive modes Pa in the lookup table LUTg. The other drive modes Pa in the lookup table LUTg also have the same structure as the current mode Pac. Additionally, Figure 22 The control circuit 31, the generation circuit 34, and the drive circuit 35 are also shown.

[0186] like Figure 22 As shown, the current mode Pac includes registers RG1 to RG5 and MUX.

[0187] Registers RG1 through RG3 are numbered sequentially from right to left on the page. Each register, for example, contains six flip-flops. Register RG1 stores parameter PM1 corresponding to the first driving voltage V1. Register RG2 stores parameter PM3 corresponding to the braking voltage Vb. Register RG3 stores parameter PM5 corresponding to the second driving voltage V2.

[0188] Registers RG4 and RG5 each contain, for example, five flip-flops. Register RG4 stores parameter PM2 corresponding to the first driving period T1. Register RG5 stores parameter PM4 corresponding to the braking period Tb.

[0189] The MUX is a circuit that selects one of registers RG1 to RG3 based on the drive pulse Pu output from the generation circuit 34, and outputs the parameter PM stored in the selected register.

[0190] The generation circuit 34 receives signals CLK and PWM from MCU2. The generation circuit 34 obtains parameters PM2 and PM4 from the current mode Pac. The generation circuit 34 receives a correction value Vam from the control circuit 31. Based on the signals CLK and PWM, parameters PM2 and PM4, and the correction value Vam, the generation circuit 34 generates a drive pulse Pu. The generation circuit 34 sends the generated drive pulse Pu to the MUX of the current mode Pac.

[0191] When the drive pulse Pu rises, the MUX selects any one of registers RG1 to RG3 and outputs parameter PM from the selected register to the drive circuit 35. First, register RG1 is selected, and parameter PM1 is output from register RG1 to the drive circuit 35. Next, register RG2 is selected, and parameter PM3 is output from register RG2 to the drive circuit 35. Then, register RG3 is selected, and parameter PM5 is output from register RG3 to the drive circuit 35.

[0192] 2.2 Effects of this implementation method

[0193] According to this embodiment, it achieves the same effect as the first embodiment.

[0194] 3. Third Implementation Method

[0195] The semiconductor device according to the third embodiment will be described. In the semiconductor device 1 of the third embodiment, the configuration of the lookup table LUTg and the configuration of the generation circuit 34 are different from those of the first embodiment. Hereinafter, the differences from the first embodiment will be described.

[0196] 3.1 Structure of the lookup table LUTg

[0197] use Figure 23 The configuration of the lookup table LUTg of the semiconductor device 1 in the third embodiment will be described. Figure 23 This is a diagram illustrating an example of the configuration of the lookup table LUTg of the semiconductor device 1 in this embodiment. Figure 23 Only the current mode Pac is shown among the seven drive modes Pa in the lookup table LUTg. The other drive modes Pa in the lookup table LUTg also have the same structure as the current mode Pac. Additionally, Figure 23 The control circuit 31, the generation circuit 34, and the drive circuit 35 are also shown.

[0198] like Figure 23 As shown, the current mode Pac includes registers RG1 to RG32.

[0199] Registers RG1 through RG32, from right to left on the page, are RG1, RG2, ..., RG31, RG32. Registers RG1 through RG32 hold the parameter PM up to the next on / off state based on the PWM signal. Each of registers RG1 through RG32 contains, for example, six flip-flops. Registers RG1 through RG6 store the parameter PM1 corresponding to the first drive voltage V1. Registers RG7 through RG10 store the parameter PM3 corresponding to the braking voltage Vb. Registers RG11 through RG32 store the parameter PM5 corresponding to the second drive voltage V2. Registers RG1 through RG32 constitute the shift register SR.

[0200] The generation circuit 34 receives signals CLK and PWM from MCU2. The generation circuit 34 also receives a correction value Vam from the control circuit 31. Based on the signals CLK, PWM, and the correction value Vam, the generation circuit 34 generates a drive pulse Pu. The generation circuit 34 then sends the generated drive pulse Pu to the shift register SR of the current mode Pac.

[0201] The shift register SR shifts the values ​​stored in registers RG1 to RG32 at the rising time of the drive pulse Pu, and outputs parameter PM from register RG1 to drive circuit 35. First, parameter PM1 is output from register RG1 to drive circuit 35 6 times. Next, parameter PM3 is output from register RG1 to drive circuit 35 4 times. Then, parameter PM5 is output from register RG1 to drive circuit 35 22 times.

[0202] 3.2 Structure of the Generating Circuit

[0203] use Figure 24 The configuration of the generation circuit 34 of the semiconductor device 1 in the third embodiment will be described. Figure 24 This is a circuit diagram illustrating an example of the configuration of the generation circuit 34 of the semiconductor device 1 in this embodiment.

[0204] like Figure 24 As shown, the generation circuit 34 includes a signal generation circuit 61, AND circuits 62, 67 and 68, NAND circuits 63 and 64, an n-multiplier circuit 65 (n is an integer greater than 2), an inverter circuit 66 and an OR circuit 69.

[0205] Signal generation circuit 61 generates signals based on the PWM signal and signals based on the correction value Vam. Signal generation circuit 61 outputs a "H" (high) level signal Sg3 at the timing of the rise or fall of the PWM signal. Signal Sg3 is input to AND circuit 62. Additionally, signal generation circuit 61 outputs signals Sg4 to Sg8 based on the value of the correction value Vam. Signal Sg4 indicates the timing of the advance braking voltage Vb supply. Signal Sg5 controls the length of the first drive period T1 when the timing of the advance braking voltage Vb supply is determined. Signals Sg4 and Sg5 are input to NAND circuit 63. Signal Sg6 indicates a delay in the timing of the braking voltage Vb supply. Signal Sg7 controls the length of the first drive period T1 when the timing of the braking voltage Vb supply is delayed. Signals Sg6 and Sg7 are input to NAND circuit 64. Signal Sg8 indicates the generation of a signal whose frequency is n times that of signal CLK. Signal Sg8 is input to n-multiplier circuit 65.

[0206] For example, when the correction value Vam is 0, the signal generation circuit 61 outputs "L" (low) level signals Sg4 to Sg7. The signal generation circuit 61 outputs a signal Sg8 that makes n equal to 1.

[0207] When the correction value Vam is negative, the signal generation circuit 61 outputs a "H" level signal Sg4 and "L" level signals Sg6 and Sg7. The signal generation circuit 61 determines a period based on the absolute value of the correction value Vam, outputting a "H" level signal Sg5 during the determined period and an "L" level signal Sg5 during other periods. The signal generation circuit 61 outputs a signal Sg8 where n is an integer greater than or equal to 2 (corresponding to the determined period).

[0208] When the correction value Vam is positive, the signal generation circuit 61 outputs signals Sg4 and Sg5 at the "L" level and signal Sg6 at the "H" level. The signal generation circuit 61 determines a period based on the absolute value of the correction value Vam, outputting signal Sg7 at the "H" level during the determined period and signal Sg7 at the "L" level during other periods. The signal generation circuit 61 outputs signal Sg8 that sets n to 1.

[0209] AND circuit 62 receives signals CLK and Sg3, and outputs the result of the AND operation of signals CLK and Sg3 to AND circuit 67.

[0210] NAND circuit 63 receives signals Sg4 and Sg5, and outputs the result of NAND operation of signals Sg4 and Sg5 to inverter circuit 66 and AND circuit 67.

[0211] NAND circuit 64 receives signals Sg6 and Sg7, and outputs the result of the NAND operation of signals Sg6 and Sg7 to AND circuit 67.

[0212] The n-multiplier circuit 65 is a circuit that generates a signal with a frequency n times that of signal CLK based on signal Sg8. The generated signal is output to the AND circuit 68. For example, when the correction value Vam is 0 or positive, the n-multiplier circuit 65 directly outputs signal CLK based on signal Sg8. When the correction value Vam is negative, the n-multiplier circuit 65 outputs a signal with a frequency n times that of signal CLK based on signal Sg8.

[0213] Inverter circuit 66 receives the calculation result of NAND circuit 63 and outputs the signal after inverting the logic level of the calculation result to AND circuit 68.

[0214] AND circuit 67 receives the operation results of AND circuit 62, NAND circuit 63 and NAND circuit 64, and outputs the results of these AND operations to OR circuit 69.

[0215] AND circuit 68 receives signals from inverter circuit 66 and n-multiplier circuit 65, and outputs the results of these AND operations to OR circuit 69.

[0216] OR circuit 69 receives the operation results of AND circuit 67 and AND circuit 68, and outputs these OR operation results as drive pulse Pu.

[0217] Figure 25 This is a diagram showing an example of the waveform of the drive pulse Pu generated by the generation circuit 34 of the semiconductor device 1 in this embodiment. Figure 25 This represents the waveform when the switching element 41 is turned on. Figure 25 An example is the case where the correction value Vam is 0, that is, the timing of the braking voltage Vb supply is not corrected. Before time t61, signals Sg3 to Sg7 are at the "L" level.

[0218] At time t61, signals PWM and CLK rise. Signal Sg3 becomes "H" level. The operation result of AND circuit 62 is "H" level. The operation result of NAND circuit 63 is "H" level. The operation result of NAND circuit 64 is "H" level. The n-multiplier circuit 65 outputs signal CLK. The signal output from inverter circuit 66 is "L" level. The operation result of AND circuit 67 is "H" level. The operation result of AND circuit 68 is "L" level. The operation result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. Furthermore, when switching element 41 is off, at time t61, signal PWM falls. The drive pulse Pu output from OR circuit 69 also becomes "H" level when switching element 41 is on.

[0219] At time t62, signal CLK decreases. The result of AND circuit 62 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0220] At time t63, signal CLK rises. The result of AND circuit 62 is "H" level. The result of AND circuit 67 is "H" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. The period from time t61 to time t63 corresponds to parameter PM2. That is, at time t63, the first drive period T1 ends. In addition, when switch element 41 is off, at time t63, the drive pulse Pu output from OR circuit 69 also becomes "H" level when switch element 41 is on.

[0221] At time t64, signal CLK drops. The result of AND circuit 62 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0222] At time t65, signal CLK rises. The result of AND circuit 62 is "H" level. The result of AND circuit 67 is "H" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. The period from time t63 to time t65 corresponds to parameter PM4. That is, at time t65, the braking period Tb ends. In addition, when switch element 41 is off, at time t65, the drive pulse Pu output from OR circuit 69 also becomes "H" level when switch element 41 is on.

[0223] Figure 26 This is a diagram showing an example of the waveform of the drive pulse Pu generated by the generation circuit 34 of the semiconductor device 1 in this embodiment. Figure 26 This represents the waveform when the switching element 41 is turned on. Figure 26 An example is the case where the correction value Vam is negative, i.e., the case where the braking voltage Vb is supplied with timing advance. Figure 26 In the example, the n-fold frequency multiplier circuit 65 is a 2-fold frequency multiplier circuit. Before time t71, signals Sg3 to Sg7 are at the "L" level.

[0224] At time t71, signals PWM and CLK rise. Signals Sg3 to Sg5 become "H" level. The operation result of AND circuit 62 is "H" level. The operation result of NAND circuit 63 is "L" level. The operation result of NAND circuit 64 is "H" level. The n-multiplier circuit 65 outputs a "H" level signal. The signal output from inverter circuit 66 is "H" level. The operation result of AND circuit 67 is "L" level. The operation result of AND circuit 68 is "H" level. The operation result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. Furthermore, when switching element 41 is turned off, at time t71, signal PWM falls. The drive pulse Pu output from OR circuit 69 also becomes "H" level when switching element 41 is turned on.

[0225] At time t72, the n-multiplier circuit 65 outputs a signal at level "L". The result of the AND circuit 67 is at level "L". The result of the AND circuit 68 is at level "L". The result of the OR circuit 69 is at level "L". Therefore, the drive pulse Pu output from the OR circuit 69 becomes at level "L".

[0226] At time t73, signal CLK decreases. The result of AND circuit 62 is at level "L". The n-multiplier circuit 65 outputs a signal at level "H". The result of AND circuit 67 is at level "L". The result of AND circuit 68 is at level "H". The result of OR circuit 69 is at level "H". Therefore, the drive pulse Pu output from OR circuit 69 becomes at level "H". The period from time t71 to time t73 corresponds to parameter PM2. That is, at time t73, the first drive period T1 ends. In addition, when switch element 41 is off, at time t73, the drive pulse Pu output from OR circuit 69 also becomes at level "H" when switch element 41 is on.

[0227] At time t74, the n-multiplier circuit 65 outputs a signal at level "L". The result of the AND circuit 67 is at level "L". The result of the AND circuit 68 is at level "L". The result of the OR circuit 69 is at level "L". Therefore, the drive pulse Pu output from the OR circuit 69 becomes at level "L".

[0228] At time t75, signal CLK rises. Signal Sg5 becomes "L" level. The operation result of AND circuit 62 is "H" level. The operation result of NAND circuit 63 is "H" level. The signal output from inverter circuit 66 is "L" level. The operation result of AND circuit 67 is "H" level. The operation result of AND circuit 68 is "L" level. The operation result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. The period from time t73 to time t75 corresponds to parameter PM4. That is, at time t75, the braking period Tb ends. In addition, when switching element 41 is off, at time t75, the drive pulse Pu output from OR circuit 69 also becomes "H" level when switching element 41 is on.

[0229] At time t76, signal CLK drops. The result of AND circuit 62 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0230] Figure 27 This is a diagram showing an example of the waveform of the drive pulse Pu generated by the generation circuit 34 of the semiconductor device 1 in this embodiment. Figure 27 This represents the waveform when the switching element 41 is turned on. Figure 27 An example is the case where the correction value Vam is positive, i.e., the timing of the delayed braking voltage Vb supply. Before time t81, signals Sg3 to Sg7 are at the "L" level.

[0231] At time t81, signals PWM and CLK rise. Signals Sg3 and Sg6 become "H" level. The operation result of AND circuit 62 is "H" level. The operation result of NAND circuit 63 is "H" level. The operation result of NAND circuit 64 is "H" level. The n-multiplier circuit 65 outputs signal CLK. The signal output from inverter circuit 66 is "L" level. The operation result of AND circuit 67 is "H" level. The operation result of AND circuit 68 is "L" level. The operation result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. Furthermore, when switching element 41 is off, at time t81, signal PWM falls. The drive pulse Pu output from OR circuit 69 also becomes "H" level when switching element 41 is on.

[0232] At time t82, signal CLK drops. The result of AND circuit 62 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0233] At time t83, signal CLK rises. Signal Sg7 becomes "H" level. The result of AND circuit 62 is "H" level. The result of NAND circuit 64 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0234] At time t84, signal CLK drops. The result of AND circuit 62 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0235] At time t85, signal CLK rises. Signal Sg7 becomes "L" level. The operation result of AND circuit 62 is "H" level. The operation result of NAND circuit 64 is "H" level. The operation result of AND circuit 67 is "H" level. The operation result of AND circuit 68 is "L" level. The operation result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. The period from time t81 to time t85 corresponds to parameter PM2. That is, at time t85, the first drive period T1 ends. In addition, when switch element 41 is off, at time t85, the drive pulse Pu output from OR circuit 69 also becomes "H" level when switch element 41 is on.

[0236] At time t86, signal CLK drops. The result of AND circuit 62 is "L" level. The result of AND circuit 67 is "L" level. The result of AND circuit 68 is "L" level. The result of OR circuit 69 is "L" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "L" level.

[0237] At time t87, signal CLK rises. Signal Sg7 becomes "L" level. The operation result of AND circuit 62 is "H" level. The operation result of NAND circuit 64 is "H" level. The operation result of AND circuit 67 is "H" level. The operation result of AND circuit 68 is "L" level. The operation result of OR circuit 69 is "H" level. Therefore, the drive pulse Pu output from OR circuit 69 becomes "H" level. The period from time t85 to time t87 corresponds to parameter PM4. That is, at time t87, the braking period Tb ends. In addition, when switch element 41 is off, at time t87, the drive pulse Pu output from OR circuit 69 also becomes "H" level, just as when switch element 41 is on.

[0238] 3.3 Active gate control operation

[0239] The active gate control operation of the semiconductor device 1 according to the third embodiment will be described. The flowchart showing an example of the active gate control operation of the semiconductor device 1 according to this embodiment is similar to that shown in the first embodiment, except that step S111 is replaced by the following process. Figures 18-21 It is the same. In step S111, the generation circuit 34 receives a correction value Vam from the determination unit 303, the correction unit 304 or the switching unit 305, and generates a drive pulse Pu based on the correction value Vam.

[0240] 3.4 Effects of this implementation method

[0241] According to this embodiment, it achieves the same effect as the first embodiment.

[0242] 4. Variations, etc.

[0243] As described above, the semiconductor device (1) of the embodiment includes a first meter (LUT) including multiple drive modes (Pa), a controller (2) including the first meter, and a driver circuit (3). The driver circuit (3) includes: a second meter (LUTg) including at least a first mode (Pac) and a second mode (Pa) of the multiple drive modes (Pa) of the first meter (LUT); a control circuit (31); a generation circuit (34) that generates drive pulses (Pu) according to the first mode; and a drive circuit (35) that drives a switching element (41) by a voltage (Vdv) or current (Idv) based on the first mode at the timing of the drive pulse. When the switching element (41) is turned on or off, if the change (Δ) of the first information (Id / Vds / Temp) of the switching element is less than the first threshold (TH1 / TH2 / TH3), the control circuit (31) generates a correction value (Vam), and the generation circuit (34) generates a drive pulse (Pu) according to the first mode (Pac) and the correction value. If the change of the first information of the switching element is greater than or equal to the first threshold, the control circuit (31) replaces the first mode (Pac) with the second mode (Pas), and the generation circuit (34) generates a drive pulse (Pu) according to the replaced first mode (Pacr).

[0244] Furthermore, the implementation method is not limited to the manner described above, and various modifications are possible.

[0245] The flowcharts described in the above embodiments can be changed in the order of processing as much as possible.

[0246] In the above embodiments, the case of switching element 41 within the voltage control system 4 was described as an example, but the above embodiments can all be applied to the case of controlling the switching element 41 by current (current drive). That is, the drive mode Pa can be determined not by voltage and time, but by current and time. In other words, in the above drive mode Pa, voltage can be replaced by current. For example, in the case of current drive, in Figure 1 , Figure 3 , Figures 5 to 11 , Figure 14 as well as Figure 19 In this context, "drive voltage Vdv" is replaced with "drive current Idv". "First drive voltage V1" is replaced with "first drive current I1". "Braking voltage Vb" is replaced with "braking current Ib". "Second drive voltage V2" is replaced with "second drive current I2". Furthermore, the first drive current I1 is the current supplied to the gate of the switching element 41 for turning it on or off. When the switching element 41 is on or off, the braking current Ib is lower than the first drive current I1. Additionally, in... Figures 12-27In this process, parameter PM1 of drive mode Pa is replaced with a parameter corresponding to the first drive current I1, parameter PM3 of drive mode Pa is replaced with a parameter corresponding to the braking current Ib, and parameter PM5 of drive mode Pa is replaced with a parameter corresponding to the second drive current I2. Generation circuit 34 generates a drive pulse Pu based on the drive mode Pa (current mode Pac) stored in RAM within memory 32, controlling the timing of the drive current Idv supplied to the gate of the opposing switching element 41. Drive circuit 35 drives the switching element 41 based on the current of drive mode Pa (current mode Pac) stored in RAM within memory 32, according to the timing of the drive pulse Pu.

[0247] In the first embodiment, the adder 52 and counter 53 of the generation circuit 34 can also be replaced by an up-down counter. In this case, the up-down counter generates an sum value Vad by increasing or decreasing the value of parameter PM2 by a correction value Vam. When the count value Cnt has not reached the sum value Vad, the up-down counter outputs a first value as a signal Sg1, and when the count value Cnt reaches the sum value Vad, it outputs a second value as a signal Sg1.

[0248] Furthermore, the number of driving modes Pa contained in the lookup table LUTg stored in memory 32 may not be 7; for example, it may be 3. In this case, for example, it may be the current mode Pac(ic, jc, kc) and the driving mode Pa(ic±1, jc, kc), or it may be the current mode Pac(ic, jc, kc) and the driving mode Pa(ic, jc±1, kc), or it may be the current mode Pac(ic, jc, kc) and the driving mode Pa(ic, jc, kc±1).

[0249] For example, when the switching unit 305 receives the category CL and change amount Δ from the determination unit 303, it determines one of the two driving modes Pa adjacent to the current mode Pac, which has been switched to the current mode Pac (the switching mode Pas). The switching unit 305 sends the switching mode Pas determined as the lookup table LUTg, and switches the current mode Pac in the lookup table LUTg to the switching mode Pas. Thus, the memory 32 is in a state where the current mode Pac and the driving mode Pa adjacent to the current mode Pac are stored.

[0250] Considering two drive modes Pa adjacent to the current mode Pac, which are drive modes Pa(ic±1, jc, kc), the switching element 41 is turned on or off, and the drain current Id, drain voltage Vds, or temperature Temp rises (change ΔId>0). In this case, the switching unit 305 determines the drive mode Pa(ic+1, jc, kc) as the switching mode Pas.

[0251] When two drive modes Pa adjacent to the current mode Pac are drive modes Pa(ic±1, jc, kc), the switching element 41 is turned on or off, and the drain current Id, drain voltage Vds, or temperature Temp decreases (change ΔId < 0), the switching unit 305 determines the drive mode Pa(ic-1, jc, kc) as the switching mode Pas.

[0252] The same applies to the case where the two driving modes Pa adjacent to the current mode Pac are driving modes Pa(ic, jc±1, kc) and the case where the two driving modes Pa adjacent to the current mode Pac are driving modes Pa(ic, jc, kc±1).

[0253] In this specification, "connection" means electrical connection, which does not exclude the presence of other components in between.

[0254] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

[0255] Explanation of reference numerals in the attached figures

[0256] 1…Semiconductor device, 2…MCU, 3…Gate driver, 4…System, 21…Processor, 22…Memory, 23…Communication interface circuit, 31…Control circuit, 32…Memory, 33…Communication interface circuit, 34…Generation circuit, 35…Driver circuit, 41…Switching element, 51…MUX, 52…Adder, 53, 54…Counter, 55…Waveform shaping circuit, 61…Signal generation circuit, 62, 67, 68…AND circuit, 63, 64…NAND circuit, 65…n-frequency multiplier circuit, 66…Inverter circuit, 69…OR circuit, 301…Acquisition unit, 302…Loading unit, 303…Decision unit, 304…Correction unit, 305…Switching unit, LUT, LUTg…Look-up table, Pa, Pa1, Pa2…Drive mode, Pac…Current mode.

Claims

1. A semiconductor device, characterized in that, have: The first table contains multiple drive modes; The controller contains the first table; The second table contains at least the first mode and the second mode among the plurality of driving modes in the first table; as well as The driver circuit includes a control circuit, a generation circuit, and a drive circuit. The generation circuit generates drive pulses based on a first mode, and the drive circuit drives a switching element by means of voltage or current based on the first mode, according to the timing of the drive pulses. At the timing when the switching element is turned on or off When the change in the first information of the switching element is less than a first threshold, the control circuit generates a correction value. The generating circuit then generates the drive pulse based on the first mode and the correction value. When the change in the first information of the switching element is greater than or equal to the first threshold, the control circuit replaces the first mode with the second mode, and the generation circuit generates the drive pulse based on the replaced first mode.

2. The semiconductor device according to claim 1, characterized in that, The plurality of driving modes include a first driving mode when the switching element is on and a second driving mode when the switching element is off.

3. The semiconductor device according to claim 1, characterized in that, The multiple driving modes are based on combinations of the drain current, drain voltage, and temperature of the switching element.

4. The semiconductor device according to claim 3, characterized in that, The second table includes: The third mode is based on a combination of the first drain current, the first drain voltage, and the first temperature; The fourth mode is based on a combination of a second drain current that is higher than the first drain current, the first drain voltage, and the first temperature; The fifth mode is based on a combination of a third drain current that is lower than the first drain current, the first drain voltage, and the first temperature. The sixth mode is based on a combination of the first drain current, a second drain voltage that is higher than the first drain voltage, and the first temperature; The seventh mode is based on a combination of the first drain current, a third drain voltage that is lower than the first drain voltage, and the first temperature. The eighth mode is based on a combination of the first drain current, the first drain voltage, and a second temperature higher than the first temperature; and The ninth mode is based on a combination of the first drain current, the first drain voltage, and a third temperature lower than the first temperature. The first mode is the third mode. The second mode is any one of the fourth to the ninth modes.

5. The semiconductor device according to claim 1, characterized in that, Each of the plurality of driving modes includes a first parameter corresponding to a first voltage, a second parameter corresponding to a first period of supplying the first voltage, a third parameter corresponding to a second voltage supplied after the first period, a fourth parameter corresponding to a second period of supplying the second voltage, and a fifth parameter corresponding to a third voltage supplied after the second period.

6. The semiconductor device according to claim 5, characterized in that, The first voltage is the voltage supplied to the gate of the switching element for turning it on or off.

7. The semiconductor device according to claim 5, characterized in that, When the switching element is turned on, the second voltage is lower than the first voltage.

8. The semiconductor device according to claim 5, characterized in that, When the switching element is turned off, the second voltage is higher than the first voltage.

9. The semiconductor device according to claim 5, characterized in that, When the change in the first information of the switching element is less than a first threshold, the generation circuit generates the driving pulse based on the second and fourth parameters of the first mode, and the correction value. When the change in the first information of the switching element is greater than or equal to the first threshold, the generation circuit generates the driving pulse based on the second parameter and the fourth parameter of the permuted first mode.

10. The semiconductor device according to claim 5, characterized in that, Each of the plurality of driving modes includes a first register storing the first parameter, a second register storing the second parameter, a third register storing the third parameter, a fourth register storing the fourth parameter, and a fifth register storing the fifth parameter. The first register, the second register, and the third register constitute a shift register.

11. The semiconductor device according to claim 1, characterized in that, Each of the plurality of driving modes includes a first parameter corresponding to a first current, a second parameter corresponding to a first period of supplying the first current, a third parameter corresponding to a second current supplied after the first period, a fourth parameter corresponding to a second period of supplying the second current, and a fifth parameter corresponding to a third current supplied after the second period.

12. The semiconductor device according to claim 11, characterized in that, The first current is the current supplied to the gate of the switching element for turning it on or off.

13. The semiconductor device according to claim 11, characterized in that, When the switching element is turned on or off, the second current is lower than the first current.

14. The semiconductor device according to claim 1, characterized in that, The first mode is a drive mode that is expected to change at the timing of the switching element being turned on or off based on the first information.

15. The semiconductor device according to claim 14, characterized in that, The second mode is the driving mode corresponding to the case where the first information is increased or decreased from the first mode.

16. The semiconductor device according to claim 1, characterized in that, The first piece of information is the drain current, drain voltage, or temperature of the switching element.

17. The semiconductor device according to claim 1, characterized in that, The correction value is generated based on the change in the first information.

18. The semiconductor device according to claim 1, characterized in that, The switching element is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).

19. The semiconductor device according to claim 1, characterized in that, The switching element is a silicon carbide MOSFET.

Images