Gate driver circuit

Abstract

A gate driver circuit for a switching converter including a first switch and a second switch, the gate driver circuit comprising: a first switch gate driver configured to receive a first control signal, receive a first delay signal, and provide a first switch gate drive signal to turn on the first switch when both the first control signal and the first delay signal are in a first state; a second switch gate driver configured to receive a second control signal and provide a second switch gate drive signal to drive a switching operation of the second switch; a first delay generator including a replica of the second switch gate driver and a first delay signal generator.

Description

field

[0001] This disclosure relates to gate driver circuits. Specifically, this disclosure relates to a gate driver circuit for a switching converter. background

[0002] For switching converters, seamlessly switching current from one path to another is crucial. Ideally, one switch is off while the other takes over the current at the same time. Overlapping, where both switches in a pair are on, must be avoided. If both switches are in the on state simultaneously, it can cause short circuits at different low-impedance voltage nodes (such as power supply voltage nodes and ground nodes).

[0003] There are known methods that produce significant non-overlap times, in which current is kept flowing through the parasitic diode. Other known methods use a digitally programmable delay between the switching activation signals for the high-side and low-side switches. Other known methods use adaptive dead-time minimization to prevent overlap, but these methods require complex circuit configurations.

[0004] Each known method has one or more of the following drawbacks:

[0005] 1. Long non-overlapping time leading to high losses and parasitic bipolar effects.

[0006] 2. High complexity.

[0007] 3. The current consumption for condition detection is high.

[0008] 4. Problems caused by rapid changes in load current at the output node. Overview

[0009] It is desirable to provide a gate driver circuit that mitigates or overcomes one or more of the aforementioned problems.

[0010] According to a first aspect of this disclosure, a gate driver circuit for a switch converter is provided, the switch converter including a first switch and a second switch, the gate driver circuit including: a first switch gate driver configured to receive a first control signal, receive a first delay signal, and provide a first switch gate drive signal to turn on the first switch when both the first control signal and the first delay signal are in a first state; a second switch gate driver configured to receive a second control signal and provide a second switch gate drive signal to drive a switching operation of the second switch; and a first delay generator including a replica second switch gate driver and a first delay signal generator, wherein the replica second switch gate driver is configured to provide a replica second switch gate drive signal to the first delay signal generator, the replica second switch gate drive signal depending on the first control signal, and the first delay signal generator is configured to generate a first delay signal depending on the replica second switch gate drive signal.

[0011] Optionally, the second gate switch driver and the replica second gate switch driver have substantially similar circuit topologies.

[0012] Optionally, the second switch gate driver includes one or more second-side transistors, and the duplicated second switch gate driver includes one or more duplicated second-side transistors.

[0013] Optionally, the second switch gate driver includes one or more second-side PMOS transistors, and the replicated second switch gate driver includes one or more replicated second-side PMOS transistors, and / or the second switch gate driver includes one or more second-side NMOS transistors, and the replicated second switch gate driver includes one or more replicated second-side NMOS transistors.

[0014] Optionally, the second switch driver transistor ratio is provided by: i) the ratio between the transistor ratio of one of the one or more second-side transistors and the transistor ratio of another of the one or more second-side transistors, or ii) the ratio between the transistor ratio of the second switch and the transistor ratio of one of the one or more second-side transistors, and the replicated second switch driver transistor ratio is provided by: i) the ratio between the transistor ratio of one of the one or more replicated second-side transistors and the transistor ratio of another of the one or more replicated second-side transistors, or ii) the ratio between the transistor ratio of the replicated second switch and the transistor ratio of one of the one or more replicated second-side transistors, and the second switch driver transistor ratio and the replicated second switch driver transistor ratio are approximately equal.

[0015] Optionally, the transistor ratio of one of the one or more second-side transistors is the width-to-length ratio of one of the one or more second-side transistors, the transistor ratio of another of the one or more second-side transistors is the width-to-length ratio of another of the one or more second-side transistors, the transistor ratio of the second switch is the width-to-length ratio of the second switch, the transistor ratio of one of the one or more replicated second-side transistors is the width-to-length ratio of one of the one or more replicated second-side transistors, the transistor ratio of another of the one or more replicated second-side transistors is the width-to-length ratio of another of the one or more replicated second-side transistors, and the transistor ratio of the replicated second switch is the width-to-length ratio of the replicated second switch.

[0016] Optionally, the second switch gate driver includes one or more second-side logic gates, and the duplicated second switch gate driver includes one or more duplicated second-side logic gates of the same type as the one or more second-side logic gates.

[0017] Optionally, the second switch gate driver is positioned close enough to the replica second switch gate driver to withstand substantially similar operating temperatures during operation.

[0018] Optionally, the second gate driver includes: a first gate driver switch; a second gate driver switch coupled to the first gate driver switch at the output node of the second gate driver, wherein a second gate drive signal is provided from the output node of the second gate driver; a first drive circuit for driving the switching of the first gate driver switch; and a second drive circuit for driving the switching of the second gate driver switch.

[0019] Optionally, the first driving circuit includes a first buffer circuit and a first NAND gate, and the second driving circuit includes a second buffer circuit and a third buffer circuit or an AND circuit.

[0020] Optionally, the replica second gate driver includes: a first delay generator switch; a second delay generator switch coupled to the first delay generator switch at the output node of the replica second gate driver, wherein a replica second gate drive signal is provided from the output node of the replica second gate driver; a replica first drive circuit for driving a switching operation of the first delay generator switch; and a replica second drive circuit for driving a switching operation of the second delay generator switch.

[0021] Optionally, the replication first driving circuit includes a second NAND gate, a first inverter circuit, and a second inverter circuit, and the replication second driving circuit includes a third NAND gate and a third inverter circuit.

[0022] Optionally, the gate driver circuit includes a programmable delay circuit configured to: receive a first delay generator switch indicator signal from a replicating first driver circuit, apply a delay parameter to the first delay generator switch indicator signal, and provide the first delay generator switch indicator signal to a replicating second driver circuit after the delay parameter has been applied. The replicating second driver circuit is configured to provide a delayed gate drive signal to a second delay generator switch after the delay parameter has been applied, the delayed gate drive signal depending on the first control signal and the first delay generator switch indicator signal.

[0023] Optionally, the programmable delay circuit is configured to receive a configuration signal, the delay parameters of which depend on the configuration signal.

[0024] Optionally, the gate driver circuit includes a first level shifter and a second level shifter, the first level shifter being configured to level shift a first control signal, and the second level shifter being configured to provide a configuration signal to a first delay generator to correct the switching delay generated by the first level shifter.

[0025] Optionally, the first delay signal generator includes: a third delay generator switch; a fourth delay generator switch coupled to the third delay generator switch at a first node, the fourth delay generator switch including a fourth delay generator switch gate terminal coupled to the output node of the replica second switch gate driver; and a delay signal generator buffer circuit including a first input terminal coupled to the first node and a first output terminal for providing the first delay signal.

[0026] Optionally, the third delay generator switch is driven by fewer inverter stages compared to the fourth delay generator switch.

[0027] Optionally, the first switch and the fourth delay generator switch have one or more of the following: the same transistor type and / or approximately equal transistor width and / or length.

[0028] Optionally, the gate driver circuit includes: a fourth buffer circuit configured to receive a first control signal and provide a first replication control signal; and a fourth inverter circuit configured to receive the first replication control signal and provide a second replication control signal, wherein the replication first drive circuit is configured to receive the second replication control signal and drive the switching operation of the first delay generator switch based on the second replication control signal and the second delay generator switch indicator signal.

[0029] Optionally, the third delay generator switch includes a third delay generator switch gate terminal configured to receive a second replication control signal.

[0030] Optionally, the first state is the ON state.

[0031] Optionally, the first switch is a high-side switch and the second switch is a low-side switch, and / or the first switch is a low-side switch and the second switch is a high-side switch.

[0032] Optionally, the second gate switch driver is configured to receive a second delayed signal and, when both the second control signal and the second delayed signal are in a first state or a second state, provide a second gate switch drive signal to turn on the second switch. The gate driver circuit includes a second delay generator, which includes a replica of the first gate switch driver and a second delay signal generator. The replica of the first gate switch driver is configured to provide a replica of the first gate switch drive signal to the second delay signal generator, the replica of the first gate switch drive signal depending on the second control signal, and the second delay signal generator is configured to generate a second delayed signal depending on the replica of the first gate switch drive signal.

[0033] Optionally, the first switch gate driver and the replica of the first switch gate driver have substantially similar circuit topologies, and / or the second switch gate driver and the replica of the second switch gate driver have substantially similar circuit topologies.

[0034] Optionally, the first switch gate driver includes one or more first-side transistors, and the replica first switch gate driver includes one or more replica first-side transistors, and / or the second switch gate driver includes one or more second-side transistors, and the replica second switch gate driver includes one or more replica second-side transistors.

[0035] Optionally, the first switch gate driver includes one or more first-side PMOS transistors, and the replicated first switch gate driver includes one or more replicated first-side PMOS transistors, and / or the first switch gate driver includes one or more first-side NMOS transistors, and the replicated first switch gate driver includes one or more replicated first-side NMOS transistors, and / or the second switch gate driver includes one or more second-side PMOS transistors, and the replicated second switch gate driver includes one or more replicated second-side PMOS transistors, and / or the second switch gate driver includes one or more second-side NMOS transistors, and the replicated second switch gate driver includes one or more replicated second-side NMOS transistors.

[0036] Optionally, the first switch driver transistor ratio is provided by: i) the ratio between the transistor ratio of one or more first-side transistors and the transistor ratio of another one or more first-side transistors, or ii) the ratio between the transistor ratio of the first switch and the transistor ratio of one or more first-side transistors. The replicated first switch driver transistor ratio is provided by: i) the ratio between the transistor ratio of one or more replicated first-side transistors and the transistor ratio of another one or more replicated first-side transistors, or ii) the ratio between the transistor ratio of the replicated first switch and the transistor ratio of one or more replicated first-side transistors, and the first switch driver transistor ratio and the replicated first switch driver transistor ratio are approximately equal. The second switch driver transistor ratio is provided by: i) the ratio between the transistor ratio of one or more second-side transistors and the transistor ratio of another transistor in one or more second-side transistors, or ii) the ratio between the transistor ratio of the second switch and the transistor ratio of one or more second-side transistors, and the replica second switch driver transistor ratio is provided by: i) the ratio between the transistor ratio of one or more replica second-side transistors and the transistor ratio of another transistor in one or more replica second-side transistors, or ii) the ratio between the transistor ratio of the replica second switch and the transistor ratio of one or more replica second-side transistors, and the second switch driver transistor ratio and the replica second switch driver transistor ratio are approximately equal.

[0037] Optionally, the transistor ratio of one of the one or more first-side transistors is the width-to-length ratio of one of the one or more first-side transistors, the transistor ratio of another one or more first-side transistors is the width-to-length ratio of another one or more first-side transistors, the transistor ratio of the first switch is the width-to-length ratio of the first switch, the transistor ratio of one of the one or more replicated first-side transistors is the width-to-length ratio of one of the one or more replicated first-side transistors, the transistor ratio of another one or more replicated first-side transistors is the width-to-length ratio of another one or more replicated first-side transistors, and the transistor ratio of the replicated first switch is the width-to-length ratio of the replicated first switch. The transistor ratio of one of the transistors in one or more second-side transistors is the width-to-length ratio of one of the transistors in one or more second-side transistors, the transistor ratio of another transistor in one or more second-side transistors is the width-to-length ratio of another transistor in one or more second-side transistors, the transistor ratio of the second switch is the width-to-length ratio of the second switch, the transistor ratio of one of the transistors in one or more replicated second-side transistors is the width-to-length ratio of one of the transistors in one or more replicated second-side transistors, the transistor ratio of another transistor in one or more replicated second-side transistors is the width-to-length ratio of another transistor in one or more replicated second-side transistors, and the transistor ratio of the replicated second switch is the width-to-length ratio of the replicated second switch.

[0038] Optionally, the first switch gate driver includes one or more first-side logic gates, and the replica first switch gate driver includes one or more replica first-side logic gates of the same type as the one or more first-side logic gates, and / or the second switch gate driver includes one or more second-side logic gates, and the replica second switch gate driver includes one or more replica second-side logic gates of the same type as the one or more second-side logic gates.

[0039] Optionally, the first gate switch driver is positioned sufficiently close to a replica of the first gate switch driver to withstand substantially similar operating temperatures during operation, and / or the second gate switch driver is positioned sufficiently close to a replica of the second gate switch driver to withstand substantially similar operating temperatures during operation.

[0040] According to a second aspect of this disclosure, a method is provided for providing a gate driver circuit for a switch converter, the switch converter including a first switch and a second switch, the gate driver circuit including: a first switch gate driver configured to receive a first control signal, receive a first delay signal, and provide a first switch gate drive signal to turn on the first switch when both the first control signal and the first delay signal are in a first state; a second switch gate driver configured to receive a second control signal and provide a second switch gate drive signal to drive a switching operation of the second switch; and a first delay generator including a replica second switch gate driver and a first delay signal generator, wherein the replica second switch gate driver is configured to provide a replica second switch gate drive signal to the first delay signal generator, the replica second switch gate drive signal depending on the first control signal, and the first delay signal generator is configured to generate a first delay signal depending on the replica second switch gate drive signal.

[0041] It should be recognized that the approach of the second aspect may include the use and / or provision of the features described in the first aspect, and may include other features as described herein. Brief description of the attached diagram

[0042] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0043] Figure 1A This is a schematic diagram of a gate driver circuit for a switch converter according to a first embodiment of the present disclosure. Figure 1B This is a timing diagram showing the example waveform. Figure 1C This is a schematic diagram of a specific embodiment of the gate driver circuit according to the second embodiment of the present disclosure. Figure 1D It is possible Figure 1C A schematic diagram illustrating the specific implementation of the gate driver and the replica gate driver in the gate driver circuit;

[0044] Figure 2A This is a schematic diagram of a portion of a specific implementation of a gate driver circuit and a switch converter according to a third embodiment of the present disclosure. Figure 2B This is a schematic diagram of another specific implementation of the gate driver circuit and switch converter according to the fourth embodiment of the present disclosure. Figure 2C According to the fifth embodiment of this disclosure Figure 2B A schematic diagram of a specific embodiment of the second switching gate driver. Figure 2D According to the sixth embodiment of this disclosure Figure 2B A schematic diagram of a specific embodiment of the delay generator;

[0045] Figure 3This is a schematic diagram of a specific implementation of a delay generator according to the seventh embodiment of the present disclosure;

[0046] Figure 4 This is a schematic diagram of a specific implementation of the gate driver circuit and the switch converter according to the eighth embodiment of the present disclosure;

[0047] Figure 5 This is a schematic diagram of a specific implementation of the high-side power stage according to the ninth embodiment of this disclosure; and

[0048] Figure 6A yes Figure 4 The table shows the results of Monte Carlo simulations of the circuit, with varying parameters for non-overlapping conditions in the Monte Carlo simulations. Figure 6B yes Figure 4 The table shows the results of Monte Carlo simulations of the circuit, including matched and non-overlapping times with delays in the Monte Carlo simulation. Figure 6C yes Figure 4 The table shows the results of the Monte Carlo simulation of the circuit, which has an absolute delay in the Monte Carlo simulation. Detailed description

[0049] Figure 1A This is a schematic diagram of a gate driver circuit 100 for a switch converter 102 according to a first embodiment of the present disclosure, the switch converter 102 including a first switch 104 and a second switch 106.

[0050] For example, switching converter 102 may be a buck converter, a boost converter, or a buck-boost converter. Switching converter 102 may include an energy storage element (not shown), such as an inductor. Switches 104 and 106 may be referred to as power switches and may each include a transistor. Switches 104 and 106 may be coupled in series between two power supply voltage terminals. During operation, switches 104 and 106 may be operated to periodically couple and decouple the energy storage element from the power supply voltage terminals to provide a regulated output voltage. The first switch 104 may be a high-side switch or a low-side switch, and the second switch 106 may be another of the high-side switch or the low-side switch.

[0051] Each of switches 104 and 106 may include an NMOS transistor and / or a PMOS transistor.

[0052] In a particular embodiment, when a power switch is created using “NMOS transistors and PMOS transistors”, one gate driver will have a negative supply voltage relative to the p-MOS source, while the other driver will have a positive supply voltage relative to the n-MOS.

[0053] The gate driver circuit 100 includes a first switch gate driver 108 (also labeled "GD1"), which is configured to receive a control signal go1 and a delay signal trnOn. The first switch gate driver 108 is configured to provide a gate drive signal G1 to turn on the first switch 104 when both the control signal go1 and the delay signal trnOn are in a first state.

[0054] Figure 1B The timing diagram 110 shows example waveforms of the control signal go1 (trace 112), the delay signal trnOn (trace 114), and the gate drive signal G1 (trace 116).

[0055] The control signal go1 can be a digital signal provided from a controller (not shown). During operation, the control signal go1 can transition between two states. Figure 1B As shown, the control signal go1 transitions between a high state and a low state, where the high state can be referred to as the "on state" and the low state can be referred to as the "off state". The delay signal trnOn also transitions between two states. The first state can be the on state, and the second state can be the off state.

[0056] The gate drive signal G1 is used to control the switching operation of the first switch 104, such that when the gate drive signal G1 is in a high state, it can "turn on" the switch to allow current to flow, and when the gate drive signal G1 is in a low state, it can "turn off" the switch to prevent current from flowing.

[0057] The delay signal trnOn applies a delay before allowing the first switch 104 to turn on, thereby preventing both switches 104 and 106 from being on simultaneously. During operation, the first switch gate driver 108 provides a gate drive signal G1 to turn on the first switch 104 when both the control signal go1 and the delay signal trnOn are high.

[0058] It should be understood that, in another embodiment, during operation, the first switch gate driver 108 can provide a gate drive signal G1 to turn on the first switch 104 when both the control signal go1 and the delay signal trnOn are low. It should be understood that, in another embodiment, the first switch 104 can be enabled when the gate drive signal G1 is low.

[0059] It should be understood that Figure 1BThe graphs are for illustrative purposes only and are for an idealized system. In a practical implementation, power switches 104 and 106 have high gate capacitance, meaning the gate voltage edge will have a longer time period but not an infinite slope. It is important to note that the falling edge of the gate voltage G1 should not end before the turn-on delay. In a symmetrical circuit with identical gate drivers, delays, and power devices for both switches, the turn-on delay will match the falling edge of the gate voltage (ignoring the following two facts: a) when the device is off, the gate voltage may be between 0V and the threshold, and b) when the turn-on signal rises, the gate voltage will not rise immediately because some combinational logic is required, and the gate driver—which in most cases has multiple stages—adds a further delay).

[0060] The gate driver circuit 100 also includes a second switch gate driver 118, which is configured to receive a control signal go2 and provide a gate drive signal G2 to drive the switching operation of the second switch 106.

[0061] Control signal go2 can be a digital signal provided from a controller (not shown). During operation, control signal go2 can transition between two states, for example, as shown with respect to control signal go1. Control signal go2 can also be the inverted version of control signal go1.

[0062] The gate driver circuit 100 also includes a delay generator 120 for generating a delayed signal trnOn. The delay generator 120 includes replicas of the second switching gate driver 122 and the delay signal generator 124.

[0063] During operation, the replica second gate switch driver 122 (also labeled "R-GD2") provides the replica second gate switch drive signal R-G2 to the delay signal generator 124. The replica gate drive signal R-G2 depends on the control signal go1.

[0064] The delay signal generator 124 is configured to generate a delay signal trnOn that depends on the replicated second switch gate drive signal R-G2.

[0065] In this example, control signal go1 is shown to be provided to the replicating second switch gate driver 122 and the first switch gate driver 108 to illustrate the dependence of each of the replicating second switch gate drive signals R-G2 and gate drive signals G1 on control signal go1. However, it should be understood that control signal go1 may be processed, modified, or used to generate intermediate signals before one or both of the generated signals R-G2 and G1. For example, the replicating gate drive signals R-G2 may be generated using the inverted control signal go1, where the gate drive signal G1 is generated using the non-inverted control signal go1.

[0066] The second gate driver 122 is a copy of the second gate driver 118. "Copy" means that the copied gate driver is designed to exhibit performance sufficiently similar to the original gate driver (which may be referred to as a "corresponding" gate driver) so that the copied gate driver can be used to extract information about the performance of the original gate driver. Specifically, the use of the copied second gate driver 122 means that information about the required delay to prevent the on-times of switches 104 and 106 from overlapping can be obtained and used to generate a suitable delay signal trnOn to prevent simultaneous on-times of switches 104 and 106.

[0067] Information about the performance of the second switching gate driver 118 is provided to the delay signal generator 124 by the replicated gate drive signal R-G2.

[0068] For example, replicating the second switch gate drive signal R-G2 can indicate when the second switch 106 is in a second state. The second state can be an off state.

[0069] In a particular embodiment, in order to be used as a replica gate driver, the replica second switch gate driver 122 may receive the same power supply voltage as the second switch gate driver 118.

[0070] In a particular embodiment, the second switch gate driver 118 and the replica second switch gate driver 122 may have substantially similar circuit topologies for use as replica gate drivers.

[0071] Essentially similar circuit topologies mean that circuits use the same or functionally similar components with the same or similar circuit layout in their physical implementation, such as when they are manufactured as part of the same integrated circuit.

[0072] In a particular embodiment, for use as a replica gate driver, and when implemented in physical circuitry (e.g., as part of an integrated circuit), the second switch gate driver 118 may be positioned close enough to the replica second switch gate driver 122 such that they both experience substantially similar operating temperatures during operation.

[0073] In summary, to provide a good match between the timing of the replica gate driver and the timing in its corresponding gate driver, they can have one or more of the following:

[0074] Similar transistor types;

[0075] Similar topologies (e.g., inverters, NAND gates, and NOR gates);

[0076] Similar power supply voltage;

[0077] Similar operating temperatures (by placing the replica gate driver and the corresponding gate driver components close to each other).

[0078] A “good match” between a replica gate driver and its corresponding gate driver can make the delay generated by the gate driver exist in the replica gate driver, and then the replica gate driver can be used to correct the delay.

[0079] Figure 1C This is a schematic diagram of a specific embodiment of the gate driver circuit 100 according to the second embodiment of the present disclosure.

[0080] In this embodiment, the gate driver circuit 100 includes a delay generator 126 for the second switch 106. It should be understood that, as those skilled in the art will recognize, the delay generator 126 and the second switch gate driver 118 can function substantially as described with respect to the delay generator 120 and the first switch gate driver 108, respectively. In another embodiment, the delay generator 126 may include the features described with respect to the delay generator 120.

[0081] The second gate switch driver 118 is configured to receive the delay signal trnOn2 and provide a second gate switch drive signal G2 to turn on the second switch 106 when both the control signal go2 and the delay signal trnOn2 are in a first state or a second state. The first state may be, for example, an ON state, and may be the same state as described with respect to the operation of the first switch 104. The second state may be a different state from the first state described with respect to the operation of the first switch 104.

[0082] Delay generator 126 is used to generate a delayed signal trnOn2. Delay generator 126 includes a replica of the first switch gate driver 128 and a delay signal generator 130.

[0083] During operation, the replica first gate switch driver 128 (also labeled "R-GD1") provides the replica first gate switch drive signal R-G1 to the delay signal generator 130. The replica gate drive signal R-G1 depends on the control signal go2.

[0084] The delay signal generator 130 is configured to generate a delay signal trnOn2 that depends on the replication of the first switch gate drive signal R-G1.

[0085] The first switch gate driver 128 is a copy of the first switch gate driver 108. The use of the first switch gate driver 128 means that information about the required delay to prevent the turn-on times of switches 104 and 106 from overlapping can be obtained, and this information can be used to generate a suitable delay signal trnOn2 to prevent the simultaneous turn-on times of switches 104 and 106.

[0086] Information about the performance of the first switching gate driver 108 is provided to the delay signal generator 130 by the replicated gate drive signal R-G1.

[0087] For example, replicating the first switch gate drive signal R-G1 can indicate when the first switch 104 is in a second state. The second state can be an off state.

[0088] In a particular embodiment, in order to be used as a replica gate driver, the replica first switch gate driver 128 may receive the same power supply voltage as the first switch gate driver 108.

[0089] In a particular embodiment, the first switch gate driver 108 and the replica first switch gate driver 128 may have substantially similar circuit topologies for use as replica gate drivers.

[0090] Figure 1D This is a schematic diagram of the specific implementation of gate drivers 108, 118 and replicated gate drivers 122, 128.

[0091] The specific implementations of gate driver 118 and replicated gate driver 122 can be found in Figure 1A It is implemented in the gate driver circuit 100.

[0092] Specific implementations of one or both of gate drivers 108 and 118 and one or both of replica gate drivers 122 and 128 may be available in Figure 1C The gate driver circuit 100 is implemented. The first switch gate driver 108 may include one or more first-side transistors 108a, 108b, and the replica first switch gate driver 128 may include one or more replica first-side transistors 128a, 128b.

[0093] Each of the first-side transistors 108a and 108b may include a PMOS transistor or an NMOS transistor.

[0094] Each of the first-side transistors 128a and 128b may include a PMOS transistor or an NMOS transistor.

[0095] The second gate switch driver 118 may include one or more second-side transistors 118a, 118b, and the duplicated second gate switch driver 122 may include one or more duplicated second-side transistors 122a, 122b.

[0096] Each of the second-side transistors 118a and 118b may include a PMOS transistor or an NMOS transistor.

[0097] Each of the second-side transistors 122a and 122b may include a PMOS transistor or an NMOS transistor.

[0098] The first switch driver transistor ratio can be provided by the following: the ratio between the transistor ratio of one transistor 108a in the first-side transistors and the transistor ratio of the other transistor 108b in the first-side transistors.

[0099] Alternatively, the first switch driver transistor ratio may be provided by the ratio between the transistor ratio of one of the first-side transistors 108a and the transistor ratio of the first switch 104.

[0100] The ratio of the transistors that replicate the first switch driver can be provided by the ratio between the transistor ratio of one transistor 128a in the first-side transistor replication and the transistor ratio of the other transistor 128b in the first-side transistor replication.

[0101] Alternatively, the ratio of the transistors replicating the first switch driver can be provided by the ratio between the transistor ratio of one or more replicating first-side transistors 128a and the transistor ratio of the replicating first switch (not shown). The replicating of the first switch can be a replica of the first switch 104.

[0102] The ratio of the first switch driver transistors and the ratio of the replica first switch driver transistors can be approximately equal.

[0103] The transistor ratio of the second switch driver can be provided by the following: the ratio between the transistor ratio of one transistor 118a in the second-side transistor and the transistor ratio of the other transistor 118b in the second-side transistor.

[0104] Alternatively, the transistor ratio of the second switch driver can be provided by the ratio between the transistor ratio of one of the one or more second-side transistors 118b and the transistor ratio of the second switch 106.

[0105] The ratio of the transistors that replicate the second switch driver can be provided by the following: the ratio between the transistor ratio of one transistor 122a in the replicated second-side transistors and the transistor ratio of the other transistor 122b in the replicated second-side transistors.

[0106] Alternatively, the ratio of the transistors driving the second switch can be provided by the ratio between the transistor ratio of one or more transistors 122a of the replicated second-side transistors and the transistor ratio of the replicated second switch (not shown). The replicated second switch can be a copy of the second switch 106.

[0107] The ratio of the second switch driver transistors and the ratio of the replicated second switch driver transistors can be approximately equal.

[0108] As previously stated, by making the ratio of the first switch-driver transistors of the first switch-gate driver 108 approximately equal to the ratio of the replicated first switch-driver transistors of the replicated first switch-gate driver 128, the replicated first switch-gate driver 128 can be used as a “copy” of the first switch-gate driver 108.

[0109] Similarly, as previously described, by making the second switch driver transistor ratio of the second switch gate driver 118 approximately equal to the replica second switch driver transistor ratio of the replica second switch gate driver 122, the replica second switch gate driver 122 can be used as a “replica” of the second switch gate driver 118.

[0110] The transistor ratio of a transistor can be defined as the width-to-length ratio of the transistor.

[0111] The width-to-length ratio is a well-known parameter in circuit design, where width refers to the physical width of the transistor gate and length refers to the physical length of the transistor gate. The width-to-length ratio can affect the properties and performance of a transistor.

[0112] The first switch-gate driver 108 may include one or more first-side logic gates 108c, which may include transistors 108a and 108b. The replica first switch-gate driver 128 may include one or more replica first-side logic gates 128c, which may include transistors 128a and 128b. The one or more first-side logic gates 108c may be of the same type as the one or more replica first-side logic gates 128c.

[0113] The second gate switch driver 118 may include one or more second-side logic gates 118c, which may include transistors 118a and 118b. The duplicated second gate switch driver 122 may include one or more duplicated second-side logic gates 122c, which may include transistors 122a and 122b. The one or more second-side logic gates 118c may be of the same type as the one or more duplicated second-side logic gates 122c.

[0114] Figure 2A According to the third embodiment of this disclosure Figure 1A This is a schematic diagram of a portion of a specific implementation of the gate driver circuit 100 and the switch converter 102. In this embodiment, the gate driver circuit 100 includes a level shifter 200 configured to level-shift a control signal go1. Level shifting refers to the process of shifting the voltage level of a signal to an appropriate level for use by subsequent circuitry.

[0115] Figure 2A The principle of the gate control circuit at an example of the high-side switch of a power inverter is shown, and includes a level shifter 200. Here, the first switch gate driver 108 turns on the gate of switch 104 (at node Gate_HS) only when the signal "go" (as control signal go1) and the delay signal trnOn are high. Turning off begins from the rising edge of "go_n", which is the inverting control signal go1.

[0116] Figure 2B According to the fourth embodiment of this disclosure Figure 1A A schematic diagram of another specific implementation of the gate driver circuit 100 and the switch converter 102 is shown. In this embodiment, the gate driver circuit 100 includes a level shifter 202 for the delay unit 120, which is configured to provide a configuration signal cfg1 to the delay generator 120. The configuration signal cfg1 can be used by the delay generator 120 to correct the switching delay caused by the level shifter 202. Optionally, multiple level shifters and signal buses can be used for delay configuration.

[0117] Figure 2C According to the fifth embodiment of this disclosure Figure 2B A schematic diagram of a specific embodiment of the second switching gate driver 118 of the gate driver circuit 100.

[0118] Figure 2C This is a schematic diagram of a specific implementation of the second switch gate driver 118 that can be used in any of the embodiments described herein, as understood by those skilled in the art. It should be understood that in other embodiments, one or both of the first switch gate driver 108 and the second switch gate driver 118 may be used as directed to... Figure 2CThe second switching gate driver 118 is shown in the figure.

[0119] The second switch gate driver 118 may include gate driver switches 204, 206 coupled together at the output node N0. During operation, a gate drive signal G2 for the second switch 106 is provided from the output node N0.

[0120] The second gate switch driver 118 also includes drive circuits 208 and 210. During operation, drive circuit 208 drives the switching of gate driver switch 204, and drive circuit 210 drives the switching of gate driver switch 206.

[0121] The driving circuit 208 may include a buffer circuit 212 and a NAND gate 214. The driving circuit 210 may include a buffer circuit 216 and an AND circuit 218. The buffer circuit 216 may include two inverters.

[0122] Figure 2D According to the sixth embodiment of this disclosure Figure 2B A schematic diagram of a specific embodiment of the delay generator 120 of the gate driver circuit 100.

[0123] Figure 2D This is a schematic diagram illustrating a specific implementation of the delay generator 120 that can be used in any of the embodiments described herein, as understood by those skilled in the art. It should be understood that in other embodiments, one or both of the delay generators 120, 126 can be used as directed for... Figure 2D The delay generator 120 is shown as an example of implementation.

[0124] In this embodiment, the delay signal generator 124 further includes a delay generator switch 220 and a delay generator switch 222 coupled together at node N1. The gate terminal of the delay generator switch 222 is coupled to node N2.

[0125] The delay signal generator 124 also includes a buffer circuit 224 having an input coupled to node N1 and configured to provide a delay signal trnOn at its output.

[0126] The first switch 104 and the delay generator switch 222 may have the same transistor type (e.g., PMOS or NMOS) and / or may have approximately equal transistor widths and / or lengths, but with a scaling factor applied. In a particular embodiment, the power switch 104 and the replica switch 222 do not have the same width. The replica is preferably much smaller (e.g., reduced to 1 / 100). The lengths may have the same (minimum) value.

[0127] The delay generator 120 also includes a buffer circuit 226 configured to receive a control signal go1 and provide a replication control signal goReplica_n. The delay generator 120 also includes an inverter circuit 228 configured to receive the replication control signal goReplica_n and provide the replication control signal goReplica.

[0128] The replicating second gate switch driver 122 includes delay generator switches 230 and 232. Delay generator switches 230 and 232 are coupled at node N2. During operation, a replicating second gate switch drive signal R-G2 is provided from node N2.

[0129] The delay generator 120 generates a delayed trnOn signal based on the voltage conversion at node N2.

[0130] The replicating second switch gate driver 122 also includes a replicating first drive circuit 234 for driving the switching operation of the delay generator switch 230 and a replicating second drive circuit 236 for driving the switching operation of the delay generator switch 232.

[0131] During operation, the replicating first drive circuit 234 provides a gate drive signal gatP to drive the switching operation of the delay generator switch 230. The gate drive signal gatP depends on the control signal go1 and the indicator signal R-I2.

[0132] During operation, the replicating second drive circuit 236 provides a gate drive signal gatN to drive the switching operation of the delay generator switch 232. The gate drive signal gatN depends on the control signal go1 and the indicator signal R-I1.

[0133] Indicator signal R-I1 indicates when the replication first drive circuit 234 controls the delay generator switch 230 to be in the off state. Indicator signal R-I2 indicates when the replication second drive circuit 236 controls the delay generator switch 232 to be in the off state.

[0134] The indicator signals R-I1 and R-I2 can be non-overlapping signals that also exist within the gate drivers 108 and 118. In the case of high-power switching, it is preferable that the last stage of the gate driver also operates without overlap.

[0135] It can be observed that Figure 2D The specific implementation of the replicating second switch gate driver 122 and Figure 2C The second switch gate driver 118 shares a substantially similar circuit design, such that the duplicated second switch gate driver 122 is used as a "copy" of the second switch gate driver 118.

[0136] The replication first driving circuit 234 in this embodiment includes NAND gate 238 and inverter circuits 240 and 242. The replication second driving circuit 236 in this embodiment includes NAND gate 244 and inverter circuit 246.

[0137] The replication first drive circuit 234 is configured to receive the replication control signal goReplica, and the gate drive signal gatP depends on the replication control signal goReplica and the indicator signal R_I2.

[0138] The replication second drive circuit 236 is configured to receive the replication control signal goReplica_n, and the gate drive signal gatN depends on the replication control signal goReplica_n and the indicator signal R-I1.

[0139] The delay generator switch 220 is configured to receive the replication control signal goReplica (also labeled gateP4LOAD) at its gate terminal.

[0140] The delay generator switch 220 can be driven by fewer inverter stages compared to the delay generator switch 222.

[0141] The replicating second gate driver 122 also includes a programmable delay circuit 248 configured to receive an indicator signal R-I1 and apply a delay parameter to it. The programmable delay circuit 248 is also configured to provide the indicator signal R-I1 after the delay parameter has been applied to the replicating second drive circuit 236, the gate drive signal gatN depending on the control signal go1 and the indicator signal R-I1 after the delay parameter is applied. The delay parameter can be set by a configuration signal cfg1, which can be provided, for example, by the user to calibrate the operation of the delay generator 120.

[0142] In cases where the gate driver circuit 100 has other blocks such as logic gates that generate additional delays, the delay generator 120 preferably compensates for the delay in the turn-off path minus the delay in the turn-on path. Timing mismatch between the edges of the go signals of the two switches 104, 106 can be compensated by logic units that match the logic units that generate the go signals at the inputs of the two power switch blocks on the high and low sides, and are provided by using replicated gate drivers 122, 128.

[0143] A more detailed study of the sub-blocks of this gate driver circuit 100 shows that the delay generator 120 preferably compensates for the following delay mismatch contributors:

[0144] Level shifter: Ddly_lvlsh = T_del_fall_lvlshLS - T_del_rise_lvlshHS

[0145] For level shifters, only the delay difference must be compensated. If a symmetrical level shifter delay can be achieved, then delay compensation is not required.

[0146] Gate driver: Ddly_gatDrv = T_del_off_drvLS - T_del_on_drvHS

[0147] For gate drivers, the turn-off delay ends when the gate voltage of the low-side switch is below its threshold, while the turn-on delay of the high-side switch ends when the (turn-on) threshold of the switch is reached.

[0148] For example, delay mismatch contributors can be compensated by using programmable delay circuit 248.

[0149] To compensate for unexpected delay variations, the configurability of the delay unit is provided by the configuration signal cfg1. For example, the range can be provided by two configuration bits.

[0150] In this embodiment of the delay generator 120, all logic gates are constructed using the same transistor types as the logic and driver levels in the main path. Preferably, devices of the minimum length are used whenever possible. In a particular embodiment, switches 104 and 106 preferably use devices of the minimum length.

[0151] In this embodiment, switch 104 is a 12V power transistor in the high-side portion of the inverter, which is turned on and off during operation by a permanent load current (applied by an inductor). Furthermore, a delay generator switch 220, which is a delay generator transistor corresponding to switch 104, is turned on using the load current supplied by P4LOAD. Switch 104 turns on just before delay generator switch 220 turns off because the gate of switch 104 is derived from a signal with fewer inverter stages, while the gate of delay generator switch 220 is derived from a signal with more inverter stages.

[0152] A specific embodiment of the delay generator 120 can be used to reduce the non-overlapping time between the turn-off of one switch (e.g., switch 106) coupled to a node and the turn-on of another switch (e.g., switch 104) coupled to the node. During operation, the delay generator 120 can effectively synchronize the edges of the "go signals" (i.e., control signals go1, go2) of the two switches. This can be achieved by using a simplified "copy" driver circuit to generate a delay that matches well with the turn-off delay in the corresponding gate driver circuit, which uses devices / circuit similar to the corresponding gate driver circuit.

[0153] In a particular embodiment, the delay provided by the delay generator 120 can be adjusted (e.g., reduced) to compensate for additional delay in the conduction path. For example, the adjustment of the delay can be controlled by a programmable delay circuit 248.

[0154] In summary, embodiments of the delay generator 120 can be used to predict the delay required to turn off the power switch and add a portion of that delay to the conduction path such that when another switch is turned off (or more precisely, when its gate voltage is below a threshold), the gate voltage reaches the threshold.

[0155] return Figure 2C In actual implementation, gate drivers 108 and 118 will use minimum length transistors with high width (e.g., 0.5 μm long) to make the driver strong enough.

[0156] A higher gate length will increase the gate capacitance, thus increasing losses and delay. Therefore, a gate driver n-MOS with a width w = 1000 μm and a length l = 0.5 μm can be used (e.g., for...). Figure 2C Gate driver switch 206 in the middle) and p-MOS with width w = 1500 μm (e.g., Figure 2C The gate driver switch 204 in the p-MOS transistor drives a power transistor (i.e., switch 106) with a width of 100 mm. P-MOS transistors are generally weaker than n-MOS transistors.

[0157] In summary, the w / l ratio of gate driver switch 206 is 2000; the w / l ratio of gate driver switch 204 is 3000; and the w / l ratio of switch 106 is 200,000.

[0158] Therefore, in this example, the ratio of the second switch driver transistors between switch 106 and gate driver switch 206 is 100, and the ratio of the second switch driver transistors between switch 106 and gate driver switch 204 is 67. These are the ratios of the final stage of gate driver 118 to power device 106.

[0159] return Figure 2D To generate the final stage of the inverter in the replica second switch gate driver 122 (which can be 1 / 1000 of gate driver 118), we can choose a w / l ratio of 1μm / 0.5μm for the n-MOS (delay generator switch 232) and a w / l ratio of 1.5μm / 0.5μm for the p-MOS (delay generator switch 230). We can then choose a replication through-device width of 100μm (node ​​N1 or delay generator switch 222). Delay generator switch 222 can be a replication of switch 106 and can be referred to as the "replica second switch".

[0160] In summary, the w / l ratio of delay generator switch 232 is 2; the w / l ratio of delay generator switch 230 is 3; and the w / l ratio of delay generator switch 222 is 200.

[0161] Therefore, in this example, the ratio of the replica second switch driver transistors between switches 222 and 232 is 100, and the ratio of the replica second switch driver transistors between switches 222 and 230 is 67.

[0162] Therefore, the two timings will be matched, or more precisely, the 1.0 μm wide n-MOS requires the same amount of time to discharge the gate of the 100 μm wide n-MOS in the replicated gate driver 122 as the 1000 μm wide n-MOS is used for the 100 mm wide n-MOS through the gate of the device.

[0163] Therefore, in both cases, the ratio of the second switch driver transistors and the ratio of the replicated second switch driver transistors are equal, such that the replicated second switch gate driver 122 can be used as a replica of the second switch gate driver 118.

[0164] Preferably, this relationship should be used for relationships based on Figure 2C All stages of the gate driver topology, and for which it should again have Figure 2C A replica gate driver of the topology. For example, we can select a factor of 3 between the inverter stages of driver device 206 (only n-MOS dimensions are provided in this example):

[0165] In a buffer circuit 216 that may include two inverters:

[0166] The width of transistor N1 is N1 = 33.33 μm.

[0167] The width of transistor N0 is N0 = 11.11 μm.

[0168] In AND circuit 218:

[0169] The width of transistor N1, N1 = 3.7 μm

[0170] The width of transistor N0 is N0 = 1.23 μm.

[0171] For replicated structures, the same level will have the following size:

[0172] Copying of buffer circuit 216:

[0173] The width of transistor N1, N1 = 0.33 μm,

[0174] The width of transistor N0, N0 = 0.11 μm,

[0175] Copying AND circuit 218:

[0176] The width of transistor N1, N1 = 0.037 μm

[0177] The width of transistor N0, N0 = 0.0123 μm.

[0178] It should be understood that manufacturing transistors with a width of only slightly more than 1 nm can be challenging. In such cases, longer or staggered devices can be used, or additional delays that may be introduced by the configurability of the replicas can be used to provide equivalent functionality.

[0179] Elements 214 and 212 can have similar scaling factors across levels. Therefore, in the example above, these scaling factors of 3, 67, and 100 determine the delays in power train and replication.

[0180] Figure 3 This is a schematic diagram of a specific implementation of the delay generator 120 according to the seventh embodiment of the present disclosure.

[0181] In this embodiment, the delay generator 120 does not have elements for compensating for the delta-delay in the level shifters 200, 202. The level shifters 200, 202 exhibit low delay variation even when the voltage between the quiet ground and the flying ground (here, LX) changes.

[0182] Figure 4 This is a schematic diagram of a specific implementation of the gate driver circuit 100 and the switch converter 102 according to the eighth embodiment of the present disclosure.

[0183] Gate driver circuit 100 includes a high-side power stage 400a, which may include a delay generator 120 and a first switching gate driver 108, such as Figure 2B As shown in the image.

[0184] Gate driver circuit 100 includes a low-side power stage 400b, which may include a delay generator 126 and a second switching gate driver 118, such as Figure 2B As shown in the image.

[0185] It should be understood that, in other embodiments, as understood by those skilled in the art, the switch converter can be implemented as a multilevel converter (e.g., comprising five power switches), wherein each switch is driven by a power stage having a delay generator according to any embodiment described herein, and is adapted for multilevel conversion.

[0186] The study was conducted in a simplified test bench with two switches and a capacitor "CFLY" representing the capacitor located between the two switches 104 and 106. Figure 4 A pair of switches, 104 and 106. Figure 4 This is a simplified schematic diagram of the test bench. Here, two clock generators 402a and 402b provide go signals go1 and go2 with opposite phases, where the edges are precisely aligned. Two voltage sources "V(C boot The same power supply voltage is provided. For both low-side and high-side switches, the input field is connected to the 0V ground potential "vss".

[0187] Figure 5 This is a schematic diagram of a specific implementation of the high-side power stage 400a according to the ninth embodiment of this disclosure.

[0188] It should be understood that the term "test bench" is well-known in electronic circuit design and is used to describe a simulation environment. As understood by those skilled in the art, the use of... Figure 5 The implementation shown uses actual and physically realizable circuit parameters, regarding Figure 4 The circuit diagram is used to perform the simulation.

[0189] Figure 6A It is used for non-overlapping functions Figure 4 The parameter table for the Monte Carlo simulation of the circuit. For example... Figure 4 The actual implementation of the circuit shown underwent 100 Monte Carlo simulations, during which process, mismatch, and parameter variations were performed. Variations in the following parameters were examined: input voltage, battery voltage, core / RTC power supply voltage, and temperature. The range covered is as follows: Figure 6A As shown.

[0190] Figure 6B yes Figure 4 The table shows the results of Monte Carlo simulations of the circuit, which includes delayed matching and non-overlapping times in the Monte Carlo simulation.

[0191] exist Figure 6BIn the diagram, the difference in delay ("D_dly") for the rising (" / ") and falling ("\") edges during the 100 runs described earlier is given. The incremental delay of the 1.5V go input in the first line is negligible. After the 1.5V to 5V level shifters (outputs "D_dly(goS0_5V\:goS1_5V / )" and "D_dly(goS1_5V\:goS0_5V / )" and after the high-voltage level shifter (output marked by number 600), the incremental delay is well below 0.5ns. Finally, the delay of the power gate driver matches well with the delay unit (output marked by number 602). The last line, indicating that S1 is on and S0 is on, indicates that the non-overlapping time is a fairly short percentage of the total time during the entire turn-off / turn-on process, approximately 1 / 3. Since the non-overlapping time never becomes 0, it appears that the configurable matching delay could be further reduced here.

[0192] It should be noted that in the table, "S0" represents the low-side switch 106 and "S1" represents the high-side switch 104.

[0193] Figure 6C yes Figure 4 The table below shows the results of the Monte Carlo simulation of the circuit, which includes absolute delays. Non-overlapping times are shown in rows 2 and 3.

[0194] It should be understood that in other embodiments, there may be more than two switches 104, 106, where non-overlapping conditions for more than two switches are desirable. For example, in some embodiments, there may be at least two switches in non-overlapping conditions plus a diode that provides an additional current path when the switches are on.

[0195] Embodiments of this disclosure provide a gate driver circuit that is easier to implement than known systems, requires less circuit area, and / or has reduced current consumption compared to known systems (e.g., no DC current and current consumption only during switching).

[0196] It should be understood that in other embodiments of this disclosure, all or only some of the signals may be inverted and low-active. For example, if switch 104 is a p-MOS, then G1 is 0 in the ON state. Alternatively, if the delay generators of GD2 and switch 106 are inverting blocks, then go2 may be replaced by a low-active go2_n (go2-not) signal.

[0197] It should be understood that the embodiments of this disclosure are primarily described with respect to switches implemented using MOS power FETs. However, in other embodiments, the switches can be implemented using different types of switches. For example, IGBTs can also be used in high-voltage / high-power applications. In other embodiments, GTOs and bipolar switches can be used to implement the switches.

[0198] The function of embodiments of this disclosure is to match the timing of the gate driver with a delay time introduced by the delay generator in a manner that the non-overlapping time is close to or slightly higher than zero.

[0199] Common reference numerals and variables among the figures indicate common features.

[0200] Various improvements and modifications can be made to the above content without departing from the scope of this disclosure.

[0201] This application also relates to the following:

[0202] Clause 1. A gate driver circuit for a switch converter, the switch converter including a first switch and a second switch, the gate driver circuit comprising:

[0203] The first switching gate driver is configured as follows:

[0204] Receive the first control signal;

[0205] Receive the first delayed signal; and

[0206] When both the first control signal and the first delay signal are in the first state, a first switch gate drive signal is provided to turn on the first switch.

[0207] The second gate switch driver is configured as follows:

[0208] Receive the second control signal; and

[0209] Provide a second switch gate drive signal to drive the switching operation of the second switch;

[0210] The first delay generator includes:

[0211] Copy the second switch gate driver; and

[0212] First delayed signal generator;

[0213] in:

[0214] The replicated second switch-gate driver is configured to provide a replicated second switch-gate drive signal to the first delayed signal generator, the replicated second switch-gate drive signal being dependent on the first control signal; and

[0215] The first delay signal generator is configured to generate the first delay signal, which depends on the replicated second switch gate drive signal.

[0216] Clause 2. The gate driver circuit according to Clause 1, wherein the second switch gate driver and the replicated second switch gate driver have substantially similar circuit topologies.

[0217] Clause 3. The gate driver circuit according to Clause 1, wherein:

[0218] The second switch gate driver includes one or more second-side transistors; and

[0219] The replicated second switch gate driver includes one or more replicated second-side transistors.

[0220] Clause 4. The gate driver circuit according to Clause 3, wherein:

[0221] The ratio of the second switch driver transistors is provided by the following:

[0222] The ratio between the transistor ratio of one of the one or more second-side transistors and the transistor ratio of another of the one or more second-side transistors; or

[0223] The ratio between the transistor ratio of the second switch and the transistor ratio of one of the one or more second-side transistors;

[0224] The ratio of the transistors in the second switch driver is provided by the following:

[0225] The ratio between the transistor ratio of one of the one or more replicated second-side transistors and the transistor ratio of another of the one or more replicated second-side transistors; or

[0226] The ratio between the transistor ratio of the replicated second switch and the transistor ratio of one of the one or more replicated second-side transistors; and

[0227] The ratio of the second switch driver transistors is approximately equal to the ratio of the replicated second switch driver transistors.

[0228] Clause 5. The gate driver circuit according to Clause 4, wherein:

[0229] The transistor ratio of one of the one or more second-side transistors is the width-to-length ratio of that one of the one or more second-side transistors;

[0230] The transistor ratio of another transistor in one or more second-side transistors is the width-to-length ratio of that other transistor in one or more second-side transistors;

[0231] The transistor ratio of the second switch is the width-to-length ratio of the second switch;

[0232] The transistor ratio of one of the one or more replicated second-side transistors is the width-to-length ratio of that one of the one or more replicated second-side transistors;

[0233] The transistor ratio of the other transistor in one or more replicated second-side transistors is the width-to-length ratio of that other transistor in one or more replicated second-side transistors; and

[0234] The transistor ratio of the replicated second switch is the width-to-length ratio of the replicated second switch.

[0235] Clause 6. The gate driver circuit according to Clause 1, wherein:

[0236] The second switch gate driver includes one or more second-side logic gates, and the replicated second switch gate driver includes one or more replicated second-side logic gates of the same type as the one or more second-side logic gates.

[0237] Clause 7. The gate driver circuit according to Clause 1, wherein:

[0238] The second switch gate driver is positioned close enough to the replicated second switch gate driver to withstand substantially similar operating temperatures during operation.

[0239] Clause 8. The gate driver circuit according to Clause 1, wherein the second switching gate driver comprises:

[0240] First gate driver switch;

[0241] A second gate driver switch is coupled to the first gate driver switch at a second gate driver output node, and the second gate driver signal is provided from the second gate driver output node;

[0242] A first driving circuit, used to drive the switching of the first gate driver switch; and

[0243] The second driving circuit is used to drive the switching of the second gate driver switch.

[0244] Clause 9. The gate driver circuit according to Clause 8, wherein:

[0245] The first driving circuit includes a first buffer circuit and a first NAND gate; and

[0246] The second driving circuit includes a second buffer circuit and a third buffer circuit or an AND circuit.

[0247] Clause 10. The gate driver circuit according to Clause 8, wherein the replicated second switch gate driver comprises:

[0248] First delay generator switch;

[0249] A second delay generator switch is coupled to the first delay generator switch at the output node of the replica second switch gate driver, and the replica second switch gate drive signal is provided from the output node of the replica second switch gate driver;

[0250] The first driving circuit is replicated, which is used to drive the switching operation of the first delay generator switch; and

[0251] A second driving circuit is replicated, which is used to drive the switching operation of the second delay generator switch.

[0252] Clause 11. The gate driver circuit according to Clause 10, wherein:

[0253] The replication first driving circuit includes:

[0254] Second NAND gate;

[0255] First inverter circuit; and

[0256] Second inverter circuit,

[0257] The replication second driving circuit includes:

[0258] The third NAND gate; and

[0259] Third inverter circuit.

[0260] Clause 12. The gate driver circuit according to Clause 10 further includes a programmable delay circuit, said programmable delay circuit being configured to:

[0261] Receives a first delay generator switch indicator signal from the first drive circuit;

[0262] Apply the delay parameter to the first delay generator switch indicator signal; and

[0263] After the delay parameter has been applied, the first delay generator switch indicator signal is provided to the replicating second drive circuit;

[0264] The replicating second drive circuit is configured to provide a delayed gate drive signal to the second delay generator switch after the delay parameter has been applied, the delayed gate drive signal depending on the first control signal and the first delay generator switch indicator signal.

[0265] Clause 13. The gate driver circuit according to Clause 12, wherein the programmable delay circuit is configured to receive a configuration signal, the delay parameter depending on the configuration signal.

[0266] Clause 14. The gate driver circuit according to Clause 13 further includes:

[0267] A first level shifter, configured to level shift the first control signal; and

[0268] A second level shifter is configured to provide the configuration signal to the first delay generator to correct the switching delay generated by the first level shifter.

[0269] Clause 15. The gate driver circuit according to Clause 10, wherein the first delay signal generator comprises:

[0270] Third delay generator switch;

[0271] A fourth delay generator switch, coupled to the third delay generator switch at a first node, the fourth delay generator switch including a fourth delay generator switch gate terminal coupled to the output node of the replicated second switch gate driver; and

[0272] The delay signal generator buffer circuit includes:

[0273] Coupled to the first input terminal of the first node; and

[0274] A first output terminal is used to provide the first delayed signal.

[0275] Clause 16. The gate driver circuit according to Clause 15, wherein the third delay generator switch is driven by fewer inverter stages than the fourth delay generator switch.

[0276] Clause 17. The gate driver circuit according to Clause 15, wherein the first switch and the fourth delay generator switch have one or more of the following:

[0277] Same transistor type; and / or

[0278] Approximately equal transistor widths and / or lengths.

[0279] Clause 18. The gate driver circuit according to Clause 15 further includes:

[0280] A fourth buffer circuit is configured to receive the first control signal and provide a first replication control signal; and

[0281] A fourth inverter circuit is configured to receive the first copy control signal and provide a second copy control signal;

[0282] in:

[0283] The replication first drive circuit is configured to receive the second replication control signal and drive the switching operation of the first delay generator switch based on the second replication control signal and the second delay generator switch indicator signal.

[0284] Clause 19. The gate driver circuit according to Clause 18, wherein the third delay generator switch includes a third delay generator switch gate terminal configured to receive the second replication control signal.

[0285] Clause 20. The gate driver circuit according to Clause 1, wherein the first state is an ON state.

[0286] Clause 21. The gate driver circuit according to Clause 1, wherein:

[0287] The first switch is a high-side switch and the second switch is a low-side switch; and / or

[0288] The first switch is a low-side switch and the second switch is a high-side switch.

[0289] Clause 22. The gate driver circuit according to Clause 1, wherein:

[0290] The second switch gate driver is configured as follows:

[0291] Receive the second delayed signal; and

[0292] When both the second control signal and the second delay signal are in the first state or the second state, the second switch gate drive signal is provided to turn on the second switch;

[0293] The gate driver circuit includes:

[0294] The second delay generator includes:

[0295] Copy the first switch gate driver; and

[0296] Second delayed signal generator; wherein:

[0297] The replicating first switch-gate driver is configured to provide a replicating first switch-gate drive signal to the second delayed signal generator, the replicating first switch-gate drive signal being dependent on the second control signal; and

[0298] The second delay signal generator is configured to generate a second delay signal that depends on the replicated first switch gate drive signal.

[0299] Clause 23. A method of providing a gate driver circuit for a switch converter, the switch converter including a first switch and a second switch, the gate driver circuit comprising:

[0300] The first switching gate driver is configured as follows:

[0301] Receive the first control signal;

[0302] Receive the first delayed signal; and

[0303] When both the first control signal and the first delay signal are in the first state, a first switch gate drive signal is provided to turn on the first switch.

[0304] The second gate switch driver is configured as follows:

[0305] Receive the second control signal; and

[0306] Provide a second switch gate drive signal to drive the switching operation of the second switch;

[0307] The first delay generator includes:

[0308] Copy the second switch gate driver; and

[0309] First delayed signal generator;

[0310] in:

[0311] The replicated second switch-gate driver is configured to provide a replicated second switch-gate drive signal to the first delayed signal generator, the replicated second switch-gate drive signal being dependent on the first control signal; and

[0312] The first delay signal generator is configured to generate the first delay signal, which depends on the replicated second switch gate drive signal.

Claims

1. A gate driver circuit for a switch converter, the switch converter including a first switch and a second switch, the gate driver circuit comprising: The first switching gate driver is configured as follows: Receive the first control signal; Receive the first delayed signal; and When both the first control signal and the first delay signal are in the first state, a first switch gate drive signal is provided to turn on the first switch. The second gate switch driver is configured as follows: Receive the second control signal; and Provide a second switch gate drive signal to drive the switching operation of the second switch; The first delay generator includes: Copy the second switch gate driver; and First delayed signal generator; in: The replicated second switch-gate driver is configured to provide a replicated second switch-gate drive signal to the first delayed signal generator, the replicated second switch-gate drive signal being dependent on the first control signal; and The first delay signal generator is configured to generate the first delay signal, which depends on the replicated second switch gate drive signal.

2. The gate driver circuit according to claim 1, wherein, The second switch gate driver and the replicated second switch gate driver have substantially similar circuit topologies.

3. The gate driver circuit according to claim 1, wherein: The second switch gate driver includes one or more second-side transistors; and The replicated second switch gate driver includes one or more replicated second-side transistors.

4. The gate driver circuit according to claim 3, wherein: The ratio of the second switch driver transistors is provided by the following: The ratio between the transistor ratio of one of the one or more second-side transistors and the transistor ratio of another of the one or more second-side transistors; or The ratio between the transistor ratio of the second switch and the transistor ratio of one of the one or more second-side transistors; The ratio of the transistors in the second switch driver is provided by the following: The ratio between the transistor ratio of one of the one or more replicated second-side transistors and the transistor ratio of the other of the one or more replicated second-side transistors; or The ratio between the transistor ratio of the replica second switch and the transistor ratio of one of the one or more replica second-side transistors; and The ratio of the second switch driver transistors is approximately equal to the ratio of the replicated second switch driver transistors.

5. The gate driver circuit according to claim 4, wherein: The transistor ratio of one of the one or more second-side transistors is the width-to-length ratio of that one of the one or more second-side transistors; The transistor ratio of another transistor in one or more second-side transistors is the width-to-length ratio of that other transistor in one or more second-side transistors; The transistor ratio of the second switch is the width-to-length ratio of the second switch; The transistor ratio of one of the one or more replicated second-side transistors is the width-to-length ratio of that one of the one or more replicated second-side transistors; The transistor ratio of the other transistor in one or more replicated second-side transistors is the width-to-length ratio of the other transistor in one or more replicated second-side transistors; and The transistor ratio of the replicated second switch is the width-to-length ratio of the replicated second switch.

6. The gate driver circuit according to claim 1, wherein: The second switch gate driver includes one or more second-side logic gates, and the replicated second switch gate driver includes one or more replicated second-side logic gates of the same type as the one or more second-side logic gates.

7. The gate driver circuit according to claim 1, wherein: The second switch gate driver is positioned close enough to the replicated second switch gate driver to withstand substantially similar operating temperatures during operation.

8. The gate driver circuit according to any one of claims 1 to 7, wherein, The second switch gate driver includes: First gate driver switch; A second gate driver switch is coupled to the first gate driver switch at a second gate driver output node, and the second gate driver signal is provided from the second gate driver output node; A first driving circuit, used to drive the switching of the first gate driver switch; and The second driving circuit is used to drive the switching of the second gate driver switch.

9. The gate driver circuit according to claim 8, wherein, The replicated second switch gate driver includes: First delay generator switch; A second delay generator switch is coupled to the first delay generator switch at the output node of the replica second switch gate driver, and the replica second switch gate drive signal is provided from the output node of the replica second switch gate driver; The first driving circuit is replicated, which is used to drive the switching operation of the first delay generator switch; and A second driving circuit is replicated, which is used to drive the switching operation of the second delay generator switch.

10. The gate driver circuit of claim 9, further comprising a programmable delay circuit, the programmable delay circuit being configured to: Receives a first delay generator switch indicator signal from the first drive circuit; Apply the delay parameter to the first delay generator switch indicator signal; and After the delay parameter has been applied, the first delay generator switch indicator signal is provided to the replicating second drive circuit; in, The replicating second drive circuit is configured to provide a delayed gate drive signal to the second delay generator switch after the delay parameter has been applied, the delayed gate drive signal depending on the first control signal and the first delay generator switch indicator signal.

11. The gate driver circuit according to claim 9, wherein, The first delay signal generator includes: Third delay generator switch; A fourth delay generator switch, coupled to the third delay generator switch at a first node, the fourth delay generator switch including a fourth delay generator switch gate terminal coupled to the output node of the replicated second switch gate driver; and The delay signal generator buffer circuit includes: Coupled to the first input terminal of the first node; and A first output terminal is used to provide the first delayed signal.

12. The gate driver circuit according to claim 11, wherein, The third delay generator switch is driven by fewer inverter stages compared to the fourth delay generator switch.

13. The gate driver circuit according to claim 11, wherein, The first switch and the fourth delay generator switch have one or more of the following: Same transistor type; and / or Approximately equal transistor widths and / or lengths.

14. The gate driver circuit of claim 11, further comprising: A fourth buffer circuit is configured to receive the first control signal and provide a first copy control signal; and A fourth inverter circuit is configured to receive the first copy control signal and provide a second copy control signal; in: The replication first drive circuit is configured to receive the second replication control signal and drive the switching operation of the first delay generator switch based on the second replication control signal and the second delay generator switch indicator signal.

15. The gate driver circuit according to claim 14, wherein, The third delay generator switch includes a third delay generator switch gate terminal, which is configured to receive the second replication control signal.

16. The gate driver circuit according to claim 1, wherein: The second switch gate driver is configured as follows: Receive the second delayed signal; and When both the second control signal and the second delay signal are in the first state or the second state, the second switch gate drive signal is provided to turn on the second switch; The gate driver circuit includes: The second delay generator includes: Copy the first switch gate driver; and Second delayed signal generator; wherein: The replicating first switch-gate driver is configured to provide a replicating first switch-gate drive signal to the second delayed signal generator, the replicating first switch-gate drive signal being dependent on the second control signal; and The second delay signal generator is configured to generate a second delay signal that depends on the replicated first switch gate drive signal.

17. A method of providing a gate driver circuit for a switch converter, the switch converter including a first switch and a second switch, the gate driver circuit including: The first switching gate driver is configured as follows: Receive the first control signal; Receive the first delayed signal; and When both the first control signal and the first delay signal are in the first state, a first switch gate drive signal is provided to turn on the first switch. The second gate switch driver is configured as follows: Receive the second control signal; and Provide a second switch gate drive signal to drive the switching operation of the second switch; The first delay generator includes: Copy the second switch gate driver; and First delayed signal generator; in: The replicated second switch-gate driver is configured to provide a replicated second switch-gate drive signal to the first delayed signal generator, the replicated second switch-gate drive signal being dependent on the first control signal; and The first delay signal generator is configured to generate the first delay signal, which depends on the replicated second switch gate drive signal.

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