Analog signal sampling switch circuit

Abstract

This application relates to the field of integrated circuit technology and discloses an analog signal sampling switch circuit, including: a driving circuit and a switching circuit connected to the driving circuit; wherein, the switching circuit is used to turn on or off an input electrical signal; the input terminal of the driving circuit is connected to the state feedback terminal of the switching circuit, and the output terminal of the driving circuit is connected to the control terminal of the switching circuit; the driving circuit is used to output a driving voltage that follows the potential change of the state feedback terminal to the control terminal of the switching circuit when the switching circuit is turned on, so as to maintain the voltage difference between the control terminal and the state feedback terminal. Through this analog signal sampling switch circuit, tracking of the input electrical signal in the continuous time domain is achieved without the need for clock control and a large-capacity sampling capacitor.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an analog signal sampling switch circuit. Background Technology

[0002] In the fields of modern biomedical engineering and precision instruments, weak signal detection technology is the core of devices such as brain-computer interfaces. In analog front-end design, the switching circuit undertakes key responsibilities such as signal input, multiplexing, and stimulation artifact shielding. Because the system needs to accommodate both high-voltage electrical stimulation and weak bioelectrical acquisition, the front-end switch must be able to withstand high transient pulses and achieve extremely high linearity transmission of small signals in the continuous time domain when in the on state.

[0003] However, when processing signals over a wide common-mode range, the drain-source on-resistance of traditional analog switches fluctuates drastically with the input level, introducing harmonic distortion and gain error. To address this issue, related technologies often employ capacitive bootstrap switching to maintain a constant gate-source voltage. However, this technology is essentially a clock-driven discrete-time sampling circuit and cannot be directly used for continuous-time signal processing at the front end. This is because the inherent clock feedthrough and charge injection effects of the bootstrap circuit during clock switching generate significant transient switching noise; simultaneously, the folding noise caused by its discrete sampling directly overwhelms the unamplified weak neural signals, making high-fidelity lossless transmission impossible. Summary of the Invention

[0004] The purpose of this application is to provide an analog signal sampling switch circuit that enables accurate tracking of the input electrical signal in the continuous time domain without the need for clock control and a large-capacity sampling capacitor.

[0005] To address the aforementioned technical problems, this application provides an analog signal sampling switch circuit, comprising: a driving circuit and a switch circuit connected to the driving circuit; wherein, the switch circuit is used to turn on or off an input electrical signal; the input terminal of the driving circuit is connected to the state feedback terminal of the switch circuit, and the output terminal of the driving circuit is connected to the control terminal of the switch circuit; the driving circuit is used to output a driving voltage that follows the potential change of the state feedback terminal to the control terminal of the switch circuit when the switch circuit is turned on, so as to maintain the voltage difference between the control terminal and the state feedback terminal.

[0006] Compared to related technologies, this application addresses the problems of harmonic distortion and gain error caused by drastic fluctuations in on-resistance of traditional analog switches over a wide common-mode range, and the contamination of weak signals by clock feedthrough, charge injection, and folding noise introduced by clock-driven capacitor bootstrap switches. Based on a pure analog feedback drive architecture that does not require clock control, this application enables the drive circuit to sense the potential of the state feedback terminal of the switch circuit in real time when the switch circuit is in the on state, and outputs a drive voltage that follows the change of the potential to the control terminal of the switch circuit in real time. This maintains a constant voltage difference between the control terminal and the state feedback terminal, thus solving the problems of nonlinear fluctuations in on-resistance with common-mode level and modulation by transient switching noise during the transmission of continuous-time signals. It achieves constant on-resistance and extremely high transconductance linearity, eliminates clock noise contamination, and ensures lossless and high-fidelity transmission of weak bioelectrical signals in the continuous-time domain. Attached Figure Description

[0007] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0008] Figure 1 This is a schematic diagram of the structure of an analog signal sampling switch circuit provided according to some embodiments of this application; Figure 2 This is a schematic diagram of the structure of an N-type analog signal sampling switch circuit according to some embodiments of this application; Figure 3 This is a schematic diagram of the structure of a P-type analog signal sampling switch circuit according to some embodiments of this application; Figure 4 This is a schematic diagram of the structure of a complementary analog signal sampling switch circuit according to some embodiments of this application. Detailed Implementation

[0009] To more clearly illustrate the technical solutions of the embodiments in this specification, the embodiments will be described in detail below with reference to the accompanying drawings. Obviously, the content described below are some examples or embodiments of this specification. For those skilled in the art, without creative effort, the technical solutions or means disclosed in this specification can be applied to other scenarios based on this technical content.

[0010] It should be understood that the terms "system," "device," "unit," and / or "module" used in this specification are a method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other words can achieve the same purpose, they may be replaced by other expressions.

[0011] Unless otherwise specified, the technical terms used to describe components, elements, etc. in this specification are not singular but may include plural. Generally speaking, terms such as "comprising" or "including" only indicate that explicitly identified steps, elements, or components are included, and these steps, elements, and components do not constitute an exclusive list, as the described method or apparatus may also include other steps or components.

[0012] This specification uses flowcharts to illustrate the operational steps performed by the apparatus or system of related embodiments. However, unless otherwise specified, the order in which these steps are described should not be construed as a limitation on the order of execution. Those skilled in the art can adjust the order of these steps based on the knowledge and information conveyed by the embodiments in this specification. Adjustments include, but are not limited to, reversing the order of steps, merging multiple steps, and splitting a step.

[0013] In the fields of modern biomedical engineering and precision instruments, weak signal detection technology has become the core of life science research and clinical medical devices (such as brain-computer interfaces and implantable neurostimulators). For such high-precision sensor terminals, the ability to stably and linearly transmit neural electrical activity at the microvolt to millivolt level directly determines the accuracy of subsequent signal processing and feature extraction. In the analog front-end design of such devices, the switching circuit undertakes key responsibilities such as signal access control, multiplexing, and stimulation artifact shielding. Since neural interfaces often need to accommodate both high-voltage electrical stimulation and weak bioelectrical acquisition, the front-end switch must be able to withstand high transient electrical stimulation pulses while achieving extremely high linearity transmission of small signals in the continuous time domain when in the on state.

[0014] However, traditional analog switches face severe performance bottlenecks when processing input electrical signals with a wide common-mode range. Their drain-source on-resistance fluctuates drastically with the input signal level, introducing harmonic distortion and gain error, thus masking the true bioelectrical characteristics. To address the nonlinearity of the on-resistance, traditional analog-to-digital converter (ADC) designs typically employ capacitive bootstrap switching technology to maintain a constant gate-source voltage in the switching transistor. However, bootstrap switches are essentially clock-driven discrete-time sampling circuits and cannot be directly applied to continuous-time signal processing at the front end. On one hand, the inherent clock feedthrough and charge injection effects of bootstrap circuits during clock switching generate significant transient switching noise; on the other hand, the folding noise caused by discrete sampling directly drowns out the unamplified weak neural electrical signals.

[0015] Therefore, advanced neural interface systems urgently require a high-performance analog switch specifically designed for the continuous-time domain. This switch must be free from dependence on clock sampling mechanisms to achieve high linearity and constant on-resistance comparable to an ADC bootstrap switch, while avoiding any clock-related switching noise injection. Only a continuous-time switch with these characteristics can truly ensure the lossless and high-fidelity extraction of weak biological signals by highly integrated and portable neural interface devices in complex electrical stimulation environments.

[0016] This application provides a continuous-time analog signal sampling switch circuit for use in high-voltage environments, aiming to solve the distortion problem of traditional analog switches and commonly used capacitive bootstrap switches in analog-to-digital converters (ADCs) when processing weak bioelectrical signals. Addressing the shortcomings of capacitive bootstrap switches, such as clock-driven operation, clock feedthrough and charge injection effects, and folding noise caused by discrete sampling, this invention achieves accurate tracking of the input electrical signal in the continuous-time domain through a purely analog-driven architecture, without the need for clock control or a large-capacity sampling capacitor. This design maintains extremely high transconductance and constant on-resistance, adapting to the stringent requirements of lossless, high-fidelity transmission of weak signals in precision analog front-ends such as neural interfaces, ensuring the accuracy of subsequent signal processing and feature extraction.

[0017] In some embodiments, such as Figure 1 As shown, this embodiment provides a high-performance, low-noise analog signal sampling switch circuit, which mainly consists of a switch circuit and a drive circuit connected together. The switch circuit is used to turn on or off the input electrical signal. The input terminal of the drive circuit is connected to the state feedback terminal of the switch circuit, and the output terminal of the drive circuit is connected to the control terminal of the switch circuit.

[0018] In this embodiment, when the switching circuit is in the ON state, the driving circuit can sense the potential changes inside the switching circuit in real time through the state feedback terminal of the switching circuit, and output a dynamically floating driving voltage to the control terminal of the switching circuit accordingly. This driving voltage does not depend on any clock control signal, but rather uses a purely analog feedback following mechanism to ensure that its changing trend is completely synchronized with the potential of the state feedback terminal. Therefore, regardless of how large the common-mode voltage of the input electrical signal fluctuates, the voltage difference between the control terminal and the state feedback terminal is locked at a constant value, thereby ensuring that the switching circuit has extremely constant on-resistance and extremely high transconductance throughout the entire signal transmission cycle.

[0019] In some embodiments, the switching circuit includes a first switching transistor and a second switching transistor; wherein the source of the first switching transistor is connected to the source of the second switching transistor as a state feedback terminal; the gate of the first switching transistor is connected to the gate of the second switching transistor as a control terminal; the drain of the first switching transistor is used to receive the input electrical signal, and the drain of the second switching transistor is used to output an output signal corresponding to the electrical signal. In this embodiment, both the first and second switching transistors are MOSFETs, and the switching circuit is constructed in a common-source back-to-back connection. The sources of the first and second switching transistors are interconnected to form a common node, which serves as the state feedback terminal connected to the input terminal of the driving circuit, allowing the driving circuit to acquire the switching source potential in real time; the gates of the first and second switching transistors are interconnected to form a unified control terminal, receiving the driving voltage output by the driving circuit; the drains of the first and second switching transistors are respectively set as signal input and output ports, completing the construction of the analog signal transmission path.

[0020] This switching circuit can be flexibly configured according to polarity requirements, such as Figure 2 The structure shown is an N-type analog signal sampling switch circuit, as follows: Figure 3 The diagram shows the structure of a P-type analog signal sampling switch circuit. Specifically, this switch circuit adopts a bidirectional back-to-back power transistor topology, including a first switch and a second switch. The first switch... The source and the second switch The source nodes are connected, and this common source node serves as the state feedback terminal, for example in... Figure 2 The N-type switch shown is an internal node. , or as Figure 3 The P-type switch shown is an internal node. First switching transistor The gate and the second switch The gates of the transistors are connected, and this common gate node serves as the control terminal. First switching transistor. The drain of the circuit serves as the signal input terminal to receive the input electrical signal. Second switching transistor The drain is used as the signal output terminal to output a high-fidelity electrical signal. .

[0021] Because a parasitic body diode forms between the substrate and the source / drain of a MOS transistor, the parasitic diode of a single MOS transistor can only conduct in one direction. In this application, the sources of the first and second switching transistors are connected together, and the parasitic body diodes of the two transistors are arranged with opposite polarities and back-to-back in reverse orientation. If a high-voltage stimulus pulse is applied to the input terminal, the parasitic diode closer to the input side is reverse-biased and cut off; if a high voltage is introduced to the output terminal, the parasitic diode on the output side is reverse-biased and cut off. Regardless of whether the high voltage enters from the input or output direction, there is always one body diode in a reverse-biased blocking state, and the high-voltage charge cannot penetrate the switch to flow to the subsequent circuit, thus achieving a bidirectional high-voltage blocking function.

[0022] In some embodiments, the driving circuit includes an open-loop differential amplifier, a load resistor, and a first controlled current source; wherein, the input terminal of the open-loop differential amplifier is connected to a state feedback terminal; one end of the first controlled current source is connected to a control terminal, and the other end of the first controlled current source is connected to a first reference potential terminal; one end of the load resistor is connected to the control terminal and one end of the first controlled current source, and the other end of the load resistor is connected to the output terminal of the open-loop differential amplifier, and the first controlled current source generates a driving voltage at the control terminal via the load resistor.

[0023] Specifically, this driving circuit is a current-type level shifting driving circuit, consisting of an open-loop differential amplifier, a load resistor, and a first controlled current source. The signal input of the open-loop differential amplifier is directly connected to the state feedback terminal of the switching circuit, continuously acquiring the common source potential of the switching transistor. One end of the first controlled current source is connected to the control terminal of the switching circuit, and the other end is connected to a first reference potential terminal (which can be either a power supply terminal or a ground terminal, flexibly selected according to the type of MOSFET). The load resistor is connected between the switch control terminal and the output of the open-loop differential amplifier. The fixed bias current output by the first controlled current source flows through the load resistor, generating a stable voltage drop. Combined with the potential matching effect of the open-loop differential amplifier, this ultimately outputs a driving voltage at the control terminal that floats synchronously with the feedback terminal potential.

[0024] In some embodiments, the open-loop differential amplifier includes a first input transistor, a second input transistor, and a second controlled current source; wherein the source of the first input transistor is connected to the source of the second input transistor and to one end of the second controlled current source, and the other end of the second controlled current source is connected to a second reference potential terminal; the gate of the first input transistor is connected to the state feedback terminal; the drain and gate of the second input transistor are shorted, and the drain of the second input transistor is connected to the other end of the load resistor.

[0025] Specifically, the gate of the first input transistor is directly connected to the switch state feedback terminal to sense the source potential change in real time; the second input transistor adopts a diode connection structure with the gate and drain shorted, and the drain terminal of the second input transistor is connected to the side of the load resistor away from the control terminal; the sources of the first and second input transistors are shorted and then connected to one end of the second controlled current source, and the other end of the second controlled current source is connected to the second reference potential terminal (the second reference potential terminal is either the power supply terminal or the ground terminal, which can be flexibly selected according to the type of MOSFET); the tail current output by the second controlled current source is twice the bias current output by the first controlled current source. This parameter design ensures the differential branch current matching, accurately locks the voltage drop value on the load resistor, and achieves a constant gate-source voltage difference.

[0026] In this application, the analog signal sampling switch circuit can be flexibly configured according to polarity requirements, such as... Figure 2 The N-type analog signal sampling switch circuit shown is as follows: Figure 3 The P-type analog signal sampling switch circuit shown, or as... Figure 4 The complementary analog signal sampling switch circuit shown achieves full-rail-to-rail input common-mode range without sacrificing linearity.

[0027] The first part uses an N-type analog signal sampling switch circuit as an example. Subsequent sections will use P-type analog signal sampling switch circuits and complementary analog signal sampling switch circuits as examples.

[0028] In some embodiments, such as Figure 2 As shown, when the analog signal sampling switch circuit is an N-type analog signal sampling switch circuit, the first switching transistor in its switching circuit... Second switching transistor When all transistors are N-channel enhancement-mode insulated-gate field-effect transistors, the drive circuit connected to the switching circuit is a continuous-time level-shift drive circuit. The drive circuit includes an open-loop differential amplifier and a load resistor. and the first controlled current source At this time, the first reference potential terminal is the external power supply, and the second reference potential terminal is the ground terminal.

[0029] The non-inverting input terminal (i.e., the first input transistor) of the open-loop differential amplifier The gate is connected to the state feedback terminal. (i.e., the first switching transistor) Second switching transistor (A common source node) enables real-time sampling and dynamic tracking of the source potential in the continuous time domain. First controlled current source One end is connected to the control terminal (i.e., the first switching transistor). Second switching transistor One end is connected to the common gate point, and the other end is connected to the external power supply AVDD. Load resistor The first controlled current source is connected in series between the control terminal and the output of the open-loop differential amplifier. The provided bias current flows entirely through the load resistor. Thus, in the load resistance A controlled static voltage drop is generated. .

[0030] Furthermore, the first input transistor of the open-loop differential amplifier Second input tube All are N-channel enhancement-mode insulated-gate field-effect transistors. This open-loop differential amplifier also includes a second controlled current source (i.e., a controlled current source providing the tail current, with a current magnitude of...). First input tube Second input tube The source terminals of the two transistors are interconnected and connected to the second controlled current source, the other end of which is grounded. (Second input transistor) The drain and gate of the transistor are shorted to form a diode connection structure, and the second input transistor... The drain and the load resistor The lower end is connected to serve as the amplifier's output. To maintain the perfect symmetry of the differential pair, the driver circuit also includes a matching resistor. It is located in the first input tube The matching resistor is located between the drain and the external power supply AVDD. One end is connected to the first input tube One end is the drain, and the other end is connected to the external power supply AVDD.

[0031] like Figure 2 As shown, since the total tail current provided by the second controlled current source is Under balanced conduction steady state, the tail current will be evenly shared between the left and right branches of the open-loop differential amplifier, i.e., flowing through the second input transistor. The current is accurate to At this time, the current supplied by the first controlled current source at the top... It was completely injected into the right branch and flowed through it. Due to the first input tube With the second input tube The dimensions are perfectly matched and the same current flows through them. According to the formula for the saturation current of a MOSFET, their gate-source voltage difference... They must be equal. Because of the first input transistor... The gate potential is forcibly locked at the switch feedback terminal potential. Utilizing the voltage follower characteristic of a differential amplifier, the second input transistor is connected to a diode. The gate (and drain) potentials will also follow and match. Therefore, the final potential of the control terminals (the gates of M1 and M2) will be raised to: .

[0032] Therefore, the voltage difference between the control terminal and the state feedback terminal (i.e., the gate-source voltage difference between the first and second switching transistors) depends only on the static voltage drop of the bias current across the resistor. This voltage difference remains completely unaffected by changes in the input common-mode signal, successfully achieving a constant on-resistance in the continuous time domain. The circuit performs particularly well at high input common-mode levels.

[0033] Unlike the common capacitor bootstrap switches in analog-to-digital converters (ADCs) that rely on a clock signal to switch charges in discrete time intervals, this invention uses a first current source at the top. With load resistance The collaborative work generates a random element in the right branch. Linear floating gate drive voltage This circuit is more suitable for use when the common-mode value is relatively high. Since the voltage drop of VGS depends only on the static voltage drop of the bias current across the resistor, this circuit avoids the charge injection and clock feedthrough effects caused by the clock signal, ensuring that the weak continuous-time signal is not modulated by sampling switch noise during transmission, thereby maintaining extremely high transconductance.

[0034] The second part uses a P-type analog signal sampling switch circuit as an example.

[0035] In some embodiments, such as Figure 3 As shown, when the analog signal sampling switch circuit is a P-type analog signal sampling switch circuit, the first switching transistor in its switching circuit... Second switching transistor When all transistors are P-channel enhancement-mode insulated-gate field-effect transistors (PMOS transistors), the drive circuit connected to the switching circuit is a continuous-time level-shift drive circuit. The drive circuit includes an open-loop differential amplifier and a load resistor. and the first controlled current source At this time, the first reference potential terminal is grounded, and the second reference potential terminal is an external power source.

[0036] The drive circuit is designed with polarity reversal based on the physical characteristics of the PMOS transistor. Specifically: the first input transistor of the open-loop differential amplifier... Second input tube All were replaced with P-channel enhancement-mode insulated-gate field-effect transistors (PMOS transistors). At this time, the first controlled current source... One end is connected to the control terminal, and the other end is directly grounded (GND). The second controlled current source (tail current source) has a magnitude of... One end of it is connected to the power supply AVDD, and the other end is connected to the first input transistor. Second input tube The common source. Matching resistor used to balance symmetry. One end is connected to the first input tube One end is the drain, and the other end is grounded.

[0037] In this structure, the load resistance Located at the high position, its upper end is connected to the second input transistor connected to the diode. The drain of the transistor is uniform, and its lower end is connected to the control terminal of the switching circuit. The drive circuit is connected through the first input transistor. The state feedback terminal of the gate real-time sensing switch circuit Potential change, and at the load resistance A constant voltage drop is generated at the control terminal (i.e., the first switching transistor). Second switching transistor The potential of the common gate point is locked as: .

[0038] This solution also eliminates the need for large-area sampling capacitors, avoiding clock noise and the load effect of capacitors on weak front-end signals, making it more suitable for use when the common-mode value is relatively low.

[0039] In the third part, to achieve full rail-to-rail input common-mode range without sacrificing linearity, this embodiment provides a complementary full rail-to-rail high-voltage analog switching circuit. This section will use a complementary analog signal sampling switching circuit as an example for explanation.

[0040] In some embodiments, the switching circuit further includes a third switching transistor and a fourth switching transistor; wherein the source of the third switching transistor is connected to the source of the fourth switching transistor to serve as a second state feedback terminal; the gate of the third switching transistor is connected to the gate of the fourth switching transistor to serve as a second control terminal; the drain of the third switching transistor is connected to the drain of the first switching transistor to receive an input electrical signal, and the drain of the fourth switching transistor is connected to the drain of the second switching transistor to receive an output signal. The driving circuit includes a first driving sub-circuit and a second driving sub-circuit; wherein the first driving sub-circuit is connected between the state feedback terminal and the control terminal, and the second driving sub-circuit is connected between the second state feedback terminal and the second control terminal; both the first and second switching transistors are N-channel enhancement-mode insulated-gate field-effect transistors, and both the third and fourth switching transistors are P-channel enhancement-mode insulated-gate field-effect transistors.

[0041] like Figure 4 As shown, the switching circuit has a first switching transistor. Second switching transistor Based on the N-type switching branch composed of N-channel enhancement-mode insulated-gate field-effect transistors, a third switching transistor is further connected in parallel. and the fourth switching transistor All are P-type switching branches composed of P-channel enhancement-mode insulated-gate field-effect transistors. For example... Figure 4 The specific wiring relationship is as follows: third switch transistor The source and the fourth switch The source connection serves as the second state feedback terminal. Third switching transistor The gate and the fourth switch The gate connection serves as the second control terminal; the third switching transistor... The drain of the first switching transistor The drains are connected in parallel to receive the input electrical signal. Fourth switching transistor The drain and the second switching transistor The drains are connected in parallel to output the corresponding electrical signal. .

[0042] Accordingly, the driving circuit includes a first driving sub-circuit and a second driving sub-circuit. The first driving sub-circuit employs the N-type driving architecture (based on NMOS differential pairs and pull-up current sources) as described in the first part of the embodiments, and is connected to the first state feedback terminal. (i.e., the first switching transistor) Second switching transistor (the common source node) and the first control terminal (i.e., the first switch) Second switching transistor Between the common gate point, used to generate a floating voltage The second driving sub-circuit adopts the P-type driving architecture (based on PMOS differential pairs and pull-down current sources) as described in the second part of the embodiment. Its circuit topology is completely complementary to the first driving sub-circuit and is connected to the second state feedback terminal (the third switch). With the fourth switching transistor (public source node) Second control terminal (third switch) With the fourth switching transistor Between the common gate point, used to generate a floating voltage .

[0043] During the steady-state conduction phase, through the parallel cooperation of the N-type switch branch and the P-type switch branch, when the input electrical signal common-mode voltage unidirectionally approaches the power supply voltage or ground voltage, at least one set of drive sub-circuits can maintain high transconductance operation and mutually cancel the fluctuation of the single tube's on-resistance with the change of common-mode potential, ensuring the gain consistency and extremely high purity of small signal transmission across the entire voltage range.

[0044] Compared to the capacitive bootstrap switch in an ADC, the most significant advantage of this application lies in its purely analog "clock-free" characteristic. In scenarios with extremely stringent requirements for background noise, such as neural electrical signal acquisition, this solution avoids noise folding caused by discrete sampling, enabling the system to capture neuronal synaptic activity losslessly in the continuous time domain. This simple and extremely low-power circuit design allows for precise control of the on-resistance through resistor biasing, providing a highly linear, low-noise analog front-end isolation and access solution for multi-channel implantable chips.

[0045] Those skilled in the art will understand that the above embodiments are specific implementations of this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application.

Claims

1. An analog signal sampling switch circuit, characterized in that, include: A driving circuit, and a switching circuit connected to the driving circuit; wherein, The switching circuit is used to turn on or block the input electrical signal. The input terminal of the driving circuit is connected to the state feedback terminal of the switching circuit, and the output terminal of the driving circuit is connected to the control terminal of the switching circuit. The driving circuit is used to output a driving voltage that follows the potential change of the state feedback terminal to the control terminal of the switching circuit when the switching circuit is turned on, so as to maintain the voltage difference between the control terminal and the state feedback terminal.

2. The analog signal sampling switch circuit according to claim 1, characterized in that, The switching circuit includes a first switching transistor and a second switching transistor; wherein... The source of the first switch is connected to the source of the second switch to serve as the state feedback terminal; The gate of the first switch is connected to the gate of the second switch to serve as the control terminal; The drain of the first switching transistor is used to receive the input electrical signal, and the drain of the second switching transistor is used to output an output signal corresponding to the electrical signal.

3. The analog signal sampling switch circuit according to claim 2, characterized in that, The driving circuit includes an open-loop differential amplifier, a load resistor, and a first controlled current source; wherein... The input terminal of the open-loop differential amplifier is connected to the state feedback terminal; One end of the first controlled current source is connected to the control terminal, and the other end of the first controlled current source is connected to the first reference potential terminal; One end of the load resistor is connected to the control terminal and one end of the first controlled current source, and the other end of the load resistor is connected to the output terminal of the open-loop differential amplifier. The first controlled current source generates the driving voltage at the control terminal via the load resistor.

4. The analog signal sampling switch circuit according to claim 3, characterized in that, The open-loop differential amplifier includes a first input transistor, a second input transistor, and a second controlled current source; wherein... The source of the first input transistor is connected to the source of the second input transistor and to one end of the second controlled current source, and the other end of the second controlled current source is connected to the second reference potential terminal; The gate of the first input transistor is connected to the state feedback terminal; The drain and gate of the second input transistor are shorted together, and the drain of the second input transistor is connected to the other end of the load resistor.

5. The analog signal sampling switch circuit according to claim 4, characterized in that, The tail current provided by the second controlled current source is twice the magnitude of the bias current provided by the first controlled current source.

6. The analog signal sampling switch circuit according to claim 4, characterized in that, The driving circuit further includes a matching resistor, one end of which is connected to the drain of the first input transistor, and the other end of which is connected to the first reference potential terminal.

7. The analog signal sampling switch circuit according to claim 6, characterized in that, When both the first input transistor and the second input transistor are N-channel enhancement-mode insulated-gate field-effect transistors The first reference potential terminal is an external power source, and the second reference potential terminal is a ground terminal.

8. The analog signal sampling switch circuit according to claim 6, characterized in that, When both the first input transistor and the second input transistor are P-channel enhancement-mode insulated-gate field-effect transistors The first reference potential terminal is a ground terminal, and the second reference potential terminal is an external power source.

9. The analog signal sampling switch circuit according to claim 2, characterized in that, The switching circuit further includes a third switching transistor and a fourth switching transistor; wherein... The source of the third switch is connected to the source of the fourth switch to serve as a second state feedback terminal. The gate of the third switch is connected to the gate of the fourth switch to serve as the second control terminal; The drain of the third switch is connected to the drain of the first switch to receive the input electrical signal, and the drain of the fourth switch is connected to the drain of the second switch to receive the output signal.

10. The analog signal sampling switch circuit according to claim 9, characterized in that, The driving circuit includes a first driving sub-circuit and a second driving sub-circuit; wherein... The first driving sub-circuit is connected between the state feedback terminal and the control terminal, and the second driving sub-circuit is connected between the second state feedback terminal and the second control terminal; The first and second switching transistors are both N-channel enhancement-mode insulated-gate field-effect transistors, and the third and fourth switching transistors are both P-channel enhancement-mode insulated-gate field-effect transistors.

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