transmitting circuitry

Abstract

A transmitting circuit includes impedance adjustment circuit and a plurality of driving circuits. The impedance adjustment circuit includes first and second impedance adjustment circuits. The first impedance adjustment circuit includes a first replica driving unit, and the first impedance adjustment circuit is configured to control an output impedance of the first replica driving unit to a first impedance value by a first impedance adjustment signal. The second impedance adjustment circuit includes a second replica driving unit, and the second impedance adjustment circuit is configured to control an output impedance of the second replica driving unit to a second impedance value by a second impedance adjustment signal, wherein the second impedance value is different from the first impedance value. The plurality of driving circuits respectively have a plurality of standard driving units, and each standard driving unit is configured to receive a corresponding one of the first impedance adjustment signal and the second impedance adjustment signal to be set to the first impedance value or the second impedance value.

Description

Technical Field

[0001] This invention relates to a circuit, and more particularly to a transmitting circuit. Background Technology

[0002] With the increasing popularity of portable electronic devices, effectively reducing the footprint and cost of semiconductor devices has become an important issue in circuit design. Summary of the Invention

[0003] This invention provides a transmitting circuit that can effectively reduce the manufacturing cost of transmitting circuits.

[0004] The transmitting circuit of the present invention includes an impedance adjustment circuit and multiple driving circuits. The impedance adjustment circuit includes a first impedance adjustment circuit and a second impedance adjustment circuit. The first impedance adjustment circuit includes a first replication driving unit, which controls the output impedance of the first replication driving unit to a first impedance value using a first impedance adjustment signal. The second impedance adjustment circuit includes a second replication driving unit, which controls the output impedance of the second replication driving unit to a second impedance value using a second impedance adjustment signal, wherein the second impedance value is different from the first impedance value. The multiple driving circuits each have multiple standard driving units, each standard driving unit receiving a corresponding one of the first impedance adjustment signal and the second impedance adjustment signal to be set to either the first impedance value or the second impedance value.

[0005] Based on the above, the manufacturing cost of the transmitting circuit of the present invention can be reduced by using a first standard driving unit and a second standard driving unit. Attached Figure Description

[0006] Figure 1 This is a circuit block diagram of the transmitting circuit according to Embodiment 1 of the present invention;

[0007] Figure 2A This is a circuit diagram of the driving circuit according to Embodiment 1 of the present invention;

[0008] Figure 2B This is a circuit diagram of the driving circuit according to Embodiment 1 of the present invention;

[0009] Figure 3A This is a circuit diagram of the first impedance adjustment circuit in Embodiment 1 of the present invention;

[0010] Figure 3B This is a circuit diagram of the second impedance adjustment circuit in Embodiment 1 of the present invention. Detailed Implementation

[0011] Figure 1This is a circuit block diagram of the transmitting circuit 1 according to Embodiment 1 of the present invention. The transmitting circuit 1 includes a processing circuit 10, driving circuits DRV1 to DRV4, and an impedance adjustment circuit 11. Generally, to simplify the design, the driving circuits DRV1 to DRV4 are designed in a modular form. That is, the driving circuits DRV1 to DRV4 are implemented based on the same standard driving unit. Each driving circuit DRV1 to DRV4 connects a corresponding number of standard driving units in parallel according to the amplitude requirements of each channel, thus meeting the driving requirements of the transmitting circuit 1. In this embodiment, although not explicitly shown, the driving circuits DRV1 to DRV4 use two different sizes of standard driving units for driving. The circuit impedance value of the first type of standard driving unit can be, for example, a preset standard impedance value, while the circuit impedance value of the second type of standard driving unit can be equivalent to the impedance value of a predetermined number of the first type of standard driving units connected in parallel. In this way, by using two standard drive units with different impedance values ​​to implement the drive circuits DRV1 to DRV4, the number of standard drive units connected in parallel and the manufacturing cost can be effectively reduced in some cases where a large number of standard drive units need to be connected in parallel in the drive circuits DRV1 to DRV4.

[0012] In detail, the processing circuit 10 can be used to perform operations such as calculations or encoding on the data to be transmitted, thereby generating input drive signals Din1 to Din4. In some embodiments, the processing circuit 10 may include, for example, circuits such as a pseudo random bit sequence (PRBS) circuit, an encoder, a multiplexer, and a filter. The drive circuits DRV1 to DRV4 can receive the input drive signals Din1 to Din4, and output signals of appropriate amplitude according to the driving of the first impedance adjustment signal Adj1 and the second impedance adjustment signal Adj2 provided by the impedance adjustment circuit 11, together forming the output signal Dout at the output terminal.

[0013] The impedance adjustment circuit 11 includes a first impedance adjustment circuit 110 and a second impedance adjustment circuit 111. The first impedance adjustment circuit 110 includes a first replication drive unit (not shown). Figure 1 The first impedance adjustment circuit 110 can control the output impedance of the first replication drive unit to a first impedance value by generating a first impedance adjustment signal Adj1. The second impedance adjustment circuit 111 includes a second replication drive unit (not shown). Figure 1The second impedance adjustment circuit 111 can control the output impedance of the second replication driving unit to a second impedance value by generating a second impedance adjustment signal Adj2. Since the first and second replication driving units are replica circuits of the first and second standard driving units, respectively, the second replication driving unit is also equivalent to a parallel circuit of multiple first replication driving units. Therefore, the second impedance value set by the second impedance adjustment circuit will be less than the first impedance value set by the first impedance adjustment circuit. In some embodiments, the first impedance value is, for example, twenty-one times the second impedance value. However, of course, the ratio between the first and second impedance values ​​can be adaptively adjusted according to different design requirements. Alternatively, there may be more than one type of replication driving unit, all of which fall within the scope of the variations disclosed herein.

[0014] Specifically, the first impedance adjustment circuit 110 includes a first replication driving unit, and the second impedance adjustment circuit 111 includes a second replication driving unit. The circuit structure and size of the two replication driving units are the same as those of the first standard driving unit and the second standard driving unit used to implement the driving circuits DRV1 to DRV4. The first impedance adjustment circuit 110 and the second impedance adjustment circuit 111 can generate a first impedance adjustment signal Adj1 and a second impedance adjustment signal Adj2, respectively, to control the output impedance of the first replication driving unit and the second replication driving unit at preset first impedance values ​​and second impedance values, respectively. In this way, the impedance adjustment circuit 11 can provide the first impedance adjustment signal Adj1 and the second impedance adjustment signal Adj2 to the first standard driving unit and the second standard driving unit corresponding to the driving circuits DRV1 to DRV4, so that the first standard driving unit and the second standard driving unit also have the first impedance value and the second impedance value, allowing the transmitting circuit 1 to perform the preset driving operation.

[0015] In some embodiments, the first standard driving unit and the first copy driving unit controlled by the first impedance adjustment signal Adj1 both have an output impedance of a first impedance value, while the second standard driving unit and the second copy driving unit controlled by the second impedance adjustment signal Adj2 both have an output impedance of a second impedance value. Naturally, the first impedance value will also be twenty-one times the second impedance value.

[0016] In some embodiments, the USB4 transmission standard requires that: driver circuit DRV1 needs to have the capability to generate an amplitude output of 0% to 7.5% of the maximum amplitude and a resolution of 2.5% of the maximum amplitude; driver circuit DRV2 needs to have the capability to generate an amplitude output of 0% to 25% of the maximum amplitude and a resolution of 5% of the maximum amplitude; driver circuit DRV3 needs to have the capability to generate an amplitude output of 52.5% to 100% of the maximum amplitude and a resolution of 2.5% of the maximum amplitude; and driver circuit DRV4 needs to have the capability to generate an amplitude output of 0% to 15% of the maximum amplitude and a resolution of 5% of the maximum amplitude.

[0017] To meet the aforementioned USB4 transmission standard, driver circuit DRV1 may, for example, include three parallel first standard driver units. Driver circuit DRV2 may, for example, include ten parallel first standard driver units. Driver circuit DRV3 may, for example, include one second standard driver unit. Driver circuit DRV4 may, for example, include six parallel first standard driver units. In this case, the first standard driver unit can receive the control of a first impedance adjustment signal Adj1 to have a first impedance value, and each first standard driver unit can provide a maximum amplitude drive capability of 2.5%. When the impedance of the second standard driver unit can be equivalent to the impedance of twenty-one parallel first standard driver units, each second standard driver unit can receive the control of a second impedance adjustment signal Adj2 to provide a maximum amplitude drive capability of 52.5%. Therefore, replacing multiple parallel first standard driver units with second standard driver units can effectively reduce manufacturing costs while meeting system requirements.

[0018] Figure 2A This is a circuit diagram of the driving circuit DRV1 according to Embodiment 1 of the present invention. Figure 2A As shown, the drive circuit DRV1 includes logic gates NAG and NOG, and a first standard drive unit 12. The detailed drive circuit DRV1 receives gate control signals CK and CKb, as well as data from the input signal Din1, to control the drive of the first standard drive unit 12. In this embodiment, although not explicitly shown, the drive circuit DRV1 is formed by three first standard drive units 12 connected in parallel, and all connected to the output terminal via a resistor Rs. In this way, the drive unit DRV1 can provide three times the drive current to the output terminal. In other embodiments, the number of first standard drive units 12 connected in parallel can, of course, be adjusted according to design requirements.

[0019] In detail, the first standard driving unit 12 includes P-type transistors P1 and P2 and N-type transistors N1 and N2 connected in series between the operating voltage VDD and the ground voltage GND. The gates of transistors P1 and N2 respectively receive the first pull-up adjustment signal Adj1p and the first pull-down adjustment signal Adj1n of the first impedance adjustment signal Adj1, which are used to control the output impedance of the first standard driving unit 12 to the first impedance value.

[0020] More specifically, due to the logical relationship between logic gates NAG and NOG, the upper half of the first standard driving unit 12 composed of transistors P1 and P2 and the lower half of the second standard driving unit composed of transistors N1 and N2 will not be turned on simultaneously. The clock signal Ck and the input driving signal will only turn on the upper half or the lower half. Therefore, in order to make the impedance seen at the output terminal of the first standard driving unit the first impedance value, the output impedances of the upper half and the lower half of the first standard driving unit 12 will be controlled to the first impedance value by the output impedances of the first pull-up adjustment signal Adj1p and the first pull-down adjustment signal Adj1n of the first adjustment signal Adj1, respectively.

[0021] Figure 2B This is a circuit diagram of the driving circuit DRV3 according to Embodiment 1 of the present invention. In this embodiment, the driving circuit DRV3 is formed by a second standard driving unit 13, and both are coupled to the output terminal through a resistor Rs. Figure 2B The drive circuit DRV3 and Figure 2A The drive circuit DRV1 in the middle is only in Figure 2A In the middle, three parallel first standard drive units 12 are in Figure 2B The first standard driving unit 12 is replaced by a second standard driving unit 13, and the gates of transistors P3 and N4 respectively receive the second pull-up adjustment signal Adj2p and the second pull-down adjustment signal Adj2n of the second impedance adjustment signal Adj2. In this embodiment, the first standard driving unit 12 and the second standard driving unit 13 have the same circuit structure, except that the impedance of the second standard driving unit 13 is the equivalent impedance of twenty-one first standard driving units 12 connected in parallel.

[0022] Figure 3A This is a circuit diagram of the first impedance adjustment circuit 110 according to Embodiment 1 of the present invention. The first impedance adjustment circuit 110 includes a first pull-up adjustment circuit 110u and a first pull-down adjustment circuit 110d. Generally speaking, the first copy drive unit 14 used to simulate and adjust the first standard drive unit 12 is divided into an upper part 14u and a lower part 14d, and is respectively disposed inside the first pull-up adjustment circuit 110u and the first pull-down adjustment circuit 110d for control and adjustment.

[0023] The first pull-up adjustment circuit 110u generates a first pull-up adjustment signal Adj1u from the first impedance adjustment signal Adj1 to control the output impedance of the upper half 14u of the first copy driving unit 14 to a first impedance value. Additionally, the first pull-down adjustment circuit 110d includes the lower half 14d of the first copy driving unit 14. The first pull-down adjustment circuit 110d generates a first pull-down adjustment signal Adj1d from the first impedance adjustment signal Adj1 to control the output impedance of the lower half 14d of the first copy driving unit 14 to a second impedance value.

[0024] In detail, the first pull-up adjustment circuit 110u includes a first pull-up transistor string and resistors Rsu1 and Rb1. The first pull-up transistor string forms the upper half 14u of the first replica drive unit 14 and includes P-type transistors Pr1 and Pr2 connected in series. Overall, transistors Pr1 and Pr2 and resistors Rsu1 and Rb1 are connected in series between the operating voltage and the ground voltage. The positive input terminal of comparator CMP-d1 is coupled to the node between resistors Rsu1 and Rb1, and receives a reference voltage Vrefu at its negative input terminal. Comparator CMP-u1 compares the voltages at the positive and negative input terminals to generate a first pull-up adjustment signal Adj1p to the gate of transistor Pr1, thereby forming a negative feedback control loop. More specifically, the gate of transistor Pr2 receives a turn-on voltage VCp, and the node between resistors Rsu1 and Rb1 can be used to set as the output node of the first pull-up adjustment circuit 110u to simulate the output impedance of the upper half of the first standard drive unit 12 through resistor Rs to the output terminal. The first pull-up adjustment circuit 110u can adjust the transistor Pr1 through the control loop formed by the comparator CMP-u1 by setting the resistance and voltage of resistors Rsu1, Rb1 and reference voltage Vrefu, so that the output impedance Rout of the first pull-up transistor string (that is, the upper half 14u of the first replication drive unit 14) looking upward from the node coupled between resistors Rsu1 and Rb1 can be controlled at the first impedance value.

[0025] Similarly, the first pull-down adjustment circuit 110d has a circuit structure similar to, but reversed, that of the first pull-up adjustment circuit 110u. The first pull-down adjustment circuit 110d can adjust the resistance value of transistor Nr2 by generating a first pull-down adjustment signal Adj1n, so that the output impedance of the lower part 14d of the first replication drive unit 14 is also controlled at the first resistance value. For the relevant circuit structure and operation of the first pull-down adjustment circuit 110d, please refer to the description of the first pull-up adjustment circuit 110u in the paragraph above; it will not be repeated here.

[0026] In some embodiments, the resistor Rb1 may be, for example, 10.8 kΩ, and the output impedance Rout of the first pull-up adjustment circuit 110u and the first pull-down adjustment circuit 110d may be controlled by the first pull-up adjustment signal Adj1p and the first pull-down adjustment signal Adj1n to a first impedance value of 3.6 kΩ.

[0027] Figure 3B This is a circuit diagram of the second impedance adjustment circuit 111 according to Embodiment 1 of the present invention. The second impedance adjustment circuit 111 includes a second pull-up adjustment circuit 111u and a second pull-down adjustment circuit 111d. Generally speaking, the second replication drive unit 15, which is used to simulate and adjust the second standard drive unit 12, is divided into an upper half 15u and a lower half 15d, and is respectively disposed inside the second pull-up adjustment circuit 111u and the second pull-down adjustment circuit 111d for control and adjustment.

[0028] and Figure 3A The first pull-up impedance adjustment circuit is similar to 110u. Figure 3B The second pull-up impedance adjustment circuit 111u includes a second pull-up transistor string and resistors Rsu2 and Rb2. The second pull-up transistor string forms the upper half 15u of the second replication drive unit 15 and has transistors Pr3 and Pr4. The second pull-up transistor string and resistors Rsu2 and Rb2 are connected in series between the operating voltage and the ground voltage. Similarly, the node between resistors Rsu2 and Rb2 can be set as the output node of the second pull-up impedance adjustment circuit 111u, and the output impedance looking towards the second pull-up transistor string (the upper half 15u of the second replication drive unit 15) from this node can simulate the output impedance of the upper half of the second standard drive unit 13. However, unlike the first pull-up impedance adjustment circuit 110u, the second pull-up impedance adjustment circuit 111u also includes nineteen first pull-up transistor strings (the upper half 14u of the first replication drive unit 14), connected in parallel to the second pull-up transistor strings.

[0029] The second pull-up adjustment circuit 111u generates a second pull-up adjustment signal Adj2u from the second impedance adjustment signal Adj2 to control the output impedance of the upper half 15u of the second copy driving unit 15 to a second impedance value. Additionally, the second pull-down adjustment circuit 111d includes the lower half 15d of the second copy driving unit 15. The second pull-down adjustment circuit 111d generates a second pull-down adjustment signal Adj2d from the second impedance adjustment signal Adj2 to control the output impedance of the lower half 15d of the second copy driving unit 15 to a second impedance value.

[0030] In this embodiment, transistors Pr3 and Pr4 of the second pull-up transistor string are connected in series with resistors Rsu2 and Rb2. Nineteen first pull-up transistor strings are connected in parallel with the second pull-up transistor strings to the node between resistors Rsu2 and Rb2, and connected to ground voltage through resistor Rb2. The positive input of comparator CMP-u2 is coupled to the node between resistors Rsu2 and Rb2, and receives a reference voltage Vrefu at its negative input. Comparator CMP-d2 compares the voltages at the positive and negative inputs to generate a second pull-up adjustment signal Adj2p, which is then provided to the gate of transistor Pr3.

[0031] Operationally, the transistors Pr1 of the nineteen first pull-up transistor strings receive the first pull-up adjustment signal Adj1p generated by the first pull-up impedance adjustment circuit 110 at their gates, and are thus set to the first impedance value. The comparator CMP-u2 adjusts the output impedance of the second pull-up transistor string to the second impedance value by sensing the voltage between resistors Rsu2 and Rb2. Specifically, since the second pull-up adjustment circuit 111u contains nineteen parallel first pull-up transistor strings, the output impedance of each first pull-up transistor string is controlled to the first impedance value by the first pull-up adjustment signal Adj1u. Furthermore, the comparator CMP-u2 can adjust the overall output impedance of the second pull-up adjustment circuit 111u (including the second pull-up transistor string and the nineteen first pull-up transistor strings) looking upwards from this node to one-fortieth of the first impedance value based on the voltage between resistors Rsu2 and Rb2. In this way, the output impedance of the second pull-up transistor string can be equivalently adjusted to the parallel connection of twenty-one first pull-up transistor strings with the first impedance value, and the second impedance value of the second pull-up transistor string is one twenty-first of the first impedance value.

[0032] In some embodiments, resistor Rb2 may be, for example, 270 ohms, and the output impedance Rout of the second pull-up adjustment circuit 111u and the second pull-down adjustment circuit 111d may be controlled at 90 ohms by the second pull-up adjustment signal Adj2p and the second pull-down adjustment signal Adj1n, which is one-fortieth of the first impedance value of 3.6 kΩ. Therefore, equivalently, the output impedance of the upper half 15u and the lower half 15 of the second replication drive unit 15 will also be adjusted to one-twenty-first of the first impedance value.

[0033] Generally, the impedance of a transistor is directly proportional to or positively correlated with its aspect ratio. Therefore, a second pull-up transistor string with a smaller impedance and aspect ratio can be designed to have a smaller area, thus effectively improving manufacturing costs. Compared to paralleling multiple first pull-up transistor strings with larger dimensions, an equivalent circuit with the same function can be achieved using fewer and smaller second pull-up transistor strings, effectively saving manufacturing area and costs in terms of both transistor count and transistor size.

[0034] Furthermore, since the second impedance adjustment circuit 111 also includes a first replication driving unit and needs to receive control from the first impedance adjustment signal Adj1, the second impedance adjustment signal Adj2 will only gradually lock after the first impedance adjustment signal Adj1 gradually converges to a steady state. Of course, the convergence order of the first impedance adjustment signal Adj1 and the second impedance adjustment signal Adj2 is corresponding... Figure 3A , Figure 3B The circuit structures of the first impedance adjustment circuit 110 and the second impedance adjustment circuit 111 are shown. In other embodiments, the first impedance adjustment signal Adj1 and the second impedance adjustment signal Adj2 may have different convergence orders due to different circuit structures. For example, Figure 3B The second impedance adjustment circuit 111 includes nineteen sets of first replication driving units and one set of second replication driving units connected in parallel. Comparators CMP-u2 and CMP-d2 adjust the output impedance to one-fortieth of the first impedance value by sensing the voltage at the output node, thus obtaining a second replication driving unit that is equivalent to twenty-one sets of first replication driving units connected in parallel. However, in other embodiments, the first replication driving units in the second impedance adjustment circuit can be removed, thus only the second replication driving units are present. In this case, the second impedance adjustment circuit can appropriately adjust the resistor Rb2 or provide other reference voltages to the negative input terminal of the comparator to give the output node of the second impedance adjustment circuit an appropriate bias voltage, so that the comparators CMP-u2 and CMP-d2 can generate a second impedance adjustment signal to adjust the output impedance to one-twenty-first of the first impedance value. In this way, the second impedance adjustment signal can converge synchronously with the first impedance adjustment signal without waiting for the convergence of the first impedance adjustment signal.

[0035] In summary, in the transmitting circuit of the present invention, the driving circuit can be formed by a first standard driving unit and a second standard driving unit, which is equivalent to multiple first standard driving units connected in parallel. In this way, the circuit that originally required multiple first standard driving units connected in parallel can be replaced by a smaller second standard driving unit, thereby effectively reducing the manufacturing cost of the transmitting circuit.

Claims

1. A transmitting circuit, characterized in that, include: Impedance adjustment circuit, including: A first impedance adjustment circuit includes a first replication driving unit, wherein the first impedance adjustment circuit is configured to control the output impedance of the first replication driving unit to a first impedance value via a first impedance adjustment signal; and The second impedance adjustment circuit includes a second replication driving unit, which is configured to control the output impedance of the second replication driving unit to a second impedance value via a second impedance adjustment signal, wherein the second impedance value is different from the first impedance value; and Multiple driving circuits, each having multiple standard driving units, each standard driving unit being used to receive a corresponding one of the first impedance adjustment signal and the second impedance adjustment signal to be set to the first impedance value or the second impedance value.

2. The transmitting circuit according to claim 1, wherein the first impedance value is greater than the second impedance value.

3. The transmitting circuit according to claim 2, wherein the first impedance value is twenty-one times the second impedance value.

4. The transmitting circuit according to claim 1, wherein the plurality of driving circuits includes a first driving circuit and a second driving circuit. The first standard driving unit in the first driving circuit has the same structure as the first copy driving unit. The first standard driving unit is used to receive the first impedance adjustment signal to set the output impedance to the first impedance value. The second standard driving unit in the second driving circuit has the same structure as the second copy driving unit. The second standard driving unit is used to receive the second impedance adjustment signal to set the output impedance to the second impedance value.

5. The transmitting circuit according to claim 1, wherein the first impedance adjustment circuit comprises: The first pull-up adjustment circuit includes the upper half of the first copy driving unit. The first pull-up adjustment circuit generates a first pull-up adjustment signal in the first impedance adjustment signal to control the impedance of the upper half of the first copy driving unit to the first impedance value. as well as The first pull-down adjustment circuit includes the lower half of the first copy driving unit. The first pull-down adjustment circuit generates a first pull-down adjustment signal in the first impedance adjustment signal to control the impedance of the lower half of the first copy driving unit to the first impedance value.

6. The transmitting circuit according to claim 5, wherein the first pull-up adjustment circuit comprises: A first pull-up transistor string forms the upper half of the first replication drive unit, the first pull-up transistor string having a first transistor connected to the operating voltage and a second transistor connected in series with the first transistor; The first resistor is coupled between the second transistor and the output terminal of the first pull-up adjustment circuit; as well as The second resistor is coupled between the output terminal of the first pull-up adjustment circuit and the ground voltage. One of the first transistor and the second transistor is controlled by the first pull-up adjustment signal, such that the output impedance of the first pull-up adjustment circuit looking at the first pull-up transistor string is the first impedance value.

7. The transmitting circuit according to claim 6, wherein the first impedance adjustment circuit comprises: A first comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output terminal of the first pull-up adjustment circuit. The second input terminal is used to receive a preset voltage. The first comparator is used to compare the voltages of the first input terminal and the second input terminal, and generates the first pull-up adjustment signal to the first transistor at the output terminal of the first comparator.

8. The transmitting circuit according to claim 6, wherein the second impedance adjustment circuit comprises: The second pull-up adjustment circuit includes the upper half of the second copy driving unit. The second pull-up adjustment circuit generates a second pull-up adjustment signal from the second impedance adjustment signal to control the output impedance of the upper half of the second copy driving unit to the second impedance value. The second pull-up adjustment circuit includes: A second pull-up transistor string forms the upper half of the second replication drive unit. The second pull-up transistor string has a third transistor connected to the operating voltage and a fourth transistor connected in series with the third transistor, wherein the third transistor is controlled by the second pull-up adjustment signal. The third resistor is coupled between the fourth transistor and the output of the second pull-up adjustment circuit; and The fourth resistor is coupled between the output terminal of the second pull-up adjustment circuit and the ground voltage.

9. The transmitting circuit according to claim 8, wherein the aspect ratio of the second pull-up transistor string is less than the aspect ratio of the first transistor string.

10. The transmitting circuit according to claim 8, wherein the second pull-up adjustment circuit further comprises: The first pull-up transistor string is coupled between the operating voltage and the output terminal of the second pull-up adjustment circuit.

11. The transmitting circuit according to claim 10, wherein the second pull-up adjustment circuit comprises nineteen strings of the first pull-up transistors connected in parallel between the operating voltage and the output terminal of the second pull-up adjustment circuit.

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